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Merge branches 'pm-epoll', 'pnp' and 'powercap'
[deliverable/linux.git] / sound / soc / codecs / cs42l52.c
1 /*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/gpio.h>
21 #include <linux/pm.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
36 #include "cs42l52.h"
37
38 struct sp_config {
39 u8 spc, format, spfs;
40 u32 srate;
41 };
42
43 struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
46 struct device *dev;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
49 u32 sysclk;
50 u8 mclksel;
51 u32 mclk;
52 u8 flags;
53 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
54 struct input_dev *beep;
55 struct work_struct beep_work;
56 int beep_rate;
57 #endif
58 };
59
60 static const struct reg_default cs42l52_reg_defaults[] = {
61 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
62 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
63 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
64 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
65 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
66 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
67 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
68 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
69 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
70 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
71 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
72 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
73 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
74 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
75 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
76 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
77 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
78 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
79 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
80 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
81 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
82 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
83 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
84 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
85 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
86 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
87 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
88 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
89 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
90 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
91 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
92 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
93 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
94 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
95 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
96 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
97 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
98 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
99 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
100 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
101 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
102 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
103 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
104 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
105 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
106 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
107 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
108 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
109 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
110 };
111
112 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
113 {
114 switch (reg) {
115 case CS42L52_CHIP:
116 case CS42L52_PWRCTL1:
117 case CS42L52_PWRCTL2:
118 case CS42L52_PWRCTL3:
119 case CS42L52_CLK_CTL:
120 case CS42L52_IFACE_CTL1:
121 case CS42L52_IFACE_CTL2:
122 case CS42L52_ADC_PGA_A:
123 case CS42L52_ADC_PGA_B:
124 case CS42L52_ANALOG_HPF_CTL:
125 case CS42L52_ADC_HPF_FREQ:
126 case CS42L52_ADC_MISC_CTL:
127 case CS42L52_PB_CTL1:
128 case CS42L52_MISC_CTL:
129 case CS42L52_PB_CTL2:
130 case CS42L52_MICA_CTL:
131 case CS42L52_MICB_CTL:
132 case CS42L52_PGAA_CTL:
133 case CS42L52_PGAB_CTL:
134 case CS42L52_PASSTHRUA_VOL:
135 case CS42L52_PASSTHRUB_VOL:
136 case CS42L52_ADCA_VOL:
137 case CS42L52_ADCB_VOL:
138 case CS42L52_ADCA_MIXER_VOL:
139 case CS42L52_ADCB_MIXER_VOL:
140 case CS42L52_PCMA_MIXER_VOL:
141 case CS42L52_PCMB_MIXER_VOL:
142 case CS42L52_BEEP_FREQ:
143 case CS42L52_BEEP_VOL:
144 case CS42L52_BEEP_TONE_CTL:
145 case CS42L52_TONE_CTL:
146 case CS42L52_MASTERA_VOL:
147 case CS42L52_MASTERB_VOL:
148 case CS42L52_HPA_VOL:
149 case CS42L52_HPB_VOL:
150 case CS42L52_SPKA_VOL:
151 case CS42L52_SPKB_VOL:
152 case CS42L52_ADC_PCM_MIXER:
153 case CS42L52_LIMITER_CTL1:
154 case CS42L52_LIMITER_CTL2:
155 case CS42L52_LIMITER_AT_RATE:
156 case CS42L52_ALC_CTL:
157 case CS42L52_ALC_RATE:
158 case CS42L52_ALC_THRESHOLD:
159 case CS42L52_NOISE_GATE_CTL:
160 case CS42L52_CLK_STATUS:
161 case CS42L52_BATT_COMPEN:
162 case CS42L52_BATT_LEVEL:
163 case CS42L52_SPK_STATUS:
164 case CS42L52_TEM_CTL:
165 case CS42L52_THE_FOLDBACK:
166 case CS42L52_CHARGE_PUMP:
167 return true;
168 default:
169 return false;
170 }
171 }
172
173 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
174 {
175 switch (reg) {
176 case CS42L52_IFACE_CTL2:
177 case CS42L52_CLK_STATUS:
178 case CS42L52_BATT_LEVEL:
179 case CS42L52_SPK_STATUS:
180 case CS42L52_CHARGE_PUMP:
181 return 1;
182 default:
183 return 0;
184 }
185 }
186
187 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
188
189 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
190
191 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
192
193 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
194
195 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
196
197 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
198
199 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
200
201 static const unsigned int limiter_tlv[] = {
202 TLV_DB_RANGE_HEAD(2),
203 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
204 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
205 };
206
207 static const char * const cs42l52_adca_text[] = {
208 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
209
210 static const char * const cs42l52_adcb_text[] = {
211 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
212
213 static const struct soc_enum adca_enum =
214 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
215 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
216
217 static const struct soc_enum adcb_enum =
218 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
219 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
220
221 static const struct snd_kcontrol_new adca_mux =
222 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
223
224 static const struct snd_kcontrol_new adcb_mux =
225 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
226
227 static const char * const mic_bias_level_text[] = {
228 "0.5 +VA", "0.6 +VA", "0.7 +VA",
229 "0.8 +VA", "0.83 +VA", "0.91 +VA"
230 };
231
232 static const struct soc_enum mic_bias_level_enum =
233 SOC_ENUM_SINGLE(CS42L52_IFACE_CTL2, 0,
234 ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
235
236 static const char * const cs42l52_mic_text[] = { "Single", "Differential" };
237
238 static const struct soc_enum mica_enum =
239 SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
240 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
241
242 static const struct soc_enum micb_enum =
243 SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
244 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
245
246 static const struct snd_kcontrol_new mica_mux =
247 SOC_DAPM_ENUM("Left Mic Input Capture Mux", mica_enum);
248
249 static const struct snd_kcontrol_new micb_mux =
250 SOC_DAPM_ENUM("Right Mic Input Capture Mux", micb_enum);
251
252 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
253
254 static const struct soc_enum digital_output_mux_enum =
255 SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
256 ARRAY_SIZE(digital_output_mux_text),
257 digital_output_mux_text);
258
259 static const struct snd_kcontrol_new digital_output_mux =
260 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
261
262 static const char * const hp_gain_num_text[] = {
263 "0.3959", "0.4571", "0.5111", "0.6047",
264 "0.7099", "0.8399", "1.000", "1.1430"
265 };
266
267 static const struct soc_enum hp_gain_enum =
268 SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
269 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
270
271 static const char * const beep_pitch_text[] = {
272 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
273 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
274 };
275
276 static const struct soc_enum beep_pitch_enum =
277 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
278 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
279
280 static const char * const beep_ontime_text[] = {
281 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
282 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
283 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
284 };
285
286 static const struct soc_enum beep_ontime_enum =
287 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
288 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
289
290 static const char * const beep_offtime_text[] = {
291 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
292 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
293 };
294
295 static const struct soc_enum beep_offtime_enum =
296 SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
297 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
298
299 static const char * const beep_config_text[] = {
300 "Off", "Single", "Multiple", "Continuous"
301 };
302
303 static const struct soc_enum beep_config_enum =
304 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
305 ARRAY_SIZE(beep_config_text), beep_config_text);
306
307 static const char * const beep_bass_text[] = {
308 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
309 };
310
311 static const struct soc_enum beep_bass_enum =
312 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
313 ARRAY_SIZE(beep_bass_text), beep_bass_text);
314
315 static const char * const beep_treble_text[] = {
316 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
317 };
318
319 static const struct soc_enum beep_treble_enum =
320 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
321 ARRAY_SIZE(beep_treble_text), beep_treble_text);
322
323 static const char * const ng_threshold_text[] = {
324 "-34dB", "-37dB", "-40dB", "-43dB",
325 "-46dB", "-52dB", "-58dB", "-64dB"
326 };
327
328 static const struct soc_enum ng_threshold_enum =
329 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
330 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
331
332 static const char * const cs42l52_ng_delay_text[] = {
333 "50ms", "100ms", "150ms", "200ms"};
334
335 static const struct soc_enum ng_delay_enum =
336 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
337 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
338
339 static const char * const cs42l52_ng_type_text[] = {
340 "Apply Specific", "Apply All"
341 };
342
343 static const struct soc_enum ng_type_enum =
344 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
345 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
346
347 static const char * const left_swap_text[] = {
348 "Left", "LR 2", "Right"};
349
350 static const char * const right_swap_text[] = {
351 "Right", "LR 2", "Left"};
352
353 static const unsigned int swap_values[] = { 0, 1, 3 };
354
355 static const struct soc_enum adca_swap_enum =
356 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1,
357 ARRAY_SIZE(left_swap_text),
358 left_swap_text,
359 swap_values);
360
361 static const struct snd_kcontrol_new adca_mixer =
362 SOC_DAPM_ENUM("Route", adca_swap_enum);
363
364 static const struct soc_enum pcma_swap_enum =
365 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1,
366 ARRAY_SIZE(left_swap_text),
367 left_swap_text,
368 swap_values);
369
370 static const struct snd_kcontrol_new pcma_mixer =
371 SOC_DAPM_ENUM("Route", pcma_swap_enum);
372
373 static const struct soc_enum adcb_swap_enum =
374 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1,
375 ARRAY_SIZE(right_swap_text),
376 right_swap_text,
377 swap_values);
378
379 static const struct snd_kcontrol_new adcb_mixer =
380 SOC_DAPM_ENUM("Route", adcb_swap_enum);
381
382 static const struct soc_enum pcmb_swap_enum =
383 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1,
384 ARRAY_SIZE(right_swap_text),
385 right_swap_text,
386 swap_values);
387
388 static const struct snd_kcontrol_new pcmb_mixer =
389 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
390
391
392 static const struct snd_kcontrol_new passthrul_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
394
395 static const struct snd_kcontrol_new passthrur_ctl =
396 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
397
398 static const struct snd_kcontrol_new spkl_ctl =
399 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
400
401 static const struct snd_kcontrol_new spkr_ctl =
402 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
403
404 static const struct snd_kcontrol_new hpl_ctl =
405 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
406
407 static const struct snd_kcontrol_new hpr_ctl =
408 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
409
410 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
411
412 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
413 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
414
415 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
416 CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
417
418 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
419
420 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
421 CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
422
423 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
424 CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
425
426 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
427
428 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
429 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
430
431 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
432
433 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
434 CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
435 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
436 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
437 6, 0x7f, 0x19, ipd_tlv),
438
439 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
440
441 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
442 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
443
444 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
445 CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
446
447 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
448 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
449 0, 0x7f, 0x19, mix_tlv),
450 SOC_DOUBLE_R("PCM Mixer Switch",
451 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
452
453 SOC_ENUM("Beep Config", beep_config_enum),
454 SOC_ENUM("Beep Pitch", beep_pitch_enum),
455 SOC_ENUM("Beep on Time", beep_ontime_enum),
456 SOC_ENUM("Beep off Time", beep_offtime_enum),
457 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
458 0, 0x07, 0x1f, beep_tlv),
459 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
460 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
461 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
462
463 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
464 SOC_SINGLE_TLV("Treble Gain Volume",
465 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
466 SOC_SINGLE_TLV("Bass Gain Volume",
467 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
468
469 /* Limiter */
470 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
471 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
472 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
473 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
474 SOC_SINGLE_TLV("Limiter Release Rate Volume",
475 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
476 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
477 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
478
479 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
480 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
481 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
482
483 /* ALC */
484 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
485 0, 63, 0, limiter_tlv),
486 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
487 0, 63, 0, limiter_tlv),
488 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
489 5, 7, 0, limiter_tlv),
490 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
491 2, 7, 0, limiter_tlv),
492
493 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
494 CS42L52_PGAB_CTL, 7, 1, 1),
495 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
496 CS42L52_PGAB_CTL, 6, 1, 1),
497 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
498
499 /* Noise gate */
500 SOC_ENUM("NG Type Switch", ng_type_enum),
501 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
502 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
503 SOC_ENUM("NG Threshold", ng_threshold_enum),
504 SOC_ENUM("NG Delay", ng_delay_enum),
505
506 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
507
508 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
509 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
510 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
511 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
512 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
513
514 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
515 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
516 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
517
518 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
519 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
520 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
521 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
522
523 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
524 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
525
526 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
527 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
528
529 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
530 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
531
532 };
533
534 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
535
536 SND_SOC_DAPM_INPUT("AIN1L"),
537 SND_SOC_DAPM_INPUT("AIN1R"),
538 SND_SOC_DAPM_INPUT("AIN2L"),
539 SND_SOC_DAPM_INPUT("AIN2R"),
540 SND_SOC_DAPM_INPUT("AIN3L"),
541 SND_SOC_DAPM_INPUT("AIN3R"),
542 SND_SOC_DAPM_INPUT("AIN4L"),
543 SND_SOC_DAPM_INPUT("AIN4R"),
544 SND_SOC_DAPM_INPUT("MICA"),
545 SND_SOC_DAPM_INPUT("MICB"),
546 SND_SOC_DAPM_SIGGEN("Beep"),
547
548 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
549 SND_SOC_NOPM, 0, 0),
550 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
551 SND_SOC_NOPM, 0, 0),
552
553 SND_SOC_DAPM_MUX("MICA Mux", SND_SOC_NOPM, 0, 0, &mica_mux),
554 SND_SOC_DAPM_MUX("MICB Mux", SND_SOC_NOPM, 0, 0, &micb_mux),
555
556 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
557 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
558 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
559 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
560
561 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
562 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
563
564 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
565 0, 0, &adca_mixer),
566 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
567 0, 0, &adcb_mixer),
568
569 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
570 0, 0, &digital_output_mux),
571
572 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
573 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
574
575 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
576 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
577
578 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
579 SND_SOC_NOPM, 0, 0),
580 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
581 SND_SOC_NOPM, 0, 0),
582
583 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
584 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
585
586 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
587 6, 0, &passthrul_ctl),
588 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
589 7, 0, &passthrur_ctl),
590
591 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
592 0, 0, &pcma_mixer),
593 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
594 0, 0, &pcmb_mixer),
595
596 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
597 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
598
599 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
600 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
601
602 SND_SOC_DAPM_OUTPUT("HPOUTA"),
603 SND_SOC_DAPM_OUTPUT("HPOUTB"),
604 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
605 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
606
607 };
608
609 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
610
611 {"Capture", NULL, "AIFOUTL"},
612 {"Capture", NULL, "AIFOUTL"},
613
614 {"AIFOUTL", NULL, "Output Mux"},
615 {"AIFOUTR", NULL, "Output Mux"},
616
617 {"Output Mux", "ADC", "ADC Left"},
618 {"Output Mux", "ADC", "ADC Right"},
619
620 {"ADC Left", NULL, "Charge Pump"},
621 {"ADC Right", NULL, "Charge Pump"},
622
623 {"Charge Pump", NULL, "ADC Left Mux"},
624 {"Charge Pump", NULL, "ADC Right Mux"},
625
626 {"ADC Left Mux", "Input1A", "AIN1L"},
627 {"ADC Right Mux", "Input1B", "AIN1R"},
628 {"ADC Left Mux", "Input2A", "AIN2L"},
629 {"ADC Right Mux", "Input2B", "AIN2R"},
630 {"ADC Left Mux", "Input3A", "AIN3L"},
631 {"ADC Right Mux", "Input3B", "AIN3R"},
632 {"ADC Left Mux", "Input4A", "AIN4L"},
633 {"ADC Right Mux", "Input4B", "AIN4R"},
634 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
635 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
636
637 {"PGA Left", "Switch", "AIN1L"},
638 {"PGA Right", "Switch", "AIN1R"},
639 {"PGA Left", "Switch", "AIN2L"},
640 {"PGA Right", "Switch", "AIN2R"},
641 {"PGA Left", "Switch", "AIN3L"},
642 {"PGA Right", "Switch", "AIN3R"},
643 {"PGA Left", "Switch", "AIN4L"},
644 {"PGA Right", "Switch", "AIN4R"},
645
646 {"PGA Left", "Switch", "PGA MICA"},
647 {"PGA MICA", NULL, "MICA"},
648
649 {"PGA Right", "Switch", "PGA MICB"},
650 {"PGA MICB", NULL, "MICB"},
651
652 {"HPOUTA", NULL, "HP Left Amp"},
653 {"HPOUTB", NULL, "HP Right Amp"},
654 {"HP Left Amp", NULL, "Bypass Left"},
655 {"HP Right Amp", NULL, "Bypass Right"},
656 {"Bypass Left", "Switch", "PGA Left"},
657 {"Bypass Right", "Switch", "PGA Right"},
658 {"HP Left Amp", "Switch", "DAC Left"},
659 {"HP Right Amp", "Switch", "DAC Right"},
660
661 {"SPKOUTA", NULL, "SPK Left Amp"},
662 {"SPKOUTB", NULL, "SPK Right Amp"},
663
664 {"SPK Left Amp", NULL, "Beep"},
665 {"SPK Right Amp", NULL, "Beep"},
666 {"SPK Left Amp", "Switch", "Playback"},
667 {"SPK Right Amp", "Switch", "Playback"},
668
669 {"DAC Left", NULL, "Beep"},
670 {"DAC Right", NULL, "Beep"},
671 {"DAC Left", NULL, "Playback"},
672 {"DAC Right", NULL, "Playback"},
673
674 {"Output Mux", "DSP", "Playback"},
675 {"Output Mux", "DSP", "Playback"},
676
677 {"AIFINL", NULL, "Playback"},
678 {"AIFINR", NULL, "Playback"},
679
680 };
681
682 struct cs42l52_clk_para {
683 u32 mclk;
684 u32 rate;
685 u8 speed;
686 u8 group;
687 u8 videoclk;
688 u8 ratio;
689 u8 mclkdiv2;
690 };
691
692 static const struct cs42l52_clk_para clk_map_table[] = {
693 /*8k*/
694 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
695 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
696 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
697 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
698 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
699
700 /*11.025k*/
701 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
702 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
703
704 /*16k*/
705 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
706 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
707 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
708 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
709 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
710
711 /*22.05k*/
712 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
713 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
714
715 /* 32k */
716 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
717 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
718 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
719 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
720 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
721
722 /* 44.1k */
723 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
724 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
725
726 /* 48k */
727 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
728 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
729 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
730 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
731 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
732
733 /* 88.2k */
734 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
735 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
736
737 /* 96k */
738 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
739 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
740 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
741 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
742 };
743
744 static int cs42l52_get_clk(int mclk, int rate)
745 {
746 int i, ret = -EINVAL;
747 u_int mclk1, mclk2 = 0;
748
749 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
750 if (clk_map_table[i].rate == rate) {
751 mclk1 = clk_map_table[i].mclk;
752 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
753 mclk2 = mclk1;
754 ret = i;
755 }
756 }
757 }
758 return ret;
759 }
760
761 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
762 int clk_id, unsigned int freq, int dir)
763 {
764 struct snd_soc_codec *codec = codec_dai->codec;
765 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
766
767 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
768 cs42l52->sysclk = freq;
769 } else {
770 dev_err(codec->dev, "Invalid freq parameter\n");
771 return -EINVAL;
772 }
773 return 0;
774 }
775
776 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
777 {
778 struct snd_soc_codec *codec = codec_dai->codec;
779 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
780 u8 iface = 0;
781
782 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
783 case SND_SOC_DAIFMT_CBM_CFM:
784 iface = CS42L52_IFACE_CTL1_MASTER;
785 break;
786 case SND_SOC_DAIFMT_CBS_CFS:
787 iface = CS42L52_IFACE_CTL1_SLAVE;
788 break;
789 default:
790 return -EINVAL;
791 }
792
793 /* interface format */
794 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
795 case SND_SOC_DAIFMT_I2S:
796 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
797 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
798 break;
799 case SND_SOC_DAIFMT_RIGHT_J:
800 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
801 break;
802 case SND_SOC_DAIFMT_LEFT_J:
803 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
804 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
805 break;
806 case SND_SOC_DAIFMT_DSP_A:
807 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
808 break;
809 case SND_SOC_DAIFMT_DSP_B:
810 break;
811 default:
812 return -EINVAL;
813 }
814
815 /* clock inversion */
816 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
817 case SND_SOC_DAIFMT_NB_NF:
818 break;
819 case SND_SOC_DAIFMT_IB_IF:
820 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
821 break;
822 case SND_SOC_DAIFMT_IB_NF:
823 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
824 break;
825 case SND_SOC_DAIFMT_NB_IF:
826 break;
827 default:
828 return -EINVAL;
829 }
830 cs42l52->config.format = iface;
831 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
832
833 return 0;
834 }
835
836 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
837 {
838 struct snd_soc_codec *codec = dai->codec;
839
840 if (mute)
841 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
842 CS42L52_PB_CTL1_MUTE_MASK,
843 CS42L52_PB_CTL1_MUTE);
844 else
845 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
846 CS42L52_PB_CTL1_MUTE_MASK,
847 CS42L52_PB_CTL1_UNMUTE);
848
849 return 0;
850 }
851
852 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
853 struct snd_pcm_hw_params *params,
854 struct snd_soc_dai *dai)
855 {
856 struct snd_soc_codec *codec = dai->codec;
857 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
858 u32 clk = 0;
859 int index;
860
861 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
862 if (index >= 0) {
863 cs42l52->sysclk = clk_map_table[index].mclk;
864
865 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
866 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
867 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
868 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
869 clk_map_table[index].mclkdiv2;
870
871 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
872 } else {
873 dev_err(codec->dev, "can't get correct mclk\n");
874 return -EINVAL;
875 }
876
877 return 0;
878 }
879
880 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
881 enum snd_soc_bias_level level)
882 {
883 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
884
885 switch (level) {
886 case SND_SOC_BIAS_ON:
887 break;
888 case SND_SOC_BIAS_PREPARE:
889 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
890 CS42L52_PWRCTL1_PDN_CODEC, 0);
891 break;
892 case SND_SOC_BIAS_STANDBY:
893 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
894 regcache_cache_only(cs42l52->regmap, false);
895 regcache_sync(cs42l52->regmap);
896 }
897 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
898 break;
899 case SND_SOC_BIAS_OFF:
900 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
901 regcache_cache_only(cs42l52->regmap, true);
902 break;
903 }
904 codec->dapm.bias_level = level;
905
906 return 0;
907 }
908
909 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
910
911 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
912 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
913 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
914 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
915
916 static struct snd_soc_dai_ops cs42l52_ops = {
917 .hw_params = cs42l52_pcm_hw_params,
918 .digital_mute = cs42l52_digital_mute,
919 .set_fmt = cs42l52_set_fmt,
920 .set_sysclk = cs42l52_set_sysclk,
921 };
922
923 static struct snd_soc_dai_driver cs42l52_dai = {
924 .name = "cs42l52",
925 .playback = {
926 .stream_name = "Playback",
927 .channels_min = 1,
928 .channels_max = 2,
929 .rates = CS42L52_RATES,
930 .formats = CS42L52_FORMATS,
931 },
932 .capture = {
933 .stream_name = "Capture",
934 .channels_min = 1,
935 .channels_max = 2,
936 .rates = CS42L52_RATES,
937 .formats = CS42L52_FORMATS,
938 },
939 .ops = &cs42l52_ops,
940 };
941
942 static int cs42l52_suspend(struct snd_soc_codec *codec)
943 {
944 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
945
946 return 0;
947 }
948
949 static int cs42l52_resume(struct snd_soc_codec *codec)
950 {
951 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
952
953 return 0;
954 }
955
956 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
957 static int beep_rates[] = {
958 261, 522, 585, 667, 706, 774, 889, 1000,
959 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
960 };
961
962 static void cs42l52_beep_work(struct work_struct *work)
963 {
964 struct cs42l52_private *cs42l52 =
965 container_of(work, struct cs42l52_private, beep_work);
966 struct snd_soc_codec *codec = cs42l52->codec;
967 struct snd_soc_dapm_context *dapm = &codec->dapm;
968 int i;
969 int val = 0;
970 int best = 0;
971
972 if (cs42l52->beep_rate) {
973 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
974 if (abs(cs42l52->beep_rate - beep_rates[i]) <
975 abs(cs42l52->beep_rate - beep_rates[best]))
976 best = i;
977 }
978
979 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
980 beep_rates[best], cs42l52->beep_rate);
981
982 val = (best << CS42L52_BEEP_RATE_SHIFT);
983
984 snd_soc_dapm_enable_pin(dapm, "Beep");
985 } else {
986 dev_dbg(codec->dev, "Disabling beep\n");
987 snd_soc_dapm_disable_pin(dapm, "Beep");
988 }
989
990 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
991 CS42L52_BEEP_RATE_MASK, val);
992
993 snd_soc_dapm_sync(dapm);
994 }
995
996 /* For usability define a way of injecting beep events for the device -
997 * many systems will not have a keyboard.
998 */
999 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
1000 unsigned int code, int hz)
1001 {
1002 struct snd_soc_codec *codec = input_get_drvdata(dev);
1003 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1004
1005 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1006
1007 switch (code) {
1008 case SND_BELL:
1009 if (hz)
1010 hz = 261;
1011 case SND_TONE:
1012 break;
1013 default:
1014 return -1;
1015 }
1016
1017 /* Kick the beep from a workqueue */
1018 cs42l52->beep_rate = hz;
1019 schedule_work(&cs42l52->beep_work);
1020 return 0;
1021 }
1022
1023 static ssize_t cs42l52_beep_set(struct device *dev,
1024 struct device_attribute *attr,
1025 const char *buf, size_t count)
1026 {
1027 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1028 long int time;
1029 int ret;
1030
1031 ret = kstrtol(buf, 10, &time);
1032 if (ret != 0)
1033 return ret;
1034
1035 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1036
1037 return count;
1038 }
1039
1040 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1041
1042 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1043 {
1044 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1045 int ret;
1046
1047 cs42l52->beep = devm_input_allocate_device(codec->dev);
1048 if (!cs42l52->beep) {
1049 dev_err(codec->dev, "Failed to allocate beep device\n");
1050 return;
1051 }
1052
1053 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1054 cs42l52->beep_rate = 0;
1055
1056 cs42l52->beep->name = "CS42L52 Beep Generator";
1057 cs42l52->beep->phys = dev_name(codec->dev);
1058 cs42l52->beep->id.bustype = BUS_I2C;
1059
1060 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1061 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1062 cs42l52->beep->event = cs42l52_beep_event;
1063 cs42l52->beep->dev.parent = codec->dev;
1064 input_set_drvdata(cs42l52->beep, codec);
1065
1066 ret = input_register_device(cs42l52->beep);
1067 if (ret != 0) {
1068 cs42l52->beep = NULL;
1069 dev_err(codec->dev, "Failed to register beep device\n");
1070 }
1071
1072 ret = device_create_file(codec->dev, &dev_attr_beep);
1073 if (ret != 0) {
1074 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1075 ret);
1076 }
1077 }
1078
1079 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1080 {
1081 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1082
1083 device_remove_file(codec->dev, &dev_attr_beep);
1084 cancel_work_sync(&cs42l52->beep_work);
1085 cs42l52->beep = NULL;
1086
1087 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1088 CS42L52_BEEP_EN_MASK, 0);
1089 }
1090 #else
1091 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1092 {
1093 }
1094
1095 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1096 {
1097 }
1098 #endif
1099
1100 static int cs42l52_probe(struct snd_soc_codec *codec)
1101 {
1102 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1103 int ret;
1104
1105 codec->control_data = cs42l52->regmap;
1106 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1107 if (ret < 0) {
1108 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1109 return ret;
1110 }
1111 regcache_cache_only(cs42l52->regmap, true);
1112
1113 cs42l52_init_beep(codec);
1114
1115 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1116
1117 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1118 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1119
1120 return ret;
1121 }
1122
1123 static int cs42l52_remove(struct snd_soc_codec *codec)
1124 {
1125 cs42l52_free_beep(codec);
1126 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1127
1128 return 0;
1129 }
1130
1131 static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1132 .probe = cs42l52_probe,
1133 .remove = cs42l52_remove,
1134 .suspend = cs42l52_suspend,
1135 .resume = cs42l52_resume,
1136 .set_bias_level = cs42l52_set_bias_level,
1137
1138 .dapm_widgets = cs42l52_dapm_widgets,
1139 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1140 .dapm_routes = cs42l52_audio_map,
1141 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1142
1143 .controls = cs42l52_snd_controls,
1144 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1145 };
1146
1147 /* Current and threshold powerup sequence Pg37 */
1148 static const struct reg_default cs42l52_threshold_patch[] = {
1149
1150 { 0x00, 0x99 },
1151 { 0x3E, 0xBA },
1152 { 0x47, 0x80 },
1153 { 0x32, 0xBB },
1154 { 0x32, 0x3B },
1155 { 0x00, 0x00 },
1156
1157 };
1158
1159 static struct regmap_config cs42l52_regmap = {
1160 .reg_bits = 8,
1161 .val_bits = 8,
1162
1163 .max_register = CS42L52_MAX_REGISTER,
1164 .reg_defaults = cs42l52_reg_defaults,
1165 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1166 .readable_reg = cs42l52_readable_register,
1167 .volatile_reg = cs42l52_volatile_register,
1168 .cache_type = REGCACHE_RBTREE,
1169 };
1170
1171 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1172 const struct i2c_device_id *id)
1173 {
1174 struct cs42l52_private *cs42l52;
1175 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1176 int ret;
1177 unsigned int devid = 0;
1178 unsigned int reg;
1179
1180 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1181 GFP_KERNEL);
1182 if (cs42l52 == NULL)
1183 return -ENOMEM;
1184 cs42l52->dev = &i2c_client->dev;
1185
1186 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1187 if (IS_ERR(cs42l52->regmap)) {
1188 ret = PTR_ERR(cs42l52->regmap);
1189 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1190 return ret;
1191 }
1192
1193 if (pdata)
1194 cs42l52->pdata = *pdata;
1195
1196 if (cs42l52->pdata.reset_gpio) {
1197 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1198 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1199 if (ret < 0) {
1200 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1201 cs42l52->pdata.reset_gpio, ret);
1202 return ret;
1203 }
1204 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1205 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1206 }
1207
1208 i2c_set_clientdata(i2c_client, cs42l52);
1209
1210 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1211 ARRAY_SIZE(cs42l52_threshold_patch));
1212 if (ret != 0)
1213 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1214 ret);
1215
1216 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1217 devid = reg & CS42L52_CHIP_ID_MASK;
1218 if (devid != CS42L52_CHIP_ID) {
1219 ret = -ENODEV;
1220 dev_err(&i2c_client->dev,
1221 "CS42L52 Device ID (%X). Expected %X\n",
1222 devid, CS42L52_CHIP_ID);
1223 return ret;
1224 }
1225
1226 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1227 reg & 0xFF);
1228
1229 /* Set Platform Data */
1230 if (cs42l52->pdata.mica_cfg)
1231 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1232 CS42L52_MIC_CTL_TYPE_MASK,
1233 cs42l52->pdata.mica_cfg <<
1234 CS42L52_MIC_CTL_TYPE_SHIFT);
1235
1236 if (cs42l52->pdata.micb_cfg)
1237 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1238 CS42L52_MIC_CTL_TYPE_MASK,
1239 cs42l52->pdata.micb_cfg <<
1240 CS42L52_MIC_CTL_TYPE_SHIFT);
1241
1242 if (cs42l52->pdata.mica_sel)
1243 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1244 CS42L52_MIC_CTL_MIC_SEL_MASK,
1245 cs42l52->pdata.mica_sel <<
1246 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1247 if (cs42l52->pdata.micb_sel)
1248 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1249 CS42L52_MIC_CTL_MIC_SEL_MASK,
1250 cs42l52->pdata.micb_sel <<
1251 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1252
1253 if (cs42l52->pdata.chgfreq)
1254 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1255 CS42L52_CHARGE_PUMP_MASK,
1256 cs42l52->pdata.chgfreq <<
1257 CS42L52_CHARGE_PUMP_SHIFT);
1258
1259 if (cs42l52->pdata.micbias_lvl)
1260 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1261 CS42L52_IFACE_CTL2_BIAS_LVL,
1262 cs42l52->pdata.micbias_lvl);
1263
1264 ret = snd_soc_register_codec(&i2c_client->dev,
1265 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1266 if (ret < 0)
1267 return ret;
1268 return 0;
1269 }
1270
1271 static int cs42l52_i2c_remove(struct i2c_client *client)
1272 {
1273 snd_soc_unregister_codec(&client->dev);
1274 return 0;
1275 }
1276
1277 static const struct i2c_device_id cs42l52_id[] = {
1278 { "cs42l52", 0 },
1279 { }
1280 };
1281 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1282
1283 static struct i2c_driver cs42l52_i2c_driver = {
1284 .driver = {
1285 .name = "cs42l52",
1286 .owner = THIS_MODULE,
1287 },
1288 .id_table = cs42l52_id,
1289 .probe = cs42l52_i2c_probe,
1290 .remove = cs42l52_i2c_remove,
1291 };
1292
1293 module_i2c_driver(cs42l52_i2c_driver);
1294
1295 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1296 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1297 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1298 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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