2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
4 * Copyright 2012 CirrusLogic, Inc.
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/of_gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
43 struct cs42l52_private
{
44 struct regmap
*regmap
;
45 struct snd_soc_codec
*codec
;
47 struct sp_config config
;
48 struct cs42l52_platform_data pdata
;
53 struct input_dev
*beep
;
54 struct work_struct beep_work
;
58 static const struct reg_default cs42l52_reg_defaults
[] = {
59 { CS42L52_PWRCTL1
, 0x9F }, /* r02 PWRCTL 1 */
60 { CS42L52_PWRCTL2
, 0x07 }, /* r03 PWRCTL 2 */
61 { CS42L52_PWRCTL3
, 0xFF }, /* r04 PWRCTL 3 */
62 { CS42L52_CLK_CTL
, 0xA0 }, /* r05 Clocking Ctl */
63 { CS42L52_IFACE_CTL1
, 0x00 }, /* r06 Interface Ctl 1 */
64 { CS42L52_ADC_PGA_A
, 0x80 }, /* r08 Input A Select */
65 { CS42L52_ADC_PGA_B
, 0x80 }, /* r09 Input B Select */
66 { CS42L52_ANALOG_HPF_CTL
, 0xA5 }, /* r0A Analog HPF Ctl */
67 { CS42L52_ADC_HPF_FREQ
, 0x00 }, /* r0B ADC HPF Corner Freq */
68 { CS42L52_ADC_MISC_CTL
, 0x00 }, /* r0C Misc. ADC Ctl */
69 { CS42L52_PB_CTL1
, 0x60 }, /* r0D Playback Ctl 1 */
70 { CS42L52_MISC_CTL
, 0x02 }, /* r0E Misc. Ctl */
71 { CS42L52_PB_CTL2
, 0x00 }, /* r0F Playback Ctl 2 */
72 { CS42L52_MICA_CTL
, 0x00 }, /* r10 MICA Amp Ctl */
73 { CS42L52_MICB_CTL
, 0x00 }, /* r11 MICB Amp Ctl */
74 { CS42L52_PGAA_CTL
, 0x00 }, /* r12 PGAA Vol, Misc. */
75 { CS42L52_PGAB_CTL
, 0x00 }, /* r13 PGAB Vol, Misc. */
76 { CS42L52_PASSTHRUA_VOL
, 0x00 }, /* r14 Bypass A Vol */
77 { CS42L52_PASSTHRUB_VOL
, 0x00 }, /* r15 Bypass B Vol */
78 { CS42L52_ADCA_VOL
, 0x00 }, /* r16 ADCA Volume */
79 { CS42L52_ADCB_VOL
, 0x00 }, /* r17 ADCB Volume */
80 { CS42L52_ADCA_MIXER_VOL
, 0x80 }, /* r18 ADCA Mixer Volume */
81 { CS42L52_ADCB_MIXER_VOL
, 0x80 }, /* r19 ADCB Mixer Volume */
82 { CS42L52_PCMA_MIXER_VOL
, 0x00 }, /* r1A PCMA Mixer Volume */
83 { CS42L52_PCMB_MIXER_VOL
, 0x00 }, /* r1B PCMB Mixer Volume */
84 { CS42L52_BEEP_FREQ
, 0x00 }, /* r1C Beep Freq on Time */
85 { CS42L52_BEEP_VOL
, 0x00 }, /* r1D Beep Volume off Time */
86 { CS42L52_BEEP_TONE_CTL
, 0x00 }, /* r1E Beep Tone Cfg. */
87 { CS42L52_TONE_CTL
, 0x00 }, /* r1F Tone Ctl */
88 { CS42L52_MASTERA_VOL
, 0x00 }, /* r20 Master A Volume */
89 { CS42L52_MASTERB_VOL
, 0x00 }, /* r21 Master B Volume */
90 { CS42L52_HPA_VOL
, 0x00 }, /* r22 Headphone A Volume */
91 { CS42L52_HPB_VOL
, 0x00 }, /* r23 Headphone B Volume */
92 { CS42L52_SPKA_VOL
, 0x00 }, /* r24 Speaker A Volume */
93 { CS42L52_SPKB_VOL
, 0x00 }, /* r25 Speaker B Volume */
94 { CS42L52_ADC_PCM_MIXER
, 0x00 }, /* r26 Channel Mixer and Swap */
95 { CS42L52_LIMITER_CTL1
, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
96 { CS42L52_LIMITER_CTL2
, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
97 { CS42L52_LIMITER_AT_RATE
, 0xC0 }, /* r29 Limiter Attack Rate */
98 { CS42L52_ALC_CTL
, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
99 { CS42L52_ALC_RATE
, 0x3F }, /* r2B ALC Release Rate */
100 { CS42L52_ALC_THRESHOLD
, 0x3f }, /* r2C ALC Thresholds */
101 { CS42L52_NOISE_GATE_CTL
, 0x00 }, /* r2D Noise Gate Ctl */
102 { CS42L52_CLK_STATUS
, 0x00 }, /* r2E Overflow and Clock Status */
103 { CS42L52_BATT_COMPEN
, 0x00 }, /* r2F battery Compensation */
104 { CS42L52_BATT_LEVEL
, 0x00 }, /* r30 VP Battery Level */
105 { CS42L52_SPK_STATUS
, 0x00 }, /* r31 Speaker Status */
106 { CS42L52_TEM_CTL
, 0x3B }, /* r32 Temp Ctl */
107 { CS42L52_THE_FOLDBACK
, 0x00 }, /* r33 Foldback */
110 static bool cs42l52_readable_register(struct device
*dev
, unsigned int reg
)
114 case CS42L52_PWRCTL1
:
115 case CS42L52_PWRCTL2
:
116 case CS42L52_PWRCTL3
:
117 case CS42L52_CLK_CTL
:
118 case CS42L52_IFACE_CTL1
:
119 case CS42L52_IFACE_CTL2
:
120 case CS42L52_ADC_PGA_A
:
121 case CS42L52_ADC_PGA_B
:
122 case CS42L52_ANALOG_HPF_CTL
:
123 case CS42L52_ADC_HPF_FREQ
:
124 case CS42L52_ADC_MISC_CTL
:
125 case CS42L52_PB_CTL1
:
126 case CS42L52_MISC_CTL
:
127 case CS42L52_PB_CTL2
:
128 case CS42L52_MICA_CTL
:
129 case CS42L52_MICB_CTL
:
130 case CS42L52_PGAA_CTL
:
131 case CS42L52_PGAB_CTL
:
132 case CS42L52_PASSTHRUA_VOL
:
133 case CS42L52_PASSTHRUB_VOL
:
134 case CS42L52_ADCA_VOL
:
135 case CS42L52_ADCB_VOL
:
136 case CS42L52_ADCA_MIXER_VOL
:
137 case CS42L52_ADCB_MIXER_VOL
:
138 case CS42L52_PCMA_MIXER_VOL
:
139 case CS42L52_PCMB_MIXER_VOL
:
140 case CS42L52_BEEP_FREQ
:
141 case CS42L52_BEEP_VOL
:
142 case CS42L52_BEEP_TONE_CTL
:
143 case CS42L52_TONE_CTL
:
144 case CS42L52_MASTERA_VOL
:
145 case CS42L52_MASTERB_VOL
:
146 case CS42L52_HPA_VOL
:
147 case CS42L52_HPB_VOL
:
148 case CS42L52_SPKA_VOL
:
149 case CS42L52_SPKB_VOL
:
150 case CS42L52_ADC_PCM_MIXER
:
151 case CS42L52_LIMITER_CTL1
:
152 case CS42L52_LIMITER_CTL2
:
153 case CS42L52_LIMITER_AT_RATE
:
154 case CS42L52_ALC_CTL
:
155 case CS42L52_ALC_RATE
:
156 case CS42L52_ALC_THRESHOLD
:
157 case CS42L52_NOISE_GATE_CTL
:
158 case CS42L52_CLK_STATUS
:
159 case CS42L52_BATT_COMPEN
:
160 case CS42L52_BATT_LEVEL
:
161 case CS42L52_SPK_STATUS
:
162 case CS42L52_TEM_CTL
:
163 case CS42L52_THE_FOLDBACK
:
164 case CS42L52_CHARGE_PUMP
:
171 static bool cs42l52_volatile_register(struct device
*dev
, unsigned int reg
)
174 case CS42L52_IFACE_CTL2
:
175 case CS42L52_CLK_STATUS
:
176 case CS42L52_BATT_LEVEL
:
177 case CS42L52_SPK_STATUS
:
178 case CS42L52_CHARGE_PUMP
:
185 static DECLARE_TLV_DB_SCALE(hl_tlv
, -10200, 50, 0);
187 static DECLARE_TLV_DB_SCALE(hpd_tlv
, -9600, 50, 1);
189 static DECLARE_TLV_DB_SCALE(ipd_tlv
, -9600, 100, 0);
191 static DECLARE_TLV_DB_SCALE(mic_tlv
, 1600, 100, 0);
193 static DECLARE_TLV_DB_SCALE(pga_tlv
, -600, 50, 0);
195 static DECLARE_TLV_DB_SCALE(mix_tlv
, -50, 50, 0);
197 static DECLARE_TLV_DB_SCALE(beep_tlv
, -56, 200, 0);
199 static const DECLARE_TLV_DB_RANGE(limiter_tlv
,
200 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
201 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
204 static const char * const cs42l52_adca_text
[] = {
205 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
207 static const char * const cs42l52_adcb_text
[] = {
208 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
210 static SOC_ENUM_SINGLE_DECL(adca_enum
,
211 CS42L52_ADC_PGA_A
, 5, cs42l52_adca_text
);
213 static SOC_ENUM_SINGLE_DECL(adcb_enum
,
214 CS42L52_ADC_PGA_B
, 5, cs42l52_adcb_text
);
216 static const struct snd_kcontrol_new adca_mux
=
217 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum
);
219 static const struct snd_kcontrol_new adcb_mux
=
220 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum
);
222 static const char * const mic_bias_level_text
[] = {
223 "0.5 +VA", "0.6 +VA", "0.7 +VA",
224 "0.8 +VA", "0.83 +VA", "0.91 +VA"
227 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum
,
228 CS42L52_IFACE_CTL2
, 0, mic_bias_level_text
);
230 static const char * const cs42l52_mic_text
[] = { "MIC1", "MIC2" };
232 static SOC_ENUM_SINGLE_DECL(mica_enum
,
233 CS42L52_MICA_CTL
, 5, cs42l52_mic_text
);
235 static SOC_ENUM_SINGLE_DECL(micb_enum
,
236 CS42L52_MICB_CTL
, 5, cs42l52_mic_text
);
238 static const char * const digital_output_mux_text
[] = {"ADC", "DSP"};
240 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum
,
241 CS42L52_ADC_MISC_CTL
, 6,
242 digital_output_mux_text
);
244 static const struct snd_kcontrol_new digital_output_mux
=
245 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum
);
247 static const char * const hp_gain_num_text
[] = {
248 "0.3959", "0.4571", "0.5111", "0.6047",
249 "0.7099", "0.8399", "1.000", "1.1430"
252 static SOC_ENUM_SINGLE_DECL(hp_gain_enum
,
256 static const char * const beep_pitch_text
[] = {
257 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
258 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
261 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum
,
262 CS42L52_BEEP_FREQ
, 4,
265 static const char * const beep_ontime_text
[] = {
266 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
267 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
268 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
271 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum
,
272 CS42L52_BEEP_FREQ
, 0,
275 static const char * const beep_offtime_text
[] = {
276 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
277 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
280 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum
,
284 static const char * const beep_config_text
[] = {
285 "Off", "Single", "Multiple", "Continuous"
288 static SOC_ENUM_SINGLE_DECL(beep_config_enum
,
289 CS42L52_BEEP_TONE_CTL
, 6,
292 static const char * const beep_bass_text
[] = {
293 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
296 static SOC_ENUM_SINGLE_DECL(beep_bass_enum
,
297 CS42L52_BEEP_TONE_CTL
, 1,
300 static const char * const beep_treble_text
[] = {
301 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
304 static SOC_ENUM_SINGLE_DECL(beep_treble_enum
,
305 CS42L52_BEEP_TONE_CTL
, 3,
308 static const char * const ng_threshold_text
[] = {
309 "-34dB", "-37dB", "-40dB", "-43dB",
310 "-46dB", "-52dB", "-58dB", "-64dB"
313 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum
,
314 CS42L52_NOISE_GATE_CTL
, 2,
317 static const char * const cs42l52_ng_delay_text
[] = {
318 "50ms", "100ms", "150ms", "200ms"};
320 static SOC_ENUM_SINGLE_DECL(ng_delay_enum
,
321 CS42L52_NOISE_GATE_CTL
, 0,
322 cs42l52_ng_delay_text
);
324 static const char * const cs42l52_ng_type_text
[] = {
325 "Apply Specific", "Apply All"
328 static SOC_ENUM_SINGLE_DECL(ng_type_enum
,
329 CS42L52_NOISE_GATE_CTL
, 6,
330 cs42l52_ng_type_text
);
332 static const char * const left_swap_text
[] = {
333 "Left", "LR 2", "Right"};
335 static const char * const right_swap_text
[] = {
336 "Right", "LR 2", "Left"};
338 static const unsigned int swap_values
[] = { 0, 1, 3 };
340 static const struct soc_enum adca_swap_enum
=
341 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER
, 2, 3,
342 ARRAY_SIZE(left_swap_text
),
346 static const struct snd_kcontrol_new adca_mixer
=
347 SOC_DAPM_ENUM("Route", adca_swap_enum
);
349 static const struct soc_enum pcma_swap_enum
=
350 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER
, 6, 3,
351 ARRAY_SIZE(left_swap_text
),
355 static const struct snd_kcontrol_new pcma_mixer
=
356 SOC_DAPM_ENUM("Route", pcma_swap_enum
);
358 static const struct soc_enum adcb_swap_enum
=
359 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER
, 0, 3,
360 ARRAY_SIZE(right_swap_text
),
364 static const struct snd_kcontrol_new adcb_mixer
=
365 SOC_DAPM_ENUM("Route", adcb_swap_enum
);
367 static const struct soc_enum pcmb_swap_enum
=
368 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER
, 4, 3,
369 ARRAY_SIZE(right_swap_text
),
373 static const struct snd_kcontrol_new pcmb_mixer
=
374 SOC_DAPM_ENUM("Route", pcmb_swap_enum
);
377 static const struct snd_kcontrol_new passthrul_ctl
=
378 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL
, 6, 1, 0);
380 static const struct snd_kcontrol_new passthrur_ctl
=
381 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL
, 7, 1, 0);
383 static const struct snd_kcontrol_new spkl_ctl
=
384 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3
, 0, 1, 1);
386 static const struct snd_kcontrol_new spkr_ctl
=
387 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3
, 2, 1, 1);
389 static const struct snd_kcontrol_new hpl_ctl
=
390 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3
, 4, 1, 1);
392 static const struct snd_kcontrol_new hpr_ctl
=
393 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3
, 6, 1, 1);
395 static const struct snd_kcontrol_new cs42l52_snd_controls
[] = {
397 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL
,
398 CS42L52_MASTERB_VOL
, 0, 0x34, 0xE4, hl_tlv
),
400 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL
,
401 CS42L52_HPB_VOL
, 0, 0x34, 0xC0, hpd_tlv
),
403 SOC_ENUM("Headphone Analog Gain", hp_gain_enum
),
405 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL
,
406 CS42L52_SPKB_VOL
, 0, 0x40, 0xC0, hl_tlv
),
408 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL
,
409 CS42L52_PASSTHRUB_VOL
, 0, 0x88, 0x90, pga_tlv
),
411 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL
, 4, 5, 1, 0),
413 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL
,
414 CS42L52_MICB_CTL
, 0, 0x10, 0, mic_tlv
),
416 SOC_ENUM("MIC Bias Level", mic_bias_level_enum
),
418 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL
,
419 CS42L52_ADCB_VOL
, 0, 0xA0, 0x78, ipd_tlv
),
420 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
421 CS42L52_ADCA_MIXER_VOL
, CS42L52_ADCB_MIXER_VOL
,
422 0, 0x19, 0x7F, ipd_tlv
),
424 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL
, 0, 1, 1, 0),
426 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL
,
427 CS42L52_ADCB_MIXER_VOL
, 7, 1, 1),
429 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL
,
430 CS42L52_PGAB_CTL
, 0, 0x28, 0x24, pga_tlv
),
432 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
433 CS42L52_PCMA_MIXER_VOL
, CS42L52_PCMB_MIXER_VOL
,
434 0, 0x19, 0x7f, mix_tlv
),
435 SOC_DOUBLE_R("PCM Mixer Switch",
436 CS42L52_PCMA_MIXER_VOL
, CS42L52_PCMB_MIXER_VOL
, 7, 1, 1),
438 SOC_ENUM("Beep Config", beep_config_enum
),
439 SOC_ENUM("Beep Pitch", beep_pitch_enum
),
440 SOC_ENUM("Beep on Time", beep_ontime_enum
),
441 SOC_ENUM("Beep off Time", beep_offtime_enum
),
442 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL
,
443 0, 0x07, 0x1f, beep_tlv
),
444 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL
, 5, 1, 1),
445 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum
),
446 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum
),
448 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL
, 0, 1, 1),
449 SOC_SINGLE_TLV("Treble Gain Volume",
450 CS42L52_TONE_CTL
, 4, 15, 1, hl_tlv
),
451 SOC_SINGLE_TLV("Bass Gain Volume",
452 CS42L52_TONE_CTL
, 0, 15, 1, hl_tlv
),
455 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
456 CS42L52_LIMITER_CTL1
, 5, 7, 0, limiter_tlv
),
457 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
458 CS42L52_LIMITER_CTL1
, 2, 7, 0, limiter_tlv
),
459 SOC_SINGLE_TLV("Limiter Release Rate Volume",
460 CS42L52_LIMITER_CTL2
, 0, 63, 0, limiter_tlv
),
461 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
462 CS42L52_LIMITER_AT_RATE
, 0, 63, 0, limiter_tlv
),
464 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1
, 1, 1, 0),
465 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1
, 0, 1, 0),
466 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2
, 7, 1, 0),
469 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL
,
470 0, 63, 0, limiter_tlv
),
471 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE
,
472 0, 63, 0, limiter_tlv
),
473 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD
,
474 5, 7, 0, limiter_tlv
),
475 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD
,
476 2, 7, 0, limiter_tlv
),
478 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL
,
479 CS42L52_PGAB_CTL
, 7, 1, 1),
480 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL
,
481 CS42L52_PGAB_CTL
, 6, 1, 1),
482 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL
, 6, 7, 1, 0),
485 SOC_ENUM("NG Type Switch", ng_type_enum
),
486 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL
, 6, 1, 0),
487 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL
, 5, 1, 1),
488 SOC_ENUM("NG Threshold", ng_threshold_enum
),
489 SOC_ENUM("NG Delay", ng_delay_enum
),
491 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL
, 5, 7, 1, 0),
493 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL
, 1, 3, 1, 1),
494 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL
, 0, 2, 1, 1),
495 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL
, 1, 1, 0),
496 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL
, 0, 1, 0),
497 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL
, 2, 1, 0),
499 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN
, 7, 1, 0),
500 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN
, 6, 1, 0),
501 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN
, 0, 0x0f, 0),
503 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A
, 0, 1, 0),
504 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B
, 0, 1, 0),
505 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A
, 1, 1, 0),
506 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B
, 1, 1, 0),
508 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A
, 2, 1, 0),
509 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B
, 2, 1, 0),
511 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A
, 3, 1, 0),
512 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B
, 3, 1, 0),
514 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A
, 4, 1, 0),
515 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B
, 4, 1, 0),
519 static const struct snd_kcontrol_new cs42l52_mica_controls
[] = {
520 SOC_ENUM("MICA Select", mica_enum
),
523 static const struct snd_kcontrol_new cs42l52_micb_controls
[] = {
524 SOC_ENUM("MICB Select", micb_enum
),
527 static int cs42l52_add_mic_controls(struct snd_soc_codec
*codec
)
529 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
530 struct cs42l52_platform_data
*pdata
= &cs42l52
->pdata
;
532 if (!pdata
->mica_diff_cfg
)
533 snd_soc_add_codec_controls(codec
, cs42l52_mica_controls
,
534 ARRAY_SIZE(cs42l52_mica_controls
));
536 if (!pdata
->micb_diff_cfg
)
537 snd_soc_add_codec_controls(codec
, cs42l52_micb_controls
,
538 ARRAY_SIZE(cs42l52_micb_controls
));
543 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets
[] = {
545 SND_SOC_DAPM_INPUT("AIN1L"),
546 SND_SOC_DAPM_INPUT("AIN1R"),
547 SND_SOC_DAPM_INPUT("AIN2L"),
548 SND_SOC_DAPM_INPUT("AIN2R"),
549 SND_SOC_DAPM_INPUT("AIN3L"),
550 SND_SOC_DAPM_INPUT("AIN3R"),
551 SND_SOC_DAPM_INPUT("AIN4L"),
552 SND_SOC_DAPM_INPUT("AIN4R"),
553 SND_SOC_DAPM_INPUT("MICA"),
554 SND_SOC_DAPM_INPUT("MICB"),
555 SND_SOC_DAPM_SIGGEN("Beep"),
557 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL
, 0,
559 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL
, 0,
562 SND_SOC_DAPM_ADC("ADC Left", NULL
, CS42L52_PWRCTL1
, 1, 1),
563 SND_SOC_DAPM_ADC("ADC Right", NULL
, CS42L52_PWRCTL1
, 2, 1),
564 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1
, 3, 1, NULL
, 0),
565 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1
, 4, 1, NULL
, 0),
567 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM
, 0, 0, &adca_mux
),
568 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM
, 0, 0, &adcb_mux
),
570 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM
,
572 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM
,
575 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM
,
576 0, 0, &digital_output_mux
),
578 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2
, 1, 1, NULL
, 0),
579 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2
, 2, 1, NULL
, 0),
581 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2
, 0, 1, NULL
, 0),
582 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1
, 7, 1, NULL
, 0),
584 SND_SOC_DAPM_AIF_IN("AIFINL", NULL
, 0,
586 SND_SOC_DAPM_AIF_IN("AIFINR", NULL
, 0,
589 SND_SOC_DAPM_DAC("DAC Left", NULL
, SND_SOC_NOPM
, 0, 0),
590 SND_SOC_DAPM_DAC("DAC Right", NULL
, SND_SOC_NOPM
, 0, 0),
592 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL
,
593 6, 0, &passthrul_ctl
),
594 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL
,
595 7, 0, &passthrur_ctl
),
597 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM
,
599 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM
,
602 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM
, 0, 0, &hpl_ctl
),
603 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM
, 0, 0, &hpr_ctl
),
605 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM
, 0, 0, &spkl_ctl
),
606 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM
, 0, 0, &spkr_ctl
),
608 SND_SOC_DAPM_OUTPUT("HPOUTA"),
609 SND_SOC_DAPM_OUTPUT("HPOUTB"),
610 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
611 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
615 static const struct snd_soc_dapm_route cs42l52_audio_map
[] = {
617 {"Capture", NULL
, "AIFOUTL"},
618 {"Capture", NULL
, "AIFOUTL"},
620 {"AIFOUTL", NULL
, "Output Mux"},
621 {"AIFOUTR", NULL
, "Output Mux"},
623 {"Output Mux", "ADC", "ADC Left"},
624 {"Output Mux", "ADC", "ADC Right"},
626 {"ADC Left", NULL
, "Charge Pump"},
627 {"ADC Right", NULL
, "Charge Pump"},
629 {"Charge Pump", NULL
, "ADC Left Mux"},
630 {"Charge Pump", NULL
, "ADC Right Mux"},
632 {"ADC Left Mux", "Input1A", "AIN1L"},
633 {"ADC Right Mux", "Input1B", "AIN1R"},
634 {"ADC Left Mux", "Input2A", "AIN2L"},
635 {"ADC Right Mux", "Input2B", "AIN2R"},
636 {"ADC Left Mux", "Input3A", "AIN3L"},
637 {"ADC Right Mux", "Input3B", "AIN3R"},
638 {"ADC Left Mux", "Input4A", "AIN4L"},
639 {"ADC Right Mux", "Input4B", "AIN4R"},
640 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
641 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
643 {"PGA Left", "Switch", "AIN1L"},
644 {"PGA Right", "Switch", "AIN1R"},
645 {"PGA Left", "Switch", "AIN2L"},
646 {"PGA Right", "Switch", "AIN2R"},
647 {"PGA Left", "Switch", "AIN3L"},
648 {"PGA Right", "Switch", "AIN3R"},
649 {"PGA Left", "Switch", "AIN4L"},
650 {"PGA Right", "Switch", "AIN4R"},
652 {"PGA Left", "Switch", "PGA MICA"},
653 {"PGA MICA", NULL
, "MICA"},
655 {"PGA Right", "Switch", "PGA MICB"},
656 {"PGA MICB", NULL
, "MICB"},
658 {"HPOUTA", NULL
, "HP Left Amp"},
659 {"HPOUTB", NULL
, "HP Right Amp"},
660 {"HP Left Amp", NULL
, "Bypass Left"},
661 {"HP Right Amp", NULL
, "Bypass Right"},
662 {"Bypass Left", "Switch", "PGA Left"},
663 {"Bypass Right", "Switch", "PGA Right"},
664 {"HP Left Amp", "Switch", "DAC Left"},
665 {"HP Right Amp", "Switch", "DAC Right"},
667 {"SPKOUTA", NULL
, "SPK Left Amp"},
668 {"SPKOUTB", NULL
, "SPK Right Amp"},
670 {"SPK Left Amp", NULL
, "Beep"},
671 {"SPK Right Amp", NULL
, "Beep"},
672 {"SPK Left Amp", "Switch", "Playback"},
673 {"SPK Right Amp", "Switch", "Playback"},
675 {"DAC Left", NULL
, "Beep"},
676 {"DAC Right", NULL
, "Beep"},
677 {"DAC Left", NULL
, "Playback"},
678 {"DAC Right", NULL
, "Playback"},
680 {"Output Mux", "DSP", "Playback"},
681 {"Output Mux", "DSP", "Playback"},
683 {"AIFINL", NULL
, "Playback"},
684 {"AIFINR", NULL
, "Playback"},
688 struct cs42l52_clk_para
{
698 static const struct cs42l52_clk_para clk_map_table
[] = {
700 {12288000, 8000, CLK_QS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
701 {18432000, 8000, CLK_QS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
702 {12000000, 8000, CLK_QS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 0},
703 {24000000, 8000, CLK_QS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 1},
704 {27000000, 8000, CLK_QS_MODE
, CLK_32K
, CLK_27M_MCLK
, CLK_R_125
, 0},
707 {11289600, 11025, CLK_QS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
708 {16934400, 11025, CLK_QS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
711 {12288000, 16000, CLK_HS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
712 {18432000, 16000, CLK_HS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
713 {12000000, 16000, CLK_HS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 0},
714 {24000000, 16000, CLK_HS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 1},
715 {27000000, 16000, CLK_HS_MODE
, CLK_32K
, CLK_27M_MCLK
, CLK_R_125
, 1},
718 {11289600, 22050, CLK_HS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
719 {16934400, 22050, CLK_HS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
722 {12288000, 32000, CLK_SS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
723 {18432000, 32000, CLK_SS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_128
, 0},
724 {12000000, 32000, CLK_SS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 0},
725 {24000000, 32000, CLK_SS_MODE
, CLK_32K
, CLK_NO_27M
, CLK_R_125
, 1},
726 {27000000, 32000, CLK_SS_MODE
, CLK_32K
, CLK_27M_MCLK
, CLK_R_125
, 0},
729 {11289600, 44100, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
730 {16934400, 44100, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
733 {12288000, 48000, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
734 {18432000, 48000, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
735 {12000000, 48000, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_125
, 0},
736 {24000000, 48000, CLK_SS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_125
, 1},
737 {27000000, 48000, CLK_SS_MODE
, CLK_NO_32K
, CLK_27M_MCLK
, CLK_R_125
, 1},
740 {11289600, 88200, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
741 {16934400, 88200, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
744 {12288000, 96000, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
745 {18432000, 96000, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_128
, 0},
746 {12000000, 96000, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_125
, 0},
747 {24000000, 96000, CLK_DS_MODE
, CLK_NO_32K
, CLK_NO_27M
, CLK_R_125
, 1},
750 static int cs42l52_get_clk(int mclk
, int rate
)
752 int i
, ret
= -EINVAL
;
753 u_int mclk1
, mclk2
= 0;
755 for (i
= 0; i
< ARRAY_SIZE(clk_map_table
); i
++) {
756 if (clk_map_table
[i
].rate
== rate
) {
757 mclk1
= clk_map_table
[i
].mclk
;
758 if (abs(mclk
- mclk1
) < abs(mclk
- mclk2
)) {
767 static int cs42l52_set_sysclk(struct snd_soc_dai
*codec_dai
,
768 int clk_id
, unsigned int freq
, int dir
)
770 struct snd_soc_codec
*codec
= codec_dai
->codec
;
771 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
773 if ((freq
>= CS42L52_MIN_CLK
) && (freq
<= CS42L52_MAX_CLK
)) {
774 cs42l52
->sysclk
= freq
;
776 dev_err(codec
->dev
, "Invalid freq parameter\n");
782 static int cs42l52_set_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
784 struct snd_soc_codec
*codec
= codec_dai
->codec
;
785 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
788 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
789 case SND_SOC_DAIFMT_CBM_CFM
:
790 iface
= CS42L52_IFACE_CTL1_MASTER
;
792 case SND_SOC_DAIFMT_CBS_CFS
:
793 iface
= CS42L52_IFACE_CTL1_SLAVE
;
799 /* interface format */
800 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
801 case SND_SOC_DAIFMT_I2S
:
802 iface
|= CS42L52_IFACE_CTL1_ADC_FMT_I2S
|
803 CS42L52_IFACE_CTL1_DAC_FMT_I2S
;
805 case SND_SOC_DAIFMT_RIGHT_J
:
806 iface
|= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J
;
808 case SND_SOC_DAIFMT_LEFT_J
:
809 iface
|= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J
|
810 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J
;
812 case SND_SOC_DAIFMT_DSP_A
:
813 iface
|= CS42L52_IFACE_CTL1_DSP_MODE_EN
;
815 case SND_SOC_DAIFMT_DSP_B
:
821 /* clock inversion */
822 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
823 case SND_SOC_DAIFMT_NB_NF
:
825 case SND_SOC_DAIFMT_IB_IF
:
826 iface
|= CS42L52_IFACE_CTL1_INV_SCLK
;
828 case SND_SOC_DAIFMT_IB_NF
:
829 iface
|= CS42L52_IFACE_CTL1_INV_SCLK
;
831 case SND_SOC_DAIFMT_NB_IF
:
836 cs42l52
->config
.format
= iface
;
837 snd_soc_write(codec
, CS42L52_IFACE_CTL1
, cs42l52
->config
.format
);
842 static int cs42l52_digital_mute(struct snd_soc_dai
*dai
, int mute
)
844 struct snd_soc_codec
*codec
= dai
->codec
;
847 snd_soc_update_bits(codec
, CS42L52_PB_CTL1
,
848 CS42L52_PB_CTL1_MUTE_MASK
,
849 CS42L52_PB_CTL1_MUTE
);
851 snd_soc_update_bits(codec
, CS42L52_PB_CTL1
,
852 CS42L52_PB_CTL1_MUTE_MASK
,
853 CS42L52_PB_CTL1_UNMUTE
);
858 static int cs42l52_pcm_hw_params(struct snd_pcm_substream
*substream
,
859 struct snd_pcm_hw_params
*params
,
860 struct snd_soc_dai
*dai
)
862 struct snd_soc_codec
*codec
= dai
->codec
;
863 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
867 index
= cs42l52_get_clk(cs42l52
->sysclk
, params_rate(params
));
869 cs42l52
->sysclk
= clk_map_table
[index
].mclk
;
871 clk
|= (clk_map_table
[index
].speed
<< CLK_SPEED_SHIFT
) |
872 (clk_map_table
[index
].group
<< CLK_32K_SR_SHIFT
) |
873 (clk_map_table
[index
].videoclk
<< CLK_27M_MCLK_SHIFT
) |
874 (clk_map_table
[index
].ratio
<< CLK_RATIO_SHIFT
) |
875 clk_map_table
[index
].mclkdiv2
;
877 snd_soc_write(codec
, CS42L52_CLK_CTL
, clk
);
879 dev_err(codec
->dev
, "can't get correct mclk\n");
886 static int cs42l52_set_bias_level(struct snd_soc_codec
*codec
,
887 enum snd_soc_bias_level level
)
889 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
892 case SND_SOC_BIAS_ON
:
894 case SND_SOC_BIAS_PREPARE
:
895 snd_soc_update_bits(codec
, CS42L52_PWRCTL1
,
896 CS42L52_PWRCTL1_PDN_CODEC
, 0);
898 case SND_SOC_BIAS_STANDBY
:
899 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
) {
900 regcache_cache_only(cs42l52
->regmap
, false);
901 regcache_sync(cs42l52
->regmap
);
903 snd_soc_write(codec
, CS42L52_PWRCTL1
, CS42L52_PWRCTL1_PDN_ALL
);
905 case SND_SOC_BIAS_OFF
:
906 snd_soc_write(codec
, CS42L52_PWRCTL1
, CS42L52_PWRCTL1_PDN_ALL
);
907 regcache_cache_only(cs42l52
->regmap
, true);
914 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
916 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
917 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
918 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
919 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
921 static struct snd_soc_dai_ops cs42l52_ops
= {
922 .hw_params
= cs42l52_pcm_hw_params
,
923 .digital_mute
= cs42l52_digital_mute
,
924 .set_fmt
= cs42l52_set_fmt
,
925 .set_sysclk
= cs42l52_set_sysclk
,
928 static struct snd_soc_dai_driver cs42l52_dai
= {
931 .stream_name
= "Playback",
934 .rates
= CS42L52_RATES
,
935 .formats
= CS42L52_FORMATS
,
938 .stream_name
= "Capture",
941 .rates
= CS42L52_RATES
,
942 .formats
= CS42L52_FORMATS
,
947 static int beep_rates
[] = {
948 261, 522, 585, 667, 706, 774, 889, 1000,
949 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
952 static void cs42l52_beep_work(struct work_struct
*work
)
954 struct cs42l52_private
*cs42l52
=
955 container_of(work
, struct cs42l52_private
, beep_work
);
956 struct snd_soc_codec
*codec
= cs42l52
->codec
;
957 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
962 if (cs42l52
->beep_rate
) {
963 for (i
= 0; i
< ARRAY_SIZE(beep_rates
); i
++) {
964 if (abs(cs42l52
->beep_rate
- beep_rates
[i
]) <
965 abs(cs42l52
->beep_rate
- beep_rates
[best
]))
969 dev_dbg(codec
->dev
, "Set beep rate %dHz for requested %dHz\n",
970 beep_rates
[best
], cs42l52
->beep_rate
);
972 val
= (best
<< CS42L52_BEEP_RATE_SHIFT
);
974 snd_soc_dapm_enable_pin(dapm
, "Beep");
976 dev_dbg(codec
->dev
, "Disabling beep\n");
977 snd_soc_dapm_disable_pin(dapm
, "Beep");
980 snd_soc_update_bits(codec
, CS42L52_BEEP_FREQ
,
981 CS42L52_BEEP_RATE_MASK
, val
);
983 snd_soc_dapm_sync(dapm
);
986 /* For usability define a way of injecting beep events for the device -
987 * many systems will not have a keyboard.
989 static int cs42l52_beep_event(struct input_dev
*dev
, unsigned int type
,
990 unsigned int code
, int hz
)
992 struct snd_soc_codec
*codec
= input_get_drvdata(dev
);
993 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
995 dev_dbg(codec
->dev
, "Beep event %x %x\n", code
, hz
);
1007 /* Kick the beep from a workqueue */
1008 cs42l52
->beep_rate
= hz
;
1009 schedule_work(&cs42l52
->beep_work
);
1013 static ssize_t
cs42l52_beep_set(struct device
*dev
,
1014 struct device_attribute
*attr
,
1015 const char *buf
, size_t count
)
1017 struct cs42l52_private
*cs42l52
= dev_get_drvdata(dev
);
1021 ret
= kstrtol(buf
, 10, &time
);
1025 input_event(cs42l52
->beep
, EV_SND
, SND_TONE
, time
);
1030 static DEVICE_ATTR(beep
, 0200, NULL
, cs42l52_beep_set
);
1032 static void cs42l52_init_beep(struct snd_soc_codec
*codec
)
1034 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
1037 cs42l52
->beep
= devm_input_allocate_device(codec
->dev
);
1038 if (!cs42l52
->beep
) {
1039 dev_err(codec
->dev
, "Failed to allocate beep device\n");
1043 INIT_WORK(&cs42l52
->beep_work
, cs42l52_beep_work
);
1044 cs42l52
->beep_rate
= 0;
1046 cs42l52
->beep
->name
= "CS42L52 Beep Generator";
1047 cs42l52
->beep
->phys
= dev_name(codec
->dev
);
1048 cs42l52
->beep
->id
.bustype
= BUS_I2C
;
1050 cs42l52
->beep
->evbit
[0] = BIT_MASK(EV_SND
);
1051 cs42l52
->beep
->sndbit
[0] = BIT_MASK(SND_BELL
) | BIT_MASK(SND_TONE
);
1052 cs42l52
->beep
->event
= cs42l52_beep_event
;
1053 cs42l52
->beep
->dev
.parent
= codec
->dev
;
1054 input_set_drvdata(cs42l52
->beep
, codec
);
1056 ret
= input_register_device(cs42l52
->beep
);
1058 cs42l52
->beep
= NULL
;
1059 dev_err(codec
->dev
, "Failed to register beep device\n");
1062 ret
= device_create_file(codec
->dev
, &dev_attr_beep
);
1064 dev_err(codec
->dev
, "Failed to create keyclick file: %d\n",
1069 static void cs42l52_free_beep(struct snd_soc_codec
*codec
)
1071 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
1073 device_remove_file(codec
->dev
, &dev_attr_beep
);
1074 cancel_work_sync(&cs42l52
->beep_work
);
1075 cs42l52
->beep
= NULL
;
1077 snd_soc_update_bits(codec
, CS42L52_BEEP_TONE_CTL
,
1078 CS42L52_BEEP_EN_MASK
, 0);
1081 static int cs42l52_probe(struct snd_soc_codec
*codec
)
1083 struct cs42l52_private
*cs42l52
= snd_soc_codec_get_drvdata(codec
);
1085 regcache_cache_only(cs42l52
->regmap
, true);
1087 cs42l52_add_mic_controls(codec
);
1089 cs42l52_init_beep(codec
);
1091 cs42l52
->sysclk
= CS42L52_DEFAULT_CLK
;
1092 cs42l52
->config
.format
= CS42L52_DEFAULT_FORMAT
;
1097 static int cs42l52_remove(struct snd_soc_codec
*codec
)
1099 cs42l52_free_beep(codec
);
1104 static const struct snd_soc_codec_driver soc_codec_dev_cs42l52
= {
1105 .probe
= cs42l52_probe
,
1106 .remove
= cs42l52_remove
,
1107 .set_bias_level
= cs42l52_set_bias_level
,
1108 .suspend_bias_off
= true,
1110 .dapm_widgets
= cs42l52_dapm_widgets
,
1111 .num_dapm_widgets
= ARRAY_SIZE(cs42l52_dapm_widgets
),
1112 .dapm_routes
= cs42l52_audio_map
,
1113 .num_dapm_routes
= ARRAY_SIZE(cs42l52_audio_map
),
1115 .controls
= cs42l52_snd_controls
,
1116 .num_controls
= ARRAY_SIZE(cs42l52_snd_controls
),
1119 /* Current and threshold powerup sequence Pg37 */
1120 static const struct reg_default cs42l52_threshold_patch
[] = {
1131 static const struct regmap_config cs42l52_regmap
= {
1135 .max_register
= CS42L52_MAX_REGISTER
,
1136 .reg_defaults
= cs42l52_reg_defaults
,
1137 .num_reg_defaults
= ARRAY_SIZE(cs42l52_reg_defaults
),
1138 .readable_reg
= cs42l52_readable_register
,
1139 .volatile_reg
= cs42l52_volatile_register
,
1140 .cache_type
= REGCACHE_RBTREE
,
1143 static int cs42l52_i2c_probe(struct i2c_client
*i2c_client
,
1144 const struct i2c_device_id
*id
)
1146 struct cs42l52_private
*cs42l52
;
1147 struct cs42l52_platform_data
*pdata
= dev_get_platdata(&i2c_client
->dev
);
1149 unsigned int devid
= 0;
1153 cs42l52
= devm_kzalloc(&i2c_client
->dev
, sizeof(struct cs42l52_private
),
1155 if (cs42l52
== NULL
)
1157 cs42l52
->dev
= &i2c_client
->dev
;
1159 cs42l52
->regmap
= devm_regmap_init_i2c(i2c_client
, &cs42l52_regmap
);
1160 if (IS_ERR(cs42l52
->regmap
)) {
1161 ret
= PTR_ERR(cs42l52
->regmap
);
1162 dev_err(&i2c_client
->dev
, "regmap_init() failed: %d\n", ret
);
1166 cs42l52
->pdata
= *pdata
;
1168 pdata
= devm_kzalloc(&i2c_client
->dev
,
1169 sizeof(struct cs42l52_platform_data
),
1172 dev_err(&i2c_client
->dev
, "could not allocate pdata\n");
1175 if (i2c_client
->dev
.of_node
) {
1176 if (of_property_read_bool(i2c_client
->dev
.of_node
,
1177 "cirrus,mica-differential-cfg"))
1178 pdata
->mica_diff_cfg
= true;
1180 if (of_property_read_bool(i2c_client
->dev
.of_node
,
1181 "cirrus,micb-differential-cfg"))
1182 pdata
->micb_diff_cfg
= true;
1184 if (of_property_read_u32(i2c_client
->dev
.of_node
,
1185 "cirrus,micbias-lvl", &val32
) >= 0)
1186 pdata
->micbias_lvl
= val32
;
1188 if (of_property_read_u32(i2c_client
->dev
.of_node
,
1189 "cirrus,chgfreq-divisor", &val32
) >= 0)
1190 pdata
->chgfreq
= val32
;
1193 of_get_named_gpio(i2c_client
->dev
.of_node
,
1194 "cirrus,reset-gpio", 0);
1196 cs42l52
->pdata
= *pdata
;
1199 if (cs42l52
->pdata
.reset_gpio
) {
1200 ret
= devm_gpio_request_one(&i2c_client
->dev
,
1201 cs42l52
->pdata
.reset_gpio
,
1202 GPIOF_OUT_INIT_HIGH
,
1205 dev_err(&i2c_client
->dev
, "Failed to request /RST %d: %d\n",
1206 cs42l52
->pdata
.reset_gpio
, ret
);
1209 gpio_set_value_cansleep(cs42l52
->pdata
.reset_gpio
, 0);
1210 gpio_set_value_cansleep(cs42l52
->pdata
.reset_gpio
, 1);
1213 i2c_set_clientdata(i2c_client
, cs42l52
);
1215 ret
= regmap_register_patch(cs42l52
->regmap
, cs42l52_threshold_patch
,
1216 ARRAY_SIZE(cs42l52_threshold_patch
));
1218 dev_warn(cs42l52
->dev
, "Failed to apply regmap patch: %d\n",
1221 ret
= regmap_read(cs42l52
->regmap
, CS42L52_CHIP
, ®
);
1222 devid
= reg
& CS42L52_CHIP_ID_MASK
;
1223 if (devid
!= CS42L52_CHIP_ID
) {
1225 dev_err(&i2c_client
->dev
,
1226 "CS42L52 Device ID (%X). Expected %X\n",
1227 devid
, CS42L52_CHIP_ID
);
1231 dev_info(&i2c_client
->dev
, "Cirrus Logic CS42L52, Revision: %02X\n",
1232 reg
& CS42L52_CHIP_REV_MASK
);
1234 /* Set Platform Data */
1235 if (cs42l52
->pdata
.mica_diff_cfg
)
1236 regmap_update_bits(cs42l52
->regmap
, CS42L52_MICA_CTL
,
1237 CS42L52_MIC_CTL_TYPE_MASK
,
1238 cs42l52
->pdata
.mica_diff_cfg
<<
1239 CS42L52_MIC_CTL_TYPE_SHIFT
);
1241 if (cs42l52
->pdata
.micb_diff_cfg
)
1242 regmap_update_bits(cs42l52
->regmap
, CS42L52_MICB_CTL
,
1243 CS42L52_MIC_CTL_TYPE_MASK
,
1244 cs42l52
->pdata
.micb_diff_cfg
<<
1245 CS42L52_MIC_CTL_TYPE_SHIFT
);
1247 if (cs42l52
->pdata
.chgfreq
)
1248 regmap_update_bits(cs42l52
->regmap
, CS42L52_CHARGE_PUMP
,
1249 CS42L52_CHARGE_PUMP_MASK
,
1250 cs42l52
->pdata
.chgfreq
<<
1251 CS42L52_CHARGE_PUMP_SHIFT
);
1253 if (cs42l52
->pdata
.micbias_lvl
)
1254 regmap_update_bits(cs42l52
->regmap
, CS42L52_IFACE_CTL2
,
1255 CS42L52_IFACE_CTL2_BIAS_LVL
,
1256 cs42l52
->pdata
.micbias_lvl
);
1258 ret
= snd_soc_register_codec(&i2c_client
->dev
,
1259 &soc_codec_dev_cs42l52
, &cs42l52_dai
, 1);
1265 static int cs42l52_i2c_remove(struct i2c_client
*client
)
1267 snd_soc_unregister_codec(&client
->dev
);
1271 static const struct of_device_id cs42l52_of_match
[] = {
1272 { .compatible
= "cirrus,cs42l52", },
1275 MODULE_DEVICE_TABLE(of
, cs42l52_of_match
);
1278 static const struct i2c_device_id cs42l52_id
[] = {
1282 MODULE_DEVICE_TABLE(i2c
, cs42l52_id
);
1284 static struct i2c_driver cs42l52_i2c_driver
= {
1287 .owner
= THIS_MODULE
,
1288 .of_match_table
= cs42l52_of_match
,
1290 .id_table
= cs42l52_id
,
1291 .probe
= cs42l52_i2c_probe
,
1292 .remove
= cs42l52_i2c_remove
,
1295 module_i2c_driver(cs42l52_i2c_driver
);
1297 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1298 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1299 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1300 MODULE_LICENSE("GPL");