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Merge remote-tracking branches 'asoc/topic/ssm2518', 'asoc/topic/sta529', 'asoc/topic...
[deliverable/linux.git] / sound / soc / codecs / cs42l52.c
1 /*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pm.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
36 #include "cs42l52.h"
37
38 struct sp_config {
39 u8 spc, format, spfs;
40 u32 srate;
41 };
42
43 struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
46 struct device *dev;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
49 u32 sysclk;
50 u8 mclksel;
51 u32 mclk;
52 u8 flags;
53 struct input_dev *beep;
54 struct work_struct beep_work;
55 int beep_rate;
56 };
57
58 static const struct reg_default cs42l52_reg_defaults[] = {
59 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
60 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
61 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
62 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
63 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
64 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
65 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
66 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
67 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
68 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
69 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
70 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
71 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
72 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
73 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
74 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
75 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
76 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
77 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
78 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
79 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
80 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
81 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
82 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
83 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
84 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
85 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
86 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
87 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
88 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
89 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
90 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
91 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
92 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
93 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
94 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
95 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
96 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
97 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
98 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
99 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
100 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
101 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
102 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
103 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
104 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
105 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
106 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
107 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
108 };
109
110 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
111 {
112 switch (reg) {
113 case CS42L52_CHIP ... CS42L52_CHARGE_PUMP:
114 return true;
115 default:
116 return false;
117 }
118 }
119
120 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
121 {
122 switch (reg) {
123 case CS42L52_IFACE_CTL2:
124 case CS42L52_CLK_STATUS:
125 case CS42L52_BATT_LEVEL:
126 case CS42L52_SPK_STATUS:
127 case CS42L52_CHARGE_PUMP:
128 return true;
129 default:
130 return false;
131 }
132 }
133
134 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
135
136 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
137
138 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
139
140 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
141
142 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
143
144 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
145
146 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
147
148 static const unsigned int limiter_tlv[] = {
149 TLV_DB_RANGE_HEAD(2),
150 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
151 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
152 };
153
154 static const char * const cs42l52_adca_text[] = {
155 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
156
157 static const char * const cs42l52_adcb_text[] = {
158 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
159
160 static SOC_ENUM_SINGLE_DECL(adca_enum,
161 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
162
163 static SOC_ENUM_SINGLE_DECL(adcb_enum,
164 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
165
166 static const struct snd_kcontrol_new adca_mux =
167 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
168
169 static const struct snd_kcontrol_new adcb_mux =
170 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
171
172 static const char * const mic_bias_level_text[] = {
173 "0.5 +VA", "0.6 +VA", "0.7 +VA",
174 "0.8 +VA", "0.83 +VA", "0.91 +VA"
175 };
176
177 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
178 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
179
180 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
181
182 static SOC_ENUM_SINGLE_DECL(mica_enum,
183 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
184
185 static SOC_ENUM_SINGLE_DECL(micb_enum,
186 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
187
188 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
189
190 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
191 CS42L52_ADC_MISC_CTL, 6,
192 digital_output_mux_text);
193
194 static const struct snd_kcontrol_new digital_output_mux =
195 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
196
197 static const char * const hp_gain_num_text[] = {
198 "0.3959", "0.4571", "0.5111", "0.6047",
199 "0.7099", "0.8399", "1.000", "1.1430"
200 };
201
202 static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
203 CS42L52_PB_CTL1, 5,
204 hp_gain_num_text);
205
206 static const char * const beep_pitch_text[] = {
207 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
208 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
209 };
210
211 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
212 CS42L52_BEEP_FREQ, 4,
213 beep_pitch_text);
214
215 static const char * const beep_ontime_text[] = {
216 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
217 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
218 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
219 };
220
221 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
222 CS42L52_BEEP_FREQ, 0,
223 beep_ontime_text);
224
225 static const char * const beep_offtime_text[] = {
226 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
227 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
228 };
229
230 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
231 CS42L52_BEEP_VOL, 5,
232 beep_offtime_text);
233
234 static const char * const beep_config_text[] = {
235 "Off", "Single", "Multiple", "Continuous"
236 };
237
238 static SOC_ENUM_SINGLE_DECL(beep_config_enum,
239 CS42L52_BEEP_TONE_CTL, 6,
240 beep_config_text);
241
242 static const char * const beep_bass_text[] = {
243 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
244 };
245
246 static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
247 CS42L52_BEEP_TONE_CTL, 1,
248 beep_bass_text);
249
250 static const char * const beep_treble_text[] = {
251 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
252 };
253
254 static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
255 CS42L52_BEEP_TONE_CTL, 3,
256 beep_treble_text);
257
258 static const char * const ng_threshold_text[] = {
259 "-34dB", "-37dB", "-40dB", "-43dB",
260 "-46dB", "-52dB", "-58dB", "-64dB"
261 };
262
263 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
264 CS42L52_NOISE_GATE_CTL, 2,
265 ng_threshold_text);
266
267 static const char * const cs42l52_ng_delay_text[] = {
268 "50ms", "100ms", "150ms", "200ms"};
269
270 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
271 CS42L52_NOISE_GATE_CTL, 0,
272 cs42l52_ng_delay_text);
273
274 static const char * const cs42l52_ng_type_text[] = {
275 "Apply Specific", "Apply All"
276 };
277
278 static SOC_ENUM_SINGLE_DECL(ng_type_enum,
279 CS42L52_NOISE_GATE_CTL, 6,
280 cs42l52_ng_type_text);
281
282 static const char * const left_swap_text[] = {
283 "Left", "LR 2", "Right"};
284
285 static const char * const right_swap_text[] = {
286 "Right", "LR 2", "Left"};
287
288 static const unsigned int swap_values[] = { 0, 1, 3 };
289
290 static const struct soc_enum adca_swap_enum =
291 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
292 ARRAY_SIZE(left_swap_text),
293 left_swap_text,
294 swap_values);
295
296 static const struct snd_kcontrol_new adca_mixer =
297 SOC_DAPM_ENUM("Route", adca_swap_enum);
298
299 static const struct soc_enum pcma_swap_enum =
300 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
301 ARRAY_SIZE(left_swap_text),
302 left_swap_text,
303 swap_values);
304
305 static const struct snd_kcontrol_new pcma_mixer =
306 SOC_DAPM_ENUM("Route", pcma_swap_enum);
307
308 static const struct soc_enum adcb_swap_enum =
309 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
310 ARRAY_SIZE(right_swap_text),
311 right_swap_text,
312 swap_values);
313
314 static const struct snd_kcontrol_new adcb_mixer =
315 SOC_DAPM_ENUM("Route", adcb_swap_enum);
316
317 static const struct soc_enum pcmb_swap_enum =
318 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
319 ARRAY_SIZE(right_swap_text),
320 right_swap_text,
321 swap_values);
322
323 static const struct snd_kcontrol_new pcmb_mixer =
324 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
325
326
327 static const struct snd_kcontrol_new passthrul_ctl =
328 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
329
330 static const struct snd_kcontrol_new passthrur_ctl =
331 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
332
333 static const struct snd_kcontrol_new spkl_ctl =
334 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
335
336 static const struct snd_kcontrol_new spkr_ctl =
337 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
338
339 static const struct snd_kcontrol_new hpl_ctl =
340 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
341
342 static const struct snd_kcontrol_new hpr_ctl =
343 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
344
345 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
346
347 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
348 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
349
350 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
351 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
352
353 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
354
355 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
356 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
357
358 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
359 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pga_tlv),
360
361 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
362
363 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
364 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
365
366 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
367
368 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
369 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
370 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
371 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
372 0, 0x19, 0x7F, ipd_tlv),
373
374 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
375
376 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
377 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
378
379 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
380 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
381
382 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
383 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
384 0, 0x19, 0x7f, mix_tlv),
385 SOC_DOUBLE_R("PCM Mixer Switch",
386 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
387
388 SOC_ENUM("Beep Config", beep_config_enum),
389 SOC_ENUM("Beep Pitch", beep_pitch_enum),
390 SOC_ENUM("Beep on Time", beep_ontime_enum),
391 SOC_ENUM("Beep off Time", beep_offtime_enum),
392 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
393 0, 0x07, 0x1f, beep_tlv),
394 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
395 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
396 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
397
398 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
399 SOC_SINGLE_TLV("Treble Gain Volume",
400 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
401 SOC_SINGLE_TLV("Bass Gain Volume",
402 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
403
404 /* Limiter */
405 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
406 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
407 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
408 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
409 SOC_SINGLE_TLV("Limiter Release Rate Volume",
410 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
411 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
412 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
413
414 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
415 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
416 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
417
418 /* ALC */
419 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
420 0, 63, 0, limiter_tlv),
421 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
422 0, 63, 0, limiter_tlv),
423 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
424 5, 7, 0, limiter_tlv),
425 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
426 2, 7, 0, limiter_tlv),
427
428 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
429 CS42L52_PGAB_CTL, 7, 1, 1),
430 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
431 CS42L52_PGAB_CTL, 6, 1, 1),
432 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
433
434 /* Noise gate */
435 SOC_ENUM("NG Type Switch", ng_type_enum),
436 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
437 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
438 SOC_ENUM("NG Threshold", ng_threshold_enum),
439 SOC_ENUM("NG Delay", ng_delay_enum),
440
441 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
442
443 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
444 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
445 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
446 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
447 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
448
449 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
450 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
451 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
452
453 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
454 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
455 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
456 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
457
458 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
459 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
460
461 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
462 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
463
464 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
465 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
466
467 };
468
469 static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
470 SOC_ENUM("MICA Select", mica_enum),
471 };
472
473 static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
474 SOC_ENUM("MICB Select", micb_enum),
475 };
476
477 static int cs42l52_add_mic_controls(struct snd_soc_codec *codec)
478 {
479 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
480 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
481
482 if (!pdata->mica_diff_cfg)
483 snd_soc_add_codec_controls(codec, cs42l52_mica_controls,
484 ARRAY_SIZE(cs42l52_mica_controls));
485
486 if (!pdata->micb_diff_cfg)
487 snd_soc_add_codec_controls(codec, cs42l52_micb_controls,
488 ARRAY_SIZE(cs42l52_micb_controls));
489
490 return 0;
491 }
492
493 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
494
495 SND_SOC_DAPM_INPUT("AIN1L"),
496 SND_SOC_DAPM_INPUT("AIN1R"),
497 SND_SOC_DAPM_INPUT("AIN2L"),
498 SND_SOC_DAPM_INPUT("AIN2R"),
499 SND_SOC_DAPM_INPUT("AIN3L"),
500 SND_SOC_DAPM_INPUT("AIN3R"),
501 SND_SOC_DAPM_INPUT("AIN4L"),
502 SND_SOC_DAPM_INPUT("AIN4R"),
503 SND_SOC_DAPM_INPUT("MICA"),
504 SND_SOC_DAPM_INPUT("MICB"),
505 SND_SOC_DAPM_SIGGEN("Beep"),
506
507 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
508 SND_SOC_NOPM, 0, 0),
509 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
510 SND_SOC_NOPM, 0, 0),
511
512 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
513 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
514 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
515 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
516
517 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
518 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
519
520 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
521 0, 0, &adca_mixer),
522 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
523 0, 0, &adcb_mixer),
524
525 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
526 0, 0, &digital_output_mux),
527
528 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
529 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
530
531 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
532 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
533
534 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
535 SND_SOC_NOPM, 0, 0),
536 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
537 SND_SOC_NOPM, 0, 0),
538
539 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
540 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
541
542 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
543 6, 0, &passthrul_ctl),
544 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
545 7, 0, &passthrur_ctl),
546
547 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
548 0, 0, &pcma_mixer),
549 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
550 0, 0, &pcmb_mixer),
551
552 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
553 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
554
555 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
556 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
557
558 SND_SOC_DAPM_OUTPUT("HPOUTA"),
559 SND_SOC_DAPM_OUTPUT("HPOUTB"),
560 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
561 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
562
563 };
564
565 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
566
567 {"Capture", NULL, "AIFOUTL"},
568 {"Capture", NULL, "AIFOUTL"},
569
570 {"AIFOUTL", NULL, "Output Mux"},
571 {"AIFOUTR", NULL, "Output Mux"},
572
573 {"Output Mux", "ADC", "ADC Left"},
574 {"Output Mux", "ADC", "ADC Right"},
575
576 {"ADC Left", NULL, "Charge Pump"},
577 {"ADC Right", NULL, "Charge Pump"},
578
579 {"Charge Pump", NULL, "ADC Left Mux"},
580 {"Charge Pump", NULL, "ADC Right Mux"},
581
582 {"ADC Left Mux", "Input1A", "AIN1L"},
583 {"ADC Right Mux", "Input1B", "AIN1R"},
584 {"ADC Left Mux", "Input2A", "AIN2L"},
585 {"ADC Right Mux", "Input2B", "AIN2R"},
586 {"ADC Left Mux", "Input3A", "AIN3L"},
587 {"ADC Right Mux", "Input3B", "AIN3R"},
588 {"ADC Left Mux", "Input4A", "AIN4L"},
589 {"ADC Right Mux", "Input4B", "AIN4R"},
590 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
591 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
592
593 {"PGA Left", "Switch", "AIN1L"},
594 {"PGA Right", "Switch", "AIN1R"},
595 {"PGA Left", "Switch", "AIN2L"},
596 {"PGA Right", "Switch", "AIN2R"},
597 {"PGA Left", "Switch", "AIN3L"},
598 {"PGA Right", "Switch", "AIN3R"},
599 {"PGA Left", "Switch", "AIN4L"},
600 {"PGA Right", "Switch", "AIN4R"},
601
602 {"PGA Left", "Switch", "PGA MICA"},
603 {"PGA MICA", NULL, "MICA"},
604
605 {"PGA Right", "Switch", "PGA MICB"},
606 {"PGA MICB", NULL, "MICB"},
607
608 {"HPOUTA", NULL, "HP Left Amp"},
609 {"HPOUTB", NULL, "HP Right Amp"},
610 {"HP Left Amp", NULL, "Bypass Left"},
611 {"HP Right Amp", NULL, "Bypass Right"},
612 {"Bypass Left", "Switch", "PGA Left"},
613 {"Bypass Right", "Switch", "PGA Right"},
614 {"HP Left Amp", "Switch", "DAC Left"},
615 {"HP Right Amp", "Switch", "DAC Right"},
616
617 {"SPKOUTA", NULL, "SPK Left Amp"},
618 {"SPKOUTB", NULL, "SPK Right Amp"},
619
620 {"SPK Left Amp", NULL, "Beep"},
621 {"SPK Right Amp", NULL, "Beep"},
622 {"SPK Left Amp", "Switch", "Playback"},
623 {"SPK Right Amp", "Switch", "Playback"},
624
625 {"DAC Left", NULL, "Beep"},
626 {"DAC Right", NULL, "Beep"},
627 {"DAC Left", NULL, "Playback"},
628 {"DAC Right", NULL, "Playback"},
629
630 {"Output Mux", "DSP", "Playback"},
631 {"Output Mux", "DSP", "Playback"},
632
633 {"AIFINL", NULL, "Playback"},
634 {"AIFINR", NULL, "Playback"},
635
636 };
637
638 struct cs42l52_clk_para {
639 u32 mclk;
640 u32 rate;
641 u8 speed;
642 u8 group;
643 u8 videoclk;
644 u8 ratio;
645 u8 mclkdiv2;
646 };
647
648 static const struct cs42l52_clk_para clk_map_table[] = {
649 /*8k*/
650 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
651 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
652 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
653 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
654 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
655
656 /*11.025k*/
657 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
658 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
659
660 /*16k*/
661 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
662 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
663 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
664 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
665 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
666
667 /*22.05k*/
668 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
669 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
670
671 /* 32k */
672 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
673 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
674 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
675 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
676 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
677
678 /* 44.1k */
679 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
680 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
681
682 /* 48k */
683 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
684 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
685 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
686 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
687 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
688
689 /* 88.2k */
690 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
691 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
692
693 /* 96k */
694 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
695 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
696 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
697 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
698 };
699
700 static int cs42l52_get_clk(int mclk, int rate)
701 {
702 int i, ret = -EINVAL;
703 u_int mclk1, mclk2 = 0;
704
705 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
706 if (clk_map_table[i].rate == rate) {
707 mclk1 = clk_map_table[i].mclk;
708 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
709 mclk2 = mclk1;
710 ret = i;
711 }
712 }
713 }
714 return ret;
715 }
716
717 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
718 int clk_id, unsigned int freq, int dir)
719 {
720 struct snd_soc_codec *codec = codec_dai->codec;
721 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
722
723 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
724 cs42l52->sysclk = freq;
725 } else {
726 dev_err(codec->dev, "Invalid freq parameter\n");
727 return -EINVAL;
728 }
729 return 0;
730 }
731
732 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
733 {
734 struct snd_soc_codec *codec = codec_dai->codec;
735 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
736 u8 iface = 0;
737
738 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
739 case SND_SOC_DAIFMT_CBM_CFM:
740 iface = CS42L52_IFACE_CTL1_MASTER;
741 break;
742 case SND_SOC_DAIFMT_CBS_CFS:
743 iface = CS42L52_IFACE_CTL1_SLAVE;
744 break;
745 default:
746 return -EINVAL;
747 }
748
749 /* interface format */
750 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
751 case SND_SOC_DAIFMT_I2S:
752 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
753 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
754 break;
755 case SND_SOC_DAIFMT_RIGHT_J:
756 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
757 break;
758 case SND_SOC_DAIFMT_LEFT_J:
759 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
760 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
761 break;
762 case SND_SOC_DAIFMT_DSP_A:
763 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
764 break;
765 case SND_SOC_DAIFMT_DSP_B:
766 break;
767 default:
768 return -EINVAL;
769 }
770
771 /* clock inversion */
772 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
773 case SND_SOC_DAIFMT_NB_NF:
774 break;
775 case SND_SOC_DAIFMT_IB_IF:
776 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
777 break;
778 case SND_SOC_DAIFMT_IB_NF:
779 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
780 break;
781 case SND_SOC_DAIFMT_NB_IF:
782 break;
783 default:
784 return -EINVAL;
785 }
786 cs42l52->config.format = iface;
787 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
788
789 return 0;
790 }
791
792 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
793 {
794 struct snd_soc_codec *codec = dai->codec;
795
796 if (mute)
797 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
798 CS42L52_PB_CTL1_MUTE_MASK,
799 CS42L52_PB_CTL1_MUTE);
800 else
801 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
802 CS42L52_PB_CTL1_MUTE_MASK,
803 CS42L52_PB_CTL1_UNMUTE);
804
805 return 0;
806 }
807
808 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
809 struct snd_pcm_hw_params *params,
810 struct snd_soc_dai *dai)
811 {
812 struct snd_soc_codec *codec = dai->codec;
813 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
814 u32 clk = 0;
815 int index;
816
817 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
818 if (index >= 0) {
819 cs42l52->sysclk = clk_map_table[index].mclk;
820
821 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
822 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
823 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
824 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
825 clk_map_table[index].mclkdiv2;
826
827 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
828 } else {
829 dev_err(codec->dev, "can't get correct mclk\n");
830 return -EINVAL;
831 }
832
833 return 0;
834 }
835
836 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
837 enum snd_soc_bias_level level)
838 {
839 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
840
841 switch (level) {
842 case SND_SOC_BIAS_ON:
843 break;
844 case SND_SOC_BIAS_PREPARE:
845 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
846 CS42L52_PWRCTL1_PDN_CODEC, 0);
847 break;
848 case SND_SOC_BIAS_STANDBY:
849 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
850 regcache_cache_only(cs42l52->regmap, false);
851 regcache_sync(cs42l52->regmap);
852 }
853 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
854 break;
855 case SND_SOC_BIAS_OFF:
856 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
857 regcache_cache_only(cs42l52->regmap, true);
858 break;
859 }
860
861 return 0;
862 }
863
864 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
865
866 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
867 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
868 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
869 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
870
871 static const struct snd_soc_dai_ops cs42l52_ops = {
872 .hw_params = cs42l52_pcm_hw_params,
873 .digital_mute = cs42l52_digital_mute,
874 .set_fmt = cs42l52_set_fmt,
875 .set_sysclk = cs42l52_set_sysclk,
876 };
877
878 static struct snd_soc_dai_driver cs42l52_dai = {
879 .name = "cs42l52",
880 .playback = {
881 .stream_name = "Playback",
882 .channels_min = 1,
883 .channels_max = 2,
884 .rates = CS42L52_RATES,
885 .formats = CS42L52_FORMATS,
886 },
887 .capture = {
888 .stream_name = "Capture",
889 .channels_min = 1,
890 .channels_max = 2,
891 .rates = CS42L52_RATES,
892 .formats = CS42L52_FORMATS,
893 },
894 .ops = &cs42l52_ops,
895 };
896
897 static int beep_rates[] = {
898 261, 522, 585, 667, 706, 774, 889, 1000,
899 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
900 };
901
902 static void cs42l52_beep_work(struct work_struct *work)
903 {
904 struct cs42l52_private *cs42l52 =
905 container_of(work, struct cs42l52_private, beep_work);
906 struct snd_soc_codec *codec = cs42l52->codec;
907 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
908 int i;
909 int val = 0;
910 int best = 0;
911
912 if (cs42l52->beep_rate) {
913 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
914 if (abs(cs42l52->beep_rate - beep_rates[i]) <
915 abs(cs42l52->beep_rate - beep_rates[best]))
916 best = i;
917 }
918
919 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
920 beep_rates[best], cs42l52->beep_rate);
921
922 val = (best << CS42L52_BEEP_RATE_SHIFT);
923
924 snd_soc_dapm_enable_pin(dapm, "Beep");
925 } else {
926 dev_dbg(codec->dev, "Disabling beep\n");
927 snd_soc_dapm_disable_pin(dapm, "Beep");
928 }
929
930 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
931 CS42L52_BEEP_RATE_MASK, val);
932
933 snd_soc_dapm_sync(dapm);
934 }
935
936 /* For usability define a way of injecting beep events for the device -
937 * many systems will not have a keyboard.
938 */
939 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
940 unsigned int code, int hz)
941 {
942 struct snd_soc_codec *codec = input_get_drvdata(dev);
943 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
944
945 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
946
947 switch (code) {
948 case SND_BELL:
949 if (hz)
950 hz = 261;
951 case SND_TONE:
952 break;
953 default:
954 return -1;
955 }
956
957 /* Kick the beep from a workqueue */
958 cs42l52->beep_rate = hz;
959 schedule_work(&cs42l52->beep_work);
960 return 0;
961 }
962
963 static ssize_t cs42l52_beep_set(struct device *dev,
964 struct device_attribute *attr,
965 const char *buf, size_t count)
966 {
967 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
968 long int time;
969 int ret;
970
971 ret = kstrtol(buf, 10, &time);
972 if (ret != 0)
973 return ret;
974
975 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
976
977 return count;
978 }
979
980 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
981
982 static void cs42l52_init_beep(struct snd_soc_codec *codec)
983 {
984 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
985 int ret;
986
987 cs42l52->beep = devm_input_allocate_device(codec->dev);
988 if (!cs42l52->beep) {
989 dev_err(codec->dev, "Failed to allocate beep device\n");
990 return;
991 }
992
993 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
994 cs42l52->beep_rate = 0;
995
996 cs42l52->beep->name = "CS42L52 Beep Generator";
997 cs42l52->beep->phys = dev_name(codec->dev);
998 cs42l52->beep->id.bustype = BUS_I2C;
999
1000 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1001 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1002 cs42l52->beep->event = cs42l52_beep_event;
1003 cs42l52->beep->dev.parent = codec->dev;
1004 input_set_drvdata(cs42l52->beep, codec);
1005
1006 ret = input_register_device(cs42l52->beep);
1007 if (ret != 0) {
1008 cs42l52->beep = NULL;
1009 dev_err(codec->dev, "Failed to register beep device\n");
1010 }
1011
1012 ret = device_create_file(codec->dev, &dev_attr_beep);
1013 if (ret != 0) {
1014 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1015 ret);
1016 }
1017 }
1018
1019 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1020 {
1021 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1022
1023 device_remove_file(codec->dev, &dev_attr_beep);
1024 cancel_work_sync(&cs42l52->beep_work);
1025 cs42l52->beep = NULL;
1026
1027 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1028 CS42L52_BEEP_EN_MASK, 0);
1029 }
1030
1031 static int cs42l52_probe(struct snd_soc_codec *codec)
1032 {
1033 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1034
1035 regcache_cache_only(cs42l52->regmap, true);
1036
1037 cs42l52_add_mic_controls(codec);
1038
1039 cs42l52_init_beep(codec);
1040
1041 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1042 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1043
1044 return 0;
1045 }
1046
1047 static int cs42l52_remove(struct snd_soc_codec *codec)
1048 {
1049 cs42l52_free_beep(codec);
1050
1051 return 0;
1052 }
1053
1054 static const struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1055 .probe = cs42l52_probe,
1056 .remove = cs42l52_remove,
1057 .set_bias_level = cs42l52_set_bias_level,
1058 .suspend_bias_off = true,
1059
1060 .dapm_widgets = cs42l52_dapm_widgets,
1061 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1062 .dapm_routes = cs42l52_audio_map,
1063 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1064
1065 .controls = cs42l52_snd_controls,
1066 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1067 };
1068
1069 /* Current and threshold powerup sequence Pg37 */
1070 static const struct reg_sequence cs42l52_threshold_patch[] = {
1071
1072 { 0x00, 0x99 },
1073 { 0x3E, 0xBA },
1074 { 0x47, 0x80 },
1075 { 0x32, 0xBB },
1076 { 0x32, 0x3B },
1077 { 0x00, 0x00 },
1078
1079 };
1080
1081 static const struct regmap_config cs42l52_regmap = {
1082 .reg_bits = 8,
1083 .val_bits = 8,
1084
1085 .max_register = CS42L52_MAX_REGISTER,
1086 .reg_defaults = cs42l52_reg_defaults,
1087 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1088 .readable_reg = cs42l52_readable_register,
1089 .volatile_reg = cs42l52_volatile_register,
1090 .cache_type = REGCACHE_RBTREE,
1091 };
1092
1093 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1094 const struct i2c_device_id *id)
1095 {
1096 struct cs42l52_private *cs42l52;
1097 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1098 int ret;
1099 unsigned int devid = 0;
1100 unsigned int reg;
1101 u32 val32;
1102
1103 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1104 GFP_KERNEL);
1105 if (cs42l52 == NULL)
1106 return -ENOMEM;
1107 cs42l52->dev = &i2c_client->dev;
1108
1109 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1110 if (IS_ERR(cs42l52->regmap)) {
1111 ret = PTR_ERR(cs42l52->regmap);
1112 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1113 return ret;
1114 }
1115 if (pdata) {
1116 cs42l52->pdata = *pdata;
1117 } else {
1118 pdata = devm_kzalloc(&i2c_client->dev,
1119 sizeof(struct cs42l52_platform_data),
1120 GFP_KERNEL);
1121 if (!pdata) {
1122 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1123 return -ENOMEM;
1124 }
1125 if (i2c_client->dev.of_node) {
1126 if (of_property_read_bool(i2c_client->dev.of_node,
1127 "cirrus,mica-differential-cfg"))
1128 pdata->mica_diff_cfg = true;
1129
1130 if (of_property_read_bool(i2c_client->dev.of_node,
1131 "cirrus,micb-differential-cfg"))
1132 pdata->micb_diff_cfg = true;
1133
1134 if (of_property_read_u32(i2c_client->dev.of_node,
1135 "cirrus,micbias-lvl", &val32) >= 0)
1136 pdata->micbias_lvl = val32;
1137
1138 if (of_property_read_u32(i2c_client->dev.of_node,
1139 "cirrus,chgfreq-divisor", &val32) >= 0)
1140 pdata->chgfreq = val32;
1141
1142 pdata->reset_gpio =
1143 of_get_named_gpio(i2c_client->dev.of_node,
1144 "cirrus,reset-gpio", 0);
1145 }
1146 cs42l52->pdata = *pdata;
1147 }
1148
1149 if (cs42l52->pdata.reset_gpio) {
1150 ret = devm_gpio_request_one(&i2c_client->dev,
1151 cs42l52->pdata.reset_gpio,
1152 GPIOF_OUT_INIT_HIGH,
1153 "CS42L52 /RST");
1154 if (ret < 0) {
1155 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1156 cs42l52->pdata.reset_gpio, ret);
1157 return ret;
1158 }
1159 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1160 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1161 }
1162
1163 i2c_set_clientdata(i2c_client, cs42l52);
1164
1165 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1166 ARRAY_SIZE(cs42l52_threshold_patch));
1167 if (ret != 0)
1168 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1169 ret);
1170
1171 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1172 devid = reg & CS42L52_CHIP_ID_MASK;
1173 if (devid != CS42L52_CHIP_ID) {
1174 ret = -ENODEV;
1175 dev_err(&i2c_client->dev,
1176 "CS42L52 Device ID (%X). Expected %X\n",
1177 devid, CS42L52_CHIP_ID);
1178 return ret;
1179 }
1180
1181 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1182 reg & CS42L52_CHIP_REV_MASK);
1183
1184 /* Set Platform Data */
1185 if (cs42l52->pdata.mica_diff_cfg)
1186 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1187 CS42L52_MIC_CTL_TYPE_MASK,
1188 cs42l52->pdata.mica_diff_cfg <<
1189 CS42L52_MIC_CTL_TYPE_SHIFT);
1190
1191 if (cs42l52->pdata.micb_diff_cfg)
1192 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1193 CS42L52_MIC_CTL_TYPE_MASK,
1194 cs42l52->pdata.micb_diff_cfg <<
1195 CS42L52_MIC_CTL_TYPE_SHIFT);
1196
1197 if (cs42l52->pdata.chgfreq)
1198 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1199 CS42L52_CHARGE_PUMP_MASK,
1200 cs42l52->pdata.chgfreq <<
1201 CS42L52_CHARGE_PUMP_SHIFT);
1202
1203 if (cs42l52->pdata.micbias_lvl)
1204 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1205 CS42L52_IFACE_CTL2_BIAS_LVL,
1206 cs42l52->pdata.micbias_lvl);
1207
1208 ret = snd_soc_register_codec(&i2c_client->dev,
1209 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1210 if (ret < 0)
1211 return ret;
1212 return 0;
1213 }
1214
1215 static int cs42l52_i2c_remove(struct i2c_client *client)
1216 {
1217 snd_soc_unregister_codec(&client->dev);
1218 return 0;
1219 }
1220
1221 static const struct of_device_id cs42l52_of_match[] = {
1222 { .compatible = "cirrus,cs42l52", },
1223 {},
1224 };
1225 MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1226
1227
1228 static const struct i2c_device_id cs42l52_id[] = {
1229 { "cs42l52", 0 },
1230 { }
1231 };
1232 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1233
1234 static struct i2c_driver cs42l52_i2c_driver = {
1235 .driver = {
1236 .name = "cs42l52",
1237 .of_match_table = cs42l52_of_match,
1238 },
1239 .id_table = cs42l52_id,
1240 .probe = cs42l52_i2c_probe,
1241 .remove = cs42l52_i2c_remove,
1242 };
1243
1244 module_i2c_driver(cs42l52_i2c_driver);
1245
1246 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1247 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1248 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1249 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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