projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: cs53l30: Add codec driver support for Cirrus CS53L30
[deliverable/linux.git] / sound / soc / codecs / cs53l30.c
1 /*
2 * cs53l30.c -- CS53l30 ALSA Soc Audio driver
3 *
4 * Copyright 2015 Cirrus Logic, Inc.
5 *
6 * Authors: Paul Handrigan <Paul.Handrigan@cirrus.com>,
7 * Tim Howe <Tim.Howe@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/of_gpio.h>
20 #include <linux/regulator/consumer.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24
25 #include "cs53l30.h"
26
27 #define CS53L30_NUM_SUPPLIES 2
28 static const char *const cs53l30_supply_names[CS53L30_NUM_SUPPLIES] = {
29 "VA",
30 "VP",
31 };
32
33 struct cs53l30_private {
34 struct regulator_bulk_data supplies[CS53L30_NUM_SUPPLIES];
35 struct regmap *regmap;
36 struct gpio_desc *reset_gpio;
37 struct clk *mclk;
38 bool use_sdout2;
39 u32 mclk_rate;
40 };
41
42 static const struct reg_default cs53l30_reg_defaults[] = {
43 { CS53L30_PWRCTL, CS53L30_PWRCTL_DEFAULT },
44 { CS53L30_MCLKCTL, CS53L30_MCLKCTL_DEFAULT },
45 { CS53L30_INT_SR_CTL, CS53L30_INT_SR_CTL_DEFAULT },
46 { CS53L30_MICBIAS_CTL, CS53L30_MICBIAS_CTL_DEFAULT },
47 { CS53L30_ASPCFG_CTL, CS53L30_ASPCFG_CTL_DEFAULT },
48 { CS53L30_ASP_CTL1, CS53L30_ASP_CTL1_DEFAULT },
49 { CS53L30_ASP_TDMTX_CTL1, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
50 { CS53L30_ASP_TDMTX_CTL2, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
51 { CS53L30_ASP_TDMTX_CTL3, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
52 { CS53L30_ASP_TDMTX_CTL4, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
53 { CS53L30_ASP_TDMTX_EN1, CS53L30_ASP_TDMTX_ENx_DEFAULT },
54 { CS53L30_ASP_TDMTX_EN2, CS53L30_ASP_TDMTX_ENx_DEFAULT },
55 { CS53L30_ASP_TDMTX_EN3, CS53L30_ASP_TDMTX_ENx_DEFAULT },
56 { CS53L30_ASP_TDMTX_EN4, CS53L30_ASP_TDMTX_ENx_DEFAULT },
57 { CS53L30_ASP_TDMTX_EN5, CS53L30_ASP_TDMTX_ENx_DEFAULT },
58 { CS53L30_ASP_TDMTX_EN6, CS53L30_ASP_TDMTX_ENx_DEFAULT },
59 { CS53L30_ASP_CTL2, CS53L30_ASP_CTL2_DEFAULT },
60 { CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DEFAULT },
61 { CS53L30_LRCK_CTL1, CS53L30_LRCK_CTLx_DEFAULT },
62 { CS53L30_LRCK_CTL2, CS53L30_LRCK_CTLx_DEFAULT },
63 { CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_DEFAULT },
64 { CS53L30_MUTEP_CTL2, CS53L30_MUTEP_CTL2_DEFAULT },
65 { CS53L30_INBIAS_CTL1, CS53L30_INBIAS_CTL1_DEFAULT },
66 { CS53L30_INBIAS_CTL2, CS53L30_INBIAS_CTL2_DEFAULT },
67 { CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_STR_CTL_DEFAULT },
68 { CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_STR_CTL_DEFAULT },
69 { CS53L30_ADCDMIC1_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
70 { CS53L30_ADCDMIC1_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
71 { CS53L30_ADC1_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
72 { CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
73 { CS53L30_ADC1A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
74 { CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
75 { CS53L30_ADC1A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
76 { CS53L30_ADC1B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
77 { CS53L30_ADCDMIC2_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
78 { CS53L30_ADCDMIC2_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
79 { CS53L30_ADC2_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
80 { CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
81 { CS53L30_ADC2A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
82 { CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
83 { CS53L30_ADC2A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
84 { CS53L30_ADC2B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
85 { CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK },
86 };
87
88 static bool cs53l30_volatile_register(struct device *dev, unsigned int reg)
89 {
90 if (reg == CS53L30_IS)
91 return true;
92 else
93 return false;
94 }
95
96 static bool cs53l30_writeable_register(struct device *dev, unsigned int reg)
97 {
98 switch (reg) {
99 case CS53L30_DEVID_AB:
100 case CS53L30_DEVID_CD:
101 case CS53L30_DEVID_E:
102 case CS53L30_REVID:
103 case CS53L30_IS:
104 return false;
105 default:
106 return true;
107 }
108 }
109
110 static bool cs53l30_readable_register(struct device *dev, unsigned int reg)
111 {
112 switch (reg) {
113 case CS53L30_DEVID_AB:
114 case CS53L30_DEVID_CD:
115 case CS53L30_DEVID_E:
116 case CS53L30_REVID:
117 case CS53L30_PWRCTL:
118 case CS53L30_MCLKCTL:
119 case CS53L30_INT_SR_CTL:
120 case CS53L30_MICBIAS_CTL:
121 case CS53L30_ASPCFG_CTL:
122 case CS53L30_ASP_CTL1:
123 case CS53L30_ASP_TDMTX_CTL1:
124 case CS53L30_ASP_TDMTX_CTL2:
125 case CS53L30_ASP_TDMTX_CTL3:
126 case CS53L30_ASP_TDMTX_CTL4:
127 case CS53L30_ASP_TDMTX_EN1:
128 case CS53L30_ASP_TDMTX_EN2:
129 case CS53L30_ASP_TDMTX_EN3:
130 case CS53L30_ASP_TDMTX_EN4:
131 case CS53L30_ASP_TDMTX_EN5:
132 case CS53L30_ASP_TDMTX_EN6:
133 case CS53L30_ASP_CTL2:
134 case CS53L30_SFT_RAMP:
135 case CS53L30_LRCK_CTL1:
136 case CS53L30_LRCK_CTL2:
137 case CS53L30_MUTEP_CTL1:
138 case CS53L30_MUTEP_CTL2:
139 case CS53L30_INBIAS_CTL1:
140 case CS53L30_INBIAS_CTL2:
141 case CS53L30_DMIC1_STR_CTL:
142 case CS53L30_DMIC2_STR_CTL:
143 case CS53L30_ADCDMIC1_CTL1:
144 case CS53L30_ADCDMIC1_CTL2:
145 case CS53L30_ADC1_CTL3:
146 case CS53L30_ADC1_NG_CTL:
147 case CS53L30_ADC1A_AFE_CTL:
148 case CS53L30_ADC1B_AFE_CTL:
149 case CS53L30_ADC1A_DIG_VOL:
150 case CS53L30_ADC1B_DIG_VOL:
151 case CS53L30_ADCDMIC2_CTL1:
152 case CS53L30_ADCDMIC2_CTL2:
153 case CS53L30_ADC2_CTL3:
154 case CS53L30_ADC2_NG_CTL:
155 case CS53L30_ADC2A_AFE_CTL:
156 case CS53L30_ADC2B_AFE_CTL:
157 case CS53L30_ADC2A_DIG_VOL:
158 case CS53L30_ADC2B_DIG_VOL:
159 case CS53L30_INT_MASK:
160 return true;
161 default:
162 return false;
163 }
164 }
165
166 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0);
167 static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0);
168 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
169 static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1);
170 static DECLARE_TLV_DB_SCALE(pga_preamp_tlv, 0, 10000, 0);
171
172 static const char * const input1_sel_text[] = {
173 "DMIC1 On AB In",
174 "DMIC1 On A In",
175 "DMIC1 On B In",
176 "ADC1 On AB In",
177 "ADC1 On A In",
178 "ADC1 On B In",
179 "DMIC1 Off ADC1 Off",
180 };
181
182 unsigned int const input1_sel_values[] = {
183 CS53L30_CH_TYPE,
184 CS53L30_ADCxB_PDN | CS53L30_CH_TYPE,
185 CS53L30_ADCxA_PDN | CS53L30_CH_TYPE,
186 CS53L30_DMICx_PDN,
187 CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
188 CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
189 CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
190 };
191
192 static const char * const input2_sel_text[] = {
193 "DMIC2 On AB In",
194 "DMIC2 On A In",
195 "DMIC2 On B In",
196 "ADC2 On AB In",
197 "ADC2 On A In",
198 "ADC2 On B In",
199 "DMIC2 Off ADC2 Off",
200 };
201
202 unsigned int const input2_sel_values[] = {
203 0x0,
204 CS53L30_ADCxB_PDN,
205 CS53L30_ADCxA_PDN,
206 CS53L30_DMICx_PDN,
207 CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
208 CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
209 CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
210 };
211
212 static const char * const input1_route_sel_text[] = {
213 "ADC1_SEL", "DMIC1_SEL",
214 };
215
216 static const struct soc_enum input1_route_sel_enum =
217 SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, CS53L30_CH_TYPE_SHIFT,
218 ARRAY_SIZE(input1_route_sel_text),
219 input1_route_sel_text);
220
221 static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0,
222 CS53L30_ADCDMICx_PDN_MASK, input1_sel_text,
223 input1_sel_values);
224
225 static const struct snd_kcontrol_new input1_route_sel_mux =
226 SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum);
227
228 static const char * const input2_route_sel_text[] = {
229 "ADC2_SEL", "DMIC2_SEL",
230 };
231
232 /* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */
233 static const struct soc_enum input2_route_sel_enum =
234 SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0,
235 ARRAY_SIZE(input2_route_sel_text),
236 input2_route_sel_text);
237
238 static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0,
239 CS53L30_ADCDMICx_PDN_MASK, input2_sel_text,
240 input2_sel_values);
241
242 static const struct snd_kcontrol_new input2_route_sel_mux =
243 SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum);
244
245 /*
246 * TB = 6144*(MCLK(int) scaling factor)/MCLK(internal)
247 * TB - Time base
248 * NOTE: If MCLK_INT_SCALE = 0, then TB=1
249 */
250 static const char * const cs53l30_ng_delay_text[] = {
251 "TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms",
252 };
253
254 static const struct soc_enum adc1_ng_delay_enum =
255 SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
256 ARRAY_SIZE(cs53l30_ng_delay_text),
257 cs53l30_ng_delay_text);
258
259 static const struct soc_enum adc2_ng_delay_enum =
260 SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
261 ARRAY_SIZE(cs53l30_ng_delay_text),
262 cs53l30_ng_delay_text);
263
264 /* The noise gate threshold selected will depend on NG Boost */
265 static const char * const cs53l30_ng_thres_text[] = {
266 "-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB",
267 "-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB",
268 };
269
270 static const struct soc_enum adc1_ng_thres_enum =
271 SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
272 ARRAY_SIZE(cs53l30_ng_thres_text),
273 cs53l30_ng_thres_text);
274
275 static const struct soc_enum adc2_ng_thres_enum =
276 SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
277 ARRAY_SIZE(cs53l30_ng_thres_text),
278 cs53l30_ng_thres_text);
279
280 /* Corner frequencies are with an Fs of 48kHz. */
281 static const char * const hpf_corner_freq_text[] = {
282 "1.86Hz", "120Hz", "235Hz", "466Hz",
283 };
284
285 static const struct soc_enum adc1_hpf_enum =
286 SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
287 ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
288
289 static const struct soc_enum adc2_hpf_enum =
290 SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
291 ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
292
293 static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
294 SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP,
295 CS53L30_DIGSFT_SHIFT, 1, 0),
296 SOC_SINGLE("ADC1 Noise Gate Ganging Switch", CS53L30_ADC1_CTL3,
297 CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
298 SOC_SINGLE("ADC2 Noise Gate Ganging Switch", CS53L30_ADC2_CTL3,
299 CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
300 SOC_SINGLE("ADC1A Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
301 CS53L30_ADCxA_NG_SHIFT, 1, 0),
302 SOC_SINGLE("ADC1B Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
303 CS53L30_ADCxB_NG_SHIFT, 1, 0),
304 SOC_SINGLE("ADC2A Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
305 CS53L30_ADCxA_NG_SHIFT, 1, 0),
306 SOC_SINGLE("ADC2B Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
307 CS53L30_ADCxB_NG_SHIFT, 1, 0),
308 SOC_SINGLE("ADC1 Notch Filter Switch", CS53L30_ADCDMIC1_CTL2,
309 CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
310 SOC_SINGLE("ADC2 Notch Filter Switch", CS53L30_ADCDMIC2_CTL2,
311 CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
312 SOC_SINGLE("ADC1A Invert Switch", CS53L30_ADCDMIC1_CTL2,
313 CS53L30_ADCxA_INV_SHIFT, 1, 0),
314 SOC_SINGLE("ADC1B Invert Switch", CS53L30_ADCDMIC1_CTL2,
315 CS53L30_ADCxB_INV_SHIFT, 1, 0),
316 SOC_SINGLE("ADC2A Invert Switch", CS53L30_ADCDMIC2_CTL2,
317 CS53L30_ADCxA_INV_SHIFT, 1, 0),
318 SOC_SINGLE("ADC2B Invert Switch", CS53L30_ADCDMIC2_CTL2,
319 CS53L30_ADCxB_INV_SHIFT, 1, 0),
320
321 SOC_SINGLE_TLV("ADC1A Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
322 CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
323 SOC_SINGLE_TLV("ADC1B Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
324 CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
325 SOC_SINGLE_TLV("ADC2A Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
326 CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
327 SOC_SINGLE_TLV("ADC2B Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
328 CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
329 SOC_SINGLE_TLV("ADC1 NG Boost Volume", CS53L30_ADC1_NG_CTL,
330 CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
331 SOC_SINGLE_TLV("ADC2 NG Boost Volume", CS53L30_ADC2_NG_CTL,
332 CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
333
334 SOC_DOUBLE_R_TLV("ADC1 Pre Amp Gain", CS53L30_ADC1A_AFE_CTL,
335 CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
336 2, 0, pga_preamp_tlv),
337 SOC_DOUBLE_R_TLV("ADC2 Pre Amp Gain", CS53L30_ADC2A_AFE_CTL,
338 CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
339 2, 0, pga_preamp_tlv),
340
341 SOC_ENUM("Input 1 Channel Select", input1_sel_enum),
342 SOC_ENUM("Input 2 Channel Select", input2_sel_enum),
343
344 SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum),
345 SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum),
346 SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum),
347 SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum),
348 SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum),
349 SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
350
351 SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
352 CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
353 SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
354 CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
355 SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
356 CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
357 SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
358 CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
359
360 SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
361 CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
362 SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
363 CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
364 SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
365 CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
366 SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
367 CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
368 };
369
370 static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
371 SND_SOC_DAPM_INPUT("IN1_DMIC1"),
372 SND_SOC_DAPM_INPUT("IN2"),
373 SND_SOC_DAPM_INPUT("IN3_DMIC2"),
374 SND_SOC_DAPM_INPUT("IN4"),
375 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL,
376 CS53L30_MIC1_BIAS_PDN_SHIFT, 1, NULL, 0),
377 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL,
378 CS53L30_MIC2_BIAS_PDN_SHIFT, 1, NULL, 0),
379 SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL,
380 CS53L30_MIC3_BIAS_PDN_SHIFT, 1, NULL, 0),
381 SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL,
382 CS53L30_MIC4_BIAS_PDN_SHIFT, 1, NULL, 0),
383
384 SND_SOC_DAPM_AIF_OUT("ASP_SDOUT1", NULL, 0, CS53L30_ASP_CTL1,
385 CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
386 SND_SOC_DAPM_AIF_OUT("ASP_SDOUT2", NULL, 0, CS53L30_ASP_CTL2,
387 CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
388
389 SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0,
390 &input1_route_sel_mux),
391 SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0,
392 &input2_route_sel_mux),
393
394 SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1,
395 CS53L30_ADCxA_PDN_SHIFT, 1),
396 SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1,
397 CS53L30_ADCxB_PDN_SHIFT, 1),
398 SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1,
399 CS53L30_ADCxA_PDN_SHIFT, 1),
400 SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1,
401 CS53L30_ADCxB_PDN_SHIFT, 1),
402 SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1,
403 CS53L30_DMICx_PDN_SHIFT, 1),
404 SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1,
405 CS53L30_DMICx_PDN_SHIFT, 1),
406 };
407
408 static const struct snd_soc_dapm_route cs53l30_dapm_routes[] = {
409 /* ADC Input Paths */
410 {"ADC1A", NULL, "IN1_DMIC1"},
411 {"Input Mux 1", "ADC1_SEL", "ADC1A"},
412 {"ADC1B", NULL, "IN2"},
413
414 {"ADC2A", NULL, "IN3_DMIC2"},
415 {"Input Mux 2", "ADC2_SEL", "ADC2A"},
416 {"ADC2B", NULL, "IN4"},
417
418 /* MIC Bias Paths */
419 {"ADC1A", NULL, "MIC1 Bias"},
420 {"ADC1B", NULL, "MIC2 Bias"},
421 {"ADC2A", NULL, "MIC3 Bias"},
422 {"ADC2B", NULL, "MIC4 Bias"},
423
424 /* DMIC Paths */
425 {"DMIC1", NULL, "IN1_DMIC1"},
426 {"Input Mux 1", "DMIC1_SEL", "DMIC1"},
427
428 {"DMIC2", NULL, "IN3_DMIC2"},
429 {"Input Mux 2", "DMIC2_SEL", "DMIC2"},
430 };
431
432 static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout1[] = {
433 /* Output Paths when using SDOUT1 only */
434 {"ASP_SDOUT1", NULL, "ADC1A" },
435 {"ASP_SDOUT1", NULL, "Input Mux 1"},
436 {"ASP_SDOUT1", NULL, "ADC1B"},
437
438 {"ASP_SDOUT1", NULL, "ADC2A"},
439 {"ASP_SDOUT1", NULL, "Input Mux 2"},
440 {"ASP_SDOUT1", NULL, "ADC2B"},
441
442 {"Capture", NULL, "ASP_SDOUT1"},
443 };
444
445 static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout2[] = {
446 /* Output Paths when using both SDOUT1 and SDOUT2 */
447 {"ASP_SDOUT1", NULL, "ADC1A" },
448 {"ASP_SDOUT1", NULL, "Input Mux 1"},
449 {"ASP_SDOUT1", NULL, "ADC1B"},
450
451 {"ASP_SDOUT2", NULL, "ADC2A"},
452 {"ASP_SDOUT2", NULL, "Input Mux 2"},
453 {"ASP_SDOUT2", NULL, "ADC2B"},
454
455 {"Capture", NULL, "ASP_SDOUT1"},
456 {"Capture", NULL, "ASP_SDOUT2"},
457 };
458
459 struct cs53l30_mclk_div {
460 u32 mclk_rate;
461 u32 srate;
462 u8 asp_rate;
463 u8 internal_fs_ratio;
464 u8 mclk_int_scale;
465 };
466
467 static struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = {
468 /* NOTE: Enable MCLK_INT_SCALE to save power. */
469
470 /* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */
471 {5644800, 11025, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
472 {5644800, 22050, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
473 {5644800, 44100, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
474
475 {6000000, 8000, 0x1, 0, CS53L30_MCLK_INT_SCALE},
476 {6000000, 11025, 0x2, 0, CS53L30_MCLK_INT_SCALE},
477 {6000000, 12000, 0x4, 0, CS53L30_MCLK_INT_SCALE},
478 {6000000, 16000, 0x5, 0, CS53L30_MCLK_INT_SCALE},
479 {6000000, 22050, 0x6, 0, CS53L30_MCLK_INT_SCALE},
480 {6000000, 24000, 0x8, 0, CS53L30_MCLK_INT_SCALE},
481 {6000000, 32000, 0x9, 0, CS53L30_MCLK_INT_SCALE},
482 {6000000, 44100, 0xA, 0, CS53L30_MCLK_INT_SCALE},
483 {6000000, 48000, 0xC, 0, CS53L30_MCLK_INT_SCALE},
484
485 {6144000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
486 {6144000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
487 {6144000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
488 {6144000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
489 {6144000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
490 {6144000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
491 {6144000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
492 {6144000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
493 {6144000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
494
495 {6400000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
496 {6400000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
497 {6400000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
498 {6400000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
499 {6400000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
500 {6400000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
501 {6400000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
502 {6400000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
503 {6400000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
504 };
505
506 struct cs53l30_mclkx_div {
507 u32 mclkx;
508 u8 ratio;
509 u8 mclkdiv;
510 };
511
512 static struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = {
513 {5644800, 1, CS53L30_MCLK_DIV_BY_1},
514 {6000000, 1, CS53L30_MCLK_DIV_BY_1},
515 {6144000, 1, CS53L30_MCLK_DIV_BY_1},
516 {11289600, 2, CS53L30_MCLK_DIV_BY_2},
517 {12288000, 2, CS53L30_MCLK_DIV_BY_2},
518 {12000000, 2, CS53L30_MCLK_DIV_BY_2},
519 {19200000, 3, CS53L30_MCLK_DIV_BY_3},
520 };
521
522 static int cs53l30_get_mclkx_coeff(int mclkx)
523 {
524 int i;
525
526 for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) {
527 if (cs53l30_mclkx_coeffs[i].mclkx == mclkx)
528 return i;
529 }
530
531 return -EINVAL;
532 }
533
534 static int cs53l30_get_mclk_coeff(int mclk_rate, int srate)
535 {
536 int i;
537
538 for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) {
539 if (cs53l30_mclk_coeffs[i].mclk_rate == mclk_rate &&
540 cs53l30_mclk_coeffs[i].srate == srate)
541 return i;
542 }
543
544 return -EINVAL;
545 }
546
547 static int cs53l30_set_sysclk(struct snd_soc_dai *dai,
548 int clk_id, unsigned int freq, int dir)
549 {
550 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
551 int mclkx_coeff;
552 u32 mclk_rate;
553
554 /* MCLKX -> MCLK */
555 mclkx_coeff = cs53l30_get_mclkx_coeff(freq);
556 if (mclkx_coeff < 0)
557 return mclkx_coeff;
558
559 mclk_rate = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx /
560 cs53l30_mclkx_coeffs[mclkx_coeff].ratio;
561
562 regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
563 CS53L30_MCLK_DIV_MASK,
564 cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv);
565
566 priv->mclk_rate = mclk_rate;
567
568 return 0;
569 }
570
571 static int cs53l30_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
572 {
573 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
574 u8 aspcfg = 0, aspctl1 = 0;
575
576 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
577 case SND_SOC_DAIFMT_CBM_CFM:
578 aspcfg |= CS53L30_ASP_MS;
579 break;
580 case SND_SOC_DAIFMT_CBS_CFS:
581 break;
582 default:
583 return -EINVAL;
584 }
585
586 /* DAI mode */
587 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
588 case SND_SOC_DAIFMT_I2S:
589 /* Set TDM_PDN to turn off TDM mode -- Reset default */
590 aspctl1 |= CS53L30_ASP_TDM_PDN;
591 break;
592 case SND_SOC_DAIFMT_DSP_A:
593 /* Clear TDM_PDN and SHIFT_LEFT, invert SCLK */
594 aspcfg |= CS53L30_ASP_SCLK_INV;
595 break;
596 default:
597 return -EINVAL;
598 }
599
600 /* Check to see if the SCLK is inverted */
601 if (fmt & (SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_IB_IF))
602 aspcfg ^= CS53L30_ASP_SCLK_INV;
603
604 regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
605 CS53L30_ASP_MS | CS53L30_ASP_SCLK_INV, aspcfg);
606
607 regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
608 CS53L30_ASP_TDM_PDN | CS53L30_SHIFT_LEFT, aspctl1);
609
610 return 0;
611 }
612
613 static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream,
614 struct snd_pcm_hw_params *params,
615 struct snd_soc_dai *dai)
616 {
617 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
618 int srate = params_rate(params);
619 int mclk_coeff;
620
621 /* MCLK -> srate */
622 mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk_rate, srate);
623 if (mclk_coeff < 0)
624 return -EINVAL;
625
626 regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL,
627 CS53L30_INTRNL_FS_RATIO_MASK,
628 cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio);
629
630 regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
631 CS53L30_MCLK_INT_SCALE_MASK,
632 cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale);
633
634 regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
635 CS53L30_ASP_RATE_MASK,
636 cs53l30_mclk_coeffs[mclk_coeff].asp_rate);
637
638 return 0;
639 }
640
641 static int cs53l30_set_bias_level(struct snd_soc_codec *codec,
642 enum snd_soc_bias_level level)
643 {
644 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
645 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
646 unsigned int reg;
647 int i, inter_max_check, ret;
648
649 switch (level) {
650 case SND_SOC_BIAS_ON:
651 break;
652 case SND_SOC_BIAS_PREPARE:
653 if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
654 regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
655 CS53L30_PDN_LP_MASK, 0);
656 break;
657 case SND_SOC_BIAS_STANDBY:
658 if (dapm->bias_level == SND_SOC_BIAS_OFF) {
659 ret = clk_prepare_enable(priv->mclk);
660 if (ret) {
661 dev_err(codec->dev,
662 "failed to enable MCLK: %d\n", ret);
663 return ret;
664 }
665 regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
666 CS53L30_MCLK_DIS_MASK, 0);
667 regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
668 CS53L30_PDN_ULP_MASK, 0);
669 msleep(50);
670 } else {
671 regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
672 CS53L30_PDN_ULP_MASK,
673 CS53L30_PDN_ULP);
674 }
675 break;
676 case SND_SOC_BIAS_OFF:
677 regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
678 CS53L30_PDN_DONE, 0);
679 /*
680 * If digital softramp is set, the amount of time required
681 * for power down increases and depends on the digital
682 * volume setting.
683 */
684
685 /* Set the max possible time if digsft is set */
686 regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg);
687 if (reg & CS53L30_DIGSFT_MASK)
688 inter_max_check = CS53L30_PDN_POLL_MAX;
689 else
690 inter_max_check = 10;
691
692 regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
693 CS53L30_PDN_ULP_MASK,
694 CS53L30_PDN_ULP);
695 /* PDN_DONE will take a min of 20ms to be set.*/
696 msleep(20);
697 /* Clr status */
698 regmap_read(priv->regmap, CS53L30_IS, &reg);
699 for (i = 0; i < inter_max_check; i++) {
700 if (inter_max_check < 10) {
701 usleep_range(1000, 1100);
702 regmap_read(priv->regmap, CS53L30_IS, &reg);
703 if (reg & CS53L30_PDN_DONE)
704 break;
705 } else {
706 usleep_range(10000, 10100);
707 regmap_read(priv->regmap, CS53L30_IS, &reg);
708 if (reg & CS53L30_PDN_DONE)
709 break;
710 }
711 }
712 /* PDN_DONE is set. We now can disable the MCLK */
713 regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
714 CS53L30_PDN_DONE, CS53L30_PDN_DONE);
715 regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
716 CS53L30_MCLK_DIS_MASK,
717 CS53L30_MCLK_DIS);
718 clk_disable_unprepare(priv->mclk);
719 break;
720 }
721
722 return 0;
723 }
724
725 static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate)
726 {
727 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
728 u8 val = tristate ? CS53L30_ASP_3ST : 0;
729
730 return regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
731 CS53L30_ASP_3ST_MASK, val);
732 }
733
734 unsigned int const cs53l30_src_rates[] = {
735 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
736 };
737
738 static struct snd_pcm_hw_constraint_list src_constraints = {
739 .count = ARRAY_SIZE(cs53l30_src_rates),
740 .list = cs53l30_src_rates,
741 };
742
743 static int cs53l30_pcm_startup(struct snd_pcm_substream *substream,
744 struct snd_soc_dai *dai)
745 {
746 snd_pcm_hw_constraint_list(substream->runtime, 0,
747 SNDRV_PCM_HW_PARAM_RATE, &src_constraints);
748
749 return 0;
750 }
751
752 /*
753 * Note: CS53L30 counts the slot number per byte while ASoC counts the slot
754 * number per slot_width. So there is a difference between the slots of ASoC
755 * and the slots of CS53L30.
756 */
757 static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai,
758 unsigned int tx_mask, unsigned int rx_mask,
759 int slots, int slot_width)
760 {
761 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
762 unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48};
763 unsigned int slot_next, slot_step;
764 u64 tx_enable = 0;
765 int i;
766
767 if (!rx_mask) {
768 dev_err(dai->dev, "rx masks must not be 0\n");
769 return -EINVAL;
770 }
771
772 /* Assuming slot_width is not supposed to be greater than 64 */
773 if (slots <= 0 || slot_width <= 0 || slot_width > 64) {
774 dev_err(dai->dev, "invalid slot number or slot width\n");
775 return -EINVAL;
776 }
777
778 if (slot_width & 0x7) {
779 dev_err(dai->dev, "slot width must count in byte\n");
780 return -EINVAL;
781 }
782
783 /* How many bytes in each ASoC slot */
784 slot_step = slot_width >> 3;
785
786 for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) {
787 /* Find the first slot from LSB */
788 slot_next = __ffs(rx_mask);
789 /* Save the slot location by converting to CS53L30 slot */
790 loc[i] = slot_next * slot_step;
791 /* Create the mask of CS53L30 slot */
792 tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i];
793 /* Clear this slot from rx_mask */
794 rx_mask &= ~(1 << slot_next);
795 }
796
797 /* Error out to avoid slot shift */
798 if (rx_mask && i == CS53L30_TDM_SLOT_MAX) {
799 dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n",
800 CS53L30_TDM_SLOT_MAX);
801 return -EINVAL;
802 }
803
804 /* Validate the last CS53L30 slot */
805 slot_next = loc[CS53L30_TDM_SLOT_MAX - 1] + slot_step - 1;
806 if (slot_next > 47) {
807 dev_err(dai->dev, "slot selection out of bounds: %u\n",
808 slot_next);
809 return -EINVAL;
810 }
811
812 for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) {
813 regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i),
814 CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]);
815 dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]);
816 }
817
818 for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) {
819 regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i),
820 tx_enable & 0xff);
821 tx_enable >>= 8;
822 dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n",
823 CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff);
824 }
825
826 return 0;
827 }
828
829 /* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
830 #define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
831
832 #define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
833 SNDRV_PCM_FMTBIT_S24_LE)
834
835 static const struct snd_soc_dai_ops cs53l30_ops = {
836 .startup = cs53l30_pcm_startup,
837 .hw_params = cs53l30_pcm_hw_params,
838 .set_fmt = cs53l30_set_dai_fmt,
839 .set_sysclk = cs53l30_set_sysclk,
840 .set_tristate = cs53l30_set_tristate,
841 .set_tdm_slot = cs53l30_set_dai_tdm_slot,
842 };
843
844 static struct snd_soc_dai_driver cs53l30_dai = {
845 .name = "cs53l30",
846 .capture = {
847 .stream_name = "Capture",
848 .channels_min = 1,
849 .channels_max = 4,
850 .rates = CS53L30_RATES,
851 .formats = CS53L30_FORMATS,
852 },
853 .ops = &cs53l30_ops,
854 .symmetric_rates = 1,
855 };
856
857 static int cs53l30_codec_probe(struct snd_soc_codec *codec)
858 {
859 struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
860 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
861
862 if (priv->use_sdout2)
863 snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout2,
864 ARRAY_SIZE(cs53l30_dapm_routes_sdout2));
865 else
866 snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout1,
867 ARRAY_SIZE(cs53l30_dapm_routes_sdout1));
868
869 return 0;
870 }
871
872 static struct snd_soc_codec_driver cs53l30_driver = {
873 .probe = cs53l30_codec_probe,
874 .set_bias_level = cs53l30_set_bias_level,
875
876 .dapm_widgets = cs53l30_dapm_widgets,
877 .num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets),
878 .dapm_routes = cs53l30_dapm_routes,
879 .num_dapm_routes = ARRAY_SIZE(cs53l30_dapm_routes),
880
881 .controls = cs53l30_snd_controls,
882 .num_controls = ARRAY_SIZE(cs53l30_snd_controls),
883 };
884
885 static struct regmap_config cs53l30_regmap = {
886 .reg_bits = 8,
887 .val_bits = 8,
888
889 .max_register = CS53L30_MAX_REGISTER,
890 .reg_defaults = cs53l30_reg_defaults,
891 .num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults),
892 .volatile_reg = cs53l30_volatile_register,
893 .writeable_reg = cs53l30_writeable_register,
894 .readable_reg = cs53l30_readable_register,
895 .cache_type = REGCACHE_RBTREE,
896 };
897
898 static int cs53l30_i2c_probe(struct i2c_client *client,
899 const struct i2c_device_id *id)
900 {
901 const struct device_node *np = client->dev.of_node;
902 struct device *dev = &client->dev;
903 struct cs53l30_private *cs53l30;
904 unsigned int devid = 0;
905 unsigned int reg;
906 int ret = 0, i;
907 u8 val;
908
909 cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL);
910 if (!cs53l30)
911 return -ENOMEM;
912
913 for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++)
914 cs53l30->supplies[i].supply = cs53l30_supply_names[i];
915
916 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies),
917 cs53l30->supplies);
918 if (ret) {
919 dev_err(dev, "failed to get supplies: %d\n", ret);
920 return ret;
921 }
922
923 ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
924 cs53l30->supplies);
925 if (ret) {
926 dev_err(dev, "failed to enable supplies: %d\n", ret);
927 return ret;
928 }
929
930 /* Reset the Device */
931 cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset",
932 GPIOD_OUT_LOW);
933 if (IS_ERR(cs53l30->reset_gpio)) {
934 ret = PTR_ERR(cs53l30->reset_gpio);
935 goto error;
936 }
937
938 if (cs53l30->reset_gpio)
939 gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
940
941 i2c_set_clientdata(client, cs53l30);
942
943 cs53l30->mclk_rate = 0;
944
945 cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap);
946 if (IS_ERR(cs53l30->regmap)) {
947 ret = PTR_ERR(cs53l30->regmap);
948 dev_err(dev, "regmap_init() failed: %d\n", ret);
949 goto error;
950 }
951
952 /* Initialize codec */
953 ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg);
954 devid = reg << 12;
955
956 ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg);
957 devid |= reg << 4;
958
959 ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg);
960 devid |= (reg & 0xF0) >> 4;
961
962 if (devid != CS53L30_DEVID) {
963 ret = -ENODEV;
964 dev_err(dev, "Device ID (%X). Expected %X\n",
965 devid, CS53L30_DEVID);
966 goto error;
967 }
968
969 ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg);
970 if (ret < 0) {
971 dev_err(dev, "failed to get Revision ID: %d\n", ret);
972 goto error;
973 }
974
975 /* Check if MCLK provided */
976 cs53l30->mclk = devm_clk_get(dev, "mclk");
977 if (IS_ERR(cs53l30->mclk)) {
978 if (PTR_ERR(cs53l30->mclk) == -EPROBE_DEFER) {
979 ret = -EPROBE_DEFER;
980 goto error;
981 }
982 /* Otherwise mark the mclk pointer to NULL */
983 cs53l30->mclk = NULL;
984 }
985
986 if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val))
987 regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL,
988 CS53L30_MIC_BIAS_CTRL_MASK, val);
989
990 if (of_property_read_bool(np, "cirrus,use-sdout2"))
991 cs53l30->use_sdout2 = true;
992
993 dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF);
994
995 ret = snd_soc_register_codec(dev, &cs53l30_driver, &cs53l30_dai, 1);
996 if (ret) {
997 dev_err(dev, "failed to register codec: %d\n", ret);
998 goto error;
999 }
1000
1001 return 0;
1002
1003 error:
1004 regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
1005 cs53l30->supplies);
1006 return ret;
1007 }
1008
1009 static int cs53l30_i2c_remove(struct i2c_client *client)
1010 {
1011 struct cs53l30_private *cs53l30 = i2c_get_clientdata(client);
1012
1013 snd_soc_unregister_codec(&client->dev);
1014
1015 /* Hold down reset */
1016 if (cs53l30->reset_gpio)
1017 gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
1018
1019 regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
1020 cs53l30->supplies);
1021
1022 return 0;
1023 }
1024
1025 #ifdef CONFIG_PM
1026 static int cs53l30_runtime_suspend(struct device *dev)
1027 {
1028 struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
1029
1030 regcache_cache_only(cs53l30->regmap, true);
1031
1032 /* Hold down reset */
1033 if (cs53l30->reset_gpio)
1034 gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
1035
1036 regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
1037 cs53l30->supplies);
1038
1039 return 0;
1040 }
1041
1042 static int cs53l30_runtime_resume(struct device *dev)
1043 {
1044 struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
1045 int ret;
1046
1047 ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
1048 cs53l30->supplies);
1049 if (ret) {
1050 dev_err(dev, "failed to enable supplies: %d\n", ret);
1051 return ret;
1052 }
1053
1054 if (cs53l30->reset_gpio)
1055 gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
1056
1057 regcache_cache_only(cs53l30->regmap, false);
1058 regcache_sync(cs53l30->regmap);
1059
1060 return 0;
1061 }
1062 #endif
1063
1064 static const struct dev_pm_ops cs53l30_runtime_pm = {
1065 SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume,
1066 NULL)
1067 };
1068
1069 static const struct of_device_id cs53l30_of_match[] = {
1070 { .compatible = "cirrus,cs53l30", },
1071 {},
1072 };
1073
1074 MODULE_DEVICE_TABLE(of, cs53l30_of_match);
1075
1076 static const struct i2c_device_id cs53l30_id[] = {
1077 { "cs53l30", 0 },
1078 {}
1079 };
1080
1081 MODULE_DEVICE_TABLE(i2c, cs53l30_id);
1082
1083 static struct i2c_driver cs53l30_i2c_driver = {
1084 .driver = {
1085 .name = "cs53l30",
1086 .pm = &cs53l30_runtime_pm,
1087 },
1088 .id_table = cs53l30_id,
1089 .probe = cs53l30_i2c_probe,
1090 .remove = cs53l30_i2c_remove,
1091 };
1092
1093 module_i2c_driver(cs53l30_i2c_driver);
1094
1095 MODULE_DESCRIPTION("ASoC CS53L30 driver");
1096 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
1097 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.074186 seconds and 5 git commands to generate.