sound/soc/codecs/es8328.c

   1 /*
   2  * es8328.c  --  ES8328 ALSA SoC Audio driver
   3  *
   4  * Copyright 2014 Sutajio Ko-Usagi PTE LTD
   5  *
   6  * Author: Sean Cross <xobs@kosagi.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/of_device.h>
  16 #include <linux/module.h>
  17 #include <linux/pm.h>
  18 #include <linux/regmap.h>
  19 #include <linux/slab.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <sound/core.h>
  22 #include <sound/initval.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/tlv.h>
  27 #include "es8328.h"
  28
  29 #define ES8328_SYSCLK_RATE_1X 11289600
  30 #define ES8328_SYSCLK_RATE_2X 22579200
  31
  32 /* Run the codec at 22.5792 or 11.2896 MHz to support these rates */
  33 static struct {
  34         int rate;
  35         u8 ratio;
  36 } mclk_ratios[] = {
  37         { 8000, 9 },
  38         {11025, 7 },
  39         {22050, 4 },
  40         {44100, 2 },
  41 };
  42
  43 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
  44 enum sgtl5000_regulator_supplies {
  45         DVDD,
  46         AVDD,
  47         PVDD,
  48         HPVDD,
  49         ES8328_SUPPLY_NUM
  50 };
  51
  52 /* vddd is optional supply */
  53 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
  54         "DVDD",
  55         "AVDD",
  56         "PVDD",
  57         "HPVDD",
  58 };
  59
  60 #define ES8328_RATES (SNDRV_PCM_RATE_44100 | \
  61                 SNDRV_PCM_RATE_22050 | \
  62                 SNDRV_PCM_RATE_11025)
  63 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  64                 SNDRV_PCM_FMTBIT_S18_3LE | \
  65                 SNDRV_PCM_FMTBIT_S20_3LE | \
  66                 SNDRV_PCM_FMTBIT_S24_LE | \
  67                 SNDRV_PCM_FMTBIT_S32_LE)
  68
  69 struct es8328_priv {
  70         struct regmap *regmap;
  71         struct clk *clk;
  72         int playback_fs;
  73         bool deemph;
  74         struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
  75 };
  76
  77 /*
  78  * ES8328 Controls
  79  */
  80
  81 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
  82                                           "L + R Invert"};
  83 static SOC_ENUM_SINGLE_DECL(adcpol,
  84                             ES8328_ADCCONTROL6, 6, adcpol_txt);
  85
  86 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
  87 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
  88 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
  89 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  90 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
  91
  92 static const struct {
  93         int rate;
  94         unsigned int val;
  95 } deemph_settings[] = {
  96         { 0,     ES8328_DACCONTROL6_DEEMPH_OFF },
  97         { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
  98         { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
  99         { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
 100 };
 101
 102 static int es8328_set_deemph(struct snd_soc_codec *codec)
 103 {
 104         struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec);
 105         int val, i, best;
 106
 107         /*
 108          * If we're using deemphasis select the nearest available sample
 109          * rate.
 110          */
 111         if (es8328->deemph) {
 112                 best = 0;
 113                 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
 114                         if (abs(deemph_settings[i].rate - es8328->playback_fs) <
 115                             abs(deemph_settings[best].rate - es8328->playback_fs))
 116                                 best = i;
 117                 }
 118
 119                 val = deemph_settings[best].val;
 120         } else {
 121                 val = ES8328_DACCONTROL6_DEEMPH_OFF;
 122         }
 123
 124         dev_dbg(codec->dev, "Set deemphasis %d\n", val);
 125
 126         return snd_soc_update_bits(codec, ES8328_DACCONTROL6,
 127                         ES8328_DACCONTROL6_DEEMPH_MASK, val);
 128 }
 129
 130 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
 131                              struct snd_ctl_elem_value *ucontrol)
 132 {
 133         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 134         struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec);
 135
 136         ucontrol->value.integer.value[0] = es8328->deemph;
 137         return 0;
 138 }
 139
 140 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
 141                              struct snd_ctl_elem_value *ucontrol)
 142 {
 143         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 144         struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec);
 145         unsigned int deemph = ucontrol->value.integer.value[0];
 146         int ret;
 147
 148         if (deemph > 1)
 149                 return -EINVAL;
 150
 151         ret = es8328_set_deemph(codec);
 152         if (ret < 0)
 153                 return ret;
 154
 155         es8328->deemph = deemph;
 156
 157         return 0;
 158 }
 159
 160
 161
 162 static const struct snd_kcontrol_new es8328_snd_controls[] = {
 163         SOC_DOUBLE_R_TLV("Capture Digital Volume",
 164                 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
 165                  0, 0xc0, 1, dac_adc_tlv),
 166         SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
 167
 168         SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
 169                     es8328_get_deemph, es8328_put_deemph),
 170
 171         SOC_ENUM("Capture Polarity", adcpol),
 172
 173         SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
 174                         ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
 175         SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
 176                         ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
 177         SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
 178                         ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
 179         SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
 180                         ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
 181
 182         SOC_DOUBLE_R_TLV("PCM Volume",
 183                         ES8328_LDACVOL, ES8328_RDACVOL,
 184                         0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
 185
 186         SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
 187                         ES8328_LOUT1VOL, ES8328_ROUT1VOL,
 188                         0, ES8328_OUT1VOL_MAX, 0, play_tlv),
 189
 190         SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
 191                         ES8328_LOUT2VOL, ES8328_ROUT2VOL,
 192                         0, ES8328_OUT2VOL_MAX, 0, play_tlv),
 193
 194         SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
 195                         4, 0, 8, 0, mic_tlv),
 196 };
 197
 198 /*
 199  * DAPM Controls
 200  */
 201
 202 static const char * const es8328_line_texts[] = {
 203         "Line 1", "Line 2", "PGA", "Differential"};
 204
 205 static const struct soc_enum es8328_lline_enum =
 206         SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
 207                               ARRAY_SIZE(es8328_line_texts),
 208                               es8328_line_texts);
 209 static const struct snd_kcontrol_new es8328_left_line_controls =
 210         SOC_DAPM_ENUM("Route", es8328_lline_enum);
 211
 212 static const struct soc_enum es8328_rline_enum =
 213         SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
 214                               ARRAY_SIZE(es8328_line_texts),
 215                               es8328_line_texts);
 216 static const struct snd_kcontrol_new es8328_right_line_controls =
 217         SOC_DAPM_ENUM("Route", es8328_lline_enum);
 218
 219 /* Left Mixer */
 220 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
 221         SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
 222         SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
 223         SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
 224         SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
 225 };
 226
 227 /* Right Mixer */
 228 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
 229         SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
 230         SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
 231         SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
 232         SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
 233 };
 234
 235 static const char * const es8328_pga_sel[] = {
 236         "Line 1", "Line 2", "Line 3", "Differential"};
 237
 238 /* Left PGA Mux */
 239 static const struct soc_enum es8328_lpga_enum =
 240         SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
 241                               ARRAY_SIZE(es8328_pga_sel),
 242                               es8328_pga_sel);
 243 static const struct snd_kcontrol_new es8328_left_pga_controls =
 244         SOC_DAPM_ENUM("Route", es8328_lpga_enum);
 245
 246 /* Right PGA Mux */
 247 static const struct soc_enum es8328_rpga_enum =
 248         SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
 249                               ARRAY_SIZE(es8328_pga_sel),
 250                               es8328_pga_sel);
 251 static const struct snd_kcontrol_new es8328_right_pga_controls =
 252         SOC_DAPM_ENUM("Route", es8328_rpga_enum);
 253
 254 /* Differential Mux */
 255 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
 256 static SOC_ENUM_SINGLE_DECL(diffmux,
 257                             ES8328_ADCCONTROL3, 7, es8328_diff_sel);
 258 static const struct snd_kcontrol_new es8328_diffmux_controls =
 259         SOC_DAPM_ENUM("Route", diffmux);
 260
 261 /* Mono ADC Mux */
 262 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
 263         "Mono (Right)", "Digital Mono"};
 264 static SOC_ENUM_SINGLE_DECL(monomux,
 265                             ES8328_ADCCONTROL3, 3, es8328_mono_mux);
 266 static const struct snd_kcontrol_new es8328_monomux_controls =
 267         SOC_DAPM_ENUM("Route", monomux);
 268
 269 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
 270         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
 271                 &es8328_diffmux_controls),
 272         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
 273                 &es8328_monomux_controls),
 274         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
 275                 &es8328_monomux_controls),
 276
 277         SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
 278                         ES8328_ADCPOWER_AINL_OFF, 1,
 279                         &es8328_left_pga_controls),
 280         SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
 281                         ES8328_ADCPOWER_AINR_OFF, 1,
 282                         &es8328_right_pga_controls),
 283
 284         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
 285                 &es8328_left_line_controls),
 286         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
 287                 &es8328_right_line_controls),
 288
 289         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
 290                         ES8328_ADCPOWER_ADCR_OFF, 1),
 291         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
 292                         ES8328_ADCPOWER_ADCL_OFF, 1),
 293
 294         SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
 295                         ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
 296         SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
 297                         ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
 298
 299         SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
 300                         ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
 301         SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
 302                         ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
 303
 304         SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
 305                         ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
 306         SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
 307                         ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
 308
 309         SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
 310                         ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
 311         SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
 312                         ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
 313
 314         SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
 315                         ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
 316         SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
 317                         ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
 318
 319         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
 320                         ES8328_DACPOWER_RDAC_OFF, 1),
 321         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
 322                         ES8328_DACPOWER_LDAC_OFF, 1),
 323
 324         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 325                 &es8328_left_mixer_controls[0],
 326                 ARRAY_SIZE(es8328_left_mixer_controls)),
 327         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 328                 &es8328_right_mixer_controls[0],
 329                 ARRAY_SIZE(es8328_right_mixer_controls)),
 330
 331         SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
 332                         ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
 333         SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
 334                         ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
 335         SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
 336                         ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
 337         SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
 338                         ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
 339
 340         SND_SOC_DAPM_OUTPUT("LOUT1"),
 341         SND_SOC_DAPM_OUTPUT("ROUT1"),
 342         SND_SOC_DAPM_OUTPUT("LOUT2"),
 343         SND_SOC_DAPM_OUTPUT("ROUT2"),
 344
 345         SND_SOC_DAPM_INPUT("LINPUT1"),
 346         SND_SOC_DAPM_INPUT("LINPUT2"),
 347         SND_SOC_DAPM_INPUT("RINPUT1"),
 348         SND_SOC_DAPM_INPUT("RINPUT2"),
 349 };
 350
 351 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
 352
 353         { "Left Line Mux", "Line 1", "LINPUT1" },
 354         { "Left Line Mux", "Line 2", "LINPUT2" },
 355         { "Left Line Mux", "PGA", "Left PGA Mux" },
 356         { "Left Line Mux", "Differential", "Differential Mux" },
 357
 358         { "Right Line Mux", "Line 1", "RINPUT1" },
 359         { "Right Line Mux", "Line 2", "RINPUT2" },
 360         { "Right Line Mux", "PGA", "Right PGA Mux" },
 361         { "Right Line Mux", "Differential", "Differential Mux" },
 362
 363         { "Left PGA Mux", "Line 1", "LINPUT1" },
 364         { "Left PGA Mux", "Line 2", "LINPUT2" },
 365         { "Left PGA Mux", "Differential", "Differential Mux" },
 366
 367         { "Right PGA Mux", "Line 1", "RINPUT1" },
 368         { "Right PGA Mux", "Line 2", "RINPUT2" },
 369         { "Right PGA Mux", "Differential", "Differential Mux" },
 370
 371         { "Differential Mux", "Line 1", "LINPUT1" },
 372         { "Differential Mux", "Line 1", "RINPUT1" },
 373         { "Differential Mux", "Line 2", "LINPUT2" },
 374         { "Differential Mux", "Line 2", "RINPUT2" },
 375
 376         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
 377         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
 378         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
 379
 380         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
 381         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
 382         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
 383
 384         { "Left ADC", NULL, "Left ADC Mux" },
 385         { "Right ADC", NULL, "Right ADC Mux" },
 386
 387         { "ADC DIG", NULL, "ADC STM" },
 388         { "ADC DIG", NULL, "ADC Vref" },
 389         { "ADC DIG", NULL, "ADC DLL" },
 390
 391         { "Left ADC", NULL, "ADC DIG" },
 392         { "Right ADC", NULL, "ADC DIG" },
 393
 394         { "Mic Bias", NULL, "Mic Bias Gen" },
 395
 396         { "Left Line Mux", "Line 1", "LINPUT1" },
 397         { "Left Line Mux", "Line 2", "LINPUT2" },
 398         { "Left Line Mux", "PGA", "Left PGA Mux" },
 399         { "Left Line Mux", "Differential", "Differential Mux" },
 400
 401         { "Right Line Mux", "Line 1", "RINPUT1" },
 402         { "Right Line Mux", "Line 2", "RINPUT2" },
 403         { "Right Line Mux", "PGA", "Right PGA Mux" },
 404         { "Right Line Mux", "Differential", "Differential Mux" },
 405
 406         { "Left Out 1", NULL, "Left DAC" },
 407         { "Right Out 1", NULL, "Right DAC" },
 408         { "Left Out 2", NULL, "Left DAC" },
 409         { "Right Out 2", NULL, "Right DAC" },
 410
 411         { "Left Mixer", "Playback Switch", "Left DAC" },
 412         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
 413         { "Left Mixer", "Right Playback Switch", "Right DAC" },
 414         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
 415
 416         { "Right Mixer", "Left Playback Switch", "Left DAC" },
 417         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
 418         { "Right Mixer", "Playback Switch", "Right DAC" },
 419         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
 420
 421         { "DAC DIG", NULL, "DAC STM" },
 422         { "DAC DIG", NULL, "DAC Vref" },
 423         { "DAC DIG", NULL, "DAC DLL" },
 424
 425         { "Left DAC", NULL, "DAC DIG" },
 426         { "Right DAC", NULL, "DAC DIG" },
 427
 428         { "Left Out 1", NULL, "Left Mixer" },
 429         { "LOUT1", NULL, "Left Out 1" },
 430         { "Right Out 1", NULL, "Right Mixer" },
 431         { "ROUT1", NULL, "Right Out 1" },
 432
 433         { "Left Out 2", NULL, "Left Mixer" },
 434         { "LOUT2", NULL, "Left Out 2" },
 435         { "Right Out 2", NULL, "Right Mixer" },
 436         { "ROUT2", NULL, "Right Out 2" },
 437 };
 438
 439 static int es8328_mute(struct snd_soc_dai *dai, int mute)
 440 {
 441         return snd_soc_update_bits(dai->codec, ES8328_DACCONTROL3,
 442                         ES8328_DACCONTROL3_DACMUTE,
 443                         mute ? ES8328_DACCONTROL3_DACMUTE : 0);
 444 }
 445
 446 static int es8328_hw_params(struct snd_pcm_substream *substream,
 447         struct snd_pcm_hw_params *params,
 448         struct snd_soc_dai *dai)
 449 {
 450         struct snd_soc_codec *codec = dai->codec;
 451         struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec);
 452         int clk_rate = clk_get_rate(es8328->clk);
 453         int i;
 454         int reg;
 455         int val;
 456         int wl;
 457         u8 ratio;
 458
 459         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 460                 reg = ES8328_DACCONTROL2;
 461         else
 462                 reg = ES8328_ADCCONTROL5;
 463
 464         switch (clk_rate) {
 465         case ES8328_SYSCLK_RATE_1X:
 466                 val = 0;
 467                 break;
 468         case ES8328_SYSCLK_RATE_2X:
 469                 val = ES8328_MASTERMODE_MCLKDIV2;
 470                 break;
 471         default:
 472                 dev_err(codec->dev,
 473                         "%s: clock is running at %d Hz, not %d or %d Hz\n",
 474                          __func__, clk_rate,
 475                          ES8328_SYSCLK_RATE_1X, ES8328_SYSCLK_RATE_2X);
 476                 return -EINVAL;
 477         }
 478         snd_soc_update_bits(codec, ES8328_MASTERMODE,
 479                         ES8328_MASTERMODE_MCLKDIV2, val);
 480
 481         switch (params_width(params)) {
 482         case 16:
 483                 wl = 3;
 484                 break;
 485         case 18:
 486                 wl = 2;
 487                 break;
 488         case 20:
 489                 wl = 1;
 490                 break;
 491         case 24:
 492                 wl = 0;
 493                 break;
 494         case 32:
 495                 wl = 4;
 496                 break;
 497         default:
 498                 return -EINVAL;
 499         }
 500
 501         /* find master mode MCLK to sampling frequency ratio */
 502         ratio = mclk_ratios[0].rate;
 503         for (i = 1; i < ARRAY_SIZE(mclk_ratios); i++)
 504                 if (params_rate(params) <= mclk_ratios[i].rate)
 505                         ratio = mclk_ratios[i].ratio;
 506
 507         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 508                 snd_soc_update_bits(codec, ES8328_DACCONTROL1,
 509                                 ES8328_DACCONTROL1_DACWL_MASK,
 510                                 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
 511
 512                 es8328->playback_fs = params_rate(params);
 513                 es8328_set_deemph(codec);
 514         } else
 515                 snd_soc_update_bits(codec, ES8328_ADCCONTROL4,
 516                                 ES8328_ADCCONTROL4_ADCWL_MASK,
 517                                 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
 518
 519         return snd_soc_update_bits(codec, reg, ES8328_RATEMASK, ratio);
 520 }
 521
 522 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
 523                 unsigned int fmt)
 524 {
 525         struct snd_soc_codec *codec = codec_dai->codec;
 526         u8 dac_mode = 0;
 527         u8 adc_mode = 0;
 528
 529         /* set master/slave audio interface */
 530         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM)
 531                 return -EINVAL;
 532
 533         /* interface format */
 534         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 535         case SND_SOC_DAIFMT_I2S:
 536                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
 537                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
 538                 break;
 539         case SND_SOC_DAIFMT_RIGHT_J:
 540                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
 541                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
 542                 break;
 543         case SND_SOC_DAIFMT_LEFT_J:
 544                 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
 545                 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         /* clock inversion */
 552         if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
 553                 return -EINVAL;
 554
 555         snd_soc_update_bits(codec, ES8328_DACCONTROL1,
 556                         ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
 557         snd_soc_update_bits(codec, ES8328_ADCCONTROL4,
 558                         ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
 559
 560         /* Master serial port mode, with BCLK generated automatically */
 561         snd_soc_update_bits(codec, ES8328_MASTERMODE,
 562                         ES8328_MASTERMODE_MSC, ES8328_MASTERMODE_MSC);
 563
 564         return 0;
 565 }
 566
 567 static int es8328_set_bias_level(struct snd_soc_codec *codec,
 568                                  enum snd_soc_bias_level level)
 569 {
 570         switch (level) {
 571         case SND_SOC_BIAS_ON:
 572                 break;
 573
 574         case SND_SOC_BIAS_PREPARE:
 575                 /* VREF, VMID=2x50k, digital enabled */
 576                 snd_soc_write(codec, ES8328_CHIPPOWER, 0);
 577                 snd_soc_update_bits(codec, ES8328_CONTROL1,
 578                                 ES8328_CONTROL1_VMIDSEL_MASK |
 579                                 ES8328_CONTROL1_ENREF,
 580                                 ES8328_CONTROL1_VMIDSEL_50k |
 581                                 ES8328_CONTROL1_ENREF);
 582                 break;
 583
 584         case SND_SOC_BIAS_STANDBY:
 585                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 586                         snd_soc_update_bits(codec, ES8328_CONTROL1,
 587                                         ES8328_CONTROL1_VMIDSEL_MASK |
 588                                         ES8328_CONTROL1_ENREF,
 589                                         ES8328_CONTROL1_VMIDSEL_5k |
 590                                         ES8328_CONTROL1_ENREF);
 591
 592                         /* Charge caps */
 593                         msleep(100);
 594                 }
 595
 596                 snd_soc_write(codec, ES8328_CONTROL2,
 597                                 ES8328_CONTROL2_OVERCURRENT_ON |
 598                                 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
 599
 600                 /* VREF, VMID=2*500k, digital stopped */
 601                 snd_soc_update_bits(codec, ES8328_CONTROL1,
 602                                 ES8328_CONTROL1_VMIDSEL_MASK |
 603                                 ES8328_CONTROL1_ENREF,
 604                                 ES8328_CONTROL1_VMIDSEL_500k |
 605                                 ES8328_CONTROL1_ENREF);
 606                 break;
 607
 608         case SND_SOC_BIAS_OFF:
 609                 snd_soc_update_bits(codec, ES8328_CONTROL1,
 610                                 ES8328_CONTROL1_VMIDSEL_MASK |
 611                                 ES8328_CONTROL1_ENREF,
 612                                 0);
 613                 break;
 614         }
 615         return 0;
 616 }
 617
 618 static const struct snd_soc_dai_ops es8328_dai_ops = {
 619         .hw_params      = es8328_hw_params,
 620         .digital_mute   = es8328_mute,
 621         .set_fmt        = es8328_set_dai_fmt,
 622 };
 623
 624 static struct snd_soc_dai_driver es8328_dai = {
 625         .name = "es8328-hifi-analog",
 626         .playback = {
 627                 .stream_name = "Playback",
 628                 .channels_min = 2,
 629                 .channels_max = 2,
 630                 .rates = ES8328_RATES,
 631                 .formats = ES8328_FORMATS,
 632         },
 633         .capture = {
 634                 .stream_name = "Capture",
 635                 .channels_min = 2,
 636                 .channels_max = 2,
 637                 .rates = ES8328_RATES,
 638                 .formats = ES8328_FORMATS,
 639         },
 640         .ops = &es8328_dai_ops,
 641 };
 642
 643 static int es8328_suspend(struct snd_soc_codec *codec)
 644 {
 645         struct es8328_priv *es8328;
 646         int ret;
 647
 648         es8328 = snd_soc_codec_get_drvdata(codec);
 649
 650         clk_disable_unprepare(es8328->clk);
 651
 652         ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 653                         es8328->supplies);
 654         if (ret) {
 655                 dev_err(codec->dev, "unable to disable regulators\n");
 656                 return ret;
 657         }
 658         return 0;
 659 }
 660
 661 static int es8328_resume(struct snd_soc_codec *codec)
 662 {
 663         struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
 664         struct es8328_priv *es8328;
 665         int ret;
 666
 667         es8328 = snd_soc_codec_get_drvdata(codec);
 668
 669         ret = clk_prepare_enable(es8328->clk);
 670         if (ret) {
 671                 dev_err(codec->dev, "unable to enable clock\n");
 672                 return ret;
 673         }
 674
 675         ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
 676                                         es8328->supplies);
 677         if (ret) {
 678                 dev_err(codec->dev, "unable to enable regulators\n");
 679                 return ret;
 680         }
 681
 682         regcache_mark_dirty(regmap);
 683         ret = regcache_sync(regmap);
 684         if (ret) {
 685                 dev_err(codec->dev, "unable to sync regcache\n");
 686                 return ret;
 687         }
 688
 689         return 0;
 690 }
 691
 692 static int es8328_codec_probe(struct snd_soc_codec *codec)
 693 {
 694         struct es8328_priv *es8328;
 695         int ret;
 696
 697         es8328 = snd_soc_codec_get_drvdata(codec);
 698
 699         ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
 700                                         es8328->supplies);
 701         if (ret) {
 702                 dev_err(codec->dev, "unable to enable regulators\n");
 703                 return ret;
 704         }
 705
 706         /* Setup clocks */
 707         es8328->clk = devm_clk_get(codec->dev, NULL);
 708         if (IS_ERR(es8328->clk)) {
 709                 dev_err(codec->dev, "codec clock missing or invalid\n");
 710                 ret = PTR_ERR(es8328->clk);
 711                 goto clk_fail;
 712         }
 713
 714         ret = clk_prepare_enable(es8328->clk);
 715         if (ret) {
 716                 dev_err(codec->dev, "unable to prepare codec clk\n");
 717                 goto clk_fail;
 718         }
 719
 720         return 0;
 721
 722 clk_fail:
 723         regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 724                                es8328->supplies);
 725         return ret;
 726 }
 727
 728 static int es8328_remove(struct snd_soc_codec *codec)
 729 {
 730         struct es8328_priv *es8328;
 731
 732         es8328 = snd_soc_codec_get_drvdata(codec);
 733
 734         if (es8328->clk)
 735                 clk_disable_unprepare(es8328->clk);
 736
 737         regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
 738                                es8328->supplies);
 739
 740         return 0;
 741 }
 742
 743 const struct regmap_config es8328_regmap_config = {
 744         .reg_bits       = 8,
 745         .val_bits       = 8,
 746         .max_register   = ES8328_REG_MAX,
 747         .cache_type     = REGCACHE_RBTREE,
 748         .use_single_rw  = true,
 749 };
 750 EXPORT_SYMBOL_GPL(es8328_regmap_config);
 751
 752 static struct snd_soc_codec_driver es8328_codec_driver = {
 753         .probe            = es8328_codec_probe,
 754         .suspend          = es8328_suspend,
 755         .resume           = es8328_resume,
 756         .remove           = es8328_remove,
 757         .set_bias_level   = es8328_set_bias_level,
 758         .suspend_bias_off = true,
 759
 760         .controls         = es8328_snd_controls,
 761         .num_controls     = ARRAY_SIZE(es8328_snd_controls),
 762         .dapm_widgets     = es8328_dapm_widgets,
 763         .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
 764         .dapm_routes      = es8328_dapm_routes,
 765         .num_dapm_routes  = ARRAY_SIZE(es8328_dapm_routes),
 766 };
 767
 768 int es8328_probe(struct device *dev, struct regmap *regmap)
 769 {
 770         struct es8328_priv *es8328;
 771         int ret;
 772         int i;
 773
 774         if (IS_ERR(regmap))
 775                 return PTR_ERR(regmap);
 776
 777         es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
 778         if (es8328 == NULL)
 779                 return -ENOMEM;
 780
 781         es8328->regmap = regmap;
 782
 783         for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
 784                 es8328->supplies[i].supply = supply_names[i];
 785
 786         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
 787                                 es8328->supplies);
 788         if (ret) {
 789                 dev_err(dev, "unable to get regulators\n");
 790                 return ret;
 791         }
 792
 793         dev_set_drvdata(dev, es8328);
 794
 795         return snd_soc_register_codec(dev,
 796                         &es8328_codec_driver, &es8328_dai, 1);
 797 }
 798 EXPORT_SYMBOL_GPL(es8328_probe);
 799
 800 MODULE_DESCRIPTION("ASoC ES8328 driver");
 801 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
 802 MODULE_LICENSE("GPL");