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[deliverable/linux.git] / sound / soc / codecs / max98090.c
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/clk.h>
21 #include <sound/jack.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/max98090.h>
27 #include "max98090.h"
28
29 /* Allows for sparsely populated register maps */
30 static const struct reg_default max98090_reg[] = {
31 { 0x00, 0x00 }, /* 00 Software Reset */
32 { 0x03, 0x04 }, /* 03 Interrupt Masks */
33 { 0x04, 0x00 }, /* 04 System Clock Quick */
34 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
35 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
36 { 0x07, 0x00 }, /* 07 DAC Path Quick */
37 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
38 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
39 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
40 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
41 { 0x0C, 0x00 }, /* 0C Reserved */
42 { 0x0D, 0x00 }, /* 0D Input Config */
43 { 0x0E, 0x1B }, /* 0E Line Input Level */
44 { 0x0F, 0x00 }, /* 0F Line Config */
45
46 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
47 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
48 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
49 { 0x13, 0x00 }, /* 13 Digital Mic Config */
50 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
51 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
52 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
53 { 0x17, 0x03 }, /* 17 Left ADC Level */
54 { 0x18, 0x03 }, /* 18 Right ADC Level */
55 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
56 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
57 { 0x1B, 0x00 }, /* 1B System Clock */
58 { 0x1C, 0x00 }, /* 1C Clock Mode */
59 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
60 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
61 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
62
63 { 0x20, 0x00 }, /* 20 Any Clock 4 */
64 { 0x21, 0x00 }, /* 21 Master Mode */
65 { 0x22, 0x00 }, /* 22 Interface Format */
66 { 0x23, 0x00 }, /* 23 TDM Format 1*/
67 { 0x24, 0x00 }, /* 24 TDM Format 2*/
68 { 0x25, 0x00 }, /* 25 I/O Configuration */
69 { 0x26, 0x80 }, /* 26 Filter Config */
70 { 0x27, 0x00 }, /* 27 DAI Playback Level */
71 { 0x28, 0x00 }, /* 28 EQ Playback Level */
72 { 0x29, 0x00 }, /* 29 Left HP Mixer */
73 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
74 { 0x2B, 0x00 }, /* 2B HP Control */
75 { 0x2C, 0x1A }, /* 2C Left HP Volume */
76 { 0x2D, 0x1A }, /* 2D Right HP Volume */
77 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
78 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
79
80 { 0x30, 0x00 }, /* 30 Spk Control */
81 { 0x31, 0x2C }, /* 31 Left Spk Volume */
82 { 0x32, 0x2C }, /* 32 Right Spk Volume */
83 { 0x33, 0x00 }, /* 33 ALC Timing */
84 { 0x34, 0x00 }, /* 34 ALC Compressor */
85 { 0x35, 0x00 }, /* 35 ALC Expander */
86 { 0x36, 0x00 }, /* 36 ALC Gain */
87 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
88 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
89 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
90 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
91 { 0x3B, 0x00 }, /* 3B Line OutR Control */
92 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
93 { 0x3D, 0x00 }, /* 3D Jack Detect */
94 { 0x3E, 0x00 }, /* 3E Input Enable */
95 { 0x3F, 0x00 }, /* 3F Output Enable */
96
97 { 0x40, 0x00 }, /* 40 Level Control */
98 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
99 { 0x42, 0x00 }, /* 42 Bias Control */
100 { 0x43, 0x00 }, /* 43 DAC Control */
101 { 0x44, 0x06 }, /* 44 ADC Control */
102 { 0x45, 0x00 }, /* 45 Device Shutdown */
103 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
104 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
105 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
106 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
107 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
108 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
109 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
112 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
113
114 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
115 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
116 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
117 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
118 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
119 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
120 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
121 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
122 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
123 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
124 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
125 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
128 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
129 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
130
131 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
132 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
133 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
134 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
135 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
136 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
137 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
138 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
139 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
140 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
141 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
144 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
145 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
146 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
147
148 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
149 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
150 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
151 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
152 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
153 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
154 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
155 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
156 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
157 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
160 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
161 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
162 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
163 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
164
165 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
166 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
167 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
168 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
169 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
170 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
171 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
172 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
173 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
176 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
177 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
178 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
179 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
180 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
181
182 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
183 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
184 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
185 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
186 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
187 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
188 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
189 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
192 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
193 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
194 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
195 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
196 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
197 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
198
199 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
200 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
201 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
202 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
203 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
204 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
205 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
208 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
209 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
210 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
211 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
212 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
213 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
214 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
215
216 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
217 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
218 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
219 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
220 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
221 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
224 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
225 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
226 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
227 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
228 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
229 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
230 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
231 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
232
233 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
234 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
235 { 0xC2, 0x00 }, /* C2 Sample Rate */
236 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
237 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
238 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
239 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
240 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
241 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
242 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
243 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
244 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
245 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
246 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
247 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
248 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
249
250 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
251 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
252 };
253
254 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
255 {
256 switch (reg) {
257 case M98090_REG_SOFTWARE_RESET:
258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
261 return true;
262 default:
263 return false;
264 }
265 }
266
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
268 {
269 switch (reg) {
270 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
271 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
272 case M98090_REG_REVISION_ID:
273 return true;
274 default:
275 return false;
276 }
277 }
278
279 static int max98090_reset(struct max98090_priv *max98090)
280 {
281 int ret;
282
283 /* Reset the codec by writing to this write-only reset register */
284 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
285 M98090_SWRESET_MASK);
286 if (ret < 0) {
287 dev_err(max98090->codec->dev,
288 "Failed to reset codec: %d\n", ret);
289 return ret;
290 }
291
292 msleep(20);
293 return ret;
294 }
295
296 static const unsigned int max98090_micboost_tlv[] = {
297 TLV_DB_RANGE_HEAD(2),
298 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
299 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
300 };
301
302 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
303
304 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
305 -600, 600, 0);
306
307 static const unsigned int max98090_line_tlv[] = {
308 TLV_DB_RANGE_HEAD(2),
309 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
310 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
311 };
312
313 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
315
316 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
317 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
318
319 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
320
321 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
322 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
323 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
324 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
325 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
326
327 static const unsigned int max98090_mixout_tlv[] = {
328 TLV_DB_RANGE_HEAD(2),
329 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
330 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
331 };
332
333 static const unsigned int max98090_hp_tlv[] = {
334 TLV_DB_RANGE_HEAD(5),
335 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
336 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
337 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
338 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
339 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
340 };
341
342 static const unsigned int max98090_spk_tlv[] = {
343 TLV_DB_RANGE_HEAD(5),
344 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
345 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
346 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
347 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
348 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
349 };
350
351 static const unsigned int max98090_rcv_lout_tlv[] = {
352 TLV_DB_RANGE_HEAD(5),
353 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
354 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
355 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
356 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
357 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
358 };
359
360 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362 {
363 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
364 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
365 struct soc_mixer_control *mc =
366 (struct soc_mixer_control *)kcontrol->private_value;
367 unsigned int mask = (1 << fls(mc->max)) - 1;
368 unsigned int val = snd_soc_read(codec, mc->reg);
369 unsigned int *select;
370
371 switch (mc->reg) {
372 case M98090_REG_MIC1_INPUT_LEVEL:
373 select = &(max98090->pa1en);
374 break;
375 case M98090_REG_MIC2_INPUT_LEVEL:
376 select = &(max98090->pa2en);
377 break;
378 case M98090_REG_ADC_SIDETONE:
379 select = &(max98090->sidetone);
380 break;
381 default:
382 return -EINVAL;
383 }
384
385 val = (val >> mc->shift) & mask;
386
387 if (val >= 1) {
388 /* If on, return the volume */
389 val = val - 1;
390 *select = val;
391 } else {
392 /* If off, return last stored value */
393 val = *select;
394 }
395
396 ucontrol->value.integer.value[0] = val;
397 return 0;
398 }
399
400 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_value *ucontrol)
402 {
403 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
404 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
405 struct soc_mixer_control *mc =
406 (struct soc_mixer_control *)kcontrol->private_value;
407 unsigned int mask = (1 << fls(mc->max)) - 1;
408 unsigned int sel = ucontrol->value.integer.value[0];
409 unsigned int val = snd_soc_read(codec, mc->reg);
410 unsigned int *select;
411
412 switch (mc->reg) {
413 case M98090_REG_MIC1_INPUT_LEVEL:
414 select = &(max98090->pa1en);
415 break;
416 case M98090_REG_MIC2_INPUT_LEVEL:
417 select = &(max98090->pa2en);
418 break;
419 case M98090_REG_ADC_SIDETONE:
420 select = &(max98090->sidetone);
421 break;
422 default:
423 return -EINVAL;
424 }
425
426 val = (val >> mc->shift) & mask;
427
428 *select = sel;
429
430 /* Setting a volume is only valid if it is already On */
431 if (val >= 1) {
432 sel = sel + 1;
433 } else {
434 /* Write what was already there */
435 sel = val;
436 }
437
438 snd_soc_update_bits(codec, mc->reg,
439 mask << mc->shift,
440 sel << mc->shift);
441
442 return 0;
443 }
444
445 static const char *max98090_perf_pwr_text[] =
446 { "High Performance", "Low Power" };
447 static const char *max98090_pwr_perf_text[] =
448 { "Low Power", "High Performance" };
449
450 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
451 M98090_REG_BIAS_CONTROL,
452 M98090_VCM_MODE_SHIFT,
453 max98090_pwr_perf_text);
454
455 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
456
457 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
458 M98090_REG_ADC_CONTROL,
459 M98090_OSR128_SHIFT,
460 max98090_osr128_text);
461
462 static const char *max98090_mode_text[] = { "Voice", "Music" };
463
464 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
465 M98090_REG_FILTER_CONFIG,
466 M98090_MODE_SHIFT,
467 max98090_mode_text);
468
469 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
470 M98090_REG_FILTER_CONFIG,
471 M98090_FLT_DMIC34MODE_SHIFT,
472 max98090_mode_text);
473
474 static const char *max98090_drcatk_text[] =
475 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
476
477 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
478 M98090_REG_DRC_TIMING,
479 M98090_DRCATK_SHIFT,
480 max98090_drcatk_text);
481
482 static const char *max98090_drcrls_text[] =
483 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
484
485 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
486 M98090_REG_DRC_TIMING,
487 M98090_DRCRLS_SHIFT,
488 max98090_drcrls_text);
489
490 static const char *max98090_alccmp_text[] =
491 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
492
493 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
494 M98090_REG_DRC_COMPRESSOR,
495 M98090_DRCCMP_SHIFT,
496 max98090_alccmp_text);
497
498 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
499
500 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
501 M98090_REG_DRC_EXPANDER,
502 M98090_DRCEXP_SHIFT,
503 max98090_drcexp_text);
504
505 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
506 M98090_REG_DAC_CONTROL,
507 M98090_PERFMODE_SHIFT,
508 max98090_perf_pwr_text);
509
510 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
511 M98090_REG_DAC_CONTROL,
512 M98090_DACHP_SHIFT,
513 max98090_pwr_perf_text);
514
515 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
516 M98090_REG_ADC_CONTROL,
517 M98090_ADCHP_SHIFT,
518 max98090_pwr_perf_text);
519
520 static const struct snd_kcontrol_new max98090_snd_controls[] = {
521 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
522
523 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
524 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
525
526 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
527 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
528 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
529 max98090_put_enab_tlv, max98090_micboost_tlv),
530
531 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
532 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
533 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
534 max98090_put_enab_tlv, max98090_micboost_tlv),
535
536 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
537 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
538 max98090_mic_tlv),
539
540 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
541 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
542 max98090_mic_tlv),
543
544 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
545 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
546 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
547
548 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
549 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
550 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
551
552 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
553 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
554 max98090_line_tlv),
555
556 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
557 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
558 max98090_line_tlv),
559
560 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
561 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
562 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
563 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
564
565 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
566 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 max98090_avg_tlv),
568 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
569 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
570 max98090_avg_tlv),
571
572 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
573 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
574 max98090_av_tlv),
575 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
576 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
577 max98090_av_tlv),
578
579 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
580 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
581 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
582 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
583
584 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
586 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
587 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
588 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
589 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
590 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
591 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
592 SOC_ENUM("Filter Mode", max98090_mode_enum),
593 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
594 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
595 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
596 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
597 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
598 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
599 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
600 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
601 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
602 max98090_put_enab_tlv, max98090_sdg_tlv),
603 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
604 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
605 max98090_dvg_tlv),
606 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
607 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
608 max98090_dv_tlv),
609 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
610 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
611 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
612 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
613 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
614 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
615 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
616 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
617 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
618 1),
619 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
620 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
621 max98090_dv_tlv),
622
623 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
624 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
625 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
626 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
627 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
628 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
629 max98090_alcmakeup_tlv),
630 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
631 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
632 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
633 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
634 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
635 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
636 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
637 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
638
639 SOC_ENUM("DAC HP Playback Performance Mode",
640 max98090_dac_perfmode_enum),
641 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
642
643 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
644 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
645 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
646 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
647 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
648 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
649
650 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
651 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
652 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
653 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
654 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
655 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
656
657 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
658 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
659 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
660 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
661 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
662 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
663
664 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
665 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
666 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
667
668 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
669 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
670 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
671 0, max98090_spk_tlv),
672
673 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
674 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
675 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
676
677 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
678 M98090_HPLM_SHIFT, 1, 1),
679 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
680 M98090_HPRM_SHIFT, 1, 1),
681
682 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
683 M98090_SPLM_SHIFT, 1, 1),
684 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
685 M98090_SPRM_SHIFT, 1, 1),
686
687 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
688 M98090_RCVLM_SHIFT, 1, 1),
689 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
690 M98090_RCVRM_SHIFT, 1, 1),
691
692 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
693 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
694 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
695 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
696 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
697 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
698
699 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
700 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
701 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 };
703
704 static const struct snd_kcontrol_new max98091_snd_controls[] = {
705
706 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
707 M98090_DMIC34_ZEROPAD_SHIFT,
708 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
709
710 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
711 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
712 M98090_FLT_DMIC34HPF_SHIFT,
713 M98090_FLT_DMIC34HPF_NUM - 1, 0),
714
715 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
716 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
717 max98090_avg_tlv),
718 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
719 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
720 max98090_avg_tlv),
721
722 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
723 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
724 max98090_av_tlv),
725 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
726 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
727 max98090_av_tlv),
728
729 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
730 M98090_REG_DMIC34_BIQUAD_BASE, 15),
731 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
732 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
733
734 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
735 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
736 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
737 };
738
739 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
740 struct snd_kcontrol *kcontrol, int event)
741 {
742 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
743 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
744
745 unsigned int val = snd_soc_read(codec, w->reg);
746
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
748 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
749 else
750 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
751
752 if (val >= 1) {
753 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
754 max98090->pa1en = val - 1; /* Update for volatile */
755 } else {
756 max98090->pa2en = val - 1; /* Update for volatile */
757 }
758 }
759
760 switch (event) {
761 case SND_SOC_DAPM_POST_PMU:
762 /* If turning on, set to most recently selected volume */
763 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
764 val = max98090->pa1en + 1;
765 else
766 val = max98090->pa2en + 1;
767 break;
768 case SND_SOC_DAPM_POST_PMD:
769 /* If turning off, turn off */
770 val = 0;
771 break;
772 default:
773 return -EINVAL;
774 }
775
776 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
777 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
778 val << M98090_MIC_PA1EN_SHIFT);
779 else
780 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
781 val << M98090_MIC_PA2EN_SHIFT);
782
783 return 0;
784 }
785
786 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
787 struct snd_kcontrol *kcontrol, int event)
788 {
789 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
790 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
791
792 if (event & SND_SOC_DAPM_POST_PMU)
793 max98090->shdn_pending = true;
794
795 return 0;
796
797 }
798
799 static const char *mic1_mux_text[] = { "IN12", "IN56" };
800
801 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
802 M98090_REG_INPUT_MODE,
803 M98090_EXTMIC1_SHIFT,
804 mic1_mux_text);
805
806 static const struct snd_kcontrol_new max98090_mic1_mux =
807 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
808
809 static const char *mic2_mux_text[] = { "IN34", "IN56" };
810
811 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
812 M98090_REG_INPUT_MODE,
813 M98090_EXTMIC2_SHIFT,
814 mic2_mux_text);
815
816 static const struct snd_kcontrol_new max98090_mic2_mux =
817 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
818
819 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
820
821 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
822
823 static const struct snd_kcontrol_new max98090_dmic_mux =
824 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
825
826 static const char *max98090_micpre_text[] = { "Off", "On" };
827
828 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
829 M98090_REG_MIC1_INPUT_LEVEL,
830 M98090_MIC_PA1EN_SHIFT,
831 max98090_micpre_text);
832
833 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
834 M98090_REG_MIC2_INPUT_LEVEL,
835 M98090_MIC_PA2EN_SHIFT,
836 max98090_micpre_text);
837
838 /* LINEA mixer switch */
839 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
840 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
841 M98090_IN1SEEN_SHIFT, 1, 0),
842 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
843 M98090_IN3SEEN_SHIFT, 1, 0),
844 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
845 M98090_IN5SEEN_SHIFT, 1, 0),
846 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
847 M98090_IN34DIFF_SHIFT, 1, 0),
848 };
849
850 /* LINEB mixer switch */
851 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
852 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
853 M98090_IN2SEEN_SHIFT, 1, 0),
854 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
855 M98090_IN4SEEN_SHIFT, 1, 0),
856 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
857 M98090_IN6SEEN_SHIFT, 1, 0),
858 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
859 M98090_IN56DIFF_SHIFT, 1, 0),
860 };
861
862 /* Left ADC mixer switch */
863 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
864 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
865 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
866 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
867 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
868 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
869 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
870 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
871 M98090_MIXADL_LINEA_SHIFT, 1, 0),
872 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
873 M98090_MIXADL_LINEB_SHIFT, 1, 0),
874 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
875 M98090_MIXADL_MIC1_SHIFT, 1, 0),
876 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
877 M98090_MIXADL_MIC2_SHIFT, 1, 0),
878 };
879
880 /* Right ADC mixer switch */
881 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
882 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
883 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
884 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
885 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
886 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
887 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
889 M98090_MIXADR_LINEA_SHIFT, 1, 0),
890 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
891 M98090_MIXADR_LINEB_SHIFT, 1, 0),
892 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
893 M98090_MIXADR_MIC1_SHIFT, 1, 0),
894 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
895 M98090_MIXADR_MIC2_SHIFT, 1, 0),
896 };
897
898 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
899
900 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
901 M98090_REG_IO_CONFIGURATION,
902 M98090_LTEN_SHIFT,
903 lten_mux_text);
904
905 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
906 M98090_REG_IO_CONFIGURATION,
907 M98090_LTEN_SHIFT,
908 lten_mux_text);
909
910 static const struct snd_kcontrol_new max98090_ltenl_mux =
911 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
912
913 static const struct snd_kcontrol_new max98090_ltenr_mux =
914 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
915
916 static const char *lben_mux_text[] = { "Normal", "Loopback" };
917
918 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
919 M98090_REG_IO_CONFIGURATION,
920 M98090_LBEN_SHIFT,
921 lben_mux_text);
922
923 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
924 M98090_REG_IO_CONFIGURATION,
925 M98090_LBEN_SHIFT,
926 lben_mux_text);
927
928 static const struct snd_kcontrol_new max98090_lbenl_mux =
929 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
930
931 static const struct snd_kcontrol_new max98090_lbenr_mux =
932 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
933
934 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
935
936 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
937
938 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
939 M98090_REG_ADC_SIDETONE,
940 M98090_DSTSL_SHIFT,
941 stenl_mux_text);
942
943 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
944 M98090_REG_ADC_SIDETONE,
945 M98090_DSTSR_SHIFT,
946 stenr_mux_text);
947
948 static const struct snd_kcontrol_new max98090_stenl_mux =
949 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
950
951 static const struct snd_kcontrol_new max98090_stenr_mux =
952 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
953
954 /* Left speaker mixer switch */
955 static const struct
956 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
957 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
958 M98090_MIXSPL_DACL_SHIFT, 1, 0),
959 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
960 M98090_MIXSPL_DACR_SHIFT, 1, 0),
961 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
962 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
963 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
964 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
965 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
966 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
967 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
968 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
969 };
970
971 /* Right speaker mixer switch */
972 static const struct
973 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
974 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
975 M98090_MIXSPR_DACL_SHIFT, 1, 0),
976 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
977 M98090_MIXSPR_DACR_SHIFT, 1, 0),
978 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
979 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
980 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
981 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
982 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
983 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
984 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
985 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
986 };
987
988 /* Left headphone mixer switch */
989 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
990 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
991 M98090_MIXHPL_DACL_SHIFT, 1, 0),
992 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
993 M98090_MIXHPL_DACR_SHIFT, 1, 0),
994 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
995 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
996 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
997 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
998 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
999 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1000 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1001 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1002 };
1003
1004 /* Right headphone mixer switch */
1005 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1006 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1007 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1009 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1011 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1013 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1014 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1015 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1017 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1018 };
1019
1020 /* Left receiver mixer switch */
1021 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1022 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1023 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1025 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1027 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1029 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1030 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1031 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1032 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1033 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1034 };
1035
1036 /* Right receiver mixer switch */
1037 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1038 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1039 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1041 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1043 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1045 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1046 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1047 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1048 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1049 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1050 };
1051
1052 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1053
1054 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1055 M98090_REG_LOUTR_MIXER,
1056 M98090_LINMOD_SHIFT,
1057 linmod_mux_text);
1058
1059 static const struct snd_kcontrol_new max98090_linmod_mux =
1060 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1061
1062 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1063
1064 /*
1065 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1066 */
1067 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1068 M98090_REG_HP_CONTROL,
1069 M98090_MIXHPLSEL_SHIFT,
1070 mixhpsel_mux_text);
1071
1072 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1073 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1074
1075 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1076 M98090_REG_HP_CONTROL,
1077 M98090_MIXHPRSEL_SHIFT,
1078 mixhpsel_mux_text);
1079
1080 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1081 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1082
1083 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1084 SND_SOC_DAPM_INPUT("MIC1"),
1085 SND_SOC_DAPM_INPUT("MIC2"),
1086 SND_SOC_DAPM_INPUT("DMICL"),
1087 SND_SOC_DAPM_INPUT("DMICR"),
1088 SND_SOC_DAPM_INPUT("IN1"),
1089 SND_SOC_DAPM_INPUT("IN2"),
1090 SND_SOC_DAPM_INPUT("IN3"),
1091 SND_SOC_DAPM_INPUT("IN4"),
1092 SND_SOC_DAPM_INPUT("IN5"),
1093 SND_SOC_DAPM_INPUT("IN6"),
1094 SND_SOC_DAPM_INPUT("IN12"),
1095 SND_SOC_DAPM_INPUT("IN34"),
1096 SND_SOC_DAPM_INPUT("IN56"),
1097
1098 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1099 M98090_MBEN_SHIFT, 0, NULL, 0),
1100 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1101 M98090_SHDNN_SHIFT, 0, NULL, 0),
1102 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1103 M98090_SDIEN_SHIFT, 0, NULL, 0),
1104 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1105 M98090_SDOEN_SHIFT, 0, NULL, 0),
1106 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1107 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1108 SND_SOC_DAPM_POST_PMU),
1109 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1110 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1111 SND_SOC_DAPM_POST_PMU),
1112 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1113 M98090_AHPF_SHIFT, 0, NULL, 0),
1114
1115 /*
1116 * Note: Sysclk and misc power supplies are taken care of by SHDN
1117 */
1118
1119 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1120 0, 0, &max98090_mic1_mux),
1121
1122 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1123 0, 0, &max98090_mic2_mux),
1124
1125 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1126
1127 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1128 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1129 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1130
1131 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1132 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1133 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1134
1135 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1136 &max98090_linea_mixer_controls[0],
1137 ARRAY_SIZE(max98090_linea_mixer_controls)),
1138
1139 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1140 &max98090_lineb_mixer_controls[0],
1141 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1142
1143 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1144 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1145 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1146 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1147
1148 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1149 &max98090_left_adc_mixer_controls[0],
1150 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1151
1152 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1153 &max98090_right_adc_mixer_controls[0],
1154 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1155
1156 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1157 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1158 SND_SOC_DAPM_POST_PMU),
1159 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1160 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1161 SND_SOC_DAPM_POST_PMU),
1162
1163 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1164 SND_SOC_NOPM, 0, 0),
1165 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1166 SND_SOC_NOPM, 0, 0),
1167
1168 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1169 0, 0, &max98090_lbenl_mux),
1170
1171 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1172 0, 0, &max98090_lbenr_mux),
1173
1174 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_ltenl_mux),
1176
1177 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1178 0, 0, &max98090_ltenr_mux),
1179
1180 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1181 0, 0, &max98090_stenl_mux),
1182
1183 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1184 0, 0, &max98090_stenr_mux),
1185
1186 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1187 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1188
1189 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1190 M98090_DALEN_SHIFT, 0),
1191 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1192 M98090_DAREN_SHIFT, 0),
1193
1194 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1195 &max98090_left_hp_mixer_controls[0],
1196 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1197
1198 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1199 &max98090_right_hp_mixer_controls[0],
1200 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1201
1202 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1203 &max98090_left_speaker_mixer_controls[0],
1204 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1205
1206 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1207 &max98090_right_speaker_mixer_controls[0],
1208 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1209
1210 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1211 &max98090_left_rcv_mixer_controls[0],
1212 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1213
1214 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1215 &max98090_right_rcv_mixer_controls[0],
1216 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1217
1218 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1219 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1220
1221 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1222 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1223
1224 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1225 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1226
1227 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1228 M98090_HPLEN_SHIFT, 0, NULL, 0),
1229 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1230 M98090_HPREN_SHIFT, 0, NULL, 0),
1231
1232 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1233 M98090_SPLEN_SHIFT, 0, NULL, 0),
1234 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1235 M98090_SPREN_SHIFT, 0, NULL, 0),
1236
1237 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1238 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1239 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1240 M98090_RCVREN_SHIFT, 0, NULL, 0),
1241
1242 SND_SOC_DAPM_OUTPUT("HPL"),
1243 SND_SOC_DAPM_OUTPUT("HPR"),
1244 SND_SOC_DAPM_OUTPUT("SPKL"),
1245 SND_SOC_DAPM_OUTPUT("SPKR"),
1246 SND_SOC_DAPM_OUTPUT("RCVL"),
1247 SND_SOC_DAPM_OUTPUT("RCVR"),
1248 };
1249
1250 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1251 SND_SOC_DAPM_INPUT("DMIC3"),
1252 SND_SOC_DAPM_INPUT("DMIC4"),
1253
1254 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1255 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1256 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1257 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1258 };
1259
1260 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1261 {"MIC1 Input", NULL, "MIC1"},
1262 {"MIC2 Input", NULL, "MIC2"},
1263
1264 {"DMICL", NULL, "DMICL_ENA"},
1265 {"DMICL", NULL, "DMICR_ENA"},
1266 {"DMICR", NULL, "DMICL_ENA"},
1267 {"DMICR", NULL, "DMICR_ENA"},
1268 {"DMICL", NULL, "AHPF"},
1269 {"DMICR", NULL, "AHPF"},
1270
1271 /* MIC1 input mux */
1272 {"MIC1 Mux", "IN12", "IN12"},
1273 {"MIC1 Mux", "IN56", "IN56"},
1274
1275 /* MIC2 input mux */
1276 {"MIC2 Mux", "IN34", "IN34"},
1277 {"MIC2 Mux", "IN56", "IN56"},
1278
1279 {"MIC1 Input", NULL, "MIC1 Mux"},
1280 {"MIC2 Input", NULL, "MIC2 Mux"},
1281
1282 /* Left ADC input mixer */
1283 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1284 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1285 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1286 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1287 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1288 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1289 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1290
1291 /* Right ADC input mixer */
1292 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1293 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1294 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1295 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1296 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1297 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1298 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1299
1300 /* Line A input mixer */
1301 {"LINEA Mixer", "IN1 Switch", "IN1"},
1302 {"LINEA Mixer", "IN3 Switch", "IN3"},
1303 {"LINEA Mixer", "IN5 Switch", "IN5"},
1304 {"LINEA Mixer", "IN34 Switch", "IN34"},
1305
1306 /* Line B input mixer */
1307 {"LINEB Mixer", "IN2 Switch", "IN2"},
1308 {"LINEB Mixer", "IN4 Switch", "IN4"},
1309 {"LINEB Mixer", "IN6 Switch", "IN6"},
1310 {"LINEB Mixer", "IN56 Switch", "IN56"},
1311
1312 {"LINEA Input", NULL, "LINEA Mixer"},
1313 {"LINEB Input", NULL, "LINEB Mixer"},
1314
1315 /* Inputs */
1316 {"ADCL", NULL, "Left ADC Mixer"},
1317 {"ADCR", NULL, "Right ADC Mixer"},
1318 {"ADCL", NULL, "SHDN"},
1319 {"ADCR", NULL, "SHDN"},
1320
1321 {"DMIC Mux", "ADC", "ADCL"},
1322 {"DMIC Mux", "ADC", "ADCR"},
1323 {"DMIC Mux", "DMIC", "DMICL"},
1324 {"DMIC Mux", "DMIC", "DMICR"},
1325
1326 {"LBENL Mux", "Normal", "DMIC Mux"},
1327 {"LBENL Mux", "Loopback", "LTENL Mux"},
1328 {"LBENR Mux", "Normal", "DMIC Mux"},
1329 {"LBENR Mux", "Loopback", "LTENR Mux"},
1330
1331 {"AIFOUTL", NULL, "LBENL Mux"},
1332 {"AIFOUTR", NULL, "LBENR Mux"},
1333 {"AIFOUTL", NULL, "SHDN"},
1334 {"AIFOUTR", NULL, "SHDN"},
1335 {"AIFOUTL", NULL, "SDOEN"},
1336 {"AIFOUTR", NULL, "SDOEN"},
1337
1338 {"LTENL Mux", "Normal", "AIFINL"},
1339 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1340 {"LTENR Mux", "Normal", "AIFINR"},
1341 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1342
1343 {"DACL", NULL, "LTENL Mux"},
1344 {"DACR", NULL, "LTENR Mux"},
1345
1346 {"STENL Mux", "Sidetone Left", "ADCL"},
1347 {"STENL Mux", "Sidetone Left", "DMICL"},
1348 {"STENR Mux", "Sidetone Right", "ADCR"},
1349 {"STENR Mux", "Sidetone Right", "DMICR"},
1350 {"DACL", NULL, "STENL Mux"},
1351 {"DACR", NULL, "STENR Mux"},
1352
1353 {"AIFINL", NULL, "SHDN"},
1354 {"AIFINR", NULL, "SHDN"},
1355 {"AIFINL", NULL, "SDIEN"},
1356 {"AIFINR", NULL, "SDIEN"},
1357 {"DACL", NULL, "SHDN"},
1358 {"DACR", NULL, "SHDN"},
1359
1360 /* Left headphone output mixer */
1361 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1362 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1363 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1364 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1365 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1366 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1367
1368 /* Right headphone output mixer */
1369 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1370 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1371 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1372 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1373 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1374 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1375
1376 /* Left speaker output mixer */
1377 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1378 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1379 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1380 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1381 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1382 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1383
1384 /* Right speaker output mixer */
1385 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1386 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1387 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1388 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1389 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1390 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1391
1392 /* Left Receiver output mixer */
1393 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1394 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1395 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1396 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1397 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1398 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1399
1400 /* Right Receiver output mixer */
1401 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1402 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1403 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1404 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1405 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1406 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1407
1408 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1409
1410 /*
1411 * Disable this for lowest power if bypassing
1412 * the DAC with an analog signal
1413 */
1414 {"HP Left Out", NULL, "DACL"},
1415 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1416
1417 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1418
1419 /*
1420 * Disable this for lowest power if bypassing
1421 * the DAC with an analog signal
1422 */
1423 {"HP Right Out", NULL, "DACR"},
1424 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1425
1426 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1427 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1428 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1429
1430 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1431 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1432 {"RCV Right Out", NULL, "LINMOD Mux"},
1433
1434 {"HPL", NULL, "HP Left Out"},
1435 {"HPR", NULL, "HP Right Out"},
1436 {"SPKL", NULL, "SPK Left Out"},
1437 {"SPKR", NULL, "SPK Right Out"},
1438 {"RCVL", NULL, "RCV Left Out"},
1439 {"RCVR", NULL, "RCV Right Out"},
1440 };
1441
1442 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1443 /* DMIC inputs */
1444 {"DMIC3", NULL, "DMIC3_ENA"},
1445 {"DMIC4", NULL, "DMIC4_ENA"},
1446 {"DMIC3", NULL, "AHPF"},
1447 {"DMIC4", NULL, "AHPF"},
1448 };
1449
1450 static int max98090_add_widgets(struct snd_soc_codec *codec)
1451 {
1452 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1453 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1454
1455 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1456 ARRAY_SIZE(max98090_snd_controls));
1457
1458 if (max98090->devtype == MAX98091) {
1459 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1460 ARRAY_SIZE(max98091_snd_controls));
1461 }
1462
1463 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1464 ARRAY_SIZE(max98090_dapm_widgets));
1465
1466 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1467 ARRAY_SIZE(max98090_dapm_routes));
1468
1469 if (max98090->devtype == MAX98091) {
1470 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1471 ARRAY_SIZE(max98091_dapm_widgets));
1472
1473 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1474 ARRAY_SIZE(max98091_dapm_routes));
1475 }
1476
1477 return 0;
1478 }
1479
1480 static const int pclk_rates[] = {
1481 12000000, 12000000, 13000000, 13000000,
1482 16000000, 16000000, 19200000, 19200000
1483 };
1484
1485 static const int lrclk_rates[] = {
1486 8000, 16000, 8000, 16000,
1487 8000, 16000, 8000, 16000
1488 };
1489
1490 static const int user_pclk_rates[] = {
1491 13000000, 13000000, 19200000, 19200000,
1492 };
1493
1494 static const int user_lrclk_rates[] = {
1495 44100, 48000, 44100, 48000,
1496 };
1497
1498 static const unsigned long long ni_value[] = {
1499 3528, 768, 441, 8
1500 };
1501
1502 static const unsigned long long mi_value[] = {
1503 8125, 1625, 1500, 25
1504 };
1505
1506 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1507 {
1508 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1509 unsigned long long ni;
1510 int i;
1511
1512 if (!max98090->sysclk) {
1513 dev_err(codec->dev, "No SYSCLK configured\n");
1514 return;
1515 }
1516
1517 if (!max98090->bclk || !max98090->lrclk) {
1518 dev_err(codec->dev, "No audio clocks configured\n");
1519 return;
1520 }
1521
1522 /* Skip configuration when operating as slave */
1523 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1524 M98090_MAS_MASK)) {
1525 return;
1526 }
1527
1528 /* Check for supported PCLK to LRCLK ratios */
1529 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1530 if ((pclk_rates[i] == max98090->sysclk) &&
1531 (lrclk_rates[i] == max98090->lrclk)) {
1532 dev_dbg(codec->dev,
1533 "Found supported PCLK to LRCLK rates 0x%x\n",
1534 i + 0x8);
1535
1536 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1537 M98090_FREQ_MASK,
1538 (i + 0x8) << M98090_FREQ_SHIFT);
1539 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1540 M98090_USE_M1_MASK, 0);
1541 return;
1542 }
1543 }
1544
1545 /* Check for user calculated MI and NI ratios */
1546 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1547 if ((user_pclk_rates[i] == max98090->sysclk) &&
1548 (user_lrclk_rates[i] == max98090->lrclk)) {
1549 dev_dbg(codec->dev,
1550 "Found user supported PCLK to LRCLK rates\n");
1551 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1552 i, ni_value[i], mi_value[i]);
1553
1554 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1555 M98090_FREQ_MASK, 0);
1556 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1557 M98090_USE_M1_MASK,
1558 1 << M98090_USE_M1_SHIFT);
1559
1560 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1561 (ni_value[i] >> 8) & 0x7F);
1562 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1563 ni_value[i] & 0xFF);
1564 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1565 (mi_value[i] >> 8) & 0x7F);
1566 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1567 mi_value[i] & 0xFF);
1568
1569 return;
1570 }
1571 }
1572
1573 /*
1574 * Calculate based on MI = 65536 (not as good as either method above)
1575 */
1576 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1577 M98090_FREQ_MASK, 0);
1578 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1579 M98090_USE_M1_MASK, 0);
1580
1581 /*
1582 * Configure NI when operating as master
1583 * Note: There is a small, but significant audio quality improvement
1584 * by calculating ni and mi.
1585 */
1586 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1587 * (unsigned long long int)max98090->lrclk;
1588 do_div(ni, (unsigned long long int)max98090->sysclk);
1589 dev_info(codec->dev, "No better method found\n");
1590 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1591 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1592 (ni >> 8) & 0x7F);
1593 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1594 }
1595
1596 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1597 unsigned int fmt)
1598 {
1599 struct snd_soc_codec *codec = codec_dai->codec;
1600 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1601 struct max98090_cdata *cdata;
1602 u8 regval;
1603
1604 max98090->dai_fmt = fmt;
1605 cdata = &max98090->dai[0];
1606
1607 if (fmt != cdata->fmt) {
1608 cdata->fmt = fmt;
1609
1610 regval = 0;
1611 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1612 case SND_SOC_DAIFMT_CBS_CFS:
1613 /* Set to slave mode PLL - MAS mode off */
1614 snd_soc_write(codec,
1615 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1616 snd_soc_write(codec,
1617 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1618 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1619 M98090_USE_M1_MASK, 0);
1620 max98090->master = false;
1621 break;
1622 case SND_SOC_DAIFMT_CBM_CFM:
1623 /* Set to master mode */
1624 if (max98090->tdm_slots == 4) {
1625 /* TDM */
1626 regval |= M98090_MAS_MASK |
1627 M98090_BSEL_64;
1628 } else if (max98090->tdm_slots == 3) {
1629 /* TDM */
1630 regval |= M98090_MAS_MASK |
1631 M98090_BSEL_48;
1632 } else {
1633 /* Few TDM slots, or No TDM */
1634 regval |= M98090_MAS_MASK |
1635 M98090_BSEL_32;
1636 }
1637 max98090->master = true;
1638 break;
1639 case SND_SOC_DAIFMT_CBS_CFM:
1640 case SND_SOC_DAIFMT_CBM_CFS:
1641 default:
1642 dev_err(codec->dev, "DAI clock mode unsupported");
1643 return -EINVAL;
1644 }
1645 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1646
1647 regval = 0;
1648 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1649 case SND_SOC_DAIFMT_I2S:
1650 regval |= M98090_DLY_MASK;
1651 break;
1652 case SND_SOC_DAIFMT_LEFT_J:
1653 break;
1654 case SND_SOC_DAIFMT_RIGHT_J:
1655 regval |= M98090_RJ_MASK;
1656 break;
1657 case SND_SOC_DAIFMT_DSP_A:
1658 /* Not supported mode */
1659 default:
1660 dev_err(codec->dev, "DAI format unsupported");
1661 return -EINVAL;
1662 }
1663
1664 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1665 case SND_SOC_DAIFMT_NB_NF:
1666 break;
1667 case SND_SOC_DAIFMT_NB_IF:
1668 regval |= M98090_WCI_MASK;
1669 break;
1670 case SND_SOC_DAIFMT_IB_NF:
1671 regval |= M98090_BCI_MASK;
1672 break;
1673 case SND_SOC_DAIFMT_IB_IF:
1674 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1675 break;
1676 default:
1677 dev_err(codec->dev, "DAI invert mode unsupported");
1678 return -EINVAL;
1679 }
1680
1681 /*
1682 * This accommodates an inverted logic in the MAX98090 chip
1683 * for Bit Clock Invert (BCI). The inverted logic is only
1684 * seen for the case of TDM mode. The remaining cases have
1685 * normal logic.
1686 */
1687 if (max98090->tdm_slots > 1)
1688 regval ^= M98090_BCI_MASK;
1689
1690 snd_soc_write(codec,
1691 M98090_REG_INTERFACE_FORMAT, regval);
1692 }
1693
1694 return 0;
1695 }
1696
1697 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1698 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1699 {
1700 struct snd_soc_codec *codec = codec_dai->codec;
1701 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1702 struct max98090_cdata *cdata;
1703 cdata = &max98090->dai[0];
1704
1705 if (slots < 0 || slots > 4)
1706 return -EINVAL;
1707
1708 max98090->tdm_slots = slots;
1709 max98090->tdm_width = slot_width;
1710
1711 if (max98090->tdm_slots > 1) {
1712 /* SLOTL SLOTR SLOTDLY */
1713 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1714 0 << M98090_TDM_SLOTL_SHIFT |
1715 1 << M98090_TDM_SLOTR_SHIFT |
1716 0 << M98090_TDM_SLOTDLY_SHIFT);
1717
1718 /* FSW TDM */
1719 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1720 M98090_TDM_MASK,
1721 M98090_TDM_MASK);
1722 }
1723
1724 /*
1725 * Normally advisable to set TDM first, but this permits either order
1726 */
1727 cdata->fmt = 0;
1728 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1729
1730 return 0;
1731 }
1732
1733 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1734 enum snd_soc_bias_level level)
1735 {
1736 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1737 int ret;
1738
1739 switch (level) {
1740 case SND_SOC_BIAS_ON:
1741 break;
1742
1743 case SND_SOC_BIAS_PREPARE:
1744 /*
1745 * SND_SOC_BIAS_PREPARE is called while preparing for a
1746 * transition to ON or away from ON. If current bias_level
1747 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1748 * away from ON. Disable the clock in that case, otherwise
1749 * enable it.
1750 */
1751 if (IS_ERR(max98090->mclk))
1752 break;
1753
1754 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
1755 clk_disable_unprepare(max98090->mclk);
1756 } else {
1757 ret = clk_prepare_enable(max98090->mclk);
1758 if (ret)
1759 return ret;
1760 }
1761 break;
1762
1763 case SND_SOC_BIAS_STANDBY:
1764 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1765 ret = regcache_sync(max98090->regmap);
1766 if (ret != 0) {
1767 dev_err(codec->dev,
1768 "Failed to sync cache: %d\n", ret);
1769 return ret;
1770 }
1771 }
1772 break;
1773
1774 case SND_SOC_BIAS_OFF:
1775 /* Set internal pull-up to lowest power mode */
1776 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1777 M98090_JDWK_MASK, M98090_JDWK_MASK);
1778 regcache_mark_dirty(max98090->regmap);
1779 break;
1780 }
1781 return 0;
1782 }
1783
1784 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1785
1786 static const int comp_lrclk_rates[] = {
1787 8000, 16000, 32000, 44100, 48000, 96000
1788 };
1789
1790 struct dmic_table {
1791 int pclk;
1792 struct {
1793 int freq;
1794 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1795 } settings[6]; /* One for each dmic divisor. */
1796 };
1797
1798 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1799 {
1800 .pclk = 11289600,
1801 .settings = {
1802 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1803 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1804 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1805 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1806 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1807 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1808 },
1809 },
1810 {
1811 .pclk = 12000000,
1812 .settings = {
1813 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1814 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1815 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1816 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1817 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1818 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1819 }
1820 },
1821 {
1822 .pclk = 12288000,
1823 .settings = {
1824 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1825 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1826 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1827 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1828 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1829 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1830 }
1831 },
1832 {
1833 .pclk = 13000000,
1834 .settings = {
1835 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1836 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1837 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1838 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1839 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1840 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1841 }
1842 },
1843 {
1844 .pclk = 19200000,
1845 .settings = {
1846 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1847 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1848 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1849 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1850 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1851 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1852 }
1853 },
1854 };
1855
1856 static int max98090_find_divisor(int target_freq, int pclk)
1857 {
1858 int current_diff = INT_MAX;
1859 int test_diff = INT_MAX;
1860 int divisor_index = 0;
1861 int i;
1862
1863 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1864 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1865 if (test_diff < current_diff) {
1866 current_diff = test_diff;
1867 divisor_index = i;
1868 }
1869 }
1870
1871 return divisor_index;
1872 }
1873
1874 static int max98090_find_closest_pclk(int pclk)
1875 {
1876 int m1;
1877 int m2;
1878 int i;
1879
1880 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1881 if (pclk == dmic_table[i].pclk)
1882 return i;
1883 if (pclk < dmic_table[i].pclk) {
1884 if (i == 0)
1885 return i;
1886 m1 = pclk - dmic_table[i-1].pclk;
1887 m2 = dmic_table[i].pclk - pclk;
1888 if (m1 < m2)
1889 return i - 1;
1890 else
1891 return i;
1892 }
1893 }
1894
1895 return -EINVAL;
1896 }
1897
1898 static int max98090_configure_dmic(struct max98090_priv *max98090,
1899 int target_dmic_clk, int pclk, int fs)
1900 {
1901 int micclk_index;
1902 int pclk_index;
1903 int dmic_freq;
1904 int dmic_comp;
1905 int i;
1906
1907 pclk_index = max98090_find_closest_pclk(pclk);
1908 if (pclk_index < 0)
1909 return pclk_index;
1910
1911 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1912
1913 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1914 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1915 break;
1916 }
1917
1918 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1919 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1920
1921 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1922 M98090_MICCLK_MASK,
1923 micclk_index << M98090_MICCLK_SHIFT);
1924
1925 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1926 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1927 dmic_comp << M98090_DMIC_COMP_SHIFT |
1928 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1929
1930 return 0;
1931 }
1932
1933 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1934 struct snd_pcm_hw_params *params,
1935 struct snd_soc_dai *dai)
1936 {
1937 struct snd_soc_codec *codec = dai->codec;
1938 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1939 struct max98090_cdata *cdata;
1940
1941 cdata = &max98090->dai[0];
1942 max98090->bclk = snd_soc_params_to_bclk(params);
1943 if (params_channels(params) == 1)
1944 max98090->bclk *= 2;
1945
1946 max98090->lrclk = params_rate(params);
1947
1948 switch (params_width(params)) {
1949 case 16:
1950 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1951 M98090_WS_MASK, 0);
1952 break;
1953 default:
1954 return -EINVAL;
1955 }
1956
1957 if (max98090->master)
1958 max98090_configure_bclk(codec);
1959
1960 cdata->rate = max98090->lrclk;
1961
1962 /* Update filter mode */
1963 if (max98090->lrclk < 24000)
1964 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1965 M98090_MODE_MASK, 0);
1966 else
1967 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1968 M98090_MODE_MASK, M98090_MODE_MASK);
1969
1970 /* Update sample rate mode */
1971 if (max98090->lrclk < 50000)
1972 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1973 M98090_DHF_MASK, 0);
1974 else
1975 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1976 M98090_DHF_MASK, M98090_DHF_MASK);
1977
1978 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1979 max98090->lrclk);
1980
1981 return 0;
1982 }
1983
1984 /*
1985 * PLL / Sysclk
1986 */
1987 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1988 int clk_id, unsigned int freq, int dir)
1989 {
1990 struct snd_soc_codec *codec = dai->codec;
1991 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1992
1993 /* Requested clock frequency is already setup */
1994 if (freq == max98090->sysclk)
1995 return 0;
1996
1997 if (!IS_ERR(max98090->mclk)) {
1998 freq = clk_round_rate(max98090->mclk, freq);
1999 clk_set_rate(max98090->mclk, freq);
2000 }
2001
2002 /* Setup clocks for slave mode, and using the PLL
2003 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2004 * 0x02 (when master clk is 20MHz to 40MHz)..
2005 * 0x03 (when master clk is 40MHz to 60MHz)..
2006 */
2007 if ((freq >= 10000000) && (freq <= 20000000)) {
2008 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2009 M98090_PSCLK_DIV1);
2010 max98090->pclk = freq;
2011 } else if ((freq > 20000000) && (freq <= 40000000)) {
2012 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2013 M98090_PSCLK_DIV2);
2014 max98090->pclk = freq >> 1;
2015 } else if ((freq > 40000000) && (freq <= 60000000)) {
2016 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2017 M98090_PSCLK_DIV4);
2018 max98090->pclk = freq >> 2;
2019 } else {
2020 dev_err(codec->dev, "Invalid master clock frequency\n");
2021 return -EINVAL;
2022 }
2023
2024 max98090->sysclk = freq;
2025
2026 return 0;
2027 }
2028
2029 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2030 {
2031 struct snd_soc_codec *codec = codec_dai->codec;
2032 int regval;
2033
2034 regval = mute ? M98090_DVM_MASK : 0;
2035 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
2036 M98090_DVM_MASK, regval);
2037
2038 return 0;
2039 }
2040
2041 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2042 struct snd_soc_dai *dai)
2043 {
2044 struct snd_soc_codec *codec = dai->codec;
2045 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2046
2047 switch (cmd) {
2048 case SNDRV_PCM_TRIGGER_START:
2049 case SNDRV_PCM_TRIGGER_RESUME:
2050 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2051 if (!max98090->master && dai->active == 1)
2052 queue_delayed_work(system_power_efficient_wq,
2053 &max98090->pll_det_enable_work,
2054 msecs_to_jiffies(10));
2055 break;
2056 case SNDRV_PCM_TRIGGER_STOP:
2057 case SNDRV_PCM_TRIGGER_SUSPEND:
2058 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2059 if (!max98090->master && dai->active == 1)
2060 schedule_work(&max98090->pll_det_disable_work);
2061 break;
2062 default:
2063 break;
2064 }
2065
2066 return 0;
2067 }
2068
2069 static void max98090_pll_det_enable_work(struct work_struct *work)
2070 {
2071 struct max98090_priv *max98090 =
2072 container_of(work, struct max98090_priv,
2073 pll_det_enable_work.work);
2074 struct snd_soc_codec *codec = max98090->codec;
2075 unsigned int status, mask;
2076
2077 /*
2078 * Clear status register in order to clear possibly already occurred
2079 * PLL unlock. If PLL hasn't still locked, the status will be set
2080 * again and PLL unlock interrupt will occur.
2081 * Note this will clear all status bits
2082 */
2083 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2084
2085 /*
2086 * Queue jack work in case jack state has just changed but handler
2087 * hasn't run yet
2088 */
2089 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2090 status &= mask;
2091 if (status & M98090_JDET_MASK)
2092 queue_delayed_work(system_power_efficient_wq,
2093 &max98090->jack_work,
2094 msecs_to_jiffies(100));
2095
2096 /* Enable PLL unlock interrupt */
2097 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2098 M98090_IULK_MASK,
2099 1 << M98090_IULK_SHIFT);
2100 }
2101
2102 static void max98090_pll_det_disable_work(struct work_struct *work)
2103 {
2104 struct max98090_priv *max98090 =
2105 container_of(work, struct max98090_priv, pll_det_disable_work);
2106 struct snd_soc_codec *codec = max98090->codec;
2107
2108 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2109
2110 /* Disable PLL unlock interrupt */
2111 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2112 M98090_IULK_MASK, 0);
2113 }
2114
2115 static void max98090_pll_work(struct work_struct *work)
2116 {
2117 struct max98090_priv *max98090 =
2118 container_of(work, struct max98090_priv, pll_work);
2119 struct snd_soc_codec *codec = max98090->codec;
2120
2121 if (!snd_soc_codec_is_active(codec))
2122 return;
2123
2124 dev_info(codec->dev, "PLL unlocked\n");
2125
2126 /* Toggle shutdown OFF then ON */
2127 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2128 M98090_SHDNN_MASK, 0);
2129 msleep(10);
2130 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2131 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2132
2133 /* Give PLL time to lock */
2134 msleep(10);
2135 }
2136
2137 static void max98090_jack_work(struct work_struct *work)
2138 {
2139 struct max98090_priv *max98090 = container_of(work,
2140 struct max98090_priv,
2141 jack_work.work);
2142 struct snd_soc_codec *codec = max98090->codec;
2143 int status = 0;
2144 int reg;
2145
2146 /* Read a second time */
2147 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2148
2149 /* Strong pull up allows mic detection */
2150 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2151 M98090_JDWK_MASK, 0);
2152
2153 msleep(50);
2154
2155 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2156
2157 /* Weak pull up allows only insertion detection */
2158 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2159 M98090_JDWK_MASK, M98090_JDWK_MASK);
2160 } else {
2161 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2162 }
2163
2164 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2165
2166 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2167 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2168 dev_dbg(codec->dev, "No Headset Detected\n");
2169
2170 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2171
2172 status |= 0;
2173
2174 break;
2175
2176 case 0:
2177 if (max98090->jack_state ==
2178 M98090_JACK_STATE_HEADSET) {
2179
2180 dev_dbg(codec->dev,
2181 "Headset Button Down Detected\n");
2182
2183 /*
2184 * max98090_headset_button_event(codec)
2185 * could be defined, then called here.
2186 */
2187
2188 status |= SND_JACK_HEADSET;
2189 status |= SND_JACK_BTN_0;
2190
2191 break;
2192 }
2193
2194 /* Line is reported as Headphone */
2195 /* Nokia Headset is reported as Headphone */
2196 /* Mono Headphone is reported as Headphone */
2197 dev_dbg(codec->dev, "Headphone Detected\n");
2198
2199 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2200
2201 status |= SND_JACK_HEADPHONE;
2202
2203 break;
2204
2205 case M98090_JKSNS_MASK:
2206 dev_dbg(codec->dev, "Headset Detected\n");
2207
2208 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2209
2210 status |= SND_JACK_HEADSET;
2211
2212 break;
2213
2214 default:
2215 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2216 break;
2217 }
2218
2219 snd_soc_jack_report(max98090->jack, status,
2220 SND_JACK_HEADSET | SND_JACK_BTN_0);
2221 }
2222
2223 static irqreturn_t max98090_interrupt(int irq, void *data)
2224 {
2225 struct max98090_priv *max98090 = data;
2226 struct snd_soc_codec *codec = max98090->codec;
2227 int ret;
2228 unsigned int mask;
2229 unsigned int active;
2230
2231 /* Treat interrupt before codec is initialized as spurious */
2232 if (codec == NULL)
2233 return IRQ_NONE;
2234
2235 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2236
2237 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2238
2239 if (ret != 0) {
2240 dev_err(codec->dev,
2241 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2242 ret);
2243 return IRQ_NONE;
2244 }
2245
2246 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2247
2248 if (ret != 0) {
2249 dev_err(codec->dev,
2250 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2251 ret);
2252 return IRQ_NONE;
2253 }
2254
2255 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2256 active, mask, active & mask);
2257
2258 active &= mask;
2259
2260 if (!active)
2261 return IRQ_NONE;
2262
2263 if (active & M98090_CLD_MASK)
2264 dev_err(codec->dev, "M98090_CLD_MASK\n");
2265
2266 if (active & M98090_SLD_MASK)
2267 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2268
2269 if (active & M98090_ULK_MASK) {
2270 dev_dbg(codec->dev, "M98090_ULK_MASK\n");
2271 schedule_work(&max98090->pll_work);
2272 }
2273
2274 if (active & M98090_JDET_MASK) {
2275 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2276
2277 pm_wakeup_event(codec->dev, 100);
2278
2279 queue_delayed_work(system_power_efficient_wq,
2280 &max98090->jack_work,
2281 msecs_to_jiffies(100));
2282 }
2283
2284 if (active & M98090_DRCACT_MASK)
2285 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2286
2287 if (active & M98090_DRCCLP_MASK)
2288 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2289
2290 return IRQ_HANDLED;
2291 }
2292
2293 /**
2294 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2295 *
2296 * @codec: MAX98090 codec
2297 * @jack: jack to report detection events on
2298 *
2299 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2300 * being used to bring out signals to the processor then only platform
2301 * data configuration is needed for MAX98090 and processor GPIOs should
2302 * be configured using snd_soc_jack_add_gpios() instead.
2303 *
2304 * If no jack is supplied detection will be disabled.
2305 */
2306 int max98090_mic_detect(struct snd_soc_codec *codec,
2307 struct snd_soc_jack *jack)
2308 {
2309 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2310
2311 dev_dbg(codec->dev, "max98090_mic_detect\n");
2312
2313 max98090->jack = jack;
2314 if (jack) {
2315 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2316 M98090_IJDET_MASK,
2317 1 << M98090_IJDET_SHIFT);
2318 } else {
2319 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2320 M98090_IJDET_MASK,
2321 0);
2322 }
2323
2324 /* Send an initial empty report */
2325 snd_soc_jack_report(max98090->jack, 0,
2326 SND_JACK_HEADSET | SND_JACK_BTN_0);
2327
2328 queue_delayed_work(system_power_efficient_wq,
2329 &max98090->jack_work,
2330 msecs_to_jiffies(100));
2331
2332 return 0;
2333 }
2334 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2335
2336 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2337 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2338
2339 static const struct snd_soc_dai_ops max98090_dai_ops = {
2340 .set_sysclk = max98090_dai_set_sysclk,
2341 .set_fmt = max98090_dai_set_fmt,
2342 .set_tdm_slot = max98090_set_tdm_slot,
2343 .hw_params = max98090_dai_hw_params,
2344 .digital_mute = max98090_dai_digital_mute,
2345 .trigger = max98090_dai_trigger,
2346 };
2347
2348 static struct snd_soc_dai_driver max98090_dai[] = {
2349 {
2350 .name = "HiFi",
2351 .playback = {
2352 .stream_name = "HiFi Playback",
2353 .channels_min = 2,
2354 .channels_max = 2,
2355 .rates = MAX98090_RATES,
2356 .formats = MAX98090_FORMATS,
2357 },
2358 .capture = {
2359 .stream_name = "HiFi Capture",
2360 .channels_min = 1,
2361 .channels_max = 2,
2362 .rates = MAX98090_RATES,
2363 .formats = MAX98090_FORMATS,
2364 },
2365 .ops = &max98090_dai_ops,
2366 }
2367 };
2368
2369 static int max98090_probe(struct snd_soc_codec *codec)
2370 {
2371 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2372 struct max98090_cdata *cdata;
2373 enum max98090_type devtype;
2374 int ret = 0;
2375 int err;
2376 unsigned int micbias;
2377
2378 dev_dbg(codec->dev, "max98090_probe\n");
2379
2380 max98090->mclk = devm_clk_get(codec->dev, "mclk");
2381 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2382 return -EPROBE_DEFER;
2383
2384 max98090->codec = codec;
2385
2386 /* Reset the codec, the DSP core, and disable all interrupts */
2387 max98090_reset(max98090);
2388
2389 /* Initialize private data */
2390
2391 max98090->sysclk = (unsigned)-1;
2392 max98090->pclk = (unsigned)-1;
2393 max98090->master = false;
2394
2395 cdata = &max98090->dai[0];
2396 cdata->rate = (unsigned)-1;
2397 cdata->fmt = (unsigned)-1;
2398
2399 max98090->lin_state = 0;
2400 max98090->pa1en = 0;
2401 max98090->pa2en = 0;
2402
2403 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2404 if (ret < 0) {
2405 dev_err(codec->dev, "Failed to read device revision: %d\n",
2406 ret);
2407 goto err_access;
2408 }
2409
2410 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2411 devtype = MAX98090;
2412 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2413 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2414 devtype = MAX98091;
2415 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2416 } else {
2417 devtype = MAX98090;
2418 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2419 }
2420
2421 if (max98090->devtype != devtype) {
2422 dev_warn(codec->dev, "Mismatch in DT specified CODEC type.\n");
2423 max98090->devtype = devtype;
2424 }
2425
2426 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2427
2428 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2429 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2430 max98090_pll_det_enable_work);
2431 INIT_WORK(&max98090->pll_det_disable_work,
2432 max98090_pll_det_disable_work);
2433 INIT_WORK(&max98090->pll_work, max98090_pll_work);
2434
2435 /* Enable jack detection */
2436 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2437 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2438
2439 /*
2440 * Clear any old interrupts.
2441 * An old interrupt ocurring prior to installing the ISR
2442 * can keep a new interrupt from generating a trigger.
2443 */
2444 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2445
2446 /* High Performance is default */
2447 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2448 M98090_DACHP_MASK,
2449 1 << M98090_DACHP_SHIFT);
2450 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2451 M98090_PERFMODE_MASK,
2452 0 << M98090_PERFMODE_SHIFT);
2453 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2454 M98090_ADCHP_MASK,
2455 1 << M98090_ADCHP_SHIFT);
2456
2457 /* Turn on VCM bandgap reference */
2458 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2459 M98090_VCM_MODE_MASK);
2460
2461 err = device_property_read_u32(codec->dev, "maxim,micbias", &micbias);
2462 if (err) {
2463 micbias = M98090_MBVSEL_2V8;
2464 dev_info(codec->dev, "use default 2.8v micbias\n");
2465 } else if (micbias < M98090_MBVSEL_2V2 || micbias > M98090_MBVSEL_2V8) {
2466 dev_err(codec->dev, "micbias out of range 0x%x\n", micbias);
2467 micbias = M98090_MBVSEL_2V8;
2468 }
2469
2470 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2471 M98090_MBVSEL_MASK, micbias);
2472
2473 max98090_add_widgets(codec);
2474
2475 err_access:
2476 return ret;
2477 }
2478
2479 static int max98090_remove(struct snd_soc_codec *codec)
2480 {
2481 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2482
2483 cancel_delayed_work_sync(&max98090->jack_work);
2484 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2485 cancel_work_sync(&max98090->pll_det_disable_work);
2486 cancel_work_sync(&max98090->pll_work);
2487 max98090->codec = NULL;
2488
2489 return 0;
2490 }
2491
2492 static void max98090_seq_notifier(struct snd_soc_dapm_context *dapm,
2493 enum snd_soc_dapm_type event, int subseq)
2494 {
2495 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
2496 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2497
2498 if (max98090->shdn_pending) {
2499 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2500 M98090_SHDNN_MASK, 0);
2501 msleep(40);
2502 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2503 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2504 max98090->shdn_pending = false;
2505 }
2506 }
2507
2508 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2509 .probe = max98090_probe,
2510 .remove = max98090_remove,
2511 .seq_notifier = max98090_seq_notifier,
2512 .set_bias_level = max98090_set_bias_level,
2513 };
2514
2515 static const struct regmap_config max98090_regmap = {
2516 .reg_bits = 8,
2517 .val_bits = 8,
2518
2519 .max_register = MAX98090_MAX_REGISTER,
2520 .reg_defaults = max98090_reg,
2521 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2522 .volatile_reg = max98090_volatile_register,
2523 .readable_reg = max98090_readable_register,
2524 .cache_type = REGCACHE_RBTREE,
2525 };
2526
2527 static int max98090_i2c_probe(struct i2c_client *i2c,
2528 const struct i2c_device_id *i2c_id)
2529 {
2530 struct max98090_priv *max98090;
2531 const struct acpi_device_id *acpi_id;
2532 kernel_ulong_t driver_data = 0;
2533 int ret;
2534
2535 pr_debug("max98090_i2c_probe\n");
2536
2537 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2538 GFP_KERNEL);
2539 if (max98090 == NULL)
2540 return -ENOMEM;
2541
2542 if (ACPI_HANDLE(&i2c->dev)) {
2543 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2544 &i2c->dev);
2545 if (!acpi_id) {
2546 dev_err(&i2c->dev, "No driver data\n");
2547 return -EINVAL;
2548 }
2549 driver_data = acpi_id->driver_data;
2550 } else if (i2c_id) {
2551 driver_data = i2c_id->driver_data;
2552 }
2553
2554 max98090->devtype = driver_data;
2555 i2c_set_clientdata(i2c, max98090);
2556 max98090->pdata = i2c->dev.platform_data;
2557
2558 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2559 &max98090->dmic_freq);
2560 if (ret < 0)
2561 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2562
2563 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2564 if (IS_ERR(max98090->regmap)) {
2565 ret = PTR_ERR(max98090->regmap);
2566 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2567 goto err_enable;
2568 }
2569
2570 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2571 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2572 "max98090_interrupt", max98090);
2573 if (ret < 0) {
2574 dev_err(&i2c->dev, "request_irq failed: %d\n",
2575 ret);
2576 return ret;
2577 }
2578
2579 ret = snd_soc_register_codec(&i2c->dev,
2580 &soc_codec_dev_max98090, max98090_dai,
2581 ARRAY_SIZE(max98090_dai));
2582 err_enable:
2583 return ret;
2584 }
2585
2586 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2587 {
2588 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2589
2590 /*
2591 * Enable volume smoothing, disable zero cross. This will cause
2592 * a quick 40ms ramp to mute on shutdown.
2593 */
2594 regmap_write(max98090->regmap,
2595 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2596 regmap_write(max98090->regmap,
2597 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2598 msleep(40);
2599 }
2600
2601 static int max98090_i2c_remove(struct i2c_client *client)
2602 {
2603 max98090_i2c_shutdown(client);
2604 snd_soc_unregister_codec(&client->dev);
2605 return 0;
2606 }
2607
2608 #ifdef CONFIG_PM
2609 static int max98090_runtime_resume(struct device *dev)
2610 {
2611 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2612
2613 regcache_cache_only(max98090->regmap, false);
2614
2615 max98090_reset(max98090);
2616
2617 regcache_sync(max98090->regmap);
2618
2619 return 0;
2620 }
2621
2622 static int max98090_runtime_suspend(struct device *dev)
2623 {
2624 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2625
2626 regcache_cache_only(max98090->regmap, true);
2627
2628 return 0;
2629 }
2630 #endif
2631
2632 #ifdef CONFIG_PM_SLEEP
2633 static int max98090_resume(struct device *dev)
2634 {
2635 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2636 unsigned int status;
2637
2638 regcache_mark_dirty(max98090->regmap);
2639
2640 max98090_reset(max98090);
2641
2642 /* clear IRQ status */
2643 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2644
2645 regcache_sync(max98090->regmap);
2646
2647 return 0;
2648 }
2649
2650 static int max98090_suspend(struct device *dev)
2651 {
2652 return 0;
2653 }
2654 #endif
2655
2656 static const struct dev_pm_ops max98090_pm = {
2657 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2658 max98090_runtime_resume, NULL)
2659 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2660 };
2661
2662 static const struct i2c_device_id max98090_i2c_id[] = {
2663 { "max98090", MAX98090 },
2664 { "max98091", MAX98091 },
2665 { }
2666 };
2667 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2668
2669 static const struct of_device_id max98090_of_match[] = {
2670 { .compatible = "maxim,max98090", },
2671 { .compatible = "maxim,max98091", },
2672 { }
2673 };
2674 MODULE_DEVICE_TABLE(of, max98090_of_match);
2675
2676 #ifdef CONFIG_ACPI
2677 static const struct acpi_device_id max98090_acpi_match[] = {
2678 { "193C9890", MAX98090 },
2679 { }
2680 };
2681 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2682 #endif
2683
2684 static struct i2c_driver max98090_i2c_driver = {
2685 .driver = {
2686 .name = "max98090",
2687 .pm = &max98090_pm,
2688 .of_match_table = of_match_ptr(max98090_of_match),
2689 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2690 },
2691 .probe = max98090_i2c_probe,
2692 .shutdown = max98090_i2c_shutdown,
2693 .remove = max98090_i2c_remove,
2694 .id_table = max98090_i2c_id,
2695 };
2696
2697 module_i2c_driver(max98090_i2c_driver);
2698
2699 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2700 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2701 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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