sound/soc/codecs/nau8825.h

   1 /*
   2  * NAU8825 ALSA SoC audio driver
   3  *
   4  * Copyright 2015 Google Inc.
   5  * Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef __NAU8825_H__
  13 #define __NAU8825_H__
  14
  15 #define NAU8825_REG_RESET               0x00
  16 #define NAU8825_REG_ENA_CTRL            0x01
  17 #define NAU8825_REG_IIC_ADDR_SET                0x02
  18 #define NAU8825_REG_CLK_DIVIDER         0x03
  19 #define NAU8825_REG_FLL1                0x04
  20 #define NAU8825_REG_FLL2                0x05
  21 #define NAU8825_REG_FLL3                0x06
  22 #define NAU8825_REG_FLL4                0x07
  23 #define NAU8825_REG_FLL5                0x08
  24 #define NAU8825_REG_FLL6                0x09
  25 #define NAU8825_REG_FLL_VCO_RSV         0x0a
  26 #define NAU8825_REG_HSD_CTRL            0x0c
  27 #define NAU8825_REG_JACK_DET_CTRL               0x0d
  28 #define NAU8825_REG_INTERRUPT_MASK              0x0f
  29 #define NAU8825_REG_IRQ_STATUS          0x10
  30 #define NAU8825_REG_INT_CLR_KEY_STATUS          0x11
  31 #define NAU8825_REG_INTERRUPT_DIS_CTRL          0x12
  32 #define NAU8825_REG_SAR_CTRL            0x13
  33 #define NAU8825_REG_KEYDET_CTRL         0x14
  34 #define NAU8825_REG_VDET_THRESHOLD_1            0x15
  35 #define NAU8825_REG_VDET_THRESHOLD_2            0x16
  36 #define NAU8825_REG_VDET_THRESHOLD_3            0x17
  37 #define NAU8825_REG_VDET_THRESHOLD_4            0x18
  38 #define NAU8825_REG_GPIO34_CTRL         0x19
  39 #define NAU8825_REG_GPIO12_CTRL         0x1a
  40 #define NAU8825_REG_TDM_CTRL            0x1b
  41 #define NAU8825_REG_I2S_PCM_CTRL1               0x1c
  42 #define NAU8825_REG_I2S_PCM_CTRL2               0x1d
  43 #define NAU8825_REG_LEFT_TIME_SLOT              0x1e
  44 #define NAU8825_REG_RIGHT_TIME_SLOT             0x1f
  45 #define NAU8825_REG_BIQ_CTRL            0x20
  46 #define NAU8825_REG_BIQ_COF1            0x21
  47 #define NAU8825_REG_BIQ_COF2            0x22
  48 #define NAU8825_REG_BIQ_COF3            0x23
  49 #define NAU8825_REG_BIQ_COF4            0x24
  50 #define NAU8825_REG_BIQ_COF5            0x25
  51 #define NAU8825_REG_BIQ_COF6            0x26
  52 #define NAU8825_REG_BIQ_COF7            0x27
  53 #define NAU8825_REG_BIQ_COF8            0x28
  54 #define NAU8825_REG_BIQ_COF9            0x29
  55 #define NAU8825_REG_BIQ_COF10           0x2a
  56 #define NAU8825_REG_ADC_RATE            0x2b
  57 #define NAU8825_REG_DAC_CTRL1           0x2c
  58 #define NAU8825_REG_DAC_CTRL2           0x2d
  59 #define NAU8825_REG_DAC_DGAIN_CTRL              0x2f
  60 #define NAU8825_REG_ADC_DGAIN_CTRL              0x30
  61 #define NAU8825_REG_MUTE_CTRL           0x31
  62 #define NAU8825_REG_HSVOL_CTRL          0x32
  63 #define NAU8825_REG_DACL_CTRL           0x33
  64 #define NAU8825_REG_DACR_CTRL           0x34
  65 #define NAU8825_REG_ADC_DRC_KNEE_IP12           0x38
  66 #define NAU8825_REG_ADC_DRC_KNEE_IP34           0x39
  67 #define NAU8825_REG_ADC_DRC_SLOPES              0x3a
  68 #define NAU8825_REG_ADC_DRC_ATKDCY              0x3b
  69 #define NAU8825_REG_DAC_DRC_KNEE_IP12           0x45
  70 #define NAU8825_REG_DAC_DRC_KNEE_IP34           0x46
  71 #define NAU8825_REG_DAC_DRC_SLOPES              0x47
  72 #define NAU8825_REG_DAC_DRC_ATKDCY              0x48
  73 #define NAU8825_REG_IMM_MODE_CTRL               0x4c
  74 #define NAU8825_REG_IMM_RMS_L           0x4d
  75 #define NAU8825_REG_IMM_RMS_R           0x4e
  76 #define NAU8825_REG_CLASSG_CTRL         0x50
  77 #define NAU8825_REG_OPT_EFUSE_CTRL              0x51
  78 #define NAU8825_REG_MISC_CTRL           0x55
  79 #define NAU8825_REG_I2C_DEVICE_ID               0x58
  80 #define NAU8825_REG_SARDOUT_RAM_STATUS          0x59
  81 #define NAU8825_REG_BIAS_ADJ            0x66
  82 #define NAU8825_REG_TRIM_SETTINGS               0x68
  83 #define NAU8825_REG_ANALOG_CONTROL_1            0x69
  84 #define NAU8825_REG_ANALOG_CONTROL_2            0x6a
  85 #define NAU8825_REG_ANALOG_ADC_1                0x71
  86 #define NAU8825_REG_ANALOG_ADC_2                0x72
  87 #define NAU8825_REG_RDAC                0x73
  88 #define NAU8825_REG_MIC_BIAS            0x74
  89 #define NAU8825_REG_BOOST               0x76
  90 #define NAU8825_REG_FEPGA               0x77
  91 #define NAU8825_REG_POWER_UP_CONTROL            0x7f
  92 #define NAU8825_REG_CHARGE_PUMP         0x80
  93 #define NAU8825_REG_CHARGE_PUMP_INPUT_READ              0x81
  94 #define NAU8825_REG_GENERAL_STATUS              0x82
  95 #define NAU8825_REG_MAX         NAU8825_REG_GENERAL_STATUS
  96 /* 16-bit control register address, and 16-bits control register data */
  97 #define NAU8825_REG_ADDR_LEN            16
  98 #define NAU8825_REG_DATA_LEN            16
  99
 100 /* ENA_CTRL (0x1) */
 101 #define NAU8825_ENABLE_DACR_SFT 10
 102 #define NAU8825_ENABLE_DACR     (1 << NAU8825_ENABLE_DACR_SFT)
 103 #define NAU8825_ENABLE_DACL_SFT 9
 104 #define NAU8825_ENABLE_DACL             (1 << NAU8825_ENABLE_DACL_SFT)
 105 #define NAU8825_ENABLE_ADC_SFT  8
 106 #define NAU8825_ENABLE_ADC              (1 << NAU8825_ENABLE_ADC_SFT)
 107 #define NAU8825_ENABLE_ADC_CLK_SFT      7
 108 #define NAU8825_ENABLE_ADC_CLK  (1 << NAU8825_ENABLE_ADC_CLK_SFT)
 109 #define NAU8825_ENABLE_DAC_CLK_SFT      6
 110 #define NAU8825_ENABLE_DAC_CLK  (1 << NAU8825_ENABLE_DAC_CLK_SFT)
 111 #define NAU8825_ENABLE_SAR_SFT  1
 112
 113 /* CLK_DIVIDER (0x3) */
 114 #define NAU8825_CLK_SRC_SFT                     15
 115 #define NAU8825_CLK_SRC_MASK                    (1 << NAU8825_CLK_SRC_SFT)
 116 #define NAU8825_CLK_SRC_VCO                     (1 << NAU8825_CLK_SRC_SFT)
 117 #define NAU8825_CLK_SRC_MCLK                    (0 << NAU8825_CLK_SRC_SFT)
 118 #define NAU8825_CLK_MCLK_SRC_MASK               (0xf << 0)
 119
 120 /* FLL1 (0x04) */
 121 #define NAU8825_FLL_RATIO_MASK                  (0x7f << 0)
 122
 123 /* FLL3 (0x06) */
 124 #define NAU8825_FLL_INTEGER_MASK                (0x3ff << 0)
 125 #define NAU8825_FLL_CLK_SRC_SFT         10
 126 #define NAU8825_FLL_CLK_SRC_MASK                (0x3 << NAU8825_FLL_CLK_SRC_SFT)
 127 #define NAU8825_FLL_CLK_SRC_MCLK                (0 << NAU8825_FLL_CLK_SRC_SFT)
 128 #define NAU8825_FLL_CLK_SRC_BLK         (0x2 << NAU8825_FLL_CLK_SRC_SFT)
 129 #define NAU8825_FLL_CLK_SRC_FS                  (0x3 << NAU8825_FLL_CLK_SRC_SFT)
 130
 131 /* FLL4 (0x07) */
 132 #define NAU8825_FLL_REF_DIV_MASK                (0x3 << 10)
 133
 134 /* FLL5 (0x08) */
 135 #define NAU8825_FLL_PDB_DAC_EN          (0x1 << 15)
 136 #define NAU8825_FLL_LOOP_FTR_EN         (0x1 << 14)
 137 #define NAU8825_FLL_CLK_SW_MASK         (0x1 << 13)
 138 #define NAU8825_FLL_CLK_SW_N2                   (0x1 << 13)
 139 #define NAU8825_FLL_CLK_SW_REF          (0x0 << 13)
 140 #define NAU8825_FLL_FTR_SW_MASK         (0x1 << 12)
 141 #define NAU8825_FLL_FTR_SW_ACCU         (0x1 << 12)
 142 #define NAU8825_FLL_FTR_SW_FILTER               (0x0 << 12)
 143
 144 /* FLL6 (0x9) */
 145 #define NAU8825_DCO_EN                          (0x1 << 15)
 146 #define NAU8825_SDM_EN                          (0x1 << 14)
 147
 148 /* HSD_CTRL (0xc) */
 149 #define NAU8825_HSD_AUTO_MODE   (1 << 6)
 150 /* 0 - open, 1 - short to GND */
 151 #define NAU8825_SPKR_DWN1R      (1 << 1)
 152 #define NAU8825_SPKR_DWN1L      (1 << 0)
 153
 154 /* JACK_DET_CTRL (0xd) */
 155 #define NAU8825_JACK_DET_RESTART        (1 << 9)
 156 #define NAU8825_JACK_DET_DB_BYPASS      (1 << 8)
 157 #define NAU8825_JACK_INSERT_DEBOUNCE_SFT        5
 158 #define NAU8825_JACK_INSERT_DEBOUNCE_MASK       (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
 159 #define NAU8825_JACK_EJECT_DEBOUNCE_SFT         2
 160 #define NAU8825_JACK_EJECT_DEBOUNCE_MASK        (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
 161 #define NAU8825_JACK_POLARITY   (1 << 1) /* 0 - active low, 1 - active high */
 162
 163 /* INTERRUPT_MASK (0xf) */
 164 #define NAU8825_IRQ_OUTPUT_EN (1 << 11)
 165 #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
 166 #define NAU8825_IRQ_RMS_EN (1 << 8)
 167 #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
 168 #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
 169 #define NAU8825_IRQ_EJECT_EN (1 << 2)
 170 #define NAU8825_IRQ_INSERT_EN (1 << 0)
 171
 172 /* IRQ_STATUS (0x10) */
 173 #define NAU8825_HEADSET_COMPLETION_IRQ  (1 << 10)
 174 #define NAU8825_SHORT_CIRCUIT_IRQ       (1 << 9)
 175 #define NAU8825_IMPEDANCE_MEAS_IRQ      (1 << 8)
 176 #define NAU8825_KEY_IRQ_MASK    (0x7 << 5)
 177 #define NAU8825_KEY_RELEASE_IRQ (1 << 7)
 178 #define NAU8825_KEY_LONG_PRESS_IRQ      (1 << 6)
 179 #define NAU8825_KEY_SHORT_PRESS_IRQ     (1 << 5)
 180 #define NAU8825_MIC_DETECTION_IRQ       (1 << 4)
 181 #define NAU8825_JACK_EJECTION_IRQ_MASK  (3 << 2)
 182 #define NAU8825_JACK_EJECTION_DETECTED  (1 << 2)
 183 #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0)
 184 #define NAU8825_JACK_INSERTION_DETECTED (1 << 0)
 185
 186 /* INTERRUPT_DIS_CTRL (0x12) */
 187 #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
 188 #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
 189 #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
 190 #define NAU8825_IRQ_EJECT_DIS (1 << 2)
 191 #define NAU8825_IRQ_INSERT_DIS (1 << 0)
 192
 193 /* SAR_CTRL (0x13) */
 194 #define NAU8825_SAR_ADC_EN_SFT  12
 195 #define NAU8825_SAR_ADC_EN      (1 << NAU8825_SAR_ADC_EN_SFT)
 196 #define NAU8825_SAR_INPUT_MASK  (1 << 11)
 197 #define NAU8825_SAR_INPUT_JKSLV (1 << 11)
 198 #define NAU8825_SAR_INPUT_JKR2  (0 << 11)
 199 #define NAU8825_SAR_TRACKING_GAIN_SFT   8
 200 #define NAU8825_SAR_TRACKING_GAIN_MASK  (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
 201 #define NAU8825_SAR_COMPARE_TIME_SFT    2
 202 #define NAU8825_SAR_COMPARE_TIME_MASK   (3 << 2)
 203 #define NAU8825_SAR_SAMPLING_TIME_SFT   0
 204 #define NAU8825_SAR_SAMPLING_TIME_MASK  (3 << 0)
 205
 206 /* KEYDET_CTRL (0x14) */
 207 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT    12
 208 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK   (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
 209 #define NAU8825_KEYDET_LEVELS_NR_SFT    8
 210 #define NAU8825_KEYDET_LEVELS_NR_MASK   (0x7 << 8)
 211 #define NAU8825_KEYDET_HYSTERESIS_SFT   0
 212 #define NAU8825_KEYDET_HYSTERESIS_MASK  0xf
 213
 214 /* GPIO12_CTRL (0x1a) */
 215 #define NAU8825_JKDET_PULL_UP   (1 << 11) /* 0 - pull down, 1 - pull up */
 216 #define NAU8825_JKDET_PULL_EN   (1 << 9) /* 0 - enable pull, 1 - disable */
 217 #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */
 218
 219 /* I2S_PCM_CTRL1 (0x1c) */
 220 #define NAU8825_I2S_BP_SFT      7
 221 #define NAU8825_I2S_BP_MASK     (1 << NAU8825_I2S_BP_SFT)
 222 #define NAU8825_I2S_BP_INV      (1 << NAU8825_I2S_BP_SFT)
 223 #define NAU8825_I2S_PCMB_SFT    6
 224 #define NAU8825_I2S_PCMB_MASK   (1 << NAU8825_I2S_PCMB_SFT)
 225 #define NAU8825_I2S_PCMB_EN     (1 << NAU8825_I2S_PCMB_SFT)
 226 #define NAU8825_I2S_DL_SFT      2
 227 #define NAU8825_I2S_DL_MASK     (0x3 << NAU8825_I2S_DL_SFT)
 228 #define NAU8825_I2S_DL_16       (0 << NAU8825_I2S_DL_SFT)
 229 #define NAU8825_I2S_DL_20       (1 << NAU8825_I2S_DL_SFT)
 230 #define NAU8825_I2S_DL_24       (2 << NAU8825_I2S_DL_SFT)
 231 #define NAU8825_I2S_DL_32       (3 << NAU8825_I2S_DL_SFT)
 232 #define NAU8825_I2S_DF_SFT      0
 233 #define NAU8825_I2S_DF_MASK     (0x3 << NAU8825_I2S_DF_SFT)
 234 #define NAU8825_I2S_DF_RIGTH    (0 << NAU8825_I2S_DF_SFT)
 235 #define NAU8825_I2S_DF_LEFT     (1 << NAU8825_I2S_DF_SFT)
 236 #define NAU8825_I2S_DF_I2S      (2 << NAU8825_I2S_DF_SFT)
 237 #define NAU8825_I2S_DF_PCM_AB   (3 << NAU8825_I2S_DF_SFT)
 238
 239 /* I2S_PCM_CTRL2 (0x1d) */
 240 #define NAU8825_I2S_TRISTATE    (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
 241 #define NAU8825_I2S_DRV_SFT     12
 242 #define NAU8825_I2S_DRV_MASK    (0x3 << NAU8825_I2S_DRV_SFT)
 243 #define NAU8825_I2S_MS_SFT      3
 244 #define NAU8825_I2S_MS_MASK     (1 << NAU8825_I2S_MS_SFT)
 245 #define NAU8825_I2S_MS_MASTER   (1 << NAU8825_I2S_MS_SFT)
 246 #define NAU8825_I2S_MS_SLAVE    (0 << NAU8825_I2S_MS_SFT)
 247 #define NAU8825_I2S_BLK_DIV_MASK        0x7
 248
 249 /* BIQ_CTRL (0x20) */
 250 #define NAU8825_BIQ_WRT_SFT   4
 251 #define NAU8825_BIQ_WRT_EN     (1 << NAU8825_BIQ_WRT_SFT)
 252 #define NAU8825_BIQ_PATH_SFT   0
 253 #define NAU8825_BIQ_PATH_MASK  (1 << NAU8825_BIQ_PATH_SFT)
 254 #define NAU8825_BIQ_PATH_ADC   (0 << NAU8825_BIQ_PATH_SFT)
 255 #define NAU8825_BIQ_PATH_DAC   (1 << NAU8825_BIQ_PATH_SFT)
 256
 257 /* ADC_RATE (0x2b) */
 258 #define NAU8825_ADC_SYNC_DOWN_SFT       0
 259 #define NAU8825_ADC_SYNC_DOWN_MASK      0x3
 260 #define NAU8825_ADC_SYNC_DOWN_32        0
 261 #define NAU8825_ADC_SYNC_DOWN_64        1
 262 #define NAU8825_ADC_SYNC_DOWN_128       2
 263 #define NAU8825_ADC_SYNC_DOWN_256       3
 264
 265 /* DAC_CTRL1 (0x2c) */
 266 #define NAU8825_DAC_CLIP_OFF    (1 << 7)
 267 #define NAU8825_DAC_OVERSAMPLE_SFT      0
 268 #define NAU8825_DAC_OVERSAMPLE_MASK     0x7
 269 #define NAU8825_DAC_OVERSAMPLE_64       0
 270 #define NAU8825_DAC_OVERSAMPLE_256      1
 271 #define NAU8825_DAC_OVERSAMPLE_128      2
 272 #define NAU8825_DAC_OVERSAMPLE_32       4
 273
 274 /* ADC_DGAIN_CTRL (0x30) */
 275 #define NAU8825_ADC_DIG_VOL_MASK        0xff
 276
 277 /* MUTE_CTRL (0x31) */
 278 #define NAU8825_DAC_ZERO_CROSSING_EN    (1 << 9)
 279 #define NAU8825_DAC_SOFT_MUTE   (1 << 9)
 280
 281 /* HSVOL_CTRL (0x32) */
 282 #define NAU8825_HP_MUTE (1 << 15)
 283 #define NAU8825_HP_MUTE_AUTO    (1 << 14)
 284 #define NAU8825_HPL_MUTE        (1 << 13)
 285 #define NAU8825_HPR_MUTE        (1 << 12)
 286 #define NAU8825_HPL_VOL_SFT     6
 287 #define NAU8825_HPL_VOL_MASK    (0x3f << NAU8825_HPL_VOL_SFT)
 288 #define NAU8825_HPR_VOL_SFT     0
 289 #define NAU8825_HPR_VOL_MASK    (0x3f << NAU8825_HPR_VOL_SFT)
 290 #define NAU8825_HP_VOL_MIN      0x36
 291
 292 /* DACL_CTRL (0x33) */
 293 #define NAU8825_DACL_CH_SEL_SFT 9
 294 #define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT)
 295 #define NAU8825_DACL_CH_SEL_L    (0x0 << NAU8825_DACL_CH_SEL_SFT)
 296 #define NAU8825_DACL_CH_SEL_R    (0x1 << NAU8825_DACL_CH_SEL_SFT)
 297 #define NAU8825_DACL_CH_VOL_MASK        0xff
 298
 299 /* DACR_CTRL (0x34) */
 300 #define NAU8825_DACR_CH_SEL_SFT 9
 301 #define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT)
 302 #define NAU8825_DACR_CH_SEL_L    (0x0 << NAU8825_DACR_CH_SEL_SFT)
 303 #define NAU8825_DACR_CH_SEL_R    (0x1 << NAU8825_DACR_CH_SEL_SFT)
 304 #define NAU8825_DACR_CH_VOL_MASK        0xff
 305
 306 /* IMM_MODE_CTRL (0x4C) */
 307 #define NAU8825_IMM_THD_SFT             8
 308 #define NAU8825_IMM_THD_MASK            (0x3f << NAU8825_IMM_THD_SFT)
 309 #define NAU8825_IMM_GEN_VOL_SFT 6
 310 #define NAU8825_IMM_GEN_VOL_MASK        (0x3 << NAU8825_IMM_GEN_VOL_SFT)
 311 #define NAU8825_IMM_GEN_VOL_1_2nd       (0x0 << NAU8825_IMM_GEN_VOL_SFT)
 312 #define NAU8825_IMM_GEN_VOL_1_4th       (0x1 << NAU8825_IMM_GEN_VOL_SFT)
 313 #define NAU8825_IMM_GEN_VOL_1_8th       (0x2 << NAU8825_IMM_GEN_VOL_SFT)
 314 #define NAU8825_IMM_GEN_VOL_1_16th      (0x3 << NAU8825_IMM_GEN_VOL_SFT)
 315
 316 #define NAU8825_IMM_CYC_SFT             4
 317 #define NAU8825_IMM_CYC_MASK            (0x3 << NAU8825_IMM_CYC_SFT)
 318 #define NAU8825_IMM_CYC_1024            (0x0 << NAU8825_IMM_CYC_SFT)
 319 #define NAU8825_IMM_CYC_2048            (0x1 << NAU8825_IMM_CYC_SFT)
 320 #define NAU8825_IMM_CYC_4096            (0x2 << NAU8825_IMM_CYC_SFT)
 321 #define NAU8825_IMM_CYC_8192            (0x3 << NAU8825_IMM_CYC_SFT)
 322 #define NAU8825_IMM_EN                  (1 << 3)
 323 #define NAU8825_IMM_DAC_SRC_MASK        0x7
 324 #define NAU8825_IMM_DAC_SRC_BIQ 0x0
 325 #define NAU8825_IMM_DAC_SRC_DRC 0x1
 326 #define NAU8825_IMM_DAC_SRC_MIX 0x2
 327 #define NAU8825_IMM_DAC_SRC_SIN 0x3
 328
 329 /* CLASSG_CTRL (0x50) */
 330 #define NAU8825_CLASSG_TIMER_SFT        8
 331 #define NAU8825_CLASSG_TIMER_MASK       (0x3f << NAU8825_CLASSG_TIMER_SFT)
 332 #define NAU8825_CLASSG_TIMER_1ms        (0x1 << NAU8825_CLASSG_TIMER_SFT)
 333 #define NAU8825_CLASSG_TIMER_2ms        (0x2 << NAU8825_CLASSG_TIMER_SFT)
 334 #define NAU8825_CLASSG_TIMER_8ms        (0x4 << NAU8825_CLASSG_TIMER_SFT)
 335 #define NAU8825_CLASSG_TIMER_16ms       (0x8 << NAU8825_CLASSG_TIMER_SFT)
 336 #define NAU8825_CLASSG_TIMER_32ms       (0x10 << NAU8825_CLASSG_TIMER_SFT)
 337 #define NAU8825_CLASSG_TIMER_64ms       (0x20 << NAU8825_CLASSG_TIMER_SFT)
 338 #define NAU8825_CLASSG_LDAC_EN          (0x1 << 2)
 339 #define NAU8825_CLASSG_RDAC_EN          (0x1 << 1)
 340 #define NAU8825_CLASSG_EN               (1 << 0)
 341
 342 /* I2C_DEVICE_ID (0x58) */
 343 #define NAU8825_GPIO2JD1        (1 << 7)
 344 #define NAU8825_SOFTWARE_ID_MASK        0x3
 345 #define NAU8825_SOFTWARE_ID_NAU8825     0x0
 346
 347 /* BIAS_ADJ (0x66) */
 348 #define NAU8825_BIAS_HPR_IMP            (1 << 15)
 349 #define NAU8825_BIAS_HPL_IMP            (1 << 14)
 350 #define NAU8825_BIAS_TESTDAC_SFT        8
 351 #define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT)
 352 #define NAU8825_BIAS_TESTDACR_EN        (0x2 << NAU8825_BIAS_TESTDAC_SFT)
 353 #define NAU8825_BIAS_TESTDACL_EN        (0x1 << NAU8825_BIAS_TESTDAC_SFT)
 354 #define NAU8825_BIAS_VMID       (1 << 6)
 355 #define NAU8825_BIAS_VMID_SEL_SFT       4
 356 #define NAU8825_BIAS_VMID_SEL_MASK      (3 << NAU8825_BIAS_VMID_SEL_SFT)
 357
 358 /* ANALOG_CONTROL_2 (0x6a) */
 359 #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
 360 #define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
 361 #define NAU8825_DAC_CAPACITOR_LSB (1 << 0)
 362
 363 /* ANALOG_ADC_2 (0x72) */
 364 #define NAU8825_ADC_VREFSEL_MASK        (0x3 << 8)
 365 #define NAU8825_ADC_VREFSEL_ANALOG      (0 << 8)
 366 #define NAU8825_ADC_VREFSEL_VMID        (1 << 8)
 367 #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB     (2 << 8)
 368 #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB       (3 << 8)
 369 #define NAU8825_POWERUP_ADCL    (1 << 6)
 370
 371 /* RDAC (0x73) */
 372 #define NAU8825_RDAC_FS_BCLK_ENB        (1 << 15)
 373 #define NAU8825_RDAC_EN_SFT             12
 374 #define NAU8825_RDAC_EN         (0x3 << NAU8825_RDAC_EN_SFT)
 375 #define NAU8825_RDAC_CLK_EN_SFT 8
 376 #define NAU8825_RDAC_CLK_EN             (0x3 << NAU8825_RDAC_CLK_EN_SFT)
 377 #define NAU8825_RDAC_CLK_DELAY_SFT      4
 378 #define NAU8825_RDAC_CLK_DELAY_MASK     (0x7 << NAU8825_RDAC_CLK_DELAY_SFT)
 379 #define NAU8825_RDAC_VREF_SFT   2
 380 #define NAU8825_RDAC_VREF_MASK  (0x3 << NAU8825_RDAC_VREF_SFT)
 381
 382 /* MIC_BIAS (0x74) */
 383 #define NAU8825_MICBIAS_JKSLV   (1 << 14)
 384 #define NAU8825_MICBIAS_JKR2    (1 << 12)
 385 #define NAU8825_MICBIAS_POWERUP_SFT     8
 386 #define NAU8825_MICBIAS_VOLTAGE_SFT     0
 387 #define NAU8825_MICBIAS_VOLTAGE_MASK    0x7
 388
 389 /* BOOST (0x76) */
 390 #define NAU8825_PRECHARGE_DIS   (1 << 13)
 391 #define NAU8825_GLOBAL_BIAS_EN  (1 << 12)
 392 #define NAU8825_HP_BOOST_DIS            (1 << 9)
 393 #define NAU8825_HP_BOOST_G_DIS  (1 << 8)
 394 #define NAU8825_SHORT_SHUTDOWN_EN       (1 << 6)
 395
 396 /* POWER_UP_CONTROL (0x7f) */
 397 #define NAU8825_POWERUP_INTEGR_R        (1 << 5)
 398 #define NAU8825_POWERUP_INTEGR_L        (1 << 4)
 399 #define NAU8825_POWERUP_DRV_IN_R        (1 << 3)
 400 #define NAU8825_POWERUP_DRV_IN_L        (1 << 2)
 401 #define NAU8825_POWERUP_HP_DRV_R        (1 << 1)
 402 #define NAU8825_POWERUP_HP_DRV_L        (1 << 0)
 403
 404 /* CHARGE_PUMP (0x80) */
 405 #define NAU8825_JAMNODCLOW      (1 << 10)
 406 #define NAU8825_POWER_DOWN_DACR (1 << 9)
 407 #define NAU8825_POWER_DOWN_DACL (1 << 8)
 408 #define NAU8825_CHANRGE_PUMP_EN (1 << 5)
 409
 410
 411 /* System Clock Source */
 412 enum {
 413         NAU8825_CLK_DIS = 0,
 414         NAU8825_CLK_MCLK,
 415         NAU8825_CLK_INTERNAL,
 416         NAU8825_CLK_FLL_MCLK,
 417         NAU8825_CLK_FLL_BLK,
 418         NAU8825_CLK_FLL_FS,
 419 };
 420
 421 /* Cross talk detection state */
 422 enum {
 423         NAU8825_XTALK_PREPARE = 0,
 424         NAU8825_XTALK_HPR_R2L,
 425         NAU8825_XTALK_HPL_R2L,
 426         NAU8825_XTALK_IMM,
 427         NAU8825_XTALK_DONE,
 428 };
 429
 430 struct nau8825 {
 431         struct device *dev;
 432         struct regmap *regmap;
 433         struct snd_soc_dapm_context *dapm;
 434         struct snd_soc_jack *jack;
 435         struct clk *mclk;
 436         struct work_struct xtalk_work;
 437         struct semaphore xtalk_sem;
 438         int irq;
 439         int mclk_freq; /* 0 - mclk is disabled */
 440         int button_pressed;
 441         int micbias_voltage;
 442         int vref_impedance;
 443         bool jkdet_enable;
 444         bool jkdet_pull_enable;
 445         bool jkdet_pull_up;
 446         int jkdet_polarity;
 447         int sar_threshold_num;
 448         int sar_threshold[8];
 449         int sar_hysteresis;
 450         int sar_voltage;
 451         int sar_compare_time;
 452         int sar_sampling_time;
 453         int key_debounce;
 454         int jack_insert_debounce;
 455         int jack_eject_debounce;
 456         int high_imped;
 457         int xtalk_state;
 458         int xtalk_event;
 459         int xtalk_event_mask;
 460         bool xtalk_protect;
 461         int imp_rms[NAU8825_XTALK_IMM];
 462 };
 463
 464 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
 465                                 struct snd_soc_jack *jack);
 466
 467
 468 #endif  /* __NAU8825_H__ */