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ASoC: pcm512x: Avoid the PLL for the DAC clock, if possible
[deliverable/linux.git] / sound / soc / codecs / pcm512x.c
1 /*
2 * Driver for the PCM512x CODECs
3 *
4 * Author: Mark Brown <broonie@linaro.org>
5 * Copyright 2014 Linaro Ltd
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/gcd.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/tlv.h>
29
30 #include "pcm512x.h"
31
32 #define DIV_ROUND_DOWN_ULL(ll, d) \
33 ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
34 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
35 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
36
37 #define PCM512x_NUM_SUPPLIES 3
38 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
39 "AVDD",
40 "DVDD",
41 "CPVDD",
42 };
43
44 struct pcm512x_priv {
45 struct regmap *regmap;
46 struct clk *sclk;
47 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
48 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
49 int fmt;
50 int pll_in;
51 int pll_out;
52 int pll_r;
53 int pll_j;
54 int pll_d;
55 int pll_p;
56 unsigned long real_pll;
57 };
58
59 /*
60 * We can't use the same notifier block for more than one supply and
61 * there's no way I can see to get from a callback to the caller
62 * except container_of().
63 */
64 #define PCM512x_REGULATOR_EVENT(n) \
65 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
66 unsigned long event, void *data) \
67 { \
68 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
69 supply_nb[n]); \
70 if (event & REGULATOR_EVENT_DISABLE) { \
71 regcache_mark_dirty(pcm512x->regmap); \
72 regcache_cache_only(pcm512x->regmap, true); \
73 } \
74 return 0; \
75 }
76
77 PCM512x_REGULATOR_EVENT(0)
78 PCM512x_REGULATOR_EVENT(1)
79 PCM512x_REGULATOR_EVENT(2)
80
81 static const struct reg_default pcm512x_reg_defaults[] = {
82 { PCM512x_RESET, 0x00 },
83 { PCM512x_POWER, 0x00 },
84 { PCM512x_MUTE, 0x00 },
85 { PCM512x_DSP, 0x00 },
86 { PCM512x_PLL_REF, 0x00 },
87 { PCM512x_DAC_REF, 0x00 },
88 { PCM512x_DAC_ROUTING, 0x11 },
89 { PCM512x_DSP_PROGRAM, 0x01 },
90 { PCM512x_CLKDET, 0x00 },
91 { PCM512x_AUTO_MUTE, 0x00 },
92 { PCM512x_ERROR_DETECT, 0x00 },
93 { PCM512x_DIGITAL_VOLUME_1, 0x00 },
94 { PCM512x_DIGITAL_VOLUME_2, 0x30 },
95 { PCM512x_DIGITAL_VOLUME_3, 0x30 },
96 { PCM512x_DIGITAL_MUTE_1, 0x22 },
97 { PCM512x_DIGITAL_MUTE_2, 0x00 },
98 { PCM512x_DIGITAL_MUTE_3, 0x07 },
99 { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
100 { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
101 { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
102 { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
103 { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
104 { PCM512x_VCOM_CTRL_1, 0x00 },
105 { PCM512x_VCOM_CTRL_2, 0x01 },
106 { PCM512x_BCLK_LRCLK_CFG, 0x00 },
107 { PCM512x_MASTER_MODE, 0x7c },
108 { PCM512x_GPIO_DACIN, 0x00 },
109 { PCM512x_GPIO_PLLIN, 0x00 },
110 { PCM512x_SYNCHRONIZE, 0x10 },
111 { PCM512x_PLL_COEFF_0, 0x00 },
112 { PCM512x_PLL_COEFF_1, 0x00 },
113 { PCM512x_PLL_COEFF_2, 0x00 },
114 { PCM512x_PLL_COEFF_3, 0x00 },
115 { PCM512x_PLL_COEFF_4, 0x00 },
116 { PCM512x_DSP_CLKDIV, 0x00 },
117 { PCM512x_DAC_CLKDIV, 0x00 },
118 { PCM512x_NCP_CLKDIV, 0x00 },
119 { PCM512x_OSR_CLKDIV, 0x00 },
120 { PCM512x_MASTER_CLKDIV_1, 0x00 },
121 { PCM512x_MASTER_CLKDIV_2, 0x00 },
122 { PCM512x_FS_SPEED_MODE, 0x00 },
123 { PCM512x_IDAC_1, 0x01 },
124 { PCM512x_IDAC_2, 0x00 },
125 };
126
127 static bool pcm512x_readable(struct device *dev, unsigned int reg)
128 {
129 switch (reg) {
130 case PCM512x_RESET:
131 case PCM512x_POWER:
132 case PCM512x_MUTE:
133 case PCM512x_PLL_EN:
134 case PCM512x_SPI_MISO_FUNCTION:
135 case PCM512x_DSP:
136 case PCM512x_GPIO_EN:
137 case PCM512x_BCLK_LRCLK_CFG:
138 case PCM512x_DSP_GPIO_INPUT:
139 case PCM512x_MASTER_MODE:
140 case PCM512x_PLL_REF:
141 case PCM512x_DAC_REF:
142 case PCM512x_GPIO_DACIN:
143 case PCM512x_GPIO_PLLIN:
144 case PCM512x_SYNCHRONIZE:
145 case PCM512x_PLL_COEFF_0:
146 case PCM512x_PLL_COEFF_1:
147 case PCM512x_PLL_COEFF_2:
148 case PCM512x_PLL_COEFF_3:
149 case PCM512x_PLL_COEFF_4:
150 case PCM512x_DSP_CLKDIV:
151 case PCM512x_DAC_CLKDIV:
152 case PCM512x_NCP_CLKDIV:
153 case PCM512x_OSR_CLKDIV:
154 case PCM512x_MASTER_CLKDIV_1:
155 case PCM512x_MASTER_CLKDIV_2:
156 case PCM512x_FS_SPEED_MODE:
157 case PCM512x_IDAC_1:
158 case PCM512x_IDAC_2:
159 case PCM512x_ERROR_DETECT:
160 case PCM512x_I2S_1:
161 case PCM512x_I2S_2:
162 case PCM512x_DAC_ROUTING:
163 case PCM512x_DSP_PROGRAM:
164 case PCM512x_CLKDET:
165 case PCM512x_AUTO_MUTE:
166 case PCM512x_DIGITAL_VOLUME_1:
167 case PCM512x_DIGITAL_VOLUME_2:
168 case PCM512x_DIGITAL_VOLUME_3:
169 case PCM512x_DIGITAL_MUTE_1:
170 case PCM512x_DIGITAL_MUTE_2:
171 case PCM512x_DIGITAL_MUTE_3:
172 case PCM512x_GPIO_OUTPUT_1:
173 case PCM512x_GPIO_OUTPUT_2:
174 case PCM512x_GPIO_OUTPUT_3:
175 case PCM512x_GPIO_OUTPUT_4:
176 case PCM512x_GPIO_OUTPUT_5:
177 case PCM512x_GPIO_OUTPUT_6:
178 case PCM512x_GPIO_CONTROL_1:
179 case PCM512x_GPIO_CONTROL_2:
180 case PCM512x_OVERFLOW:
181 case PCM512x_RATE_DET_1:
182 case PCM512x_RATE_DET_2:
183 case PCM512x_RATE_DET_3:
184 case PCM512x_RATE_DET_4:
185 case PCM512x_CLOCK_STATUS:
186 case PCM512x_ANALOG_MUTE_DET:
187 case PCM512x_GPIN:
188 case PCM512x_DIGITAL_MUTE_DET:
189 case PCM512x_OUTPUT_AMPLITUDE:
190 case PCM512x_ANALOG_GAIN_CTRL:
191 case PCM512x_UNDERVOLTAGE_PROT:
192 case PCM512x_ANALOG_MUTE_CTRL:
193 case PCM512x_ANALOG_GAIN_BOOST:
194 case PCM512x_VCOM_CTRL_1:
195 case PCM512x_VCOM_CTRL_2:
196 case PCM512x_CRAM_CTRL:
197 case PCM512x_FLEX_A:
198 case PCM512x_FLEX_B:
199 return true;
200 default:
201 /* There are 256 raw register addresses */
202 return reg < 0xff;
203 }
204 }
205
206 static bool pcm512x_volatile(struct device *dev, unsigned int reg)
207 {
208 switch (reg) {
209 case PCM512x_PLL_EN:
210 case PCM512x_OVERFLOW:
211 case PCM512x_RATE_DET_1:
212 case PCM512x_RATE_DET_2:
213 case PCM512x_RATE_DET_3:
214 case PCM512x_RATE_DET_4:
215 case PCM512x_CLOCK_STATUS:
216 case PCM512x_ANALOG_MUTE_DET:
217 case PCM512x_GPIN:
218 case PCM512x_DIGITAL_MUTE_DET:
219 case PCM512x_CRAM_CTRL:
220 return true;
221 default:
222 /* There are 256 raw register addresses */
223 return reg < 0xff;
224 }
225 }
226
227 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
228 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
229 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
230
231 static const char * const pcm512x_dsp_program_texts[] = {
232 "FIR interpolation with de-emphasis",
233 "Low latency IIR with de-emphasis",
234 "Fixed process flow",
235 "High attenuation with de-emphasis",
236 "Ringing-less low latency FIR",
237 };
238
239 static const unsigned int pcm512x_dsp_program_values[] = {
240 1,
241 2,
242 3,
243 5,
244 7,
245 };
246
247 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
248 PCM512x_DSP_PROGRAM, 0, 0x1f,
249 pcm512x_dsp_program_texts,
250 pcm512x_dsp_program_values);
251
252 static const char * const pcm512x_clk_missing_text[] = {
253 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
254 };
255
256 static const struct soc_enum pcm512x_clk_missing =
257 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
258
259 static const char * const pcm512x_autom_text[] = {
260 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
261 };
262
263 static const struct soc_enum pcm512x_autom_l =
264 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
265 pcm512x_autom_text);
266
267 static const struct soc_enum pcm512x_autom_r =
268 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
269 pcm512x_autom_text);
270
271 static const char * const pcm512x_ramp_rate_text[] = {
272 "1 sample/update", "2 samples/update", "4 samples/update",
273 "Immediate"
274 };
275
276 static const struct soc_enum pcm512x_vndf =
277 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
278 pcm512x_ramp_rate_text);
279
280 static const struct soc_enum pcm512x_vnuf =
281 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
282 pcm512x_ramp_rate_text);
283
284 static const struct soc_enum pcm512x_vedf =
285 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
286 pcm512x_ramp_rate_text);
287
288 static const char * const pcm512x_ramp_step_text[] = {
289 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
290 };
291
292 static const struct soc_enum pcm512x_vnds =
293 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
294 pcm512x_ramp_step_text);
295
296 static const struct soc_enum pcm512x_vnus =
297 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
298 pcm512x_ramp_step_text);
299
300 static const struct soc_enum pcm512x_veds =
301 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
302 pcm512x_ramp_step_text);
303
304 static const struct snd_kcontrol_new pcm512x_controls[] = {
305 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
306 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
307 SOC_DOUBLE_TLV("Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
308 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
309 SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
310 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
311 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
312 PCM512x_RQMR_SHIFT, 1, 1),
313
314 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
315 SOC_ENUM("DSP Program", pcm512x_dsp_program),
316
317 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
318 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
319 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
320 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
321 PCM512x_ACTL_SHIFT, 1, 0),
322 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
323 PCM512x_AMRE_SHIFT, 1, 0),
324
325 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
326 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
327 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
328 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
329 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
330 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
331 };
332
333 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
334 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
335 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
336
337 SND_SOC_DAPM_OUTPUT("OUTL"),
338 SND_SOC_DAPM_OUTPUT("OUTR"),
339 };
340
341 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
342 { "DACL", NULL, "Playback" },
343 { "DACR", NULL, "Playback" },
344
345 { "OUTL", NULL, "DACL" },
346 { "OUTR", NULL, "DACR" },
347 };
348
349 static const u32 pcm512x_dai_rates[] = {
350 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
351 88200, 96000, 176400, 192000, 384000,
352 };
353
354 static const struct snd_pcm_hw_constraint_list constraints_slave = {
355 .count = ARRAY_SIZE(pcm512x_dai_rates),
356 .list = pcm512x_dai_rates,
357 };
358
359 static const struct snd_interval pcm512x_dai_ranges_64bpf[] = {
360 {
361 .min = 8000,
362 .max = 195312,
363 }, {
364 .min = 250000,
365 .max = 390625,
366 },
367 };
368
369 static struct snd_pcm_hw_constraint_ranges constraints_64bpf = {
370 .count = ARRAY_SIZE(pcm512x_dai_ranges_64bpf),
371 .ranges = pcm512x_dai_ranges_64bpf,
372 };
373
374 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
375 struct snd_pcm_hw_rule *rule)
376 {
377 struct snd_pcm_hw_constraint_ranges *r = rule->private;
378 int frame_size;
379
380 frame_size = snd_soc_params_to_frame_size(params);
381 if (frame_size < 0)
382 return frame_size;
383
384 if (frame_size != 64)
385 return 0;
386
387 return snd_interval_ranges(hw_param_interval(params, rule->var),
388 r->count, r->ranges, r->mask);
389 }
390
391 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
392 struct snd_soc_dai *dai)
393 {
394 struct snd_soc_codec *codec = dai->codec;
395 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
396 struct device *dev = dai->dev;
397 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
398 struct snd_ratnum *rats_no_pll;
399
400 if (IS_ERR(pcm512x->sclk)) {
401 dev_err(dev, "Need SCLK for master mode: %ld\n",
402 PTR_ERR(pcm512x->sclk));
403 return PTR_ERR(pcm512x->sclk);
404 }
405
406 if (pcm512x->pll_out)
407 return snd_pcm_hw_rule_add(substream->runtime, 0,
408 SNDRV_PCM_HW_PARAM_RATE,
409 pcm512x_hw_rule_rate,
410 (void *)&constraints_64bpf,
411 SNDRV_PCM_HW_PARAM_FRAME_BITS,
412 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
413
414 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
415 GFP_KERNEL);
416 if (!constraints_no_pll)
417 return -ENOMEM;
418 constraints_no_pll->nrats = 1;
419 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
420 if (!rats_no_pll)
421 return -ENOMEM;
422 constraints_no_pll->rats = rats_no_pll;
423 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
424 rats_no_pll->den_min = 1;
425 rats_no_pll->den_max = 128;
426 rats_no_pll->den_step = 1;
427
428 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
429 SNDRV_PCM_HW_PARAM_RATE,
430 constraints_no_pll);
431 }
432
433 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
434 struct snd_soc_dai *dai)
435 {
436 struct snd_soc_codec *codec = dai->codec;
437 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
438 struct device *dev = dai->dev;
439 struct regmap *regmap = pcm512x->regmap;
440
441 if (IS_ERR(pcm512x->sclk)) {
442 dev_info(dev, "No SCLK, using BCLK: %ld\n",
443 PTR_ERR(pcm512x->sclk));
444
445 /* Disable reporting of missing SCLK as an error */
446 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
447 PCM512x_IDCH, PCM512x_IDCH);
448
449 /* Switch PLL input to BCLK */
450 regmap_update_bits(regmap, PCM512x_PLL_REF,
451 PCM512x_SREF, PCM512x_SREF_BCK);
452 }
453
454 return snd_pcm_hw_constraint_list(substream->runtime, 0,
455 SNDRV_PCM_HW_PARAM_RATE,
456 &constraints_slave);
457 }
458
459 static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
460 struct snd_soc_dai *dai)
461 {
462 struct snd_soc_codec *codec = dai->codec;
463 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
464
465 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
466 case SND_SOC_DAIFMT_CBM_CFM:
467 return pcm512x_dai_startup_master(substream, dai);
468
469 case SND_SOC_DAIFMT_CBS_CFS:
470 return pcm512x_dai_startup_slave(substream, dai);
471
472 default:
473 return -EINVAL;
474 }
475 }
476
477 static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
478 enum snd_soc_bias_level level)
479 {
480 struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev);
481 int ret;
482
483 switch (level) {
484 case SND_SOC_BIAS_ON:
485 case SND_SOC_BIAS_PREPARE:
486 break;
487
488 case SND_SOC_BIAS_STANDBY:
489 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
490 PCM512x_RQST, 0);
491 if (ret != 0) {
492 dev_err(codec->dev, "Failed to remove standby: %d\n",
493 ret);
494 return ret;
495 }
496 break;
497
498 case SND_SOC_BIAS_OFF:
499 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
500 PCM512x_RQST, PCM512x_RQST);
501 if (ret != 0) {
502 dev_err(codec->dev, "Failed to request standby: %d\n",
503 ret);
504 return ret;
505 }
506 break;
507 }
508
509 codec->dapm.bias_level = level;
510
511 return 0;
512 }
513
514 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
515 unsigned long bclk_rate)
516 {
517 struct device *dev = dai->dev;
518 unsigned long sck_rate;
519 int pow2;
520
521 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
522 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
523
524 /* select sck_rate as a multiple of bclk_rate but still with
525 * as many factors of 2 as possible, as that makes it easier
526 * to find a fast DAC rate
527 */
528 pow2 = 1 << fls((25000000 - 16000000) / bclk_rate);
529 for (; pow2; pow2 >>= 1) {
530 sck_rate = rounddown(25000000, bclk_rate * pow2);
531 if (sck_rate >= 16000000)
532 break;
533 }
534 if (!pow2) {
535 dev_err(dev, "Impossible to generate a suitable SCK\n");
536 return 0;
537 }
538
539 dev_dbg(dev, "sck_rate %lu\n", sck_rate);
540 return sck_rate;
541 }
542
543 /* pll_rate = pllin_rate * R * J.D / P
544 * 1 <= R <= 16
545 * 1 <= J <= 63
546 * 0 <= D <= 9999
547 * 1 <= P <= 15
548 * 64 MHz <= pll_rate <= 100 MHz
549 * if D == 0
550 * 1 MHz <= pllin_rate / P <= 20 MHz
551 * else if D > 0
552 * 6.667 MHz <= pllin_rate / P <= 20 MHz
553 * 4 <= J <= 11
554 * R = 1
555 */
556 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
557 unsigned long pllin_rate,
558 unsigned long pll_rate)
559 {
560 struct device *dev = dai->dev;
561 struct snd_soc_codec *codec = dai->codec;
562 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
563 unsigned long common;
564 int R, J, D, P;
565 unsigned long K; /* 10000 * J.D */
566 unsigned long num;
567 unsigned long den;
568
569 common = gcd(pll_rate, pllin_rate);
570 dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
571 pll_rate, pllin_rate, common);
572 num = pll_rate / common;
573 den = pllin_rate / common;
574
575 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
576 if (pllin_rate / den > 20000000 && num < 8) {
577 num *= 20000000 / (pllin_rate / den);
578 den *= 20000000 / (pllin_rate / den);
579 }
580 dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
581
582 P = den;
583 if (den <= 15 && num <= 16 * 63
584 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
585 /* Try the case with D = 0 */
586 D = 0;
587 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
588 for (R = 16; R; R--) {
589 if (num % R)
590 continue;
591 J = num / R;
592 if (J == 0 || J > 63)
593 continue;
594
595 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
596 pcm512x->real_pll = pll_rate;
597 goto done;
598 }
599 /* no luck */
600 }
601
602 R = 1;
603
604 if (num > 0xffffffffUL / 10000)
605 goto fallback;
606
607 /* Try to find an exact pll_rate using the D > 0 case */
608 common = gcd(10000 * num, den);
609 num = 10000 * num / common;
610 den /= common;
611 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
612
613 for (P = den; P <= 15; P++) {
614 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
615 continue;
616 if (num * P % den)
617 continue;
618 K = num * P / den;
619 /* J == 12 is ok if D == 0 */
620 if (K < 40000 || K > 120000)
621 continue;
622
623 J = K / 10000;
624 D = K % 10000;
625 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
626 pcm512x->real_pll = pll_rate;
627 goto done;
628 }
629
630 /* Fall back to an approximate pll_rate */
631
632 fallback:
633 /* find smallest possible P */
634 P = DIV_ROUND_UP(pllin_rate, 20000000);
635 if (!P)
636 P = 1;
637 else if (P > 15) {
638 dev_err(dev, "Need a slower clock as pll-input\n");
639 return -EINVAL;
640 }
641 if (pllin_rate / P < 6667000) {
642 dev_err(dev, "Need a faster clock as pll-input\n");
643 return -EINVAL;
644 }
645 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
646 if (K < 40000)
647 K = 40000;
648 /* J == 12 is ok if D == 0 */
649 if (K > 120000)
650 K = 120000;
651 J = K / 10000;
652 D = K % 10000;
653 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
654 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
655
656 done:
657 pcm512x->pll_r = R;
658 pcm512x->pll_j = J;
659 pcm512x->pll_d = D;
660 pcm512x->pll_p = P;
661 return 0;
662 }
663
664 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
665 unsigned long osr_rate,
666 unsigned long pllin_rate)
667 {
668 struct snd_soc_codec *codec = dai->codec;
669 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
670 unsigned long dac_rate;
671
672 if (!pcm512x->pll_out)
673 return 0; /* no PLL to bypass, force SCK as DAC input */
674
675 if (pllin_rate % osr_rate)
676 return 0; /* futile, quit early */
677
678 /* run DAC no faster than 6144000 Hz */
679 for (dac_rate = rounddown(6144000, osr_rate);
680 dac_rate;
681 dac_rate -= osr_rate) {
682
683 if (pllin_rate / dac_rate > 128)
684 return 0; /* DAC divider would be too big */
685
686 if (!(pllin_rate % dac_rate))
687 return dac_rate;
688
689 dac_rate -= osr_rate;
690 }
691
692 return 0;
693 }
694
695 static int pcm512x_set_dividers(struct snd_soc_dai *dai,
696 struct snd_pcm_hw_params *params)
697 {
698 struct device *dev = dai->dev;
699 struct snd_soc_codec *codec = dai->codec;
700 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
701 unsigned long pllin_rate = 0;
702 unsigned long pll_rate;
703 unsigned long sck_rate;
704 unsigned long mck_rate;
705 unsigned long bclk_rate;
706 unsigned long sample_rate;
707 unsigned long osr_rate;
708 unsigned long dacsrc_rate;
709 int bclk_div;
710 int lrclk_div;
711 int dsp_div;
712 int dac_div;
713 unsigned long dac_rate;
714 int ncp_div;
715 int osr_div;
716 int ret;
717 int idac;
718 int fssp;
719 int gpio;
720
721 lrclk_div = snd_soc_params_to_frame_size(params);
722 if (lrclk_div == 0) {
723 dev_err(dev, "No LRCLK?\n");
724 return -EINVAL;
725 }
726
727 if (!pcm512x->pll_out) {
728 sck_rate = clk_get_rate(pcm512x->sclk);
729 bclk_div = params->rate_den * 64 / lrclk_div;
730 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
731
732 mck_rate = sck_rate;
733 } else {
734 ret = snd_soc_params_to_bclk(params);
735 if (ret < 0) {
736 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
737 return ret;
738 }
739 if (ret == 0) {
740 dev_err(dev, "No BCLK?\n");
741 return -EINVAL;
742 }
743 bclk_rate = ret;
744
745 pllin_rate = clk_get_rate(pcm512x->sclk);
746
747 sck_rate = pcm512x_find_sck(dai, bclk_rate);
748 if (!sck_rate)
749 return -EINVAL;
750 pll_rate = 4 * sck_rate;
751
752 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
753 if (ret != 0)
754 return ret;
755
756 ret = regmap_write(pcm512x->regmap,
757 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
758 if (ret != 0) {
759 dev_err(dev, "Failed to write PLL P: %d\n", ret);
760 return ret;
761 }
762
763 ret = regmap_write(pcm512x->regmap,
764 PCM512x_PLL_COEFF_1, pcm512x->pll_j);
765 if (ret != 0) {
766 dev_err(dev, "Failed to write PLL J: %d\n", ret);
767 return ret;
768 }
769
770 ret = regmap_write(pcm512x->regmap,
771 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
772 if (ret != 0) {
773 dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
774 return ret;
775 }
776
777 ret = regmap_write(pcm512x->regmap,
778 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
779 if (ret != 0) {
780 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
781 return ret;
782 }
783
784 ret = regmap_write(pcm512x->regmap,
785 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
786 if (ret != 0) {
787 dev_err(dev, "Failed to write PLL R: %d\n", ret);
788 return ret;
789 }
790
791 mck_rate = pcm512x->real_pll;
792
793 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
794 }
795
796 if (bclk_div > 128) {
797 dev_err(dev, "Failed to find BCLK divider\n");
798 return -EINVAL;
799 }
800
801 /* the actual rate */
802 sample_rate = sck_rate / bclk_div / lrclk_div;
803 osr_rate = 16 * sample_rate;
804
805 /* run DSP no faster than 50 MHz */
806 dsp_div = mck_rate > 50000000 ? 2 : 1;
807
808 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
809 if (dac_rate) {
810 /* the desired clock rate is "compatible" with the pll input
811 * clock, so use that clock as dac input instead of the pll
812 * output clock since the pll will introduce jitter and thus
813 * noise.
814 */
815 dev_dbg(dev, "using pll input as dac input\n");
816 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
817 PCM512x_SDAC, PCM512x_SDAC_GPIO);
818 if (ret != 0) {
819 dev_err(codec->dev,
820 "Failed to set gpio as dacref: %d\n", ret);
821 return ret;
822 }
823
824 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
825 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
826 PCM512x_GREF, gpio);
827 if (ret != 0) {
828 dev_err(codec->dev,
829 "Failed to set gpio %d as dacin: %d\n",
830 pcm512x->pll_in, ret);
831 return ret;
832 }
833
834 dacsrc_rate = pllin_rate;
835 } else {
836 /* run DAC no faster than 6144000 Hz */
837 unsigned long dac_mul = 6144000 / osr_rate;
838 unsigned long sck_mul = sck_rate / osr_rate;
839
840 for (; dac_mul; dac_mul--) {
841 if (!(sck_mul % dac_mul))
842 break;
843 }
844 if (!dac_mul) {
845 dev_err(dev, "Failed to find DAC rate\n");
846 return -EINVAL;
847 }
848
849 dac_rate = dac_mul * osr_rate;
850 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
851 dac_rate, sample_rate);
852
853 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
854 PCM512x_SDAC, PCM512x_SDAC_SCK);
855 if (ret != 0) {
856 dev_err(codec->dev,
857 "Failed to set sck as dacref: %d\n", ret);
858 return ret;
859 }
860
861 dacsrc_rate = sck_rate;
862 }
863
864 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
865 if (dac_div > 128) {
866 dev_err(dev, "Failed to find DAC divider\n");
867 return -EINVAL;
868 }
869
870 ncp_div = DIV_ROUND_CLOSEST(dacsrc_rate / dac_div, 1536000);
871 if (ncp_div > 128 || dacsrc_rate / dac_div / ncp_div > 2048000) {
872 /* run NCP no faster than 2048000 Hz, but why? */
873 ncp_div = DIV_ROUND_UP(dacsrc_rate / dac_div, 2048000);
874 if (ncp_div > 128) {
875 dev_err(dev, "Failed to find NCP divider\n");
876 return -EINVAL;
877 }
878 }
879
880 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
881 if (osr_div > 128) {
882 dev_err(dev, "Failed to find OSR divider\n");
883 return -EINVAL;
884 }
885
886 idac = mck_rate / (dsp_div * sample_rate);
887
888 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
889 if (ret != 0) {
890 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
891 return ret;
892 }
893
894 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
895 if (ret != 0) {
896 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
897 return ret;
898 }
899
900 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
901 if (ret != 0) {
902 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
903 return ret;
904 }
905
906 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
907 if (ret != 0) {
908 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
909 return ret;
910 }
911
912 ret = regmap_write(pcm512x->regmap,
913 PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
914 if (ret != 0) {
915 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
916 return ret;
917 }
918
919 ret = regmap_write(pcm512x->regmap,
920 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
921 if (ret != 0) {
922 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
923 return ret;
924 }
925
926 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
927 if (ret != 0) {
928 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
929 return ret;
930 }
931
932 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
933 if (ret != 0) {
934 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
935 return ret;
936 }
937
938 if (sample_rate <= 48000)
939 fssp = PCM512x_FSSP_48KHZ;
940 else if (sample_rate <= 96000)
941 fssp = PCM512x_FSSP_96KHZ;
942 else if (sample_rate <= 192000)
943 fssp = PCM512x_FSSP_192KHZ;
944 else
945 fssp = PCM512x_FSSP_384KHZ;
946 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
947 PCM512x_FSSP, fssp);
948 if (ret != 0) {
949 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
950 return ret;
951 }
952
953 dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
954 dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
955 dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
956 dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
957 dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
958 dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
959 dev_dbg(codec->dev, "IDAC %d\n", idac);
960 dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
961
962 return 0;
963 }
964
965 static int pcm512x_hw_params(struct snd_pcm_substream *substream,
966 struct snd_pcm_hw_params *params,
967 struct snd_soc_dai *dai)
968 {
969 struct snd_soc_codec *codec = dai->codec;
970 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
971 int alen;
972 int gpio;
973 int ret;
974
975 dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
976 params_rate(params),
977 params_channels(params));
978
979 switch (snd_pcm_format_width(params_format(params))) {
980 case 16:
981 alen = PCM512x_ALEN_16;
982 break;
983 case 20:
984 alen = PCM512x_ALEN_20;
985 break;
986 case 24:
987 alen = PCM512x_ALEN_24;
988 break;
989 case 32:
990 alen = PCM512x_ALEN_32;
991 break;
992 default:
993 dev_err(codec->dev, "Bad frame size: %d\n",
994 snd_pcm_format_width(params_format(params)));
995 return -EINVAL;
996 }
997
998 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
999 case SND_SOC_DAIFMT_CBS_CFS:
1000 ret = regmap_update_bits(pcm512x->regmap,
1001 PCM512x_BCLK_LRCLK_CFG,
1002 PCM512x_BCKP
1003 | PCM512x_BCKO | PCM512x_LRKO,
1004 0);
1005 if (ret != 0) {
1006 dev_err(codec->dev,
1007 "Failed to enable slave mode: %d\n", ret);
1008 return ret;
1009 }
1010
1011 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1012 PCM512x_DCAS, 0);
1013 if (ret != 0) {
1014 dev_err(codec->dev,
1015 "Failed to enable clock divider autoset: %d\n",
1016 ret);
1017 return ret;
1018 }
1019 return 0;
1020 case SND_SOC_DAIFMT_CBM_CFM:
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1027 PCM512x_ALEN, alen);
1028 if (ret != 0) {
1029 dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
1030 return ret;
1031 }
1032
1033 if (pcm512x->pll_out) {
1034 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1035 if (ret != 0) {
1036 dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret);
1037 return ret;
1038 }
1039
1040 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1041 if (ret != 0) {
1042 dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret);
1043 return ret;
1044 }
1045
1046 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1047 PCM512x_IDFS | PCM512x_IDBK
1048 | PCM512x_IDSK | PCM512x_IDCH
1049 | PCM512x_IDCM | PCM512x_DCAS
1050 | PCM512x_IPLK,
1051 PCM512x_IDFS | PCM512x_IDBK
1052 | PCM512x_IDSK | PCM512x_IDCH
1053 | PCM512x_DCAS);
1054 if (ret != 0) {
1055 dev_err(codec->dev,
1056 "Failed to ignore auto-clock failures: %d\n",
1057 ret);
1058 return ret;
1059 }
1060 } else {
1061 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1062 PCM512x_IDFS | PCM512x_IDBK
1063 | PCM512x_IDSK | PCM512x_IDCH
1064 | PCM512x_IDCM | PCM512x_DCAS
1065 | PCM512x_IPLK,
1066 PCM512x_IDFS | PCM512x_IDBK
1067 | PCM512x_IDSK | PCM512x_IDCH
1068 | PCM512x_DCAS | PCM512x_IPLK);
1069 if (ret != 0) {
1070 dev_err(codec->dev,
1071 "Failed to ignore auto-clock failures: %d\n",
1072 ret);
1073 return ret;
1074 }
1075
1076 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1077 PCM512x_PLLE, 0);
1078 if (ret != 0) {
1079 dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
1080 return ret;
1081 }
1082 }
1083
1084 ret = pcm512x_set_dividers(dai, params);
1085 if (ret != 0)
1086 return ret;
1087
1088 if (pcm512x->pll_out) {
1089 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1090 PCM512x_SREF, PCM512x_SREF_GPIO);
1091 if (ret != 0) {
1092 dev_err(codec->dev,
1093 "Failed to set gpio as pllref: %d\n", ret);
1094 return ret;
1095 }
1096
1097 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1098 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1099 PCM512x_GREF, gpio);
1100 if (ret != 0) {
1101 dev_err(codec->dev,
1102 "Failed to set gpio %d as pllin: %d\n",
1103 pcm512x->pll_in, ret);
1104 return ret;
1105 }
1106
1107 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1108 PCM512x_PLLE, PCM512x_PLLE);
1109 if (ret != 0) {
1110 dev_err(codec->dev, "Failed to enable pll: %d\n", ret);
1111 return ret;
1112 }
1113 }
1114
1115 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1116 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1117 PCM512x_BCKO | PCM512x_LRKO);
1118 if (ret != 0) {
1119 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
1120 return ret;
1121 }
1122
1123 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1124 PCM512x_RLRK | PCM512x_RBCK,
1125 PCM512x_RLRK | PCM512x_RBCK);
1126 if (ret != 0) {
1127 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
1128 return ret;
1129 }
1130
1131 if (pcm512x->pll_out) {
1132 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1133 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1134 gpio, gpio);
1135 if (ret != 0) {
1136 dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1137 pcm512x->pll_out, ret);
1138 return ret;
1139 }
1140
1141 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1142 ret = regmap_update_bits(pcm512x->regmap, gpio,
1143 PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1144 if (ret != 0) {
1145 dev_err(codec->dev, "Failed to output pll on %d: %d\n",
1146 ret, pcm512x->pll_out);
1147 return ret;
1148 }
1149
1150 gpio = PCM512x_G1OE << (4 - 1);
1151 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1152 gpio, gpio);
1153 if (ret != 0) {
1154 dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1155 4, ret);
1156 return ret;
1157 }
1158
1159 gpio = PCM512x_GPIO_OUTPUT_1 + 4 - 1;
1160 ret = regmap_update_bits(pcm512x->regmap, gpio,
1161 PCM512x_GxSL, PCM512x_GxSL_PLLLK);
1162 if (ret != 0) {
1163 dev_err(codec->dev,
1164 "Failed to output pll lock on %d: %d\n",
1165 ret, 4);
1166 return ret;
1167 }
1168 }
1169
1170 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1171 PCM512x_RQSY, PCM512x_RQSY_HALT);
1172 if (ret != 0) {
1173 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
1174 return ret;
1175 }
1176
1177 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1178 PCM512x_RQSY, PCM512x_RQSY_RESUME);
1179 if (ret != 0) {
1180 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
1181 return ret;
1182 }
1183
1184 return 0;
1185 }
1186
1187 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1188 {
1189 struct snd_soc_codec *codec = dai->codec;
1190 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
1191
1192 pcm512x->fmt = fmt;
1193
1194 return 0;
1195 }
1196
1197 static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1198 .startup = pcm512x_dai_startup,
1199 .hw_params = pcm512x_hw_params,
1200 .set_fmt = pcm512x_set_fmt,
1201 };
1202
1203 static struct snd_soc_dai_driver pcm512x_dai = {
1204 .name = "pcm512x-hifi",
1205 .playback = {
1206 .stream_name = "Playback",
1207 .channels_min = 2,
1208 .channels_max = 2,
1209 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1210 .rate_min = 8000,
1211 .rate_max = 384000,
1212 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1213 SNDRV_PCM_FMTBIT_S24_LE |
1214 SNDRV_PCM_FMTBIT_S32_LE
1215 },
1216 .ops = &pcm512x_dai_ops,
1217 };
1218
1219 static struct snd_soc_codec_driver pcm512x_codec_driver = {
1220 .set_bias_level = pcm512x_set_bias_level,
1221 .idle_bias_off = true,
1222
1223 .controls = pcm512x_controls,
1224 .num_controls = ARRAY_SIZE(pcm512x_controls),
1225 .dapm_widgets = pcm512x_dapm_widgets,
1226 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1227 .dapm_routes = pcm512x_dapm_routes,
1228 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1229 };
1230
1231 static const struct regmap_range_cfg pcm512x_range = {
1232 .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1233 .range_max = PCM512x_MAX_REGISTER,
1234 .selector_reg = PCM512x_PAGE,
1235 .selector_mask = 0xff,
1236 .window_start = 0, .window_len = 0x100,
1237 };
1238
1239 const struct regmap_config pcm512x_regmap = {
1240 .reg_bits = 8,
1241 .val_bits = 8,
1242
1243 .readable_reg = pcm512x_readable,
1244 .volatile_reg = pcm512x_volatile,
1245
1246 .ranges = &pcm512x_range,
1247 .num_ranges = 1,
1248
1249 .max_register = PCM512x_MAX_REGISTER,
1250 .reg_defaults = pcm512x_reg_defaults,
1251 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1252 .cache_type = REGCACHE_RBTREE,
1253 };
1254 EXPORT_SYMBOL_GPL(pcm512x_regmap);
1255
1256 int pcm512x_probe(struct device *dev, struct regmap *regmap)
1257 {
1258 struct pcm512x_priv *pcm512x;
1259 int i, ret;
1260 u32 val;
1261
1262 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1263 if (!pcm512x)
1264 return -ENOMEM;
1265
1266 dev_set_drvdata(dev, pcm512x);
1267 pcm512x->regmap = regmap;
1268
1269 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1270 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1271
1272 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1273 pcm512x->supplies);
1274 if (ret != 0) {
1275 dev_err(dev, "Failed to get supplies: %d\n", ret);
1276 return ret;
1277 }
1278
1279 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1280 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1281 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1282
1283 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1284 ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
1285 &pcm512x->supply_nb[i]);
1286 if (ret != 0) {
1287 dev_err(dev,
1288 "Failed to register regulator notifier: %d\n",
1289 ret);
1290 }
1291 }
1292
1293 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1294 pcm512x->supplies);
1295 if (ret != 0) {
1296 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1297 return ret;
1298 }
1299
1300 /* Reset the device, verifying I/O in the process for I2C */
1301 ret = regmap_write(regmap, PCM512x_RESET,
1302 PCM512x_RSTM | PCM512x_RSTR);
1303 if (ret != 0) {
1304 dev_err(dev, "Failed to reset device: %d\n", ret);
1305 goto err;
1306 }
1307
1308 ret = regmap_write(regmap, PCM512x_RESET, 0);
1309 if (ret != 0) {
1310 dev_err(dev, "Failed to reset device: %d\n", ret);
1311 goto err;
1312 }
1313
1314 pcm512x->sclk = devm_clk_get(dev, NULL);
1315 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
1316 return -EPROBE_DEFER;
1317 if (!IS_ERR(pcm512x->sclk)) {
1318 ret = clk_prepare_enable(pcm512x->sclk);
1319 if (ret != 0) {
1320 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1321 return ret;
1322 }
1323 }
1324
1325 /* Default to standby mode */
1326 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1327 PCM512x_RQST, PCM512x_RQST);
1328 if (ret != 0) {
1329 dev_err(dev, "Failed to request standby: %d\n",
1330 ret);
1331 goto err_clk;
1332 }
1333
1334 pm_runtime_set_active(dev);
1335 pm_runtime_enable(dev);
1336 pm_runtime_idle(dev);
1337
1338 #ifdef CONFIG_OF
1339 if (dev->of_node) {
1340 const struct device_node *np = dev->of_node;
1341
1342 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1343 if (val > 6) {
1344 dev_err(dev, "Invalid pll-in\n");
1345 ret = -EINVAL;
1346 goto err_clk;
1347 }
1348 pcm512x->pll_in = val;
1349 }
1350
1351 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1352 if (val > 6) {
1353 dev_err(dev, "Invalid pll-out\n");
1354 ret = -EINVAL;
1355 goto err_clk;
1356 }
1357 pcm512x->pll_out = val;
1358 }
1359
1360 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1361 dev_err(dev,
1362 "Error: both pll-in and pll-out, or none\n");
1363 ret = -EINVAL;
1364 goto err_clk;
1365 }
1366 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1367 dev_err(dev, "Error: pll-in == pll-out\n");
1368 ret = -EINVAL;
1369 goto err_clk;
1370 }
1371 }
1372 #endif
1373
1374 ret = snd_soc_register_codec(dev, &pcm512x_codec_driver,
1375 &pcm512x_dai, 1);
1376 if (ret != 0) {
1377 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1378 goto err_pm;
1379 }
1380
1381 return 0;
1382
1383 err_pm:
1384 pm_runtime_disable(dev);
1385 err_clk:
1386 if (!IS_ERR(pcm512x->sclk))
1387 clk_disable_unprepare(pcm512x->sclk);
1388 err:
1389 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1390 pcm512x->supplies);
1391 return ret;
1392 }
1393 EXPORT_SYMBOL_GPL(pcm512x_probe);
1394
1395 void pcm512x_remove(struct device *dev)
1396 {
1397 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1398
1399 snd_soc_unregister_codec(dev);
1400 pm_runtime_disable(dev);
1401 if (!IS_ERR(pcm512x->sclk))
1402 clk_disable_unprepare(pcm512x->sclk);
1403 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1404 pcm512x->supplies);
1405 }
1406 EXPORT_SYMBOL_GPL(pcm512x_remove);
1407
1408 #ifdef CONFIG_PM
1409 static int pcm512x_suspend(struct device *dev)
1410 {
1411 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1412 int ret;
1413
1414 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1415 PCM512x_RQPD, PCM512x_RQPD);
1416 if (ret != 0) {
1417 dev_err(dev, "Failed to request power down: %d\n", ret);
1418 return ret;
1419 }
1420
1421 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1422 pcm512x->supplies);
1423 if (ret != 0) {
1424 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1425 return ret;
1426 }
1427
1428 if (!IS_ERR(pcm512x->sclk))
1429 clk_disable_unprepare(pcm512x->sclk);
1430
1431 return 0;
1432 }
1433
1434 static int pcm512x_resume(struct device *dev)
1435 {
1436 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1437 int ret;
1438
1439 if (!IS_ERR(pcm512x->sclk)) {
1440 ret = clk_prepare_enable(pcm512x->sclk);
1441 if (ret != 0) {
1442 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1443 return ret;
1444 }
1445 }
1446
1447 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1448 pcm512x->supplies);
1449 if (ret != 0) {
1450 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1451 return ret;
1452 }
1453
1454 regcache_cache_only(pcm512x->regmap, false);
1455 ret = regcache_sync(pcm512x->regmap);
1456 if (ret != 0) {
1457 dev_err(dev, "Failed to sync cache: %d\n", ret);
1458 return ret;
1459 }
1460
1461 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1462 PCM512x_RQPD, 0);
1463 if (ret != 0) {
1464 dev_err(dev, "Failed to remove power down: %d\n", ret);
1465 return ret;
1466 }
1467
1468 return 0;
1469 }
1470 #endif
1471
1472 const struct dev_pm_ops pcm512x_pm_ops = {
1473 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1474 };
1475 EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1476
1477 MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1478 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>");
1479 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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