sound/soc/codecs/rt286.c

   1 /*
   2  * rt286.c  --  RT286 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2013 Realtek Semiconductor Corp.
   5  * Author: Bard Liao <bardliao@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/dmi.h>
  21 #include <linux/acpi.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/jack.h>
  30 #include <linux/workqueue.h>
  31 #include <sound/rt286.h>
  32 #include <sound/hda_verbs.h>
  33
  34 #include "rt286.h"
  35
  36 #define RT286_VENDOR_ID 0x10ec0286
  37 #define RT288_VENDOR_ID 0x10ec0288
  38
  39 struct rt286_priv {
  40         struct regmap *regmap;
  41         struct snd_soc_codec *codec;
  42         struct rt286_platform_data pdata;
  43         struct i2c_client *i2c;
  44         struct snd_soc_jack *jack;
  45         struct delayed_work jack_detect_work;
  46         int sys_clk;
  47         int clk_id;
  48         struct reg_default *index_cache;
  49 };
  50
  51 static struct reg_default rt286_index_def[] = {
  52         { 0x01, 0xaaaa },
  53         { 0x02, 0x8aaa },
  54         { 0x03, 0x0002 },
  55         { 0x04, 0xaf01 },
  56         { 0x08, 0x000d },
  57         { 0x09, 0xd810 },
  58         { 0x0a, 0x0120 },
  59         { 0x0b, 0x0000 },
  60         { 0x0d, 0x2800 },
  61         { 0x0f, 0x0000 },
  62         { 0x19, 0x0a17 },
  63         { 0x20, 0x0020 },
  64         { 0x33, 0x0208 },
  65         { 0x49, 0x0004 },
  66         { 0x4f, 0x50e9 },
  67         { 0x50, 0x2000 },
  68         { 0x63, 0x2902 },
  69         { 0x67, 0x1111 },
  70         { 0x68, 0x1016 },
  71         { 0x69, 0x273f },
  72 };
  73 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  74
  75 static const struct reg_default rt286_reg[] = {
  76         { 0x00170500, 0x00000400 },
  77         { 0x00220000, 0x00000031 },
  78         { 0x00239000, 0x0000007f },
  79         { 0x0023a000, 0x0000007f },
  80         { 0x00270500, 0x00000400 },
  81         { 0x00370500, 0x00000400 },
  82         { 0x00870500, 0x00000400 },
  83         { 0x00920000, 0x00000031 },
  84         { 0x00935000, 0x000000c3 },
  85         { 0x00936000, 0x000000c3 },
  86         { 0x00970500, 0x00000400 },
  87         { 0x00b37000, 0x00000097 },
  88         { 0x00b37200, 0x00000097 },
  89         { 0x00b37300, 0x00000097 },
  90         { 0x00c37000, 0x00000000 },
  91         { 0x00c37100, 0x00000080 },
  92         { 0x01270500, 0x00000400 },
  93         { 0x01370500, 0x00000400 },
  94         { 0x01371f00, 0x411111f0 },
  95         { 0x01439000, 0x00000080 },
  96         { 0x0143a000, 0x00000080 },
  97         { 0x01470700, 0x00000000 },
  98         { 0x01470500, 0x00000400 },
  99         { 0x01470c00, 0x00000000 },
 100         { 0x01470100, 0x00000000 },
 101         { 0x01837000, 0x00000000 },
 102         { 0x01870500, 0x00000400 },
 103         { 0x02050000, 0x00000000 },
 104         { 0x02139000, 0x00000080 },
 105         { 0x0213a000, 0x00000080 },
 106         { 0x02170100, 0x00000000 },
 107         { 0x02170500, 0x00000400 },
 108         { 0x02170700, 0x00000000 },
 109         { 0x02270100, 0x00000000 },
 110         { 0x02370100, 0x00000000 },
 111         { 0x01870700, 0x00000020 },
 112         { 0x00830000, 0x000000c3 },
 113         { 0x00930000, 0x000000c3 },
 114         { 0x01270700, 0x00000000 },
 115 };
 116
 117 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
 118 {
 119         switch (reg) {
 120         case 0 ... 0xff:
 121         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 122         case RT286_GET_HP_SENSE:
 123         case RT286_GET_MIC1_SENSE:
 124         case RT286_PROC_COEF:
 125                 return true;
 126         default:
 127                 return false;
 128         }
 129
 130
 131 }
 132
 133 static bool rt286_readable_register(struct device *dev, unsigned int reg)
 134 {
 135         switch (reg) {
 136         case 0 ... 0xff:
 137         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 138         case RT286_GET_HP_SENSE:
 139         case RT286_GET_MIC1_SENSE:
 140         case RT286_SET_AUDIO_POWER:
 141         case RT286_SET_HPO_POWER:
 142         case RT286_SET_SPK_POWER:
 143         case RT286_SET_DMIC1_POWER:
 144         case RT286_SPK_MUX:
 145         case RT286_HPO_MUX:
 146         case RT286_ADC0_MUX:
 147         case RT286_ADC1_MUX:
 148         case RT286_SET_MIC1:
 149         case RT286_SET_PIN_HPO:
 150         case RT286_SET_PIN_SPK:
 151         case RT286_SET_PIN_DMIC1:
 152         case RT286_SPK_EAPD:
 153         case RT286_SET_AMP_GAIN_HPO:
 154         case RT286_SET_DMIC2_DEFAULT:
 155         case RT286_DACL_GAIN:
 156         case RT286_DACR_GAIN:
 157         case RT286_ADCL_GAIN:
 158         case RT286_ADCR_GAIN:
 159         case RT286_MIC_GAIN:
 160         case RT286_SPOL_GAIN:
 161         case RT286_SPOR_GAIN:
 162         case RT286_HPOL_GAIN:
 163         case RT286_HPOR_GAIN:
 164         case RT286_F_DAC_SWITCH:
 165         case RT286_F_RECMIX_SWITCH:
 166         case RT286_REC_MIC_SWITCH:
 167         case RT286_REC_I2S_SWITCH:
 168         case RT286_REC_LINE_SWITCH:
 169         case RT286_REC_BEEP_SWITCH:
 170         case RT286_DAC_FORMAT:
 171         case RT286_ADC_FORMAT:
 172         case RT286_COEF_INDEX:
 173         case RT286_PROC_COEF:
 174         case RT286_SET_AMP_GAIN_ADC_IN1:
 175         case RT286_SET_AMP_GAIN_ADC_IN2:
 176         case RT286_SET_POWER(RT286_DAC_OUT1):
 177         case RT286_SET_POWER(RT286_DAC_OUT2):
 178         case RT286_SET_POWER(RT286_ADC_IN1):
 179         case RT286_SET_POWER(RT286_ADC_IN2):
 180         case RT286_SET_POWER(RT286_DMIC2):
 181         case RT286_SET_POWER(RT286_MIC1):
 182                 return true;
 183         default:
 184                 return false;
 185         }
 186 }
 187
 188 static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
 189 {
 190         struct i2c_client *client = context;
 191         struct rt286_priv *rt286 = i2c_get_clientdata(client);
 192         u8 data[4];
 193         int ret, i;
 194
 195         /* handle index registers */
 196         if (reg <= 0xff) {
 197                 rt286_hw_write(client, RT286_COEF_INDEX, reg);
 198                 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
 199                         if (reg == rt286->index_cache[i].reg) {
 200                                 rt286->index_cache[i].def = value;
 201                                 break;
 202                         }
 203
 204                 }
 205                 reg = RT286_PROC_COEF;
 206         }
 207
 208         data[0] = (reg >> 24) & 0xff;
 209         data[1] = (reg >> 16) & 0xff;
 210         /*
 211          * 4 bit VID: reg should be 0
 212          * 12 bit VID: value should be 0
 213          * So we use an OR operator to handle it rather than use if condition.
 214          */
 215         data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
 216         data[3] = value & 0xff;
 217
 218         ret = i2c_master_send(client, data, 4);
 219
 220         if (ret == 4)
 221                 return 0;
 222         else
 223                 pr_err("ret=%d\n", ret);
 224         if (ret < 0)
 225                 return ret;
 226         else
 227                 return -EIO;
 228 }
 229
 230 static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
 231 {
 232         struct i2c_client *client = context;
 233         struct i2c_msg xfer[2];
 234         int ret;
 235         __be32 be_reg;
 236         unsigned int index, vid, buf = 0x0;
 237
 238         /* handle index registers */
 239         if (reg <= 0xff) {
 240                 rt286_hw_write(client, RT286_COEF_INDEX, reg);
 241                 reg = RT286_PROC_COEF;
 242         }
 243
 244         reg = reg | 0x80000;
 245         vid = (reg >> 8) & 0xfff;
 246
 247         if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
 248                 index = (reg >> 8) & 0xf;
 249                 reg = (reg & ~0xf0f) | index;
 250         }
 251         be_reg = cpu_to_be32(reg);
 252
 253         /* Write register */
 254         xfer[0].addr = client->addr;
 255         xfer[0].flags = 0;
 256         xfer[0].len = 4;
 257         xfer[0].buf = (u8 *)&be_reg;
 258
 259         /* Read data */
 260         xfer[1].addr = client->addr;
 261         xfer[1].flags = I2C_M_RD;
 262         xfer[1].len = 4;
 263         xfer[1].buf = (u8 *)&buf;
 264
 265         ret = i2c_transfer(client->adapter, xfer, 2);
 266         if (ret < 0)
 267                 return ret;
 268         else if (ret != 2)
 269                 return -EIO;
 270
 271         *value = be32_to_cpu(buf);
 272
 273         return 0;
 274 }
 275
 276 #ifdef CONFIG_PM
 277 static void rt286_index_sync(struct snd_soc_codec *codec)
 278 {
 279         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 280         int i;
 281
 282         for (i = 0; i < INDEX_CACHE_SIZE; i++) {
 283                 snd_soc_write(codec, rt286->index_cache[i].reg,
 284                                   rt286->index_cache[i].def);
 285         }
 286 }
 287 #endif
 288
 289 static int rt286_support_power_controls[] = {
 290         RT286_DAC_OUT1,
 291         RT286_DAC_OUT2,
 292         RT286_ADC_IN1,
 293         RT286_ADC_IN2,
 294         RT286_MIC1,
 295         RT286_DMIC1,
 296         RT286_DMIC2,
 297         RT286_SPK_OUT,
 298         RT286_HP_OUT,
 299 };
 300 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
 301
 302 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
 303 {
 304         struct snd_soc_dapm_context *dapm;
 305         unsigned int val, buf;
 306
 307         *hp = false;
 308         *mic = false;
 309
 310         if (!rt286->codec)
 311                 return -EINVAL;
 312
 313         dapm = snd_soc_codec_get_dapm(rt286->codec);
 314
 315         if (rt286->pdata.cbj_en) {
 316                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 317                 *hp = buf & 0x80000000;
 318                 if (*hp) {
 319                         /* power on HV,VERF */
 320                         regmap_update_bits(rt286->regmap,
 321                                 RT286_DC_GAIN, 0x200, 0x200);
 322
 323                         snd_soc_dapm_force_enable_pin(dapm, "HV");
 324                         snd_soc_dapm_force_enable_pin(dapm, "VREF");
 325                         /* power LDO1 */
 326                         snd_soc_dapm_force_enable_pin(dapm, "LDO1");
 327                         snd_soc_dapm_sync(dapm);
 328
 329                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
 330                         msleep(50);
 331
 332                         regmap_update_bits(rt286->regmap,
 333                                 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
 334                         msleep(300);
 335                         regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
 336
 337                         if (0x0070 == (val & 0x0070)) {
 338                                 *mic = true;
 339                         } else {
 340                                 regmap_update_bits(rt286->regmap,
 341                                         RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
 342                                 msleep(300);
 343                                 regmap_read(rt286->regmap,
 344                                         RT286_CBJ_CTRL2, &val);
 345                                 if (0x0070 == (val & 0x0070))
 346                                         *mic = true;
 347                                 else
 348                                         *mic = false;
 349                         }
 350                         regmap_update_bits(rt286->regmap,
 351                                 RT286_DC_GAIN, 0x200, 0x0);
 352
 353                 } else {
 354                         *mic = false;
 355                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
 356                 }
 357         } else {
 358                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 359                 *hp = buf & 0x80000000;
 360                 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
 361                 *mic = buf & 0x80000000;
 362         }
 363
 364         snd_soc_dapm_disable_pin(dapm, "HV");
 365         snd_soc_dapm_disable_pin(dapm, "VREF");
 366         if (!*hp)
 367                 snd_soc_dapm_disable_pin(dapm, "LDO1");
 368         snd_soc_dapm_sync(dapm);
 369
 370         return 0;
 371 }
 372
 373 static void rt286_jack_detect_work(struct work_struct *work)
 374 {
 375         struct rt286_priv *rt286 =
 376                 container_of(work, struct rt286_priv, jack_detect_work.work);
 377         int status = 0;
 378         bool hp = false;
 379         bool mic = false;
 380
 381         rt286_jack_detect(rt286, &hp, &mic);
 382
 383         if (hp == true)
 384                 status |= SND_JACK_HEADPHONE;
 385
 386         if (mic == true)
 387                 status |= SND_JACK_MICROPHONE;
 388
 389         snd_soc_jack_report(rt286->jack, status,
 390                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 391 }
 392
 393 int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
 394 {
 395         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 396         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 397
 398         rt286->jack = jack;
 399
 400         if (jack) {
 401                 /* enable IRQ */
 402                 if (rt286->jack->status & SND_JACK_HEADPHONE)
 403                         snd_soc_dapm_force_enable_pin(dapm, "LDO1");
 404                 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
 405                 /* Send an initial empty report */
 406                 snd_soc_jack_report(rt286->jack, rt286->jack->status,
 407                         SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 408         } else {
 409                 /* disable IRQ */
 410                 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
 411                 snd_soc_dapm_disable_pin(dapm, "LDO1");
 412         }
 413         snd_soc_dapm_sync(dapm);
 414
 415         return 0;
 416 }
 417 EXPORT_SYMBOL_GPL(rt286_mic_detect);
 418
 419 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
 420                          struct snd_soc_dapm_widget *sink)
 421 {
 422         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 423         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 424
 425         if (rt286->clk_id == RT286_SCLK_S_MCLK)
 426                 return 1;
 427         else
 428                 return 0;
 429 }
 430
 431 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
 432 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
 433
 434 static const struct snd_kcontrol_new rt286_snd_controls[] = {
 435         SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
 436                             RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 437         SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
 438                             RT286_ADCR_GAIN, 7, 1, 1),
 439         SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
 440                             RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 441         SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
 442                             0, 0x3, 0, mic_vol_tlv),
 443         SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
 444                             RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
 445 };
 446
 447 /* Digital Mixer */
 448 static const struct snd_kcontrol_new rt286_front_mix[] = {
 449         SOC_DAPM_SINGLE("DAC Switch",  RT286_F_DAC_SWITCH,
 450                         RT286_MUTE_SFT, 1, 1),
 451         SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
 452                         RT286_MUTE_SFT, 1, 1),
 453 };
 454
 455 /* Analog Input Mixer */
 456 static const struct snd_kcontrol_new rt286_rec_mix[] = {
 457         SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
 458                         RT286_MUTE_SFT, 1, 1),
 459         SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
 460                         RT286_MUTE_SFT, 1, 1),
 461         SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
 462                         RT286_MUTE_SFT, 1, 1),
 463         SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
 464                         RT286_MUTE_SFT, 1, 1),
 465 };
 466
 467 static const struct snd_kcontrol_new spo_enable_control =
 468         SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
 469                         RT286_SET_PIN_SFT, 1, 0);
 470
 471 static const struct snd_kcontrol_new hpol_enable_control =
 472         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
 473                         RT286_MUTE_SFT, 1, 1);
 474
 475 static const struct snd_kcontrol_new hpor_enable_control =
 476         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
 477                         RT286_MUTE_SFT, 1, 1);
 478
 479 /* ADC0 source */
 480 static const char * const rt286_adc_src[] = {
 481         "Mic", "RECMIX", "Dmic"
 482 };
 483
 484 static const int rt286_adc_values[] = {
 485         0, 4, 5,
 486 };
 487
 488 static SOC_VALUE_ENUM_SINGLE_DECL(
 489         rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
 490         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 491
 492 static const struct snd_kcontrol_new rt286_adc0_mux =
 493         SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
 494
 495 static SOC_VALUE_ENUM_SINGLE_DECL(
 496         rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
 497         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 498
 499 static const struct snd_kcontrol_new rt286_adc1_mux =
 500         SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
 501
 502 static const char * const rt286_dac_src[] = {
 503         "Front", "Surround"
 504 };
 505 /* HP-OUT source */
 506 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
 507                                 0, rt286_dac_src);
 508
 509 static const struct snd_kcontrol_new rt286_hpo_mux =
 510 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
 511
 512 /* SPK-OUT source */
 513 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
 514                                 0, rt286_dac_src);
 515
 516 static const struct snd_kcontrol_new rt286_spo_mux =
 517 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
 518
 519 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
 520                             struct snd_kcontrol *kcontrol, int event)
 521 {
 522         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 523
 524         switch (event) {
 525         case SND_SOC_DAPM_POST_PMU:
 526                 snd_soc_write(codec,
 527                         RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
 528                 break;
 529         case SND_SOC_DAPM_PRE_PMD:
 530                 snd_soc_write(codec,
 531                         RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
 532                 break;
 533
 534         default:
 535                 return 0;
 536         }
 537
 538         return 0;
 539 }
 540
 541 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
 542                                   struct snd_kcontrol *kcontrol, int event)
 543 {
 544         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 545
 546         switch (event) {
 547         case SND_SOC_DAPM_POST_PMU:
 548                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
 549                 break;
 550         case SND_SOC_DAPM_PRE_PMD:
 551                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
 552                 break;
 553         default:
 554                 return 0;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int rt286_vref_event(struct snd_soc_dapm_widget *w,
 561                              struct snd_kcontrol *kcontrol, int event)
 562 {
 563         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 564
 565         switch (event) {
 566         case SND_SOC_DAPM_PRE_PMU:
 567                 snd_soc_update_bits(codec,
 568                         RT286_CBJ_CTRL1, 0x0400, 0x0000);
 569                 mdelay(50);
 570                 break;
 571         default:
 572                 return 0;
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
 579                              struct snd_kcontrol *kcontrol, int event)
 580 {
 581         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 582
 583         switch (event) {
 584         case SND_SOC_DAPM_POST_PMU:
 585                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
 586                 break;
 587         case SND_SOC_DAPM_PRE_PMD:
 588                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
 589                 break;
 590         default:
 591                 return 0;
 592         }
 593
 594         return 0;
 595 }
 596
 597 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
 598                              struct snd_kcontrol *kcontrol, int event)
 599 {
 600         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 601
 602         switch (event) {
 603         case SND_SOC_DAPM_PRE_PMU:
 604                 snd_soc_update_bits(codec,
 605                         RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
 606                 snd_soc_update_bits(codec,
 607                         RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
 608                 break;
 609         case SND_SOC_DAPM_POST_PMD:
 610                 snd_soc_update_bits(codec,
 611                         RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
 612                 snd_soc_update_bits(codec,
 613                         RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
 614                 break;
 615         default:
 616                 return 0;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
 623         SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
 624                 12, 1, NULL, 0),
 625         SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
 626                 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
 627         SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
 628                 2, 0, NULL, 0),
 629         SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
 630                 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
 631                 SND_SOC_DAPM_POST_PMU),
 632         SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
 633                 5, 0, NULL, 0),
 634         SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
 635                 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
 636                 SND_SOC_DAPM_POST_PMD),
 637
 638         /* Input Lines */
 639         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
 640         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
 641         SND_SOC_DAPM_INPUT("MIC1"),
 642         SND_SOC_DAPM_INPUT("LINE1"),
 643         SND_SOC_DAPM_INPUT("Beep"),
 644
 645         /* DMIC */
 646         SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
 647                 NULL, 0, rt286_set_dmic1_event,
 648                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 649         SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
 650                 NULL, 0),
 651         SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
 652                 0, 0, NULL, 0),
 653
 654         /* REC Mixer */
 655         SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
 656                 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
 657
 658         /* ADCs */
 659         SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
 660         SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
 661
 662         /* ADC Mux */
 663         SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
 664                 &rt286_adc0_mux),
 665         SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
 666                 &rt286_adc1_mux),
 667
 668         /* Audio Interface */
 669         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 670         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 671         SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
 672         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
 673
 674         /* Output Side */
 675         /* DACs */
 676         SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
 677         SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
 678
 679         /* Output Mux */
 680         SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
 681         SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
 682
 683         SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
 684                 RT286_SET_PIN_SFT, 0, NULL, 0),
 685
 686         /* Output Mixer */
 687         SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
 688                         rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
 689         SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
 690                         NULL, 0),
 691
 692         /* Output Pga */
 693         SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
 694                 &spo_enable_control, rt286_spk_event,
 695                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 696         SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
 697                 &hpol_enable_control),
 698         SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
 699                 &hpor_enable_control),
 700
 701         /* Output Lines */
 702         SND_SOC_DAPM_OUTPUT("SPOL"),
 703         SND_SOC_DAPM_OUTPUT("SPOR"),
 704         SND_SOC_DAPM_OUTPUT("HPO Pin"),
 705         SND_SOC_DAPM_OUTPUT("SPDIF"),
 706 };
 707
 708 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
 709         {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
 710         {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
 711         {"Front", NULL, "MCLK MODE", is_mclk_mode},
 712         {"Surround", NULL, "MCLK MODE", is_mclk_mode},
 713
 714         {"HP Power", NULL, "LDO1"},
 715         {"HP Power", NULL, "LDO2"},
 716
 717         {"MIC1", NULL, "LDO1"},
 718         {"MIC1", NULL, "LDO2"},
 719         {"MIC1", NULL, "HV"},
 720         {"MIC1", NULL, "VREF"},
 721         {"MIC1", NULL, "MIC1 Input Buffer"},
 722
 723         {"SPO", NULL, "LDO1"},
 724         {"SPO", NULL, "LDO2"},
 725         {"SPO", NULL, "HV"},
 726         {"SPO", NULL, "VREF"},
 727
 728         {"DMIC1", NULL, "DMIC1 Pin"},
 729         {"DMIC2", NULL, "DMIC2 Pin"},
 730         {"DMIC1", NULL, "DMIC Receiver"},
 731         {"DMIC2", NULL, "DMIC Receiver"},
 732
 733         {"RECMIX", "Beep Switch", "Beep"},
 734         {"RECMIX", "Line1 Switch", "LINE1"},
 735         {"RECMIX", "Mic1 Switch", "MIC1"},
 736
 737         {"ADC 0 Mux", "Dmic", "DMIC1"},
 738         {"ADC 0 Mux", "RECMIX", "RECMIX"},
 739         {"ADC 0 Mux", "Mic", "MIC1"},
 740         {"ADC 1 Mux", "Dmic", "DMIC2"},
 741         {"ADC 1 Mux", "RECMIX", "RECMIX"},
 742         {"ADC 1 Mux", "Mic", "MIC1"},
 743
 744         {"ADC 0", NULL, "ADC 0 Mux"},
 745         {"ADC 1", NULL, "ADC 1 Mux"},
 746
 747         {"AIF1TX", NULL, "ADC 0"},
 748         {"AIF2TX", NULL, "ADC 1"},
 749
 750         {"DAC 0", NULL, "AIF1RX"},
 751         {"DAC 1", NULL, "AIF2RX"},
 752
 753         {"Front", "DAC Switch", "DAC 0"},
 754         {"Front", "RECMIX Switch", "RECMIX"},
 755
 756         {"Surround", NULL, "DAC 1"},
 757
 758         {"SPK Mux", "Front", "Front"},
 759         {"SPK Mux", "Surround", "Surround"},
 760
 761         {"HPO Mux", "Front", "Front"},
 762         {"HPO Mux", "Surround", "Surround"},
 763
 764         {"SPO", "Switch", "SPK Mux"},
 765         {"HPO L", "Switch", "HPO Mux"},
 766         {"HPO R", "Switch", "HPO Mux"},
 767         {"HPO L", NULL, "HP Power"},
 768         {"HPO R", NULL, "HP Power"},
 769
 770         {"SPOL", NULL, "SPO"},
 771         {"SPOR", NULL, "SPO"},
 772         {"HPO Pin", NULL, "HPO L"},
 773         {"HPO Pin", NULL, "HPO R"},
 774 };
 775
 776 static int rt286_hw_params(struct snd_pcm_substream *substream,
 777                             struct snd_pcm_hw_params *params,
 778                             struct snd_soc_dai *dai)
 779 {
 780         struct snd_soc_codec *codec = dai->codec;
 781         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 782         unsigned int val = 0;
 783         int d_len_code;
 784
 785         switch (params_rate(params)) {
 786         /* bit 14 0:48K 1:44.1K */
 787         case 44100:
 788                 val |= 0x4000;
 789                 break;
 790         case 48000:
 791                 break;
 792         default:
 793                 dev_err(codec->dev, "Unsupported sample rate %d\n",
 794                                         params_rate(params));
 795                 return -EINVAL;
 796         }
 797         switch (rt286->sys_clk) {
 798         case 12288000:
 799         case 24576000:
 800                 if (params_rate(params) != 48000) {
 801                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 802                                         params_rate(params), rt286->sys_clk);
 803                         return -EINVAL;
 804                 }
 805                 break;
 806         case 11289600:
 807         case 22579200:
 808                 if (params_rate(params) != 44100) {
 809                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 810                                         params_rate(params), rt286->sys_clk);
 811                         return -EINVAL;
 812                 }
 813                 break;
 814         }
 815
 816         if (params_channels(params) <= 16) {
 817                 /* bit 3:0 Number of Channel */
 818                 val |= (params_channels(params) - 1);
 819         } else {
 820                 dev_err(codec->dev, "Unsupported channels %d\n",
 821                                         params_channels(params));
 822                 return -EINVAL;
 823         }
 824
 825         d_len_code = 0;
 826         switch (params_width(params)) {
 827         /* bit 6:4 Bits per Sample */
 828         case 16:
 829                 d_len_code = 0;
 830                 val |= (0x1 << 4);
 831                 break;
 832         case 32:
 833                 d_len_code = 2;
 834                 val |= (0x4 << 4);
 835                 break;
 836         case 20:
 837                 d_len_code = 1;
 838                 val |= (0x2 << 4);
 839                 break;
 840         case 24:
 841                 d_len_code = 2;
 842                 val |= (0x3 << 4);
 843                 break;
 844         case 8:
 845                 d_len_code = 3;
 846                 break;
 847         default:
 848                 return -EINVAL;
 849         }
 850
 851         snd_soc_update_bits(codec,
 852                 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
 853         dev_dbg(codec->dev, "format val = 0x%x\n", val);
 854
 855         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
 856         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
 857
 858         return 0;
 859 }
 860
 861 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 862 {
 863         struct snd_soc_codec *codec = dai->codec;
 864
 865         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 866         case SND_SOC_DAIFMT_CBM_CFM:
 867                 snd_soc_update_bits(codec,
 868                         RT286_I2S_CTRL1, 0x800, 0x800);
 869                 break;
 870         case SND_SOC_DAIFMT_CBS_CFS:
 871                 snd_soc_update_bits(codec,
 872                         RT286_I2S_CTRL1, 0x800, 0x0);
 873                 break;
 874         default:
 875                 return -EINVAL;
 876         }
 877
 878         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 879         case SND_SOC_DAIFMT_I2S:
 880                 snd_soc_update_bits(codec,
 881                         RT286_I2S_CTRL1, 0x300, 0x0);
 882                 break;
 883         case SND_SOC_DAIFMT_LEFT_J:
 884                 snd_soc_update_bits(codec,
 885                         RT286_I2S_CTRL1, 0x300, 0x1 << 8);
 886                 break;
 887         case SND_SOC_DAIFMT_DSP_A:
 888                 snd_soc_update_bits(codec,
 889                         RT286_I2S_CTRL1, 0x300, 0x2 << 8);
 890                 break;
 891         case SND_SOC_DAIFMT_DSP_B:
 892                 snd_soc_update_bits(codec,
 893                         RT286_I2S_CTRL1, 0x300, 0x3 << 8);
 894                 break;
 895         default:
 896                 return -EINVAL;
 897         }
 898         /* bit 15 Stream Type 0:PCM 1:Non-PCM */
 899         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
 900         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
 901
 902         return 0;
 903 }
 904
 905 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
 906                                 int clk_id, unsigned int freq, int dir)
 907 {
 908         struct snd_soc_codec *codec = dai->codec;
 909         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 910
 911         dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
 912
 913         if (RT286_SCLK_S_MCLK == clk_id) {
 914                 snd_soc_update_bits(codec,
 915                         RT286_I2S_CTRL2, 0x0100, 0x0);
 916                 snd_soc_update_bits(codec,
 917                         RT286_PLL_CTRL1, 0x20, 0x20);
 918         } else {
 919                 snd_soc_update_bits(codec,
 920                         RT286_I2S_CTRL2, 0x0100, 0x0100);
 921                 snd_soc_update_bits(codec,
 922                         RT286_PLL_CTRL, 0x4, 0x4);
 923                 snd_soc_update_bits(codec,
 924                         RT286_PLL_CTRL1, 0x20, 0x0);
 925         }
 926
 927         switch (freq) {
 928         case 19200000:
 929                 if (RT286_SCLK_S_MCLK == clk_id) {
 930                         dev_err(codec->dev, "Should not use MCLK\n");
 931                         return -EINVAL;
 932                 }
 933                 snd_soc_update_bits(codec,
 934                         RT286_I2S_CTRL2, 0x40, 0x40);
 935                 break;
 936         case 24000000:
 937                 if (RT286_SCLK_S_MCLK == clk_id) {
 938                         dev_err(codec->dev, "Should not use MCLK\n");
 939                         return -EINVAL;
 940                 }
 941                 snd_soc_update_bits(codec,
 942                         RT286_I2S_CTRL2, 0x40, 0x0);
 943                 break;
 944         case 12288000:
 945         case 11289600:
 946                 snd_soc_update_bits(codec,
 947                         RT286_I2S_CTRL2, 0x8, 0x0);
 948                 snd_soc_update_bits(codec,
 949                         RT286_CLK_DIV, 0xfc1e, 0x0004);
 950                 break;
 951         case 24576000:
 952         case 22579200:
 953                 snd_soc_update_bits(codec,
 954                         RT286_I2S_CTRL2, 0x8, 0x8);
 955                 snd_soc_update_bits(codec,
 956                         RT286_CLK_DIV, 0xfc1e, 0x5406);
 957                 break;
 958         default:
 959                 dev_err(codec->dev, "Unsupported system clock\n");
 960                 return -EINVAL;
 961         }
 962
 963         rt286->sys_clk = freq;
 964         rt286->clk_id = clk_id;
 965
 966         return 0;
 967 }
 968
 969 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
 970 {
 971         struct snd_soc_codec *codec = dai->codec;
 972
 973         dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
 974         if (50 == ratio)
 975                 snd_soc_update_bits(codec,
 976                         RT286_I2S_CTRL1, 0x1000, 0x1000);
 977         else
 978                 snd_soc_update_bits(codec,
 979                         RT286_I2S_CTRL1, 0x1000, 0x0);
 980
 981
 982         return 0;
 983 }
 984
 985 static int rt286_set_bias_level(struct snd_soc_codec *codec,
 986                                  enum snd_soc_bias_level level)
 987 {
 988         switch (level) {
 989         case SND_SOC_BIAS_PREPARE:
 990                 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
 991                         snd_soc_write(codec,
 992                                 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
 993                         snd_soc_update_bits(codec,
 994                                 RT286_DC_GAIN, 0x200, 0x200);
 995                 }
 996                 break;
 997
 998         case SND_SOC_BIAS_ON:
 999                 mdelay(10);
1000                 snd_soc_update_bits(codec,
1001                         RT286_CBJ_CTRL1, 0x0400, 0x0400);
1002                 snd_soc_update_bits(codec,
1003                         RT286_DC_GAIN, 0x200, 0x0);
1004
1005                 break;
1006
1007         case SND_SOC_BIAS_STANDBY:
1008                 snd_soc_write(codec,
1009                         RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1010                 snd_soc_update_bits(codec,
1011                         RT286_CBJ_CTRL1, 0x0400, 0x0000);
1012                 break;
1013
1014         default:
1015                 break;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static irqreturn_t rt286_irq(int irq, void *data)
1022 {
1023         struct rt286_priv *rt286 = data;
1024         bool hp = false;
1025         bool mic = false;
1026         int status = 0;
1027
1028         rt286_jack_detect(rt286, &hp, &mic);
1029
1030         /* Clear IRQ */
1031         regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
1032
1033         if (hp == true)
1034                 status |= SND_JACK_HEADPHONE;
1035
1036         if (mic == true)
1037                 status |= SND_JACK_MICROPHONE;
1038
1039         snd_soc_jack_report(rt286->jack, status,
1040                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1041
1042         pm_wakeup_event(&rt286->i2c->dev, 300);
1043
1044         return IRQ_HANDLED;
1045 }
1046
1047 static int rt286_probe(struct snd_soc_codec *codec)
1048 {
1049         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1050
1051         rt286->codec = codec;
1052
1053         if (rt286->i2c->irq) {
1054                 regmap_update_bits(rt286->regmap,
1055                                         RT286_IRQ_CTRL, 0x2, 0x2);
1056
1057                 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1058                                         rt286_jack_detect_work);
1059                 schedule_delayed_work(&rt286->jack_detect_work,
1060                                         msecs_to_jiffies(1250));
1061         }
1062
1063         return 0;
1064 }
1065
1066 static int rt286_remove(struct snd_soc_codec *codec)
1067 {
1068         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1069
1070         cancel_delayed_work_sync(&rt286->jack_detect_work);
1071
1072         return 0;
1073 }
1074
1075 #ifdef CONFIG_PM
1076 static int rt286_suspend(struct snd_soc_codec *codec)
1077 {
1078         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1079
1080         regcache_cache_only(rt286->regmap, true);
1081         regcache_mark_dirty(rt286->regmap);
1082
1083         return 0;
1084 }
1085
1086 static int rt286_resume(struct snd_soc_codec *codec)
1087 {
1088         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1089
1090         regcache_cache_only(rt286->regmap, false);
1091         rt286_index_sync(codec);
1092         regcache_sync(rt286->regmap);
1093
1094         return 0;
1095 }
1096 #else
1097 #define rt286_suspend NULL
1098 #define rt286_resume NULL
1099 #endif
1100
1101 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1102 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1103                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1104
1105 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1106         .hw_params = rt286_hw_params,
1107         .set_fmt = rt286_set_dai_fmt,
1108         .set_sysclk = rt286_set_dai_sysclk,
1109         .set_bclk_ratio = rt286_set_bclk_ratio,
1110 };
1111
1112 static struct snd_soc_dai_driver rt286_dai[] = {
1113         {
1114                 .name = "rt286-aif1",
1115                 .id = RT286_AIF1,
1116                 .playback = {
1117                         .stream_name = "AIF1 Playback",
1118                         .channels_min = 1,
1119                         .channels_max = 2,
1120                         .rates = RT286_STEREO_RATES,
1121                         .formats = RT286_FORMATS,
1122                 },
1123                 .capture = {
1124                         .stream_name = "AIF1 Capture",
1125                         .channels_min = 1,
1126                         .channels_max = 2,
1127                         .rates = RT286_STEREO_RATES,
1128                         .formats = RT286_FORMATS,
1129                 },
1130                 .ops = &rt286_aif_dai_ops,
1131                 .symmetric_rates = 1,
1132         },
1133         {
1134                 .name = "rt286-aif2",
1135                 .id = RT286_AIF2,
1136                 .playback = {
1137                         .stream_name = "AIF2 Playback",
1138                         .channels_min = 1,
1139                         .channels_max = 2,
1140                         .rates = RT286_STEREO_RATES,
1141                         .formats = RT286_FORMATS,
1142                 },
1143                 .capture = {
1144                         .stream_name = "AIF2 Capture",
1145                         .channels_min = 1,
1146                         .channels_max = 2,
1147                         .rates = RT286_STEREO_RATES,
1148                         .formats = RT286_FORMATS,
1149                 },
1150                 .ops = &rt286_aif_dai_ops,
1151                 .symmetric_rates = 1,
1152         },
1153
1154 };
1155
1156 static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1157         .probe = rt286_probe,
1158         .remove = rt286_remove,
1159         .suspend = rt286_suspend,
1160         .resume = rt286_resume,
1161         .set_bias_level = rt286_set_bias_level,
1162         .idle_bias_off = true,
1163         .controls = rt286_snd_controls,
1164         .num_controls = ARRAY_SIZE(rt286_snd_controls),
1165         .dapm_widgets = rt286_dapm_widgets,
1166         .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1167         .dapm_routes = rt286_dapm_routes,
1168         .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1169 };
1170
1171 static const struct regmap_config rt286_regmap = {
1172         .reg_bits = 32,
1173         .val_bits = 32,
1174         .max_register = 0x02370100,
1175         .volatile_reg = rt286_volatile_register,
1176         .readable_reg = rt286_readable_register,
1177         .reg_write = rt286_hw_write,
1178         .reg_read = rt286_hw_read,
1179         .cache_type = REGCACHE_RBTREE,
1180         .reg_defaults = rt286_reg,
1181         .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1182 };
1183
1184 static const struct i2c_device_id rt286_i2c_id[] = {
1185         {"rt286", 0},
1186         {"rt288", 0},
1187         {}
1188 };
1189 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1190
1191 static const struct acpi_device_id rt286_acpi_match[] = {
1192         { "INT343A", 0 },
1193         {},
1194 };
1195 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1196
1197 static struct dmi_system_id force_combo_jack_table[] = {
1198         {
1199                 .ident = "Intel Wilson Beach",
1200                 .matches = {
1201                         DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1202                 }
1203         },
1204         { }
1205 };
1206
1207 static struct dmi_system_id dmi_dell_dino[] = {
1208         {
1209                 .ident = "Dell Dino",
1210                 .matches = {
1211                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1212                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
1213                 }
1214         },
1215         { }
1216 };
1217
1218 static int rt286_i2c_probe(struct i2c_client *i2c,
1219                            const struct i2c_device_id *id)
1220 {
1221         struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1222         struct rt286_priv *rt286;
1223         int i, ret, val;
1224
1225         rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1226                                 GFP_KERNEL);
1227         if (NULL == rt286)
1228                 return -ENOMEM;
1229
1230         rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1231         if (IS_ERR(rt286->regmap)) {
1232                 ret = PTR_ERR(rt286->regmap);
1233                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1234                         ret);
1235                 return ret;
1236         }
1237
1238         ret = regmap_read(rt286->regmap,
1239                 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1240         if (ret != 0) {
1241                 dev_err(&i2c->dev, "I2C error %d\n", ret);
1242                 return ret;
1243         }
1244         if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
1245                 dev_err(&i2c->dev,
1246                         "Device with ID register %x is not rt286\n", val);
1247                 return -ENODEV;
1248         }
1249
1250         rt286->index_cache = rt286_index_def;
1251         rt286->i2c = i2c;
1252         i2c_set_clientdata(i2c, rt286);
1253
1254         /* restore codec default */
1255         for (i = 0; i < INDEX_CACHE_SIZE; i++)
1256                 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1257                                 rt286->index_cache[i].def);
1258         for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1259                 regmap_write(rt286->regmap, rt286_reg[i].reg,
1260                                 rt286_reg[i].def);
1261
1262         if (pdata)
1263                 rt286->pdata = *pdata;
1264
1265         if (dmi_check_system(force_combo_jack_table) ||
1266                 dmi_check_system(dmi_dell_dino))
1267                 rt286->pdata.cbj_en = true;
1268
1269         regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1270
1271         for (i = 0; i < RT286_POWER_REG_LEN; i++)
1272                 regmap_write(rt286->regmap,
1273                         RT286_SET_POWER(rt286_support_power_controls[i]),
1274                         AC_PWRST_D1);
1275
1276         if (!rt286->pdata.cbj_en) {
1277                 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1278                 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1279                 regmap_update_bits(rt286->regmap,
1280                                         RT286_CBJ_CTRL1, 0xf000, 0xb000);
1281         } else {
1282                 regmap_update_bits(rt286->regmap,
1283                                         RT286_CBJ_CTRL1, 0xf000, 0x5000);
1284         }
1285
1286         mdelay(10);
1287
1288         if (!rt286->pdata.gpio2_en)
1289                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1290         else
1291                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1292
1293         mdelay(10);
1294
1295         regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1296         /* Power down LDO, VREF */
1297         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1298         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1299
1300         /* Set depop parameter */
1301         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1302         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1303         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1304
1305         if (dmi_check_system(dmi_dell_dino)) {
1306                 regmap_update_bits(rt286->regmap,
1307                         RT286_SET_GPIO_MASK, 0x40, 0x40);
1308                 regmap_update_bits(rt286->regmap,
1309                         RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1310                 regmap_update_bits(rt286->regmap,
1311                         RT286_SET_GPIO_DATA, 0x40, 0x40);
1312                 regmap_update_bits(rt286->regmap,
1313                         RT286_GPIO_CTRL, 0xc, 0x8);
1314         }
1315
1316         if (rt286->i2c->irq) {
1317                 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1318                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1319                 if (ret != 0) {
1320                         dev_err(&i2c->dev,
1321                                 "Failed to reguest IRQ: %d\n", ret);
1322                         return ret;
1323                 }
1324         }
1325
1326         ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1327                                      rt286_dai, ARRAY_SIZE(rt286_dai));
1328
1329         return ret;
1330 }
1331
1332 static int rt286_i2c_remove(struct i2c_client *i2c)
1333 {
1334         struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1335
1336         if (i2c->irq)
1337                 free_irq(i2c->irq, rt286);
1338         snd_soc_unregister_codec(&i2c->dev);
1339
1340         return 0;
1341 }
1342
1343
1344 static struct i2c_driver rt286_i2c_driver = {
1345         .driver = {
1346                    .name = "rt286",
1347                    .owner = THIS_MODULE,
1348                    .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1349                    },
1350         .probe = rt286_i2c_probe,
1351         .remove = rt286_i2c_remove,
1352         .id_table = rt286_i2c_id,
1353 };
1354
1355 module_i2c_driver(rt286_i2c_driver);
1356
1357 MODULE_DESCRIPTION("ASoC RT286 driver");
1358 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1359 MODULE_LICENSE("GPL");