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ASoC: add RT5651 CODEC driver
[deliverable/linux.git] / sound / soc / codecs / rt5651.c
1 /*
2 * rt5651.c -- RT5651 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28
29 #include "rt5651.h"
30
31 #define RT5651_DEVICE_ID_VALUE 0x6281
32
33 #define RT5651_PR_RANGE_BASE (0xff + 1)
34 #define RT5651_PR_SPACING 0x100
35
36 #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
37
38 static const struct regmap_range_cfg rt5651_ranges[] = {
39 { .name = "PR", .range_min = RT5651_PR_BASE,
40 .range_max = RT5651_PR_BASE + 0xb4,
41 .selector_reg = RT5651_PRIV_INDEX,
42 .selector_mask = 0xff,
43 .selector_shift = 0x0,
44 .window_start = RT5651_PRIV_DATA,
45 .window_len = 0x1, },
46 };
47
48 static struct reg_default init_list[] = {
49 {RT5651_PR_BASE + 0x3d, 0x3e00},
50 };
51
52 static const struct reg_default rt5651_reg[] = {
53 { 0x00, 0x0000 },
54 { 0x02, 0xc8c8 },
55 { 0x03, 0xc8c8 },
56 { 0x05, 0x0000 },
57 { 0x0d, 0x0000 },
58 { 0x0e, 0x0000 },
59 { 0x0f, 0x0808 },
60 { 0x10, 0x0808 },
61 { 0x19, 0xafaf },
62 { 0x1a, 0xafaf },
63 { 0x1b, 0x0c00 },
64 { 0x1c, 0x2f2f },
65 { 0x1d, 0x2f2f },
66 { 0x1e, 0x0000 },
67 { 0x27, 0x7860 },
68 { 0x28, 0x7070 },
69 { 0x29, 0x8080 },
70 { 0x2a, 0x5252 },
71 { 0x2b, 0x5454 },
72 { 0x2f, 0x0000 },
73 { 0x30, 0x5000 },
74 { 0x3b, 0x0000 },
75 { 0x3c, 0x006f },
76 { 0x3d, 0x0000 },
77 { 0x3e, 0x006f },
78 { 0x45, 0x6000 },
79 { 0x4d, 0x0000 },
80 { 0x4e, 0x0000 },
81 { 0x4f, 0x0279 },
82 { 0x50, 0x0000 },
83 { 0x51, 0x0000 },
84 { 0x52, 0x0279 },
85 { 0x53, 0xf000 },
86 { 0x61, 0x0000 },
87 { 0x62, 0x0000 },
88 { 0x63, 0x00c0 },
89 { 0x64, 0x0000 },
90 { 0x65, 0x0000 },
91 { 0x66, 0x0000 },
92 { 0x70, 0x8000 },
93 { 0x71, 0x8000 },
94 { 0x73, 0x1104 },
95 { 0x74, 0x0c00 },
96 { 0x75, 0x1400 },
97 { 0x77, 0x0c00 },
98 { 0x78, 0x4000 },
99 { 0x79, 0x0123 },
100 { 0x80, 0x0000 },
101 { 0x81, 0x0000 },
102 { 0x82, 0x0000 },
103 { 0x83, 0x0800 },
104 { 0x84, 0x0000 },
105 { 0x85, 0x0008 },
106 { 0x89, 0x0000 },
107 { 0x8e, 0x0004 },
108 { 0x8f, 0x1100 },
109 { 0x90, 0x0000 },
110 { 0x93, 0x2000 },
111 { 0x94, 0x0200 },
112 { 0xb0, 0x2080 },
113 { 0xb1, 0x0000 },
114 { 0xb4, 0x2206 },
115 { 0xb5, 0x1f00 },
116 { 0xb6, 0x0000 },
117 { 0xbb, 0x0000 },
118 { 0xbc, 0x0000 },
119 { 0xbd, 0x0000 },
120 { 0xbe, 0x0000 },
121 { 0xbf, 0x0000 },
122 { 0xc0, 0x0400 },
123 { 0xc1, 0x0000 },
124 { 0xc2, 0x0000 },
125 { 0xcf, 0x0013 },
126 { 0xd0, 0x0680 },
127 { 0xd1, 0x1c17 },
128 { 0xd3, 0xb320 },
129 { 0xd9, 0x0809 },
130 { 0xfa, 0x0010 },
131 { 0xfe, 0x10ec },
132 { 0xff, 0x6281 },
133 };
134
135 static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
136 {
137 int i;
138
139 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
140 if ((reg >= rt5651_ranges[i].window_start &&
141 reg <= rt5651_ranges[i].window_start +
142 rt5651_ranges[i].window_len) ||
143 (reg >= rt5651_ranges[i].range_min &&
144 reg <= rt5651_ranges[i].range_max)) {
145 return true;
146 }
147 }
148
149 switch (reg) {
150 case RT5651_RESET:
151 case RT5651_PRIV_DATA:
152 case RT5651_EQ_CTRL1:
153 case RT5651_ALC_1:
154 case RT5651_IRQ_CTRL2:
155 case RT5651_INT_IRQ_ST:
156 case RT5651_PGM_REG_ARR1:
157 case RT5651_PGM_REG_ARR3:
158 case RT5651_VENDOR_ID:
159 case RT5651_DEVICE_ID:
160 return true;
161 default:
162 return false;
163 }
164 }
165
166 static bool rt5651_readable_register(struct device *dev, unsigned int reg)
167 {
168 int i;
169
170 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
171 if ((reg >= rt5651_ranges[i].window_start &&
172 reg <= rt5651_ranges[i].window_start +
173 rt5651_ranges[i].window_len) ||
174 (reg >= rt5651_ranges[i].range_min &&
175 reg <= rt5651_ranges[i].range_max)) {
176 return true;
177 }
178 }
179
180 switch (reg) {
181 case RT5651_RESET:
182 case RT5651_VERSION_ID:
183 case RT5651_VENDOR_ID:
184 case RT5651_DEVICE_ID:
185 case RT5651_HP_VOL:
186 case RT5651_LOUT_CTRL1:
187 case RT5651_LOUT_CTRL2:
188 case RT5651_IN1_IN2:
189 case RT5651_IN3:
190 case RT5651_INL1_INR1_VOL:
191 case RT5651_INL2_INR2_VOL:
192 case RT5651_DAC1_DIG_VOL:
193 case RT5651_DAC2_DIG_VOL:
194 case RT5651_DAC2_CTRL:
195 case RT5651_ADC_DIG_VOL:
196 case RT5651_ADC_DATA:
197 case RT5651_ADC_BST_VOL:
198 case RT5651_STO1_ADC_MIXER:
199 case RT5651_STO2_ADC_MIXER:
200 case RT5651_AD_DA_MIXER:
201 case RT5651_STO_DAC_MIXER:
202 case RT5651_DD_MIXER:
203 case RT5651_DIG_INF_DATA:
204 case RT5651_PDM_CTL:
205 case RT5651_REC_L1_MIXER:
206 case RT5651_REC_L2_MIXER:
207 case RT5651_REC_R1_MIXER:
208 case RT5651_REC_R2_MIXER:
209 case RT5651_HPO_MIXER:
210 case RT5651_OUT_L1_MIXER:
211 case RT5651_OUT_L2_MIXER:
212 case RT5651_OUT_L3_MIXER:
213 case RT5651_OUT_R1_MIXER:
214 case RT5651_OUT_R2_MIXER:
215 case RT5651_OUT_R3_MIXER:
216 case RT5651_LOUT_MIXER:
217 case RT5651_PWR_DIG1:
218 case RT5651_PWR_DIG2:
219 case RT5651_PWR_ANLG1:
220 case RT5651_PWR_ANLG2:
221 case RT5651_PWR_MIXER:
222 case RT5651_PWR_VOL:
223 case RT5651_PRIV_INDEX:
224 case RT5651_PRIV_DATA:
225 case RT5651_I2S1_SDP:
226 case RT5651_I2S2_SDP:
227 case RT5651_ADDA_CLK1:
228 case RT5651_ADDA_CLK2:
229 case RT5651_DMIC:
230 case RT5651_TDM_CTL_1:
231 case RT5651_TDM_CTL_2:
232 case RT5651_TDM_CTL_3:
233 case RT5651_GLB_CLK:
234 case RT5651_PLL_CTRL1:
235 case RT5651_PLL_CTRL2:
236 case RT5651_PLL_MODE_1:
237 case RT5651_PLL_MODE_2:
238 case RT5651_PLL_MODE_3:
239 case RT5651_PLL_MODE_4:
240 case RT5651_PLL_MODE_5:
241 case RT5651_PLL_MODE_6:
242 case RT5651_PLL_MODE_7:
243 case RT5651_DEPOP_M1:
244 case RT5651_DEPOP_M2:
245 case RT5651_DEPOP_M3:
246 case RT5651_CHARGE_PUMP:
247 case RT5651_MICBIAS:
248 case RT5651_A_JD_CTL1:
249 case RT5651_EQ_CTRL1:
250 case RT5651_EQ_CTRL2:
251 case RT5651_ALC_1:
252 case RT5651_ALC_2:
253 case RT5651_ALC_3:
254 case RT5651_JD_CTRL1:
255 case RT5651_JD_CTRL2:
256 case RT5651_IRQ_CTRL1:
257 case RT5651_IRQ_CTRL2:
258 case RT5651_INT_IRQ_ST:
259 case RT5651_GPIO_CTRL1:
260 case RT5651_GPIO_CTRL2:
261 case RT5651_GPIO_CTRL3:
262 case RT5651_PGM_REG_ARR1:
263 case RT5651_PGM_REG_ARR2:
264 case RT5651_PGM_REG_ARR3:
265 case RT5651_PGM_REG_ARR4:
266 case RT5651_PGM_REG_ARR5:
267 case RT5651_SCB_FUNC:
268 case RT5651_SCB_CTRL:
269 case RT5651_BASE_BACK:
270 case RT5651_MP3_PLUS1:
271 case RT5651_MP3_PLUS2:
272 case RT5651_ADJ_HPF_CTRL1:
273 case RT5651_ADJ_HPF_CTRL2:
274 case RT5651_HP_CALIB_AMP_DET:
275 case RT5651_HP_CALIB2:
276 case RT5651_SV_ZCD1:
277 case RT5651_SV_ZCD2:
278 case RT5651_D_MISC:
279 case RT5651_DUMMY2:
280 case RT5651_DUMMY3:
281 return true;
282 default:
283 return false;
284 }
285 }
286
287 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
288 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
289 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
290 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
291 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
292
293 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
294 static unsigned int bst_tlv[] = {
295 TLV_DB_RANGE_HEAD(7),
296 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
297 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
298 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
299 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
300 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
301 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
302 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
303 };
304
305 /* Interface data select */
306 static const char * const rt5651_data_select[] = {
307 "Normal", "Swap", "left copy to right", "right copy to left"};
308
309 static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
310 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
311
312 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
313 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
314
315 static const struct snd_kcontrol_new rt5651_snd_controls[] = {
316 /* Headphone Output Volume */
317 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
318 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
319 /* OUTPUT Control */
320 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
321 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
322
323 /* DAC Digital Volume */
324 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
325 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
326 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
327 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
328 175, 0, dac_vol_tlv),
329 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
330 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
331 175, 0, dac_vol_tlv),
332 /* IN1/IN2 Control */
333 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
334 RT5651_BST_SFT1, 8, 0, bst_tlv),
335 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
336 RT5651_BST_SFT2, 8, 0, bst_tlv),
337 /* INL/INR Volume Control */
338 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
339 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
340 31, 1, in_vol_tlv),
341 /* ADC Digital Volume Control */
342 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
343 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
344 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
345 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
346 127, 0, adc_vol_tlv),
347 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
348 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
349 127, 0, adc_vol_tlv),
350 /* ADC Boost Volume Control */
351 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
352 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
353 3, 0, adc_bst_tlv),
354
355 /* ASRC */
356 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
357 RT5651_STO1_T_SFT, 1, 0),
358 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
359 RT5651_STO2_T_SFT, 1, 0),
360 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
361 RT5651_DMIC_1_M_SFT, 1, 0),
362
363 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
364 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
365 };
366
367 /**
368 * set_dmic_clk - Set parameter of dmic.
369 *
370 * @w: DAPM widget.
371 * @kcontrol: The kcontrol of this widget.
372 * @event: Event id.
373 *
374 * Choose dmic clock between 1MHz and 3MHz.
375 * It is better for clock to approximate 3MHz.
376 */
377 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
379 {
380 struct snd_soc_codec *codec = w->codec;
381 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
382 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
383 int i, rate, red, bound, temp;
384
385 rate = rt5651->sysclk;
386 red = 3000000 * 12;
387 for (i = 0; i < ARRAY_SIZE(div); i++) {
388 bound = div[i] * 3000000;
389 if (rate > bound)
390 continue;
391 temp = bound - rate;
392 if (temp < red) {
393 red = temp;
394 idx = i;
395 }
396 }
397 if (idx < 0)
398 dev_err(codec->dev, "Failed to set DMIC clock\n");
399 else
400 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
401 idx << RT5651_DMIC_CLK_SFT);
402
403 return idx;
404 }
405
406 static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
407 struct snd_soc_dapm_widget *sink)
408 {
409 unsigned int val;
410
411 val = snd_soc_read(source->codec, RT5651_GLB_CLK);
412 val &= RT5651_SCLK_SRC_MASK;
413 if (val == RT5651_SCLK_SRC_PLL1)
414 return 1;
415 else
416 return 0;
417 }
418
419 /* Digital Mixer */
420 static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
421 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
422 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
423 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
424 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
425 };
426
427 static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
428 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
429 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
430 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
431 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
432 };
433
434 static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
435 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
436 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
437 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
438 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
439 };
440
441 static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
442 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
443 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
444 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
445 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
446 };
447
448 static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
449 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
450 RT5651_M_ADCMIX_L_SFT, 1, 1),
451 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
452 RT5651_M_IF1_DAC_L_SFT, 1, 1),
453 };
454
455 static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
456 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
457 RT5651_M_ADCMIX_R_SFT, 1, 1),
458 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
459 RT5651_M_IF1_DAC_R_SFT, 1, 1),
460 };
461
462 static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
463 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
464 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
465 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
466 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
467 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
468 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
469 };
470
471 static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
472 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
473 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
474 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
475 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
476 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
477 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
478 };
479
480 static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
481 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
482 RT5651_M_STO_DD_L1_SFT, 1, 1),
483 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
484 RT5651_M_STO_DD_L2_SFT, 1, 1),
485 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
486 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
487 };
488
489 static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
490 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
491 RT5651_M_STO_DD_R1_SFT, 1, 1),
492 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
493 RT5651_M_STO_DD_R2_SFT, 1, 1),
494 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
495 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
496 };
497
498 /* Analog Input Mixer */
499 static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
500 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
501 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
502 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
503 RT5651_M_BST3_RM_L_SFT, 1, 1),
504 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
505 RT5651_M_BST2_RM_L_SFT, 1, 1),
506 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
507 RT5651_M_BST1_RM_L_SFT, 1, 1),
508 };
509
510 static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
511 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
512 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
513 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
514 RT5651_M_BST3_RM_R_SFT, 1, 1),
515 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
516 RT5651_M_BST2_RM_R_SFT, 1, 1),
517 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
518 RT5651_M_BST1_RM_R_SFT, 1, 1),
519 };
520
521 /* Analog Output Mixer */
522
523 static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
524 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
525 RT5651_M_BST1_OM_L_SFT, 1, 1),
526 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
527 RT5651_M_BST2_OM_L_SFT, 1, 1),
528 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
529 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
530 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
531 RT5651_M_RM_L_OM_L_SFT, 1, 1),
532 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
533 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
534 };
535
536 static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
537 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
538 RT5651_M_BST2_OM_R_SFT, 1, 1),
539 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
540 RT5651_M_BST1_OM_R_SFT, 1, 1),
541 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
542 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
543 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
544 RT5651_M_RM_R_OM_R_SFT, 1, 1),
545 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
546 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
547 };
548
549 static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
550 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
551 RT5651_M_DAC1_HM_SFT, 1, 1),
552 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
553 RT5651_M_HPVOL_HM_SFT, 1, 1),
554 };
555
556 static const struct snd_kcontrol_new rt5651_lout_mix[] = {
557 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
558 RT5651_M_DAC_L1_LM_SFT, 1, 1),
559 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
560 RT5651_M_DAC_R1_LM_SFT, 1, 1),
561 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
562 RT5651_M_OV_L_LM_SFT, 1, 1),
563 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
564 RT5651_M_OV_R_LM_SFT, 1, 1),
565 };
566
567 static const struct snd_kcontrol_new outvol_l_control =
568 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
569 RT5651_VOL_L_SFT, 1, 1);
570
571 static const struct snd_kcontrol_new outvol_r_control =
572 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
573 RT5651_VOL_R_SFT, 1, 1);
574
575 static const struct snd_kcontrol_new lout_l_mute_control =
576 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
577 RT5651_L_MUTE_SFT, 1, 1);
578
579 static const struct snd_kcontrol_new lout_r_mute_control =
580 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
581 RT5651_R_MUTE_SFT, 1, 1);
582
583 static const struct snd_kcontrol_new hpovol_l_control =
584 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
585 RT5651_VOL_L_SFT, 1, 1);
586
587 static const struct snd_kcontrol_new hpovol_r_control =
588 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
589 RT5651_VOL_R_SFT, 1, 1);
590
591 static const struct snd_kcontrol_new hpo_l_mute_control =
592 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
593 RT5651_L_MUTE_SFT, 1, 1);
594
595 static const struct snd_kcontrol_new hpo_r_mute_control =
596 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
597 RT5651_R_MUTE_SFT, 1, 1);
598
599 /* INL/R source */
600 static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
601
602 static SOC_ENUM_SINGLE_DECL(
603 rt5651_inl_enum, RT5651_INL1_INR1_VOL,
604 RT5651_INL_SEL_SFT, rt5651_inl_src);
605
606 static const struct snd_kcontrol_new rt5651_inl1_mux =
607 SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
608
609 static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
610
611 static SOC_ENUM_SINGLE_DECL(
612 rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
613 RT5651_INR_SEL_SFT, rt5651_inr1_src);
614
615 static const struct snd_kcontrol_new rt5651_inr1_mux =
616 SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
617
618 static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
619
620 static SOC_ENUM_SINGLE_DECL(
621 rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
622 RT5651_INL_SEL_SFT, rt5651_inl2_src);
623
624 static const struct snd_kcontrol_new rt5651_inl2_mux =
625 SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
626
627 static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
628
629 static SOC_ENUM_SINGLE_DECL(
630 rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
631 RT5651_INR_SEL_SFT, rt5651_inr2_src);
632
633 static const struct snd_kcontrol_new rt5651_inr2_mux =
634 SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
635
636
637 /* Stereo ADC source */
638 static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
639
640 static SOC_ENUM_SINGLE_DECL(
641 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
642 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
643
644 static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
645 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
646
647 static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
648 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
649
650 static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
651
652 static SOC_ENUM_SINGLE_DECL(
653 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
654 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
655
656 static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
657 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
658
659 static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
660 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
661
662 /* Mono ADC source */
663 static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
664
665 static SOC_ENUM_SINGLE_DECL(
666 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
667 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
668
669 static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
670 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
671
672 static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
673
674 static SOC_ENUM_SINGLE_DECL(
675 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
676 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
677
678 static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
679 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
680
681 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
682
683 static SOC_ENUM_SINGLE_DECL(
684 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
685 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
686
687 static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
688 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
689
690 static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
691
692 static SOC_ENUM_SINGLE_DECL(
693 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
694 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
695
696 static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
697 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
698
699 /* DAC2 channel source */
700
701 static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
702
703 static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
704 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
705
706 static const struct snd_kcontrol_new rt5651_dac_l2_mux =
707 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
708
709 static SOC_ENUM_SINGLE_DECL(
710 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
711 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
712
713 static const struct snd_kcontrol_new rt5651_dac_r2_mux =
714 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
715
716 /* IF2_ADC channel source */
717
718 static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
719
720 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
721 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
722
723 static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
724 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
725
726 /* PDM select */
727 static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
728
729 static SOC_ENUM_SINGLE_DECL(
730 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
731 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
732
733 static SOC_ENUM_SINGLE_DECL(
734 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
735 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
736
737 static const struct snd_kcontrol_new rt5651_pdm_l_mux =
738 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
739
740 static const struct snd_kcontrol_new rt5651_pdm_r_mux =
741 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
742
743 static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
744 struct snd_kcontrol *kcontrol, int event)
745 {
746 struct snd_soc_codec *codec = w->codec;
747 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
748
749 switch (event) {
750 case SND_SOC_DAPM_POST_PMU:
751 /* depop parameters */
752 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
753 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
754 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
755 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
756 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
757 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
758 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
759 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
760 regmap_write(rt5651->regmap, RT5651_PR_BASE +
761 RT5651_HP_DCC_INT1, 0x9f00);
762 /* headphone amp power on */
763 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
764 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
765 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
766 RT5651_PWR_HA,
767 RT5651_PWR_HA);
768 usleep_range(10000, 15000);
769 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
770 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
771 RT5651_PWR_FV1 | RT5651_PWR_FV2);
772 break;
773
774 default:
775 return 0;
776 }
777
778 return 0;
779 }
780
781 static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
782 struct snd_kcontrol *kcontrol, int event)
783 {
784 struct snd_soc_codec *codec = w->codec;
785 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
786
787 switch (event) {
788 case SND_SOC_DAPM_POST_PMU:
789 /* headphone unmute sequence */
790 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
791 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
792 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
793 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
794 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
795
796 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
797 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
798 RT5651_CP_FQ3_MASK,
799 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
800 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
801 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
802
803 regmap_write(rt5651->regmap, RT5651_PR_BASE +
804 RT5651_MAMP_INT_REG2, 0x1c00);
805 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
806 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
807 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
808 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
809 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
810 rt5651->hp_mute = 0;
811 break;
812
813 case SND_SOC_DAPM_PRE_PMD:
814 rt5651->hp_mute = 1;
815 usleep_range(70000, 75000);
816 break;
817
818 default:
819 return 0;
820 }
821
822 return 0;
823 }
824
825 static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
826 struct snd_kcontrol *kcontrol, int event)
827 {
828 struct snd_soc_codec *codec = w->codec;
829 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
830
831 switch (event) {
832 case SND_SOC_DAPM_POST_PMU:
833 if (!rt5651->hp_mute)
834 usleep_range(80000, 85000);
835
836 break;
837
838 default:
839 return 0;
840 }
841
842 return 0;
843 }
844
845 static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
846 struct snd_kcontrol *kcontrol, int event)
847 {
848 struct snd_soc_codec *codec = w->codec;
849
850 switch (event) {
851 case SND_SOC_DAPM_POST_PMU:
852 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
853 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
854 break;
855
856 case SND_SOC_DAPM_PRE_PMD:
857 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
858 RT5651_PWR_BST1_OP2, 0);
859 break;
860
861 default:
862 return 0;
863 }
864
865 return 0;
866 }
867
868 static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
869 struct snd_kcontrol *kcontrol, int event)
870 {
871 struct snd_soc_codec *codec = w->codec;
872
873 switch (event) {
874 case SND_SOC_DAPM_POST_PMU:
875 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
876 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
877 break;
878
879 case SND_SOC_DAPM_PRE_PMD:
880 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
881 RT5651_PWR_BST2_OP2, 0);
882 break;
883
884 default:
885 return 0;
886 }
887
888 return 0;
889 }
890
891 static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
892 struct snd_kcontrol *kcontrol, int event)
893 {
894 struct snd_soc_codec *codec = w->codec;
895
896 switch (event) {
897 case SND_SOC_DAPM_POST_PMU:
898 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
899 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
900 break;
901
902 case SND_SOC_DAPM_PRE_PMD:
903 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
904 RT5651_PWR_BST3_OP2, 0);
905 break;
906
907 default:
908 return 0;
909 }
910
911 return 0;
912 }
913
914 static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
915 /* ASRC */
916 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
917 15, 0, NULL, 0),
918 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
919 14, 0, NULL, 0),
920 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
921 13, 0, NULL, 0),
922 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
923 12, 0, NULL, 0),
924 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
925 11, 0, NULL, 0),
926
927 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
928 RT5651_PWR_PLL_BIT, 0, NULL, 0),
929 /* Input Side */
930 /* micbias */
931 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
932 RT5651_PWR_LDO_BIT, 0, NULL, 0),
933 SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
934 RT5651_PWR_MB1_BIT, 0),
935 /* Input Lines */
936 SND_SOC_DAPM_INPUT("MIC1"),
937 SND_SOC_DAPM_INPUT("MIC2"),
938 SND_SOC_DAPM_INPUT("MIC3"),
939
940 SND_SOC_DAPM_INPUT("IN1P"),
941 SND_SOC_DAPM_INPUT("IN2P"),
942 SND_SOC_DAPM_INPUT("IN2N"),
943 SND_SOC_DAPM_INPUT("IN3P"),
944 SND_SOC_DAPM_INPUT("DMIC L1"),
945 SND_SOC_DAPM_INPUT("DMIC R1"),
946 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
947 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
948 /* Boost */
949 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
950 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
951 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
952 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
953 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
954 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
955 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
956 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
957 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
958 /* Input Volume */
959 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
960 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
961 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
962 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
963 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
964 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
965 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
966 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
967 /* IN Mux */
968 SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
969 SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
970 SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
971 SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
972 /* REC Mixer */
973 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
974 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
975 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
976 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
977 /* ADCs */
978 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
979 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
980 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
981 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
982 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
983 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
984 /* ADC Mux */
985 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
986 &rt5651_sto1_adc_l2_mux),
987 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
988 &rt5651_sto1_adc_r2_mux),
989 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
990 &rt5651_sto1_adc_l1_mux),
991 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
992 &rt5651_sto1_adc_r1_mux),
993 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
994 &rt5651_sto2_adc_l2_mux),
995 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
996 &rt5651_sto2_adc_l1_mux),
997 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
998 &rt5651_sto2_adc_r1_mux),
999 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1000 &rt5651_sto2_adc_r2_mux),
1001 /* ADC Mixer */
1002 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
1003 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
1004 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
1005 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
1006 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1007 rt5651_sto1_adc_l_mix,
1008 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
1009 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1010 rt5651_sto1_adc_r_mix,
1011 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
1012 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1013 rt5651_sto2_adc_l_mix,
1014 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
1015 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1016 rt5651_sto2_adc_r_mix,
1017 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
1018
1019 /* Digital Interface */
1020 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
1021 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
1022 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1023 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1024 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1025 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1026 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1027 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1028 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1029 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1030 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1031 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1032 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1033 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1034 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1035 &rt5651_if2_adc_src_mux),
1036
1037 /* Digital Interface Select */
1038
1039 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1040 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1041 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1042 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1043 /* Audio Interface */
1044 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1045 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1046 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1047 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1048
1049 /* Audio DSP */
1050 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1051
1052 /* Output Side */
1053 /* DAC mixer before sound effect */
1054 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1055 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1056 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1057 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1058
1059 /* DAC2 channel Mux */
1060 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1061 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1062 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1063 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1064
1065 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1066 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1067 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1068 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1069 /* DAC Mixer */
1070 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1071 rt5651_sto_dac_l_mix,
1072 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1073 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1074 rt5651_sto_dac_r_mix,
1075 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1076 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1077 rt5651_dd_dac_l_mix,
1078 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1079 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1080 rt5651_dd_dac_r_mix,
1081 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1082
1083 /* DACs */
1084 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1085 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1086 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1087 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1088 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1089 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1090 /* OUT Mixer */
1091 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1092 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1093 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1094 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1095 /* Ouput Volume */
1096 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1097 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1098 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1099 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1100 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1101 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1102 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1103 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1104 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1105 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1106 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1107 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1109 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1110 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1111 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1112 /* HPO/LOUT/Mono Mixer */
1113 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1114 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1115 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1116 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1117 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1118 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1119 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1120 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1121 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1122 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1123
1124 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1125 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1126 SND_SOC_DAPM_POST_PMU),
1127 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1128 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1129 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1130 &hpo_l_mute_control),
1131 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1132 &hpo_r_mute_control),
1133 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1134 &lout_l_mute_control),
1135 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1136 &lout_r_mute_control),
1137 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1138
1139 /* Output Lines */
1140 SND_SOC_DAPM_OUTPUT("HPOL"),
1141 SND_SOC_DAPM_OUTPUT("HPOR"),
1142 SND_SOC_DAPM_OUTPUT("LOUTL"),
1143 SND_SOC_DAPM_OUTPUT("LOUTR"),
1144 SND_SOC_DAPM_OUTPUT("PDML"),
1145 SND_SOC_DAPM_OUTPUT("PDMR"),
1146 };
1147
1148 static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1149 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1150 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1151 {"I2S1", NULL, "I2S1 ASRC"},
1152 {"I2S2", NULL, "I2S2 ASRC"},
1153
1154 {"IN1P", NULL, "LDO"},
1155 {"IN2P", NULL, "LDO"},
1156 {"IN3P", NULL, "LDO"},
1157
1158 {"IN1P", NULL, "MIC1"},
1159 {"IN2P", NULL, "MIC2"},
1160 {"IN2N", NULL, "MIC2"},
1161 {"IN3P", NULL, "MIC3"},
1162
1163 {"BST1", NULL, "IN1P"},
1164 {"BST2", NULL, "IN2P"},
1165 {"BST2", NULL, "IN2N"},
1166 {"BST3", NULL, "IN3P"},
1167
1168 {"INL1 VOL", NULL, "IN2P"},
1169 {"INR1 VOL", NULL, "IN2N"},
1170
1171 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1172 {"RECMIXL", "BST3 Switch", "BST3"},
1173 {"RECMIXL", "BST2 Switch", "BST2"},
1174 {"RECMIXL", "BST1 Switch", "BST1"},
1175
1176 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1177 {"RECMIXR", "BST3 Switch", "BST3"},
1178 {"RECMIXR", "BST2 Switch", "BST2"},
1179 {"RECMIXR", "BST1 Switch", "BST1"},
1180
1181 {"ADC L", NULL, "RECMIXL"},
1182 {"ADC L", NULL, "ADC L Power"},
1183 {"ADC R", NULL, "RECMIXR"},
1184 {"ADC R", NULL, "ADC R Power"},
1185
1186 {"DMIC L1", NULL, "DMIC CLK"},
1187 {"DMIC R1", NULL, "DMIC CLK"},
1188
1189 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1190 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1191 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1192 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1193
1194 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1195 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1196 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1197 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1198
1199 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1200 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1201 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1202 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1203
1204 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1205 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1206 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1207 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1208
1209 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1210 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1211 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1212 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1213 {"Stereo1 Filter", NULL, "ADC ASRC"},
1214
1215 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1216 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1217 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1218
1219 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1220 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1221 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1222 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1223 {"Stereo2 Filter", NULL, "ADC ASRC"},
1224
1225 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1226 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1227 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1228
1229 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1230 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1231 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1232 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1233
1234 {"IF1 ADC1", NULL, "I2S1"},
1235
1236 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1237 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1238 {"IF2 ADC", NULL, "I2S2"},
1239
1240 {"AIF1TX", NULL, "IF1 ADC1"},
1241 {"AIF1TX", NULL, "IF1 ADC2"},
1242 {"AIF2TX", NULL, "IF2 ADC"},
1243
1244 {"IF1 DAC", NULL, "AIF1RX"},
1245 {"IF1 DAC", NULL, "I2S1"},
1246 {"IF2 DAC", NULL, "AIF2RX"},
1247 {"IF2 DAC", NULL, "I2S2"},
1248
1249 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1250 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1251 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1252 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1253 {"IF2 DAC L", NULL, "IF2 DAC"},
1254 {"IF2 DAC R", NULL, "IF2 DAC"},
1255
1256 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1257 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1258 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1259 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1260
1261 {"Audio DSP", NULL, "DAC MIXL"},
1262 {"Audio DSP", NULL, "DAC MIXR"},
1263
1264 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1265 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1266 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1267
1268 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1269 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1270 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1271
1272 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1273 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1274 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1275 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1276 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1277 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1278 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1279 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1280 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1281 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1282
1283 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1284 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1285 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1286 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1287
1288 {"DAC L1", NULL, "Stereo DAC MIXL"},
1289 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1290 {"DAC L1", NULL, "DAC L1 Power"},
1291 {"DAC R1", NULL, "Stereo DAC MIXR"},
1292 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1293 {"DAC R1", NULL, "DAC R1 Power"},
1294
1295 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1296 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1297 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1298 {"DD MIXL", NULL, "Stero2 DAC Power"},
1299
1300 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1301 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1302 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1303 {"DD MIXR", NULL, "Stero2 DAC Power"},
1304
1305 {"OUT MIXL", "BST1 Switch", "BST1"},
1306 {"OUT MIXL", "BST2 Switch", "BST2"},
1307 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1308 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1309 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1310
1311 {"OUT MIXR", "BST2 Switch", "BST2"},
1312 {"OUT MIXR", "BST1 Switch", "BST1"},
1313 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1314 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1315 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1316
1317 {"HPOVOL L", "Switch", "OUT MIXL"},
1318 {"HPOVOL R", "Switch", "OUT MIXR"},
1319 {"OUTVOL L", "Switch", "OUT MIXL"},
1320 {"OUTVOL R", "Switch", "OUT MIXR"},
1321
1322 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1323 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1324 {"HPOL MIX", NULL, "HP L Amp"},
1325 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1326 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1327 {"HPOR MIX", NULL, "HP R Amp"},
1328
1329 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1330 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1331 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1332 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1333
1334 {"HP Amp", NULL, "HPOL MIX"},
1335 {"HP Amp", NULL, "HPOR MIX"},
1336 {"HP Amp", NULL, "Amp Power"},
1337 {"HPO L Playback", "Switch", "HP Amp"},
1338 {"HPO R Playback", "Switch", "HP Amp"},
1339 {"HPOL", NULL, "HPO L Playback"},
1340 {"HPOR", NULL, "HPO R Playback"},
1341
1342 {"LOUT L Playback", "Switch", "LOUT MIX"},
1343 {"LOUT R Playback", "Switch", "LOUT MIX"},
1344 {"LOUTL", NULL, "LOUT L Playback"},
1345 {"LOUTL", NULL, "Amp Power"},
1346 {"LOUTR", NULL, "LOUT R Playback"},
1347 {"LOUTR", NULL, "Amp Power"},
1348
1349 {"PDML", NULL, "PDM L Mux"},
1350 {"PDMR", NULL, "PDM R Mux"},
1351 };
1352
1353 static int get_clk_info(int sclk, int rate)
1354 {
1355 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1356
1357 if (sclk <= 0 || rate <= 0)
1358 return -EINVAL;
1359
1360 rate = rate << 8;
1361 for (i = 0; i < ARRAY_SIZE(pd); i++)
1362 if (sclk == rate * pd[i])
1363 return i;
1364
1365 return -EINVAL;
1366 }
1367
1368 static int rt5651_hw_params(struct snd_pcm_substream *substream,
1369 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1370 {
1371 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1372 struct snd_soc_codec *codec = rtd->codec;
1373 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1374 unsigned int val_len = 0, val_clk, mask_clk;
1375 int pre_div, bclk_ms, frame_size;
1376
1377 rt5651->lrck[dai->id] = params_rate(params);
1378 pre_div = get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1379
1380 if (pre_div < 0) {
1381 dev_err(codec->dev, "Unsupported clock setting\n");
1382 return -EINVAL;
1383 }
1384 frame_size = snd_soc_params_to_frame_size(params);
1385 if (frame_size < 0) {
1386 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1387 return -EINVAL;
1388 }
1389 bclk_ms = frame_size > 32 ? 1 : 0;
1390 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1391
1392 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1393 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1394 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1395 bclk_ms, pre_div, dai->id);
1396
1397 switch (params_format(params)) {
1398 case SNDRV_PCM_FORMAT_S16_LE:
1399 break;
1400 case SNDRV_PCM_FORMAT_S20_3LE:
1401 val_len |= RT5651_I2S_DL_20;
1402 break;
1403 case SNDRV_PCM_FORMAT_S24_LE:
1404 val_len |= RT5651_I2S_DL_24;
1405 break;
1406 case SNDRV_PCM_FORMAT_S8:
1407 val_len |= RT5651_I2S_DL_8;
1408 break;
1409 default:
1410 return -EINVAL;
1411 }
1412
1413 switch (dai->id) {
1414 case RT5651_AIF1:
1415 mask_clk = RT5651_I2S_PD1_MASK;
1416 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1417 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1418 RT5651_I2S_DL_MASK, val_len);
1419 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1420 break;
1421 case RT5651_AIF2:
1422 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1423 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1424 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1425 RT5651_I2S_DL_MASK, val_len);
1426 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1427 break;
1428 default:
1429 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1430 return -EINVAL;
1431 }
1432
1433 return 0;
1434 }
1435
1436 static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1437 {
1438 struct snd_soc_codec *codec = dai->codec;
1439 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1440 unsigned int reg_val = 0;
1441
1442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1443 case SND_SOC_DAIFMT_CBM_CFM:
1444 rt5651->master[dai->id] = 1;
1445 break;
1446 case SND_SOC_DAIFMT_CBS_CFS:
1447 reg_val |= RT5651_I2S_MS_S;
1448 rt5651->master[dai->id] = 0;
1449 break;
1450 default:
1451 return -EINVAL;
1452 }
1453
1454 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1455 case SND_SOC_DAIFMT_NB_NF:
1456 break;
1457 case SND_SOC_DAIFMT_IB_NF:
1458 reg_val |= RT5651_I2S_BP_INV;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1465 case SND_SOC_DAIFMT_I2S:
1466 break;
1467 case SND_SOC_DAIFMT_LEFT_J:
1468 reg_val |= RT5651_I2S_DF_LEFT;
1469 break;
1470 case SND_SOC_DAIFMT_DSP_A:
1471 reg_val |= RT5651_I2S_DF_PCM_A;
1472 break;
1473 case SND_SOC_DAIFMT_DSP_B:
1474 reg_val |= RT5651_I2S_DF_PCM_B;
1475 break;
1476 default:
1477 return -EINVAL;
1478 }
1479
1480 switch (dai->id) {
1481 case RT5651_AIF1:
1482 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1483 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1484 RT5651_I2S_DF_MASK, reg_val);
1485 break;
1486 case RT5651_AIF2:
1487 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1488 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1489 RT5651_I2S_DF_MASK, reg_val);
1490 break;
1491 default:
1492 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1493 return -EINVAL;
1494 }
1495 return 0;
1496 }
1497
1498 static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1499 int clk_id, unsigned int freq, int dir)
1500 {
1501 struct snd_soc_codec *codec = dai->codec;
1502 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1503 unsigned int reg_val = 0;
1504
1505 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1506 return 0;
1507
1508 switch (clk_id) {
1509 case RT5651_SCLK_S_MCLK:
1510 reg_val |= RT5651_SCLK_SRC_MCLK;
1511 break;
1512 case RT5651_SCLK_S_PLL1:
1513 reg_val |= RT5651_SCLK_SRC_PLL1;
1514 break;
1515 case RT5651_SCLK_S_RCCLK:
1516 reg_val |= RT5651_SCLK_SRC_RCCLK;
1517 break;
1518 default:
1519 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1520 return -EINVAL;
1521 }
1522 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1523 RT5651_SCLK_SRC_MASK, reg_val);
1524 rt5651->sysclk = freq;
1525 rt5651->sysclk_src = clk_id;
1526
1527 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1528
1529 return 0;
1530 }
1531
1532 /**
1533 * rt5651_pll_calc - Calcualte PLL M/N/K code.
1534 * @freq_in: external clock provided to codec.
1535 * @freq_out: target clock which codec works on.
1536 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1537 *
1538 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1539 * which make calculation more efficiently.
1540 *
1541 * Returns 0 for success or negative error code.
1542 */
1543 static int rt5651_pll_calc(const unsigned int freq_in,
1544 const unsigned int freq_out, struct rt5651_pll_code *pll_code)
1545 {
1546 int max_n = RT5651_PLL_N_MAX, max_m = RT5651_PLL_M_MAX;
1547 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1548 int red_t = abs(freq_out - freq_in);
1549 bool bypass = false;
1550
1551 if (RT5651_PLL_INP_MAX < freq_in || RT5651_PLL_INP_MIN > freq_in)
1552 return -EINVAL;
1553
1554 for (n_t = 0; n_t <= max_n; n_t++) {
1555 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1556 if (in_t < 0)
1557 continue;
1558 if (in_t == freq_out) {
1559 bypass = true;
1560 n = n_t;
1561 goto code_find;
1562 }
1563 for (m_t = 0; m_t <= max_m; m_t++) {
1564 out_t = in_t / (m_t + 2);
1565 red = abs(out_t - freq_out);
1566 if (red < red_t) {
1567 n = n_t;
1568 m = m_t;
1569 if (red == 0)
1570 goto code_find;
1571 red_t = red;
1572 }
1573 }
1574 }
1575 pr_debug("Only get approximation about PLL\n");
1576
1577 code_find:
1578 pll_code->m_bp = bypass;
1579 pll_code->m_code = m;
1580 pll_code->n_code = n;
1581 pll_code->k_code = 2;
1582 return 0;
1583 }
1584
1585 static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1586 unsigned int freq_in, unsigned int freq_out)
1587 {
1588 struct snd_soc_codec *codec = dai->codec;
1589 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1590 struct rt5651_pll_code *pll_code = &rt5651->pll_code;
1591 int ret;
1592
1593 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1594 freq_out == rt5651->pll_out)
1595 return 0;
1596
1597 if (!freq_in || !freq_out) {
1598 dev_dbg(codec->dev, "PLL disabled\n");
1599
1600 rt5651->pll_in = 0;
1601 rt5651->pll_out = 0;
1602 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1603 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1604 return 0;
1605 }
1606
1607 switch (source) {
1608 case RT5651_PLL1_S_MCLK:
1609 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1610 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1611 break;
1612 case RT5651_PLL1_S_BCLK1:
1613 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1614 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1615 break;
1616 case RT5651_PLL1_S_BCLK2:
1617 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1618 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1619 break;
1620 default:
1621 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1622 return -EINVAL;
1623 }
1624
1625 ret = rt5651_pll_calc(freq_in, freq_out, pll_code);
1626 if (ret < 0) {
1627 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1628 return ret;
1629 }
1630
1631 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
1632 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
1633
1634 snd_soc_write(codec, RT5651_PLL_CTRL1,
1635 pll_code->n_code << RT5651_PLL_N_SFT | pll_code->k_code);
1636 snd_soc_write(codec, RT5651_PLL_CTRL2,
1637 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5651_PLL_M_SFT |
1638 pll_code->m_bp << RT5651_PLL_M_BP_SFT);
1639
1640 rt5651->pll_in = freq_in;
1641 rt5651->pll_out = freq_out;
1642 rt5651->pll_src = source;
1643
1644 return 0;
1645 }
1646
1647 static int rt5651_set_bias_level(struct snd_soc_codec *codec,
1648 enum snd_soc_bias_level level)
1649 {
1650 switch (level) {
1651 case SND_SOC_BIAS_PREPARE:
1652 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1653 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1654 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1655 RT5651_PWR_BG | RT5651_PWR_VREF2,
1656 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1657 RT5651_PWR_BG | RT5651_PWR_VREF2);
1658 usleep_range(10000, 15000);
1659 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1660 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1661 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1662 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1663 RT5651_PWR_LDO_DVO_MASK,
1664 RT5651_PWR_LDO_DVO_1_2V);
1665 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
1666 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
1667 snd_soc_update_bits(codec, RT5651_D_MISC,
1668 0xc00, 0xc00);
1669 }
1670 break;
1671
1672 case SND_SOC_BIAS_STANDBY:
1673 snd_soc_write(codec, RT5651_D_MISC, 0x0010);
1674 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
1675 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
1676 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
1677 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
1678 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
1679 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
1680 break;
1681
1682 default:
1683 break;
1684 }
1685 codec->dapm.bias_level = level;
1686
1687 return 0;
1688 }
1689
1690 static int rt5651_probe(struct snd_soc_codec *codec)
1691 {
1692 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1693
1694 rt5651->codec = codec;
1695
1696 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1697 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1698 RT5651_PWR_BG | RT5651_PWR_VREF2,
1699 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1700 RT5651_PWR_BG | RT5651_PWR_VREF2);
1701 usleep_range(10000, 15000);
1702 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1703 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1704 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1705
1706 rt5651_set_bias_level(codec, SND_SOC_BIAS_OFF);
1707
1708 return 0;
1709 }
1710
1711 #ifdef CONFIG_PM
1712 static int rt5651_suspend(struct snd_soc_codec *codec)
1713 {
1714 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1715
1716 regcache_cache_only(rt5651->regmap, true);
1717 regcache_mark_dirty(rt5651->regmap);
1718 return 0;
1719 }
1720
1721 static int rt5651_resume(struct snd_soc_codec *codec)
1722 {
1723 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1724
1725 regcache_cache_only(rt5651->regmap, false);
1726 snd_soc_cache_sync(codec);
1727
1728 return 0;
1729 }
1730 #else
1731 #define rt5651_suspend NULL
1732 #define rt5651_resume NULL
1733 #endif
1734
1735 #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1736 #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1737 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1738
1739 struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1740 .hw_params = rt5651_hw_params,
1741 .set_fmt = rt5651_set_dai_fmt,
1742 .set_sysclk = rt5651_set_dai_sysclk,
1743 .set_pll = rt5651_set_dai_pll,
1744 };
1745
1746 struct snd_soc_dai_driver rt5651_dai[] = {
1747 {
1748 .name = "rt5651-aif1",
1749 .id = RT5651_AIF1,
1750 .playback = {
1751 .stream_name = "AIF1 Playback",
1752 .channels_min = 1,
1753 .channels_max = 2,
1754 .rates = RT5651_STEREO_RATES,
1755 .formats = RT5651_FORMATS,
1756 },
1757 .capture = {
1758 .stream_name = "AIF1 Capture",
1759 .channels_min = 1,
1760 .channels_max = 2,
1761 .rates = RT5651_STEREO_RATES,
1762 .formats = RT5651_FORMATS,
1763 },
1764 .ops = &rt5651_aif_dai_ops,
1765 },
1766 {
1767 .name = "rt5651-aif2",
1768 .id = RT5651_AIF2,
1769 .playback = {
1770 .stream_name = "AIF2 Playback",
1771 .channels_min = 1,
1772 .channels_max = 2,
1773 .rates = RT5651_STEREO_RATES,
1774 .formats = RT5651_FORMATS,
1775 },
1776 .capture = {
1777 .stream_name = "AIF2 Capture",
1778 .channels_min = 1,
1779 .channels_max = 2,
1780 .rates = RT5651_STEREO_RATES,
1781 .formats = RT5651_FORMATS,
1782 },
1783 .ops = &rt5651_aif_dai_ops,
1784 },
1785 };
1786
1787 static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
1788 .probe = rt5651_probe,
1789 .suspend = rt5651_suspend,
1790 .resume = rt5651_resume,
1791 .set_bias_level = rt5651_set_bias_level,
1792 .idle_bias_off = true,
1793 .controls = rt5651_snd_controls,
1794 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1795 .dapm_widgets = rt5651_dapm_widgets,
1796 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1797 .dapm_routes = rt5651_dapm_routes,
1798 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1799 };
1800
1801 static const struct regmap_config rt5651_regmap = {
1802 .reg_bits = 8,
1803 .val_bits = 16,
1804
1805 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1806 RT5651_PR_SPACING),
1807 .volatile_reg = rt5651_volatile_register,
1808 .readable_reg = rt5651_readable_register,
1809
1810 .cache_type = REGCACHE_RBTREE,
1811 .reg_defaults = rt5651_reg,
1812 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1813 .ranges = rt5651_ranges,
1814 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1815 };
1816
1817 static const struct i2c_device_id rt5651_i2c_id[] = {
1818 { "rt5651", 0 },
1819 { }
1820 };
1821 MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1822
1823 static int rt5651_i2c_probe(struct i2c_client *i2c,
1824 const struct i2c_device_id *id)
1825 {
1826 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
1827 struct rt5651_priv *rt5651;
1828 int ret;
1829
1830 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1831 GFP_KERNEL);
1832 if (NULL == rt5651)
1833 return -ENOMEM;
1834
1835 i2c_set_clientdata(i2c, rt5651);
1836
1837 if (pdata)
1838 rt5651->pdata = *pdata;
1839
1840 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1841 if (IS_ERR(rt5651->regmap)) {
1842 ret = PTR_ERR(rt5651->regmap);
1843 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1844 ret);
1845 return ret;
1846 }
1847
1848 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1849 if (ret != RT5651_DEVICE_ID_VALUE) {
1850 dev_err(&i2c->dev,
1851 "Device with ID register %x is not rt5651\n", ret);
1852 return -ENODEV;
1853 }
1854
1855 regmap_write(rt5651->regmap, RT5651_RESET, 0);
1856
1857 ret = regmap_register_patch(rt5651->regmap, init_list,
1858 ARRAY_SIZE(init_list));
1859 if (ret != 0)
1860 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1861
1862 if (rt5651->pdata.in2_diff)
1863 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
1864 RT5651_IN_DF2, RT5651_IN_DF2);
1865
1866 if (rt5651->pdata.dmic_en)
1867 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
1868 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1869
1870 rt5651->hp_mute = 1;
1871
1872 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
1873 rt5651_dai, ARRAY_SIZE(rt5651_dai));
1874
1875 return ret;
1876 }
1877
1878 static int rt5651_i2c_remove(struct i2c_client *i2c)
1879 {
1880 snd_soc_unregister_codec(&i2c->dev);
1881
1882 return 0;
1883 }
1884
1885 struct i2c_driver rt5651_i2c_driver = {
1886 .driver = {
1887 .name = "rt5651",
1888 .owner = THIS_MODULE,
1889 },
1890 .probe = rt5651_i2c_probe,
1891 .remove = rt5651_i2c_remove,
1892 .id_table = rt5651_i2c_id,
1893 };
1894 module_i2c_driver(rt5651_i2c_driver);
1895
1896 MODULE_DESCRIPTION("ASoC RT5651 driver");
1897 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1898 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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