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Merge branch 'for-4.1/sensor-hub' into for-linus
[deliverable/linux.git] / sound / soc / codecs / rt5677.c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "rl6231.h"
34 #include "rt5677.h"
35 #include "rt5677-spi.h"
36
37 #define RT5677_DEVICE_ID 0x6327
38
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
41
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44 static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55 };
56
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
65 };
66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
67
68 static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
177 {RT5677_ASRC_12 , 0x0018},
178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
272 };
273
274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
275 {
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
281 return true;
282 }
283 }
284
285 switch (reg) {
286 case RT5677_RESET:
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320 }
321
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323 {
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541 }
542
543 /**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
554 {
555 struct snd_soc_codec *codec = rt5677->codec;
556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595 err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599 }
600
601 /**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
606 *
607 *
608 * Returns 0 for success or negative error code.
609 */
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
612 {
613 struct snd_soc_codec *codec = rt5677->codec;
614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
643
644 err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648 }
649
650 /**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
661 {
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
663 value, 0x0001);
664 }
665
666 /**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
671 *
672 *
673 * Returns 0 for success or negative error code.
674 */
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
677 {
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
680
681 *value &= 0xffff;
682
683 return ret;
684 }
685
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
687 {
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
689
690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
696 }
697 }
698
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700 {
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
721 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
722 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
724 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
725 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
726 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
727 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
728 rt5677_set_dsp_mode(codec, true);
729
730 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
731 codec->dev);
732 if (ret == 0) {
733 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
734 release_firmware(rt5677->fw1);
735 }
736
737 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
738 codec->dev);
739 if (ret == 0) {
740 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
741 release_firmware(rt5677->fw2);
742 }
743
744 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
745
746 regcache_cache_bypass(rt5677->regmap, false);
747 regcache_cache_only(rt5677->regmap, true);
748 } else if (!on && activity) {
749 activity = false;
750
751 regcache_cache_only(rt5677->regmap, false);
752 regcache_cache_bypass(rt5677->regmap, true);
753
754 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
755 rt5677_set_dsp_mode(codec, false);
756 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
757
758 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
759
760 regcache_cache_bypass(rt5677->regmap, false);
761 regcache_mark_dirty(rt5677->regmap);
762 regcache_sync(rt5677->regmap);
763 }
764
765 return 0;
766 }
767
768 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
769 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
770 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
771 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
772 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
773 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
774
775 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
776 static unsigned int bst_tlv[] = {
777 TLV_DB_RANGE_HEAD(7),
778 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
779 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
780 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
781 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
782 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
783 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
784 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
785 };
786
787 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
788 struct snd_ctl_elem_value *ucontrol)
789 {
790 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
791 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
792
793 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
794
795 return 0;
796 }
797
798 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
800 {
801 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
802 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
803 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
804
805 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
806
807 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
808 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
809
810 return 0;
811 }
812
813 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
814 /* OUTPUT Control */
815 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
816 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
817 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
818 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
819 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
820 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
821
822 /* DAC Digital Volume */
823 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
824 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
825 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
826 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
827 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
828 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
829 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
830 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
831
832 /* IN1/IN2 Control */
833 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
834 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
835
836 /* ADC Digital Volume Control */
837 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
838 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
839 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
840 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
841 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
842 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
843 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
844 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
845 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
846 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
847
848 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
849 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
850 adc_vol_tlv),
851 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
852 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
853 adc_vol_tlv),
854 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
855 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
856 adc_vol_tlv),
857 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
858 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
859 adc_vol_tlv),
860 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
861 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
862 adc_vol_tlv),
863
864 /* Sidetone Control */
865 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
866 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
867
868 /* ADC Boost Volume Control */
869 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
870 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
871 adc_bst_tlv),
872 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
873 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
874 adc_bst_tlv),
875 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
876 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
877 adc_bst_tlv),
878 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
879 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
880 adc_bst_tlv),
881 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
882 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
883 adc_bst_tlv),
884
885 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
886 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
887 };
888
889 /**
890 * set_dmic_clk - Set parameter of dmic.
891 *
892 * @w: DAPM widget.
893 * @kcontrol: The kcontrol of this widget.
894 * @event: Event id.
895 *
896 * Choose dmic clock between 1MHz and 3MHz.
897 * It is better for clock to approximate 3MHz.
898 */
899 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
900 struct snd_kcontrol *kcontrol, int event)
901 {
902 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
903 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
904 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
905
906 if (idx < 0)
907 dev_err(codec->dev, "Failed to set DMIC clock\n");
908 else
909 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
910 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
911 return idx;
912 }
913
914 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
915 struct snd_soc_dapm_widget *sink)
916 {
917 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
918 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
919 unsigned int val;
920
921 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
922 val &= RT5677_SCLK_SRC_MASK;
923 if (val == RT5677_SCLK_SRC_PLL1)
924 return 1;
925 else
926 return 0;
927 }
928
929 static int is_using_asrc(struct snd_soc_dapm_widget *source,
930 struct snd_soc_dapm_widget *sink)
931 {
932 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
933 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
934 unsigned int reg, shift, val;
935
936 if (source->reg == RT5677_ASRC_1) {
937 switch (source->shift) {
938 case 12:
939 reg = RT5677_ASRC_4;
940 shift = 0;
941 break;
942 case 13:
943 reg = RT5677_ASRC_4;
944 shift = 4;
945 break;
946 case 14:
947 reg = RT5677_ASRC_4;
948 shift = 8;
949 break;
950 case 15:
951 reg = RT5677_ASRC_4;
952 shift = 12;
953 break;
954 default:
955 return 0;
956 }
957 } else {
958 switch (source->shift) {
959 case 0:
960 reg = RT5677_ASRC_6;
961 shift = 8;
962 break;
963 case 1:
964 reg = RT5677_ASRC_6;
965 shift = 12;
966 break;
967 case 2:
968 reg = RT5677_ASRC_5;
969 shift = 0;
970 break;
971 case 3:
972 reg = RT5677_ASRC_5;
973 shift = 4;
974 break;
975 case 4:
976 reg = RT5677_ASRC_5;
977 shift = 8;
978 break;
979 case 5:
980 reg = RT5677_ASRC_5;
981 shift = 12;
982 break;
983 case 12:
984 reg = RT5677_ASRC_3;
985 shift = 0;
986 break;
987 case 13:
988 reg = RT5677_ASRC_3;
989 shift = 4;
990 break;
991 case 14:
992 reg = RT5677_ASRC_3;
993 shift = 12;
994 break;
995 default:
996 return 0;
997 }
998 }
999
1000 regmap_read(rt5677->regmap, reg, &val);
1001 val = (val >> shift) & 0xf;
1002
1003 switch (val) {
1004 case 1 ... 6:
1005 return 1;
1006 default:
1007 return 0;
1008 }
1009
1010 }
1011
1012 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1013 struct snd_soc_dapm_widget *sink)
1014 {
1015 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1016 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1017
1018 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1019 return 1;
1020
1021 return 0;
1022 }
1023
1024 /* Digital Mixer */
1025 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1026 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1027 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1028 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1029 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1030 };
1031
1032 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1033 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1034 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1035 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1036 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1037 };
1038
1039 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1040 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1041 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1042 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1043 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1044 };
1045
1046 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1047 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1048 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1049 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1050 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1051 };
1052
1053 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1054 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1055 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1056 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1057 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1058 };
1059
1060 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1061 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1062 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1064 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1065 };
1066
1067 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1068 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1069 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1071 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1072 };
1073
1074 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1075 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1076 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1077 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1078 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1079 };
1080
1081 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1082 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1083 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1084 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1085 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1086 };
1087
1088 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1089 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1090 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1091 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1092 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1093 };
1094
1095 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1096 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1097 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1098 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1099 RT5677_M_DAC1_L_SFT, 1, 1),
1100 };
1101
1102 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1103 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1104 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1106 RT5677_M_DAC1_R_SFT, 1, 1),
1107 };
1108
1109 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1110 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1111 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1112 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1113 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1115 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1117 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1118 };
1119
1120 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1121 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1122 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1123 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1124 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1126 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1128 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1129 };
1130
1131 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1132 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1133 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1134 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1135 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1137 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1139 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1140 };
1141
1142 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1143 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1144 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1145 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1146 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1147 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1148 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1149 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1150 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1151 };
1152
1153 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1154 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1155 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1157 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1159 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1161 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1162 };
1163
1164 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1165 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1166 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1167 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1168 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1170 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1172 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1173 };
1174
1175 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1176 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1177 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1178 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1179 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1180 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1181 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1183 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1184 };
1185
1186 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1187 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1188 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1189 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1190 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1192 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1194 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1195 };
1196
1197 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1198 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1199 RT5677_DSP_IB_01_H_SFT, 1, 1),
1200 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1201 RT5677_DSP_IB_23_H_SFT, 1, 1),
1202 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1203 RT5677_DSP_IB_45_H_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1205 RT5677_DSP_IB_6_H_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1207 RT5677_DSP_IB_7_H_SFT, 1, 1),
1208 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1209 RT5677_DSP_IB_8_H_SFT, 1, 1),
1210 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1211 RT5677_DSP_IB_9_H_SFT, 1, 1),
1212 };
1213
1214 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1215 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1216 RT5677_DSP_IB_01_L_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1218 RT5677_DSP_IB_23_L_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1220 RT5677_DSP_IB_45_L_SFT, 1, 1),
1221 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1222 RT5677_DSP_IB_6_L_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1224 RT5677_DSP_IB_7_L_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1226 RT5677_DSP_IB_8_L_SFT, 1, 1),
1227 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1228 RT5677_DSP_IB_9_L_SFT, 1, 1),
1229 };
1230
1231 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1232 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1233 RT5677_DSP_IB_01_H_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1235 RT5677_DSP_IB_23_H_SFT, 1, 1),
1236 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1237 RT5677_DSP_IB_45_H_SFT, 1, 1),
1238 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1239 RT5677_DSP_IB_6_H_SFT, 1, 1),
1240 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1241 RT5677_DSP_IB_7_H_SFT, 1, 1),
1242 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1243 RT5677_DSP_IB_8_H_SFT, 1, 1),
1244 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1245 RT5677_DSP_IB_9_H_SFT, 1, 1),
1246 };
1247
1248 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1249 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1250 RT5677_DSP_IB_01_L_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1252 RT5677_DSP_IB_23_L_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1254 RT5677_DSP_IB_45_L_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1256 RT5677_DSP_IB_6_L_SFT, 1, 1),
1257 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1258 RT5677_DSP_IB_7_L_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1260 RT5677_DSP_IB_8_L_SFT, 1, 1),
1261 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1262 RT5677_DSP_IB_9_L_SFT, 1, 1),
1263 };
1264
1265 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1266 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1267 RT5677_DSP_IB_01_H_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1269 RT5677_DSP_IB_23_H_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1271 RT5677_DSP_IB_45_H_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1273 RT5677_DSP_IB_6_H_SFT, 1, 1),
1274 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1275 RT5677_DSP_IB_7_H_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1277 RT5677_DSP_IB_8_H_SFT, 1, 1),
1278 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1279 RT5677_DSP_IB_9_H_SFT, 1, 1),
1280 };
1281
1282 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1283 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1284 RT5677_DSP_IB_01_L_SFT, 1, 1),
1285 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1286 RT5677_DSP_IB_23_L_SFT, 1, 1),
1287 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1288 RT5677_DSP_IB_45_L_SFT, 1, 1),
1289 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1290 RT5677_DSP_IB_6_L_SFT, 1, 1),
1291 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1292 RT5677_DSP_IB_7_L_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1294 RT5677_DSP_IB_8_L_SFT, 1, 1),
1295 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1296 RT5677_DSP_IB_9_L_SFT, 1, 1),
1297 };
1298
1299
1300 /* Mux */
1301 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1302 static const char * const rt5677_dac1_src[] = {
1303 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1304 "OB 01"
1305 };
1306
1307 static SOC_ENUM_SINGLE_DECL(
1308 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1309 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1310
1311 static const struct snd_kcontrol_new rt5677_dac1_mux =
1312 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1313
1314 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1315 static const char * const rt5677_adda1_src[] = {
1316 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1317 };
1318
1319 static SOC_ENUM_SINGLE_DECL(
1320 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1321 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1322
1323 static const struct snd_kcontrol_new rt5677_adda1_mux =
1324 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1325
1326
1327 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1328 static const char * const rt5677_dac2l_src[] = {
1329 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1330 "OB 2",
1331 };
1332
1333 static SOC_ENUM_SINGLE_DECL(
1334 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1335 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1336
1337 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1338 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1339
1340 static const char * const rt5677_dac2r_src[] = {
1341 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1342 "OB 3", "Haptic Generator", "VAD ADC"
1343 };
1344
1345 static SOC_ENUM_SINGLE_DECL(
1346 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1347 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1348
1349 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1350 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1351
1352 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1353 static const char * const rt5677_dac3l_src[] = {
1354 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1355 "SLB DAC 4", "OB 4"
1356 };
1357
1358 static SOC_ENUM_SINGLE_DECL(
1359 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1360 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1361
1362 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1363 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1364
1365 static const char * const rt5677_dac3r_src[] = {
1366 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1367 "SLB DAC 5", "OB 5"
1368 };
1369
1370 static SOC_ENUM_SINGLE_DECL(
1371 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1372 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1373
1374 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1375 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1376
1377 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1378 static const char * const rt5677_dac4l_src[] = {
1379 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1380 "SLB DAC 6", "OB 6"
1381 };
1382
1383 static SOC_ENUM_SINGLE_DECL(
1384 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1385 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1386
1387 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1388 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1389
1390 static const char * const rt5677_dac4r_src[] = {
1391 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1392 "SLB DAC 7", "OB 7"
1393 };
1394
1395 static SOC_ENUM_SINGLE_DECL(
1396 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1397 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1398
1399 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1400 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1401
1402 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1403 static const char * const rt5677_iob_bypass_src[] = {
1404 "Bypass", "Pass SRC"
1405 };
1406
1407 static SOC_ENUM_SINGLE_DECL(
1408 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1409 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1410
1411 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1412 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1413
1414 static SOC_ENUM_SINGLE_DECL(
1415 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1416 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1417
1418 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1419 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1420
1421 static SOC_ENUM_SINGLE_DECL(
1422 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1423 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1424
1425 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1426 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1427
1428 static SOC_ENUM_SINGLE_DECL(
1429 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1430 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1431
1432 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1433 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1434
1435 static SOC_ENUM_SINGLE_DECL(
1436 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1437 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1438
1439 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1440 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1441
1442 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1443 static const char * const rt5677_stereo_adc2_src[] = {
1444 "DD MIX1", "DMIC", "Stereo DAC MIX"
1445 };
1446
1447 static SOC_ENUM_SINGLE_DECL(
1448 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1449 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1450
1451 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1452 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1453
1454 static SOC_ENUM_SINGLE_DECL(
1455 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1456 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1457
1458 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1459 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1460
1461 static SOC_ENUM_SINGLE_DECL(
1462 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1463 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1464
1465 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1466 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1467
1468 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1469 static const char * const rt5677_dmic_src[] = {
1470 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1471 };
1472
1473 static SOC_ENUM_SINGLE_DECL(
1474 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1475 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1476
1477 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1478 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1479
1480 static SOC_ENUM_SINGLE_DECL(
1481 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1482 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1483
1484 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1485 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1486
1487 static SOC_ENUM_SINGLE_DECL(
1488 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1489 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1490
1491 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1492 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1493
1494 static SOC_ENUM_SINGLE_DECL(
1495 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1496 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1497
1498 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1499 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1500
1501 static SOC_ENUM_SINGLE_DECL(
1502 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1503 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1504
1505 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1506 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1507
1508 static SOC_ENUM_SINGLE_DECL(
1509 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1510 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1511
1512 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1513 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1514
1515 /* Stereo2 ADC Source */ /* MX-26 [0] */
1516 static const char * const rt5677_stereo2_adc_lr_src[] = {
1517 "L", "LR"
1518 };
1519
1520 static SOC_ENUM_SINGLE_DECL(
1521 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1522 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1523
1524 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1525 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1526
1527 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1528 static const char * const rt5677_stereo_adc1_src[] = {
1529 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1530 };
1531
1532 static SOC_ENUM_SINGLE_DECL(
1533 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1534 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1535
1536 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1537 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1538
1539 static SOC_ENUM_SINGLE_DECL(
1540 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1541 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1542
1543 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1544 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1545
1546 static SOC_ENUM_SINGLE_DECL(
1547 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1548 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1549
1550 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1551 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1552
1553 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1554 static const char * const rt5677_mono_adc2_l_src[] = {
1555 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1556 };
1557
1558 static SOC_ENUM_SINGLE_DECL(
1559 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1560 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1561
1562 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1563 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1564
1565 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1566 static const char * const rt5677_mono_adc1_l_src[] = {
1567 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1568 };
1569
1570 static SOC_ENUM_SINGLE_DECL(
1571 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1572 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1573
1574 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1575 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1576
1577 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1578 static const char * const rt5677_mono_adc2_r_src[] = {
1579 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1580 };
1581
1582 static SOC_ENUM_SINGLE_DECL(
1583 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1584 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1585
1586 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1587 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1588
1589 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1590 static const char * const rt5677_mono_adc1_r_src[] = {
1591 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1592 };
1593
1594 static SOC_ENUM_SINGLE_DECL(
1595 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1596 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1597
1598 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1599 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1600
1601 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1602 static const char * const rt5677_stereo4_adc2_src[] = {
1603 "DD MIX1", "DMIC", "DD MIX2"
1604 };
1605
1606 static SOC_ENUM_SINGLE_DECL(
1607 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1608 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1609
1610 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1611 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1612
1613
1614 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1615 static const char * const rt5677_stereo4_adc1_src[] = {
1616 "DD MIX1", "ADC1/2", "DD MIX2"
1617 };
1618
1619 static SOC_ENUM_SINGLE_DECL(
1620 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1621 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1622
1623 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1624 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1625
1626 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1627 static const char * const rt5677_inbound01_src[] = {
1628 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1629 "VAD ADC/DAC1 FS"
1630 };
1631
1632 static SOC_ENUM_SINGLE_DECL(
1633 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1634 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1635
1636 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1637 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1638
1639 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1640 static const char * const rt5677_inbound23_src[] = {
1641 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1642 "DAC1 FS", "IF4 DAC"
1643 };
1644
1645 static SOC_ENUM_SINGLE_DECL(
1646 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1647 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1648
1649 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1650 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1651
1652 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1653 static const char * const rt5677_inbound45_src[] = {
1654 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1655 "IF3 DAC"
1656 };
1657
1658 static SOC_ENUM_SINGLE_DECL(
1659 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1660 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1661
1662 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1663 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1664
1665 /* InBound6 Source */ /* MX-A3 [2:0] */
1666 static const char * const rt5677_inbound6_src[] = {
1667 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1668 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1669 };
1670
1671 static SOC_ENUM_SINGLE_DECL(
1672 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1673 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1674
1675 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1676 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1677
1678 /* InBound7 Source */ /* MX-A4 [14:12] */
1679 static const char * const rt5677_inbound7_src[] = {
1680 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1681 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1682 };
1683
1684 static SOC_ENUM_SINGLE_DECL(
1685 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1686 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1687
1688 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1689 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1690
1691 /* InBound8 Source */ /* MX-A4 [10:8] */
1692 static const char * const rt5677_inbound8_src[] = {
1693 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1694 "MONO ADC MIX L", "DACL1 FS"
1695 };
1696
1697 static SOC_ENUM_SINGLE_DECL(
1698 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1699 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1700
1701 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1702 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1703
1704 /* InBound9 Source */ /* MX-A4 [6:4] */
1705 static const char * const rt5677_inbound9_src[] = {
1706 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1707 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1708 };
1709
1710 static SOC_ENUM_SINGLE_DECL(
1711 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1712 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1713
1714 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1715 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1716
1717 /* VAD Source */ /* MX-9F [6:4] */
1718 static const char * const rt5677_vad_src[] = {
1719 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1720 "STO3 ADC MIX L"
1721 };
1722
1723 static SOC_ENUM_SINGLE_DECL(
1724 rt5677_vad_enum, RT5677_VAD_CTRL4,
1725 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1726
1727 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1728 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1729
1730 /* Sidetone Source */ /* MX-13 [11:9] */
1731 static const char * const rt5677_sidetone_src[] = {
1732 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1733 };
1734
1735 static SOC_ENUM_SINGLE_DECL(
1736 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1737 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1738
1739 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1740 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1741
1742 /* DAC1/2 Source */ /* MX-15 [1:0] */
1743 static const char * const rt5677_dac12_src[] = {
1744 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1745 };
1746
1747 static SOC_ENUM_SINGLE_DECL(
1748 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1749 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1750
1751 static const struct snd_kcontrol_new rt5677_dac12_mux =
1752 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1753
1754 /* DAC3 Source */ /* MX-15 [5:4] */
1755 static const char * const rt5677_dac3_src[] = {
1756 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1757 };
1758
1759 static SOC_ENUM_SINGLE_DECL(
1760 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1761 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1762
1763 static const struct snd_kcontrol_new rt5677_dac3_mux =
1764 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1765
1766 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1767 static const char * const rt5677_pdm_src[] = {
1768 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1769 };
1770
1771 static SOC_ENUM_SINGLE_DECL(
1772 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1773 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1774
1775 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1776 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1777
1778 static SOC_ENUM_SINGLE_DECL(
1779 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1780 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1781
1782 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1783 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1784
1785 static SOC_ENUM_SINGLE_DECL(
1786 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1787 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1788
1789 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1790 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1791
1792 static SOC_ENUM_SINGLE_DECL(
1793 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1794 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1795
1796 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1797 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1798
1799 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1800 static const char * const rt5677_if12_adc1_src[] = {
1801 "STO1 ADC MIX", "OB01", "VAD ADC"
1802 };
1803
1804 static SOC_ENUM_SINGLE_DECL(
1805 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1806 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1807
1808 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1809 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1810
1811 static SOC_ENUM_SINGLE_DECL(
1812 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1813 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1814
1815 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1816 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1817
1818 static SOC_ENUM_SINGLE_DECL(
1819 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1820 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1821
1822 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1823 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1824
1825 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1826 static const char * const rt5677_if12_adc2_src[] = {
1827 "STO2 ADC MIX", "OB23"
1828 };
1829
1830 static SOC_ENUM_SINGLE_DECL(
1831 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1832 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1833
1834 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1835 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1836
1837 static SOC_ENUM_SINGLE_DECL(
1838 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1839 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1840
1841 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1842 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1843
1844 static SOC_ENUM_SINGLE_DECL(
1845 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1846 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1847
1848 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1849 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1850
1851 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1852 static const char * const rt5677_if12_adc3_src[] = {
1853 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1854 };
1855
1856 static SOC_ENUM_SINGLE_DECL(
1857 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1858 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1859
1860 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1861 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1862
1863 static SOC_ENUM_SINGLE_DECL(
1864 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1865 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1866
1867 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1868 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1869
1870 static SOC_ENUM_SINGLE_DECL(
1871 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1872 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1873
1874 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1875 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1876
1877 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1878 static const char * const rt5677_if12_adc4_src[] = {
1879 "STO4 ADC MIX", "OB67", "OB01"
1880 };
1881
1882 static SOC_ENUM_SINGLE_DECL(
1883 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1884 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1885
1886 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1887 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1888
1889 static SOC_ENUM_SINGLE_DECL(
1890 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1891 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1892
1893 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1894 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1895
1896 static SOC_ENUM_SINGLE_DECL(
1897 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1898 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1899
1900 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1901 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1902
1903 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1904 static const char * const rt5677_if34_adc_src[] = {
1905 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1906 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1907 };
1908
1909 static SOC_ENUM_SINGLE_DECL(
1910 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1911 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1912
1913 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1914 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1915
1916 static SOC_ENUM_SINGLE_DECL(
1917 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1918 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1919
1920 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1921 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1922
1923 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1924 static const char * const rt5677_if12_adc_swap_src[] = {
1925 "L/R", "R/L", "L/L", "R/R"
1926 };
1927
1928 static SOC_ENUM_SINGLE_DECL(
1929 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1930 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1931
1932 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1933 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1934
1935 static SOC_ENUM_SINGLE_DECL(
1936 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1937 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1938
1939 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1940 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1941
1942 static SOC_ENUM_SINGLE_DECL(
1943 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1944 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1945
1946 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1947 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1948
1949 static SOC_ENUM_SINGLE_DECL(
1950 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1951 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1952
1953 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1954 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1955
1956 static SOC_ENUM_SINGLE_DECL(
1957 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1958 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1959
1960 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1961 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1962
1963 static SOC_ENUM_SINGLE_DECL(
1964 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1965 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1966
1967 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1968 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1969
1970 static SOC_ENUM_SINGLE_DECL(
1971 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1972 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1973
1974 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1975 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1976
1977 static SOC_ENUM_SINGLE_DECL(
1978 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1979 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1980
1981 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1982 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1983
1984 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1985 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1986 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1987 "3/1/2/4", "3/4/1/2"
1988 };
1989
1990 static SOC_ENUM_SINGLE_DECL(
1991 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1992 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1993
1994 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1995 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1996
1997 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1998 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1999 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2000 "2/3/1/4", "3/4/1/2"
2001 };
2002
2003 static SOC_ENUM_SINGLE_DECL(
2004 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2005 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2006
2007 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2008 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2009
2010 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2011 MX-3F[14:12][10:8][6:4][2:0]
2012 MX-43[14:12][10:8][6:4][2:0]
2013 MX-44[14:12][10:8][6:4][2:0] */
2014 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2015 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2016 };
2017
2018 static SOC_ENUM_SINGLE_DECL(
2019 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2020 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2021
2022 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2023 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2024
2025 static SOC_ENUM_SINGLE_DECL(
2026 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2027 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2028
2029 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2030 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2031
2032 static SOC_ENUM_SINGLE_DECL(
2033 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2034 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2035
2036 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2037 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2038
2039 static SOC_ENUM_SINGLE_DECL(
2040 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2041 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2042
2043 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2044 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2045
2046 static SOC_ENUM_SINGLE_DECL(
2047 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2048 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2049
2050 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2051 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2052
2053 static SOC_ENUM_SINGLE_DECL(
2054 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2055 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2056
2057 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2058 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2059
2060 static SOC_ENUM_SINGLE_DECL(
2061 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2062 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2063
2064 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2065 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2066
2067 static SOC_ENUM_SINGLE_DECL(
2068 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2069 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2070
2071 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2072 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2073
2074 static SOC_ENUM_SINGLE_DECL(
2075 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2076 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2077
2078 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2079 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2080
2081 static SOC_ENUM_SINGLE_DECL(
2082 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2083 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2084
2085 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2086 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2087
2088 static SOC_ENUM_SINGLE_DECL(
2089 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2090 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2091
2092 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2093 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2094
2095 static SOC_ENUM_SINGLE_DECL(
2096 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2097 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2098
2099 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2100 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2101
2102 static SOC_ENUM_SINGLE_DECL(
2103 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2104 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2105
2106 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2107 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2108
2109 static SOC_ENUM_SINGLE_DECL(
2110 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2111 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2112
2113 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2114 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2115
2116 static SOC_ENUM_SINGLE_DECL(
2117 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2118 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2119
2120 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2121 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2122
2123 static SOC_ENUM_SINGLE_DECL(
2124 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2125 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2126
2127 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2128 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2129
2130 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2131 struct snd_kcontrol *kcontrol, int event)
2132 {
2133 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2134 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2135
2136 switch (event) {
2137 case SND_SOC_DAPM_POST_PMU:
2138 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2139 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2140 break;
2141
2142 case SND_SOC_DAPM_PRE_PMD:
2143 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2144 RT5677_PWR_BST1_P, 0);
2145 break;
2146
2147 default:
2148 return 0;
2149 }
2150
2151 return 0;
2152 }
2153
2154 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2155 struct snd_kcontrol *kcontrol, int event)
2156 {
2157 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2158 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2159
2160 switch (event) {
2161 case SND_SOC_DAPM_POST_PMU:
2162 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2163 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2164 break;
2165
2166 case SND_SOC_DAPM_PRE_PMD:
2167 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2168 RT5677_PWR_BST2_P, 0);
2169 break;
2170
2171 default:
2172 return 0;
2173 }
2174
2175 return 0;
2176 }
2177
2178 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2179 struct snd_kcontrol *kcontrol, int event)
2180 {
2181 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2182 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2183
2184 switch (event) {
2185 case SND_SOC_DAPM_PRE_PMU:
2186 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2187 break;
2188
2189 case SND_SOC_DAPM_POST_PMU:
2190 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2191 break;
2192
2193 default:
2194 return 0;
2195 }
2196
2197 return 0;
2198 }
2199
2200 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2201 struct snd_kcontrol *kcontrol, int event)
2202 {
2203 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2204 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2205
2206 switch (event) {
2207 case SND_SOC_DAPM_PRE_PMU:
2208 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2209 break;
2210
2211 case SND_SOC_DAPM_POST_PMU:
2212 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2213 break;
2214
2215 default:
2216 return 0;
2217 }
2218
2219 return 0;
2220 }
2221
2222 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2223 struct snd_kcontrol *kcontrol, int event)
2224 {
2225 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2226 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2227
2228 switch (event) {
2229 case SND_SOC_DAPM_POST_PMU:
2230 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2231 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2232 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2233 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2234 break;
2235
2236 case SND_SOC_DAPM_PRE_PMD:
2237 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2238 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2239 RT5677_PWR_CLK_MB, 0);
2240 break;
2241
2242 default:
2243 return 0;
2244 }
2245
2246 return 0;
2247 }
2248
2249 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2250 struct snd_kcontrol *kcontrol, int event)
2251 {
2252 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2253 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2254 unsigned int value;
2255
2256 switch (event) {
2257 case SND_SOC_DAPM_PRE_PMU:
2258 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2259 if (value & RT5677_IF1_ADC_CTRL_MASK)
2260 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2261 RT5677_IF1_ADC_MODE_MASK,
2262 RT5677_IF1_ADC_MODE_TDM);
2263 break;
2264
2265 default:
2266 return 0;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2273 struct snd_kcontrol *kcontrol, int event)
2274 {
2275 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2276 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2277 unsigned int value;
2278
2279 switch (event) {
2280 case SND_SOC_DAPM_PRE_PMU:
2281 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2282 if (value & RT5677_IF2_ADC_CTRL_MASK)
2283 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2284 RT5677_IF2_ADC_MODE_MASK,
2285 RT5677_IF2_ADC_MODE_TDM);
2286 break;
2287
2288 default:
2289 return 0;
2290 }
2291
2292 return 0;
2293 }
2294
2295 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2296 struct snd_kcontrol *kcontrol, int event)
2297 {
2298 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2299 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2300
2301 switch (event) {
2302 case SND_SOC_DAPM_POST_PMU:
2303 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2304 !rt5677->is_vref_slow) {
2305 mdelay(20);
2306 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2307 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2308 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2309 rt5677->is_vref_slow = true;
2310 }
2311 break;
2312
2313 default:
2314 return 0;
2315 }
2316
2317 return 0;
2318 }
2319
2320 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2321 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2322 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2323 SND_SOC_DAPM_POST_PMU),
2324 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2325 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2326 SND_SOC_DAPM_POST_PMU),
2327
2328 /* ASRC */
2329 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2330 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2331 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2332 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2333 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2334 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2335 0),
2336 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2337 0),
2338 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2339 0),
2340 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2341 0),
2342 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2343 0),
2344 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2345 0),
2346 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2347 0),
2348 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2349 0),
2350 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2351 0),
2352 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2353 0),
2354 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2355 0),
2356 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2357 0),
2358 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2359 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2360 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2361 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2362 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2363 0),
2364 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2365 0),
2366
2367 /* Input Side */
2368 /* micbias */
2369 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2370 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2371 SND_SOC_DAPM_POST_PMU),
2372
2373 /* Input Lines */
2374 SND_SOC_DAPM_INPUT("DMIC L1"),
2375 SND_SOC_DAPM_INPUT("DMIC R1"),
2376 SND_SOC_DAPM_INPUT("DMIC L2"),
2377 SND_SOC_DAPM_INPUT("DMIC R2"),
2378 SND_SOC_DAPM_INPUT("DMIC L3"),
2379 SND_SOC_DAPM_INPUT("DMIC R3"),
2380 SND_SOC_DAPM_INPUT("DMIC L4"),
2381 SND_SOC_DAPM_INPUT("DMIC R4"),
2382
2383 SND_SOC_DAPM_INPUT("IN1P"),
2384 SND_SOC_DAPM_INPUT("IN1N"),
2385 SND_SOC_DAPM_INPUT("IN2P"),
2386 SND_SOC_DAPM_INPUT("IN2N"),
2387
2388 SND_SOC_DAPM_INPUT("Haptic Generator"),
2389
2390 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2391 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2392 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2393 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2394
2395 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2396 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2397 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2398 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2399 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2400 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2401 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2402 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2403
2404 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2405 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2406
2407 /* Boost */
2408 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2409 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2410 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2411 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2412 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2413 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2414
2415 /* ADCs */
2416 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2417 0, 0),
2418 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2419 0, 0),
2420 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2421
2422 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2423 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2424 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2425 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2426 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2427 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2428 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2429 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2430
2431 /* ADC Mux */
2432 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2433 &rt5677_sto1_dmic_mux),
2434 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2435 &rt5677_sto1_adc1_mux),
2436 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2437 &rt5677_sto1_adc2_mux),
2438 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2439 &rt5677_sto2_dmic_mux),
2440 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2441 &rt5677_sto2_adc1_mux),
2442 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2443 &rt5677_sto2_adc2_mux),
2444 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2445 &rt5677_sto2_adc_lr_mux),
2446 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2447 &rt5677_sto3_dmic_mux),
2448 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2449 &rt5677_sto3_adc1_mux),
2450 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2451 &rt5677_sto3_adc2_mux),
2452 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2453 &rt5677_sto4_dmic_mux),
2454 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2455 &rt5677_sto4_adc1_mux),
2456 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2457 &rt5677_sto4_adc2_mux),
2458 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2459 &rt5677_mono_dmic_l_mux),
2460 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2461 &rt5677_mono_dmic_r_mux),
2462 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2463 &rt5677_mono_adc2_l_mux),
2464 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2465 &rt5677_mono_adc1_l_mux),
2466 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2467 &rt5677_mono_adc1_r_mux),
2468 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2469 &rt5677_mono_adc2_r_mux),
2470
2471 /* ADC Mixer */
2472 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2473 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2474 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2475 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2476 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2477 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2478 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2479 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2480 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2481 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2482 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2483 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2484 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2485 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2486 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2487 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2488 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2489 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2490 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2491 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2492 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2493 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2494 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2495 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2496 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2497 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2498 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2499 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2500 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2501 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2502 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2503 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2504
2505 /* ADC PGA */
2506 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2507 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2508 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2509 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2510 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2511 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2512 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2513 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2514 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2515 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2516 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2517 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2518 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2519 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2520 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2521 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2522
2523 /* DSP */
2524 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2525 &rt5677_ib9_src_mux),
2526 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2527 &rt5677_ib8_src_mux),
2528 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2529 &rt5677_ib7_src_mux),
2530 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2531 &rt5677_ib6_src_mux),
2532 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2533 &rt5677_ib45_src_mux),
2534 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2535 &rt5677_ib23_src_mux),
2536 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2537 &rt5677_ib01_src_mux),
2538 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2539 &rt5677_ib45_bypass_src_mux),
2540 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2541 &rt5677_ib23_bypass_src_mux),
2542 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2543 &rt5677_ib01_bypass_src_mux),
2544 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2545 &rt5677_ob23_bypass_src_mux),
2546 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2547 &rt5677_ob01_bypass_src_mux),
2548
2549 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2550 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2551
2552 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2553 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2554 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2555 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2556 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2557 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2558
2559 /* Digital Interface */
2560 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2561 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2562 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2564 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2565 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2566 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2576 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2577 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2578
2579 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2580 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2581 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2583 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2587 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2588 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2597
2598 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2599 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2603 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2606
2607 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2608 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2611 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2612 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2615
2616 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2617 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2618 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2619 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2620 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2621 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2622 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2623 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2624 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2625 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2626 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2627 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2628 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2629 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2630 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2631 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2632 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2633 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2634
2635 /* Digital Interface Select */
2636 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2637 &rt5677_if1_adc1_mux),
2638 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2639 &rt5677_if1_adc2_mux),
2640 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_if1_adc3_mux),
2642 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2643 &rt5677_if1_adc4_mux),
2644 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2645 &rt5677_if1_adc1_swap_mux),
2646 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2647 &rt5677_if1_adc2_swap_mux),
2648 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2649 &rt5677_if1_adc3_swap_mux),
2650 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2651 &rt5677_if1_adc4_swap_mux),
2652 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2653 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2654 SND_SOC_DAPM_PRE_PMU),
2655 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2656 &rt5677_if2_adc1_mux),
2657 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2658 &rt5677_if2_adc2_mux),
2659 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2660 &rt5677_if2_adc3_mux),
2661 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2662 &rt5677_if2_adc4_mux),
2663 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2664 &rt5677_if2_adc1_swap_mux),
2665 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2666 &rt5677_if2_adc2_swap_mux),
2667 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2668 &rt5677_if2_adc3_swap_mux),
2669 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2670 &rt5677_if2_adc4_swap_mux),
2671 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2672 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2673 SND_SOC_DAPM_PRE_PMU),
2674 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2675 &rt5677_if3_adc_mux),
2676 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2677 &rt5677_if4_adc_mux),
2678 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2679 &rt5677_slb_adc1_mux),
2680 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2681 &rt5677_slb_adc2_mux),
2682 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2683 &rt5677_slb_adc3_mux),
2684 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2685 &rt5677_slb_adc4_mux),
2686
2687 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2688 &rt5677_if1_dac0_tdm_sel_mux),
2689 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2690 &rt5677_if1_dac1_tdm_sel_mux),
2691 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2692 &rt5677_if1_dac2_tdm_sel_mux),
2693 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2694 &rt5677_if1_dac3_tdm_sel_mux),
2695 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2696 &rt5677_if1_dac4_tdm_sel_mux),
2697 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2698 &rt5677_if1_dac5_tdm_sel_mux),
2699 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2700 &rt5677_if1_dac6_tdm_sel_mux),
2701 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2702 &rt5677_if1_dac7_tdm_sel_mux),
2703
2704 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2705 &rt5677_if2_dac0_tdm_sel_mux),
2706 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2707 &rt5677_if2_dac1_tdm_sel_mux),
2708 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2709 &rt5677_if2_dac2_tdm_sel_mux),
2710 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_if2_dac3_tdm_sel_mux),
2712 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_if2_dac4_tdm_sel_mux),
2714 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_if2_dac5_tdm_sel_mux),
2716 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_if2_dac6_tdm_sel_mux),
2718 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_if2_dac7_tdm_sel_mux),
2720
2721 /* Audio Interface */
2722 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2723 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2724 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2725 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2726 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2727 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2728 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2729 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2730 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2731 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2732
2733 /* Sidetone Mux */
2734 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sidetone_mux),
2736 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2737 RT5677_ST_EN_SFT, 0, NULL, 0),
2738
2739 /* VAD Mux*/
2740 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_vad_src_mux),
2742
2743 /* Tensilica DSP */
2744 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2745 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2746 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2747 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2748 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2749 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2750 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2751 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2752 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2753 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2754 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2755 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2756 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2757
2758 /* Output Side */
2759 /* DAC mixer before sound effect */
2760 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2761 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2762 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2763 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2764 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2765
2766 /* DAC Mux */
2767 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2768 &rt5677_dac1_mux),
2769 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2770 &rt5677_adda1_mux),
2771 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2772 &rt5677_dac12_mux),
2773 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2774 &rt5677_dac3_mux),
2775
2776 /* DAC2 channel Mux */
2777 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2778 &rt5677_dac2_l_mux),
2779 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2780 &rt5677_dac2_r_mux),
2781
2782 /* DAC3 channel Mux */
2783 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2784 &rt5677_dac3_l_mux),
2785 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2786 &rt5677_dac3_r_mux),
2787
2788 /* DAC4 channel Mux */
2789 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2790 &rt5677_dac4_l_mux),
2791 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2792 &rt5677_dac4_r_mux),
2793
2794 /* DAC Mixer */
2795 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2796 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2797 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2798 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2799 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2800 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2801 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2802 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2803 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2804 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2805 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2806 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2807 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2808 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2809
2810 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2811 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2812 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2813 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2814 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2815 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2816 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2817 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2818 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2819 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2820 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2821 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2822 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2823 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2824 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2825 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2826 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2827 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2829 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2830
2831 /* DACs */
2832 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2833 RT5677_PWR_DAC1_BIT, 0),
2834 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2835 RT5677_PWR_DAC2_BIT, 0),
2836 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2837 RT5677_PWR_DAC3_BIT, 0),
2838
2839 /* PDM */
2840 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2841 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2842 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2843 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2844
2845 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2846 1, &rt5677_pdm1_l_mux),
2847 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2848 1, &rt5677_pdm1_r_mux),
2849 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2850 1, &rt5677_pdm2_l_mux),
2851 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2852 1, &rt5677_pdm2_r_mux),
2853
2854 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2855 0, NULL, 0),
2856 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2857 0, NULL, 0),
2858 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2859 0, NULL, 0),
2860
2861 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2862 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2863 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2864 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2865 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2866 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2867
2868 /* Output Lines */
2869 SND_SOC_DAPM_OUTPUT("LOUT1"),
2870 SND_SOC_DAPM_OUTPUT("LOUT2"),
2871 SND_SOC_DAPM_OUTPUT("LOUT3"),
2872 SND_SOC_DAPM_OUTPUT("PDM1L"),
2873 SND_SOC_DAPM_OUTPUT("PDM1R"),
2874 SND_SOC_DAPM_OUTPUT("PDM2L"),
2875 SND_SOC_DAPM_OUTPUT("PDM2R"),
2876
2877 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
2878 };
2879
2880 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2881 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
2882 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
2883 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
2884 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
2885 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
2886 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
2887 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
2888 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
2889 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
2890 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
2891
2892 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2893 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
2894 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
2895 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
2896 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
2897 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
2898 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
2899 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2900 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
2901 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
2902 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
2903 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2904 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2905
2906 { "DMIC1", NULL, "DMIC L1" },
2907 { "DMIC1", NULL, "DMIC R1" },
2908 { "DMIC2", NULL, "DMIC L2" },
2909 { "DMIC2", NULL, "DMIC R2" },
2910 { "DMIC3", NULL, "DMIC L3" },
2911 { "DMIC3", NULL, "DMIC R3" },
2912 { "DMIC4", NULL, "DMIC L4" },
2913 { "DMIC4", NULL, "DMIC R4" },
2914
2915 { "DMIC L1", NULL, "DMIC CLK" },
2916 { "DMIC R1", NULL, "DMIC CLK" },
2917 { "DMIC L2", NULL, "DMIC CLK" },
2918 { "DMIC R2", NULL, "DMIC CLK" },
2919 { "DMIC L3", NULL, "DMIC CLK" },
2920 { "DMIC R3", NULL, "DMIC CLK" },
2921 { "DMIC L4", NULL, "DMIC CLK" },
2922 { "DMIC R4", NULL, "DMIC CLK" },
2923
2924 { "DMIC L1", NULL, "DMIC1 power" },
2925 { "DMIC R1", NULL, "DMIC1 power" },
2926 { "DMIC L3", NULL, "DMIC3 power" },
2927 { "DMIC R3", NULL, "DMIC3 power" },
2928 { "DMIC L4", NULL, "DMIC4 power" },
2929 { "DMIC R4", NULL, "DMIC4 power" },
2930
2931 { "BST1", NULL, "IN1P" },
2932 { "BST1", NULL, "IN1N" },
2933 { "BST2", NULL, "IN2P" },
2934 { "BST2", NULL, "IN2N" },
2935
2936 { "IN1P", NULL, "MICBIAS1" },
2937 { "IN1N", NULL, "MICBIAS1" },
2938 { "IN2P", NULL, "MICBIAS1" },
2939 { "IN2N", NULL, "MICBIAS1" },
2940
2941 { "ADC 1", NULL, "BST1" },
2942 { "ADC 1", NULL, "ADC 1 power" },
2943 { "ADC 1", NULL, "ADC1 clock" },
2944 { "ADC 2", NULL, "BST2" },
2945 { "ADC 2", NULL, "ADC 2 power" },
2946 { "ADC 2", NULL, "ADC2 clock" },
2947
2948 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2949 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2950 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2951 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2952
2953 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2954 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2955 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2956 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2957
2958 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2959 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2960 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2961 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2962
2963 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2964 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2965 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2966 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2967
2968 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2969 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2970 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2971 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2972
2973 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2974 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2975 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2976 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2977
2978 { "ADC 1_2", NULL, "ADC 1" },
2979 { "ADC 1_2", NULL, "ADC 2" },
2980
2981 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2982 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2983 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2984
2985 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2986 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2987 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2988
2989 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2990 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2991 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2992
2993 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2994 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2995 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2996
2997 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2998 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2999 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3000
3001 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3002 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3003 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3004
3005 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3006 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3007 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3008
3009 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3010 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3011 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3012
3013 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3014 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3015 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3016
3017 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3018 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3019 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3020
3021 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3022 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3023 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3024
3025 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3026 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3027 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3028
3029 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3030 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3031 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3032 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3033
3034 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3035 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3036 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3037 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3038 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3039
3040 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3041 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3042
3043 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3044 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3045 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3046 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3047
3048 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3049 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3050
3051 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3052 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3053
3054 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3055 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3056 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3057 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3058 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3059
3060 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3061 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3062
3063 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3064 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3065 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3066 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3067
3068 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3069 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3070 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3071 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3072 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3073
3074 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3075 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3076
3077 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3078 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3079 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3080 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3081
3082 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3083 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3084 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3085 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3086 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3087
3088 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3089 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3090
3091 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3092 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3093 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3094 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3095
3096 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3097 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3098 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3099 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3100
3101 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3102 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3103
3104 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3105 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3106 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3107 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3108 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3109
3110 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3111 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3112 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3113
3114 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3115 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3116
3117 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3118 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3119 { "IF1 ADC3 Mux", "OB45", "OB45" },
3120
3121 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3122 { "IF1 ADC4 Mux", "OB67", "OB67" },
3123 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3124
3125 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3126 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3127 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3128 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3129
3130 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3131 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3132 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3133 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3134
3135 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3136 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3137 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3138 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3139
3140 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3141 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3142 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3143 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3144
3145 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3146 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3147 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3148 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3149
3150 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3151 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3152 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3153 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3154 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3155 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3156 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3157 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3158
3159 { "AIF1TX", NULL, "I2S1" },
3160 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3161
3162 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3163 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3164 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3165
3166 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3167 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3168
3169 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3170 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3171 { "IF2 ADC3 Mux", "OB45", "OB45" },
3172
3173 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3174 { "IF2 ADC4 Mux", "OB67", "OB67" },
3175 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3176
3177 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3178 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3179 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3180 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3181
3182 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3183 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3184 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3185 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3186
3187 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3188 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3189 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3190 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3191
3192 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3193 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3194 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3195 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3196
3197 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3198 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3199 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3200 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3201
3202 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3203 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3204 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3205 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3206 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3207 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3208 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3209 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3210
3211 { "AIF2TX", NULL, "I2S2" },
3212 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3213
3214 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3215 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3216 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3217 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3218 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3219 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3220 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3221 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3222
3223 { "AIF3TX", NULL, "I2S3" },
3224 { "AIF3TX", NULL, "IF3 ADC Mux" },
3225
3226 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3227 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3228 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3229 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3230 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3231 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3232 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3233 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3234
3235 { "AIF4TX", NULL, "I2S4" },
3236 { "AIF4TX", NULL, "IF4 ADC Mux" },
3237
3238 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3239 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3240 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3241
3242 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3243 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3244
3245 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3246 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3247 { "SLB ADC3 Mux", "OB45", "OB45" },
3248
3249 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3250 { "SLB ADC4 Mux", "OB67", "OB67" },
3251 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3252
3253 { "SLBTX", NULL, "SLB" },
3254 { "SLBTX", NULL, "SLB ADC1 Mux" },
3255 { "SLBTX", NULL, "SLB ADC2 Mux" },
3256 { "SLBTX", NULL, "SLB ADC3 Mux" },
3257 { "SLBTX", NULL, "SLB ADC4 Mux" },
3258
3259 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3260 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3261 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3262 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3263 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3264
3265 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3266 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3267
3268 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3269 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3270 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3271 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3272 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3273 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3274
3275 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3276 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3277
3278 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3279 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3280 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3281 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3282 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3283
3284 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3285 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3286
3287 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3288 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3289 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3290 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3291 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3292 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3293 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3294 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3295
3296 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3297 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3298 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3299 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3300 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3301 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3302 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3303 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3304
3305 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3306 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3307 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3308 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3309 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3310 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3311
3312 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3313 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3314 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3315 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3316 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3317 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3318 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3319
3320 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3321 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3322 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3323 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3324 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3325 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3326 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3327
3328 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3329 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3330 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3331 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3332 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3333 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3334 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3335
3336 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3337 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3338 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3339 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3340 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3341 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3342 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3343
3344 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3345 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3346 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3347 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3348 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3349 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3350 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3351
3352 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3353 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3354 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3355 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3356 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3357 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3358 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3359
3360 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3361 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3362 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3363 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3364 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3365 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3366 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3367
3368 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3369 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3370 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3371 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3372
3373 { "OutBound2", NULL, "OB23 Bypass Mux" },
3374 { "OutBound3", NULL, "OB23 Bypass Mux" },
3375 { "OutBound4", NULL, "OB4 MIX" },
3376 { "OutBound5", NULL, "OB5 MIX" },
3377 { "OutBound6", NULL, "OB6 MIX" },
3378 { "OutBound7", NULL, "OB7 MIX" },
3379
3380 { "OB45", NULL, "OutBound4" },
3381 { "OB45", NULL, "OutBound5" },
3382 { "OB67", NULL, "OutBound6" },
3383 { "OB67", NULL, "OutBound7" },
3384
3385 { "IF1 DAC0", NULL, "AIF1RX" },
3386 { "IF1 DAC1", NULL, "AIF1RX" },
3387 { "IF1 DAC2", NULL, "AIF1RX" },
3388 { "IF1 DAC3", NULL, "AIF1RX" },
3389 { "IF1 DAC4", NULL, "AIF1RX" },
3390 { "IF1 DAC5", NULL, "AIF1RX" },
3391 { "IF1 DAC6", NULL, "AIF1RX" },
3392 { "IF1 DAC7", NULL, "AIF1RX" },
3393 { "IF1 DAC0", NULL, "I2S1" },
3394 { "IF1 DAC1", NULL, "I2S1" },
3395 { "IF1 DAC2", NULL, "I2S1" },
3396 { "IF1 DAC3", NULL, "I2S1" },
3397 { "IF1 DAC4", NULL, "I2S1" },
3398 { "IF1 DAC5", NULL, "I2S1" },
3399 { "IF1 DAC6", NULL, "I2S1" },
3400 { "IF1 DAC7", NULL, "I2S1" },
3401
3402 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3403 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3404 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3405 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3406 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3407 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3408 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3409 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3410
3411 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3412 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3413 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3414 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3415 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3416 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3417 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3418 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3419
3420 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3421 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3422 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3423 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3424 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3425 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3426 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3427 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3428
3429 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3430 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3431 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3432 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3433 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3434 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3435 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3436 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3437
3438 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3439 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3440 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3441 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3442 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3443 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3444 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3445 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3446
3447 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3448 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3449 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3450 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3451 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3452 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3453 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3454 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3455
3456 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3457 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3458 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3459 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3460 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3461 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3462 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3463 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3464
3465 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3466 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3467 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3468 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3469 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3470 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3471 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3472 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3473
3474 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3475 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3476 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3477 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3478 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3479 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3480 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3481 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3482
3483 { "IF2 DAC0", NULL, "AIF2RX" },
3484 { "IF2 DAC1", NULL, "AIF2RX" },
3485 { "IF2 DAC2", NULL, "AIF2RX" },
3486 { "IF2 DAC3", NULL, "AIF2RX" },
3487 { "IF2 DAC4", NULL, "AIF2RX" },
3488 { "IF2 DAC5", NULL, "AIF2RX" },
3489 { "IF2 DAC6", NULL, "AIF2RX" },
3490 { "IF2 DAC7", NULL, "AIF2RX" },
3491 { "IF2 DAC0", NULL, "I2S2" },
3492 { "IF2 DAC1", NULL, "I2S2" },
3493 { "IF2 DAC2", NULL, "I2S2" },
3494 { "IF2 DAC3", NULL, "I2S2" },
3495 { "IF2 DAC4", NULL, "I2S2" },
3496 { "IF2 DAC5", NULL, "I2S2" },
3497 { "IF2 DAC6", NULL, "I2S2" },
3498 { "IF2 DAC7", NULL, "I2S2" },
3499
3500 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3501 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3502 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3503 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3504 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3505 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3506 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3507 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3508
3509 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3510 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3511 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3512 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3513 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3514 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3515 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3516 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3517
3518 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3519 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3520 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3521 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3522 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3523 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3524 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3525 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3526
3527 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3528 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3529 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3530 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3531 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3532 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3533 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3534 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3535
3536 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3537 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3538 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3539 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3540 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3541 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3542 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3543 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3544
3545 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3546 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3547 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3548 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3549 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3550 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3551 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3552 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3553
3554 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3555 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3556 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3557 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3558 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3559 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3560 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3561 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3562
3563 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3564 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3565 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3566 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3567 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3568 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3569 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3570 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3571
3572 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3573 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3574 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3575 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3576 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3577 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3578 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3579 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3580
3581 { "IF3 DAC", NULL, "AIF3RX" },
3582 { "IF3 DAC", NULL, "I2S3" },
3583
3584 { "IF4 DAC", NULL, "AIF4RX" },
3585 { "IF4 DAC", NULL, "I2S4" },
3586
3587 { "IF3 DAC L", NULL, "IF3 DAC" },
3588 { "IF3 DAC R", NULL, "IF3 DAC" },
3589
3590 { "IF4 DAC L", NULL, "IF4 DAC" },
3591 { "IF4 DAC R", NULL, "IF4 DAC" },
3592
3593 { "SLB DAC0", NULL, "SLBRX" },
3594 { "SLB DAC1", NULL, "SLBRX" },
3595 { "SLB DAC2", NULL, "SLBRX" },
3596 { "SLB DAC3", NULL, "SLBRX" },
3597 { "SLB DAC4", NULL, "SLBRX" },
3598 { "SLB DAC5", NULL, "SLBRX" },
3599 { "SLB DAC6", NULL, "SLBRX" },
3600 { "SLB DAC7", NULL, "SLBRX" },
3601 { "SLB DAC0", NULL, "SLB" },
3602 { "SLB DAC1", NULL, "SLB" },
3603 { "SLB DAC2", NULL, "SLB" },
3604 { "SLB DAC3", NULL, "SLB" },
3605 { "SLB DAC4", NULL, "SLB" },
3606 { "SLB DAC5", NULL, "SLB" },
3607 { "SLB DAC6", NULL, "SLB" },
3608 { "SLB DAC7", NULL, "SLB" },
3609
3610 { "SLB DAC01", NULL, "SLB DAC0" },
3611 { "SLB DAC01", NULL, "SLB DAC1" },
3612 { "SLB DAC23", NULL, "SLB DAC2" },
3613 { "SLB DAC23", NULL, "SLB DAC3" },
3614 { "SLB DAC45", NULL, "SLB DAC4" },
3615 { "SLB DAC45", NULL, "SLB DAC5" },
3616 { "SLB DAC67", NULL, "SLB DAC6" },
3617 { "SLB DAC67", NULL, "SLB DAC7" },
3618
3619 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3620 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3621 { "ADDA1 Mux", "OB 67", "OB67" },
3622
3623 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3624 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3625 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3626 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3627 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3628 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3629
3630 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3631 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3632 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3633 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3634
3635 { "DAC1 FS", NULL, "DAC1 MIXL" },
3636 { "DAC1 FS", NULL, "DAC1 MIXR" },
3637
3638 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3639 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3640 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3641 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3642 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3643 { "DAC2 L Mux", "OB 2", "OutBound2" },
3644
3645 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3646 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3647 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3648 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3649 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3650 { "DAC2 R Mux", "OB 3", "OutBound3" },
3651 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3652 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3653
3654 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3655 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3656 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3657 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3658 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3659 { "DAC3 L Mux", "OB 4", "OutBound4" },
3660
3661 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3662 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3663 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3664 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3665 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3666 { "DAC3 R Mux", "OB 5", "OutBound5" },
3667
3668 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3669 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3670 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3671 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3672 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3673 { "DAC4 L Mux", "OB 6", "OutBound6" },
3674
3675 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3676 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3677 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3678 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3679 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3680 { "DAC4 R Mux", "OB 7", "OutBound7" },
3681
3682 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3683 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3684 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3685 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3686 { "Sidetone Mux", "ADC1", "ADC 1" },
3687 { "Sidetone Mux", "ADC2", "ADC 2" },
3688 { "Sidetone Mux", NULL, "Sidetone Power" },
3689
3690 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3691 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3692 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3693 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3694 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3695 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3696 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3697 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3698 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3699 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3700 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3701
3702 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3703 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3704 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3705 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3706 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3707 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3708 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3709 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3710 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3711 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3712 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3713 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3714
3715 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3716 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3717 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3718 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3719 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3720 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3721 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3722 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3723 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3724 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3725 { "DD1 MIXR", NULL, "dac mono3 right filter" },
3726 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3727
3728 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3729 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3730 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3731 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3732 { "DD2 MIXL", NULL, "dac mono4 left filter" },
3733 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3734 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3735 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3736 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3737 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3738 { "DD2 MIXR", NULL, "dac mono4 right filter" },
3739 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3740
3741 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3742 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3743 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3744 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3745 { "DD1 MIX", NULL, "DD1 MIXL" },
3746 { "DD1 MIX", NULL, "DD1 MIXR" },
3747 { "DD2 MIX", NULL, "DD2 MIXL" },
3748 { "DD2 MIX", NULL, "DD2 MIXR" },
3749
3750 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3751 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3752 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3753 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3754
3755 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3756 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3757 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3758 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3759
3760 { "DAC 1", NULL, "DAC12 SRC Mux" },
3761 { "DAC 2", NULL, "DAC12 SRC Mux" },
3762 { "DAC 3", NULL, "DAC3 SRC Mux" },
3763
3764 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3765 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3766 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3767 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3768 { "PDM1 L Mux", NULL, "PDM1 Power" },
3769 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3770 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3771 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3772 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3773 { "PDM1 R Mux", NULL, "PDM1 Power" },
3774 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3775 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3776 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3777 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3778 { "PDM2 L Mux", NULL, "PDM2 Power" },
3779 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3780 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3781 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3782 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3783 { "PDM2 R Mux", NULL, "PDM2 Power" },
3784
3785 { "LOUT1 amp", NULL, "DAC 1" },
3786 { "LOUT2 amp", NULL, "DAC 2" },
3787 { "LOUT3 amp", NULL, "DAC 3" },
3788
3789 { "LOUT1 vref", NULL, "LOUT1 amp" },
3790 { "LOUT2 vref", NULL, "LOUT2 amp" },
3791 { "LOUT3 vref", NULL, "LOUT3 amp" },
3792
3793 { "LOUT1", NULL, "LOUT1 vref" },
3794 { "LOUT2", NULL, "LOUT2 vref" },
3795 { "LOUT3", NULL, "LOUT3 vref" },
3796
3797 { "PDM1L", NULL, "PDM1 L Mux" },
3798 { "PDM1R", NULL, "PDM1 R Mux" },
3799 { "PDM2L", NULL, "PDM2 L Mux" },
3800 { "PDM2R", NULL, "PDM2 R Mux" },
3801 };
3802
3803 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3804 { "DMIC L2", NULL, "DMIC1 power" },
3805 { "DMIC R2", NULL, "DMIC1 power" },
3806 };
3807
3808 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3809 { "DMIC L2", NULL, "DMIC2 power" },
3810 { "DMIC R2", NULL, "DMIC2 power" },
3811 };
3812
3813 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3814 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3815 {
3816 struct snd_soc_codec *codec = dai->codec;
3817 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3818 unsigned int val_len = 0, val_clk, mask_clk;
3819 int pre_div, bclk_ms, frame_size;
3820
3821 rt5677->lrck[dai->id] = params_rate(params);
3822 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3823 if (pre_div < 0) {
3824 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3825 rt5677->sysclk, rt5677->lrck[dai->id]);
3826 return -EINVAL;
3827 }
3828 frame_size = snd_soc_params_to_frame_size(params);
3829 if (frame_size < 0) {
3830 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3831 return -EINVAL;
3832 }
3833 bclk_ms = frame_size > 32;
3834 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3835
3836 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3837 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3838 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3839 bclk_ms, pre_div, dai->id);
3840
3841 switch (params_width(params)) {
3842 case 16:
3843 break;
3844 case 20:
3845 val_len |= RT5677_I2S_DL_20;
3846 break;
3847 case 24:
3848 val_len |= RT5677_I2S_DL_24;
3849 break;
3850 case 8:
3851 val_len |= RT5677_I2S_DL_8;
3852 break;
3853 default:
3854 return -EINVAL;
3855 }
3856
3857 switch (dai->id) {
3858 case RT5677_AIF1:
3859 mask_clk = RT5677_I2S_PD1_MASK;
3860 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3861 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3862 RT5677_I2S_DL_MASK, val_len);
3863 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3864 mask_clk, val_clk);
3865 break;
3866 case RT5677_AIF2:
3867 mask_clk = RT5677_I2S_PD2_MASK;
3868 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3869 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3870 RT5677_I2S_DL_MASK, val_len);
3871 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3872 mask_clk, val_clk);
3873 break;
3874 case RT5677_AIF3:
3875 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3876 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3877 pre_div << RT5677_I2S_PD3_SFT;
3878 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3879 RT5677_I2S_DL_MASK, val_len);
3880 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3881 mask_clk, val_clk);
3882 break;
3883 case RT5677_AIF4:
3884 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3885 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3886 pre_div << RT5677_I2S_PD4_SFT;
3887 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3888 RT5677_I2S_DL_MASK, val_len);
3889 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3890 mask_clk, val_clk);
3891 break;
3892 default:
3893 break;
3894 }
3895
3896 return 0;
3897 }
3898
3899 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3900 {
3901 struct snd_soc_codec *codec = dai->codec;
3902 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3903 unsigned int reg_val = 0;
3904
3905 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3906 case SND_SOC_DAIFMT_CBM_CFM:
3907 rt5677->master[dai->id] = 1;
3908 break;
3909 case SND_SOC_DAIFMT_CBS_CFS:
3910 reg_val |= RT5677_I2S_MS_S;
3911 rt5677->master[dai->id] = 0;
3912 break;
3913 default:
3914 return -EINVAL;
3915 }
3916
3917 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3918 case SND_SOC_DAIFMT_NB_NF:
3919 break;
3920 case SND_SOC_DAIFMT_IB_NF:
3921 reg_val |= RT5677_I2S_BP_INV;
3922 break;
3923 default:
3924 return -EINVAL;
3925 }
3926
3927 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3928 case SND_SOC_DAIFMT_I2S:
3929 break;
3930 case SND_SOC_DAIFMT_LEFT_J:
3931 reg_val |= RT5677_I2S_DF_LEFT;
3932 break;
3933 case SND_SOC_DAIFMT_DSP_A:
3934 reg_val |= RT5677_I2S_DF_PCM_A;
3935 break;
3936 case SND_SOC_DAIFMT_DSP_B:
3937 reg_val |= RT5677_I2S_DF_PCM_B;
3938 break;
3939 default:
3940 return -EINVAL;
3941 }
3942
3943 switch (dai->id) {
3944 case RT5677_AIF1:
3945 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3946 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3947 RT5677_I2S_DF_MASK, reg_val);
3948 break;
3949 case RT5677_AIF2:
3950 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3951 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3952 RT5677_I2S_DF_MASK, reg_val);
3953 break;
3954 case RT5677_AIF3:
3955 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3956 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3957 RT5677_I2S_DF_MASK, reg_val);
3958 break;
3959 case RT5677_AIF4:
3960 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3961 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3962 RT5677_I2S_DF_MASK, reg_val);
3963 break;
3964 default:
3965 break;
3966 }
3967
3968
3969 return 0;
3970 }
3971
3972 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3973 int clk_id, unsigned int freq, int dir)
3974 {
3975 struct snd_soc_codec *codec = dai->codec;
3976 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3977 unsigned int reg_val = 0;
3978
3979 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3980 return 0;
3981
3982 switch (clk_id) {
3983 case RT5677_SCLK_S_MCLK:
3984 reg_val |= RT5677_SCLK_SRC_MCLK;
3985 break;
3986 case RT5677_SCLK_S_PLL1:
3987 reg_val |= RT5677_SCLK_SRC_PLL1;
3988 break;
3989 case RT5677_SCLK_S_RCCLK:
3990 reg_val |= RT5677_SCLK_SRC_RCCLK;
3991 break;
3992 default:
3993 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3994 return -EINVAL;
3995 }
3996 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3997 RT5677_SCLK_SRC_MASK, reg_val);
3998 rt5677->sysclk = freq;
3999 rt5677->sysclk_src = clk_id;
4000
4001 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4002
4003 return 0;
4004 }
4005
4006 /**
4007 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4008 * @freq_in: external clock provided to codec.
4009 * @freq_out: target clock which codec works on.
4010 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4011 *
4012 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4013 *
4014 * Returns 0 for success or negative error code.
4015 */
4016 static int rt5677_pll_calc(const unsigned int freq_in,
4017 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4018 {
4019 if (RT5677_PLL_INP_MIN > freq_in)
4020 return -EINVAL;
4021
4022 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4023 }
4024
4025 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4026 unsigned int freq_in, unsigned int freq_out)
4027 {
4028 struct snd_soc_codec *codec = dai->codec;
4029 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4030 struct rl6231_pll_code pll_code;
4031 int ret;
4032
4033 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4034 freq_out == rt5677->pll_out)
4035 return 0;
4036
4037 if (!freq_in || !freq_out) {
4038 dev_dbg(codec->dev, "PLL disabled\n");
4039
4040 rt5677->pll_in = 0;
4041 rt5677->pll_out = 0;
4042 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4043 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4044 return 0;
4045 }
4046
4047 switch (source) {
4048 case RT5677_PLL1_S_MCLK:
4049 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4050 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4051 break;
4052 case RT5677_PLL1_S_BCLK1:
4053 case RT5677_PLL1_S_BCLK2:
4054 case RT5677_PLL1_S_BCLK3:
4055 case RT5677_PLL1_S_BCLK4:
4056 switch (dai->id) {
4057 case RT5677_AIF1:
4058 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4059 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4060 break;
4061 case RT5677_AIF2:
4062 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4063 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4064 break;
4065 case RT5677_AIF3:
4066 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4067 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4068 break;
4069 case RT5677_AIF4:
4070 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4071 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4072 break;
4073 default:
4074 break;
4075 }
4076 break;
4077 default:
4078 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4079 return -EINVAL;
4080 }
4081
4082 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4083 if (ret < 0) {
4084 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4085 return ret;
4086 }
4087
4088 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4089 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4090 pll_code.n_code, pll_code.k_code);
4091
4092 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4093 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4094 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4095 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4096 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4097
4098 rt5677->pll_in = freq_in;
4099 rt5677->pll_out = freq_out;
4100 rt5677->pll_src = source;
4101
4102 return 0;
4103 }
4104
4105 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4106 unsigned int rx_mask, int slots, int slot_width)
4107 {
4108 struct snd_soc_codec *codec = dai->codec;
4109 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4110 unsigned int val = 0, slot_width_25 = 0;
4111
4112 if (rx_mask || tx_mask)
4113 val |= (1 << 12);
4114
4115 switch (slots) {
4116 case 4:
4117 val |= (1 << 10);
4118 break;
4119 case 6:
4120 val |= (2 << 10);
4121 break;
4122 case 8:
4123 val |= (3 << 10);
4124 break;
4125 case 2:
4126 default:
4127 break;
4128 }
4129
4130 switch (slot_width) {
4131 case 20:
4132 val |= (1 << 8);
4133 break;
4134 case 25:
4135 slot_width_25 = 0x8080;
4136 case 24:
4137 val |= (2 << 8);
4138 break;
4139 case 32:
4140 val |= (3 << 8);
4141 break;
4142 case 16:
4143 default:
4144 break;
4145 }
4146
4147 switch (dai->id) {
4148 case RT5677_AIF1:
4149 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4150 val);
4151 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4152 slot_width_25);
4153 break;
4154 case RT5677_AIF2:
4155 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4156 val);
4157 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4158 slot_width_25);
4159 break;
4160 default:
4161 break;
4162 }
4163
4164 return 0;
4165 }
4166
4167 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4168 enum snd_soc_bias_level level)
4169 {
4170 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4171
4172 switch (level) {
4173 case SND_SOC_BIAS_ON:
4174 break;
4175
4176 case SND_SOC_BIAS_PREPARE:
4177 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4178 rt5677_set_dsp_vad(codec, false);
4179
4180 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4181 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4182 0x0055);
4183 regmap_update_bits(rt5677->regmap,
4184 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4185 0x0f00, 0x0f00);
4186 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4187 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4188 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4189 RT5677_PWR_BG | RT5677_PWR_VREF2,
4190 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4191 RT5677_PWR_BG | RT5677_PWR_VREF2);
4192 rt5677->is_vref_slow = false;
4193 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4194 RT5677_PWR_CORE, RT5677_PWR_CORE);
4195 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4196 0x1, 0x1);
4197 }
4198 break;
4199
4200 case SND_SOC_BIAS_STANDBY:
4201 break;
4202
4203 case SND_SOC_BIAS_OFF:
4204 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4205 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4206 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4207 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4208 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4209 regmap_update_bits(rt5677->regmap,
4210 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4211
4212 if (rt5677->dsp_vad_en)
4213 rt5677_set_dsp_vad(codec, true);
4214 break;
4215
4216 default:
4217 break;
4218 }
4219 codec->dapm.bias_level = level;
4220
4221 return 0;
4222 }
4223
4224 #ifdef CONFIG_GPIOLIB
4225 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4226 {
4227 return container_of(chip, struct rt5677_priv, gpio_chip);
4228 }
4229
4230 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4231 {
4232 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4233
4234 switch (offset) {
4235 case RT5677_GPIO1 ... RT5677_GPIO5:
4236 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4237 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4238 break;
4239
4240 case RT5677_GPIO6:
4241 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4242 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4243 break;
4244
4245 default:
4246 break;
4247 }
4248 }
4249
4250 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4251 unsigned offset, int value)
4252 {
4253 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4254
4255 switch (offset) {
4256 case RT5677_GPIO1 ... RT5677_GPIO5:
4257 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4258 0x3 << (offset * 3 + 1),
4259 (0x2 | !!value) << (offset * 3 + 1));
4260 break;
4261
4262 case RT5677_GPIO6:
4263 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4264 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4265 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4266 break;
4267
4268 default:
4269 break;
4270 }
4271
4272 return 0;
4273 }
4274
4275 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4276 {
4277 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4278 int value, ret;
4279
4280 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4281 if (ret < 0)
4282 return ret;
4283
4284 return (value & (0x1 << offset)) >> offset;
4285 }
4286
4287 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4288 {
4289 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4290
4291 switch (offset) {
4292 case RT5677_GPIO1 ... RT5677_GPIO5:
4293 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4294 0x1 << (offset * 3 + 2), 0x0);
4295 break;
4296
4297 case RT5677_GPIO6:
4298 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4299 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4300 break;
4301
4302 default:
4303 break;
4304 }
4305
4306 return 0;
4307 }
4308
4309 /** Configures the gpio as
4310 * 0 - floating
4311 * 1 - pull down
4312 * 2 - pull up
4313 */
4314 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4315 int value)
4316 {
4317 int shift;
4318
4319 switch (offset) {
4320 case RT5677_GPIO1 ... RT5677_GPIO2:
4321 shift = 2 * (1 - offset);
4322 regmap_update_bits(rt5677->regmap,
4323 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4324 0x3 << shift,
4325 (value & 0x3) << shift);
4326 break;
4327
4328 case RT5677_GPIO3 ... RT5677_GPIO6:
4329 shift = 2 * (9 - offset);
4330 regmap_update_bits(rt5677->regmap,
4331 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4332 0x3 << shift,
4333 (value & 0x3) << shift);
4334 break;
4335
4336 default:
4337 break;
4338 }
4339 }
4340
4341 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4342 {
4343 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4344 struct regmap_irq_chip_data *data = rt5677->irq_data;
4345 int irq;
4346
4347 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4348 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4349 (rt5677->pdata.jd1_gpio == 2 &&
4350 offset == RT5677_GPIO2) ||
4351 (rt5677->pdata.jd1_gpio == 3 &&
4352 offset == RT5677_GPIO3)) {
4353 irq = RT5677_IRQ_JD1;
4354 } else {
4355 return -ENXIO;
4356 }
4357 }
4358
4359 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4360 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4361 (rt5677->pdata.jd2_gpio == 2 &&
4362 offset == RT5677_GPIO5) ||
4363 (rt5677->pdata.jd2_gpio == 3 &&
4364 offset == RT5677_GPIO6)) {
4365 irq = RT5677_IRQ_JD2;
4366 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4367 offset == RT5677_GPIO4) ||
4368 (rt5677->pdata.jd3_gpio == 2 &&
4369 offset == RT5677_GPIO5) ||
4370 (rt5677->pdata.jd3_gpio == 3 &&
4371 offset == RT5677_GPIO6)) {
4372 irq = RT5677_IRQ_JD3;
4373 } else {
4374 return -ENXIO;
4375 }
4376 }
4377
4378 return regmap_irq_get_virq(data, irq);
4379 }
4380
4381 static struct gpio_chip rt5677_template_chip = {
4382 .label = "rt5677",
4383 .owner = THIS_MODULE,
4384 .direction_output = rt5677_gpio_direction_out,
4385 .set = rt5677_gpio_set,
4386 .direction_input = rt5677_gpio_direction_in,
4387 .get = rt5677_gpio_get,
4388 .to_irq = rt5677_to_irq,
4389 .can_sleep = 1,
4390 };
4391
4392 static void rt5677_init_gpio(struct i2c_client *i2c)
4393 {
4394 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4395 int ret;
4396
4397 rt5677->gpio_chip = rt5677_template_chip;
4398 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4399 rt5677->gpio_chip.dev = &i2c->dev;
4400 rt5677->gpio_chip.base = -1;
4401
4402 ret = gpiochip_add(&rt5677->gpio_chip);
4403 if (ret != 0)
4404 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4405 }
4406
4407 static void rt5677_free_gpio(struct i2c_client *i2c)
4408 {
4409 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4410
4411 gpiochip_remove(&rt5677->gpio_chip);
4412 }
4413 #else
4414 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4415 int value)
4416 {
4417 }
4418
4419 static void rt5677_init_gpio(struct i2c_client *i2c)
4420 {
4421 }
4422
4423 static void rt5677_free_gpio(struct i2c_client *i2c)
4424 {
4425 }
4426 #endif
4427
4428 static int rt5677_probe(struct snd_soc_codec *codec)
4429 {
4430 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4431 int i;
4432
4433 rt5677->codec = codec;
4434
4435 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4436 snd_soc_dapm_add_routes(&codec->dapm,
4437 rt5677_dmic2_clk_2,
4438 ARRAY_SIZE(rt5677_dmic2_clk_2));
4439 } else { /*use dmic1 clock by default*/
4440 snd_soc_dapm_add_routes(&codec->dapm,
4441 rt5677_dmic2_clk_1,
4442 ARRAY_SIZE(rt5677_dmic2_clk_1));
4443 }
4444
4445 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4446
4447 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4448 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4449
4450 for (i = 0; i < RT5677_GPIO_NUM; i++)
4451 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4452
4453 if (rt5677->irq_data) {
4454 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4455 0x8000);
4456 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4457 0x0008);
4458
4459 if (rt5677->pdata.jd1_gpio)
4460 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4461 RT5677_SEL_GPIO_JD1_MASK,
4462 rt5677->pdata.jd1_gpio <<
4463 RT5677_SEL_GPIO_JD1_SFT);
4464
4465 if (rt5677->pdata.jd2_gpio)
4466 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4467 RT5677_SEL_GPIO_JD2_MASK,
4468 rt5677->pdata.jd2_gpio <<
4469 RT5677_SEL_GPIO_JD2_SFT);
4470
4471 if (rt5677->pdata.jd3_gpio)
4472 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4473 RT5677_SEL_GPIO_JD3_MASK,
4474 rt5677->pdata.jd3_gpio <<
4475 RT5677_SEL_GPIO_JD3_SFT);
4476 }
4477
4478 mutex_init(&rt5677->dsp_cmd_lock);
4479 mutex_init(&rt5677->dsp_pri_lock);
4480
4481 return 0;
4482 }
4483
4484 static int rt5677_remove(struct snd_soc_codec *codec)
4485 {
4486 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4487
4488 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4489 if (gpio_is_valid(rt5677->pow_ldo2))
4490 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4491
4492 return 0;
4493 }
4494
4495 #ifdef CONFIG_PM
4496 static int rt5677_suspend(struct snd_soc_codec *codec)
4497 {
4498 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4499
4500 if (!rt5677->dsp_vad_en) {
4501 regcache_cache_only(rt5677->regmap, true);
4502 regcache_mark_dirty(rt5677->regmap);
4503 }
4504
4505 if (gpio_is_valid(rt5677->pow_ldo2))
4506 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4507
4508 return 0;
4509 }
4510
4511 static int rt5677_resume(struct snd_soc_codec *codec)
4512 {
4513 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4514
4515 if (gpio_is_valid(rt5677->pow_ldo2)) {
4516 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4517 msleep(10);
4518 }
4519
4520 if (!rt5677->dsp_vad_en) {
4521 regcache_cache_only(rt5677->regmap, false);
4522 regcache_sync(rt5677->regmap);
4523 }
4524
4525 return 0;
4526 }
4527 #else
4528 #define rt5677_suspend NULL
4529 #define rt5677_resume NULL
4530 #endif
4531
4532 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4533 {
4534 struct i2c_client *client = context;
4535 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4536
4537 if (rt5677->is_dsp_mode) {
4538 if (reg > 0xff) {
4539 mutex_lock(&rt5677->dsp_pri_lock);
4540 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4541 reg & 0xff);
4542 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4543 mutex_unlock(&rt5677->dsp_pri_lock);
4544 } else {
4545 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4546 }
4547 } else {
4548 regmap_read(rt5677->regmap_physical, reg, val);
4549 }
4550
4551 return 0;
4552 }
4553
4554 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4555 {
4556 struct i2c_client *client = context;
4557 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4558
4559 if (rt5677->is_dsp_mode) {
4560 if (reg > 0xff) {
4561 mutex_lock(&rt5677->dsp_pri_lock);
4562 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4563 reg & 0xff);
4564 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4565 val);
4566 mutex_unlock(&rt5677->dsp_pri_lock);
4567 } else {
4568 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4569 }
4570 } else {
4571 regmap_write(rt5677->regmap_physical, reg, val);
4572 }
4573
4574 return 0;
4575 }
4576
4577 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4578 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4579 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4580
4581 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4582 .hw_params = rt5677_hw_params,
4583 .set_fmt = rt5677_set_dai_fmt,
4584 .set_sysclk = rt5677_set_dai_sysclk,
4585 .set_pll = rt5677_set_dai_pll,
4586 .set_tdm_slot = rt5677_set_tdm_slot,
4587 };
4588
4589 static struct snd_soc_dai_driver rt5677_dai[] = {
4590 {
4591 .name = "rt5677-aif1",
4592 .id = RT5677_AIF1,
4593 .playback = {
4594 .stream_name = "AIF1 Playback",
4595 .channels_min = 1,
4596 .channels_max = 2,
4597 .rates = RT5677_STEREO_RATES,
4598 .formats = RT5677_FORMATS,
4599 },
4600 .capture = {
4601 .stream_name = "AIF1 Capture",
4602 .channels_min = 1,
4603 .channels_max = 2,
4604 .rates = RT5677_STEREO_RATES,
4605 .formats = RT5677_FORMATS,
4606 },
4607 .ops = &rt5677_aif_dai_ops,
4608 },
4609 {
4610 .name = "rt5677-aif2",
4611 .id = RT5677_AIF2,
4612 .playback = {
4613 .stream_name = "AIF2 Playback",
4614 .channels_min = 1,
4615 .channels_max = 2,
4616 .rates = RT5677_STEREO_RATES,
4617 .formats = RT5677_FORMATS,
4618 },
4619 .capture = {
4620 .stream_name = "AIF2 Capture",
4621 .channels_min = 1,
4622 .channels_max = 2,
4623 .rates = RT5677_STEREO_RATES,
4624 .formats = RT5677_FORMATS,
4625 },
4626 .ops = &rt5677_aif_dai_ops,
4627 },
4628 {
4629 .name = "rt5677-aif3",
4630 .id = RT5677_AIF3,
4631 .playback = {
4632 .stream_name = "AIF3 Playback",
4633 .channels_min = 1,
4634 .channels_max = 2,
4635 .rates = RT5677_STEREO_RATES,
4636 .formats = RT5677_FORMATS,
4637 },
4638 .capture = {
4639 .stream_name = "AIF3 Capture",
4640 .channels_min = 1,
4641 .channels_max = 2,
4642 .rates = RT5677_STEREO_RATES,
4643 .formats = RT5677_FORMATS,
4644 },
4645 .ops = &rt5677_aif_dai_ops,
4646 },
4647 {
4648 .name = "rt5677-aif4",
4649 .id = RT5677_AIF4,
4650 .playback = {
4651 .stream_name = "AIF4 Playback",
4652 .channels_min = 1,
4653 .channels_max = 2,
4654 .rates = RT5677_STEREO_RATES,
4655 .formats = RT5677_FORMATS,
4656 },
4657 .capture = {
4658 .stream_name = "AIF4 Capture",
4659 .channels_min = 1,
4660 .channels_max = 2,
4661 .rates = RT5677_STEREO_RATES,
4662 .formats = RT5677_FORMATS,
4663 },
4664 .ops = &rt5677_aif_dai_ops,
4665 },
4666 {
4667 .name = "rt5677-slimbus",
4668 .id = RT5677_AIF5,
4669 .playback = {
4670 .stream_name = "SLIMBus Playback",
4671 .channels_min = 1,
4672 .channels_max = 2,
4673 .rates = RT5677_STEREO_RATES,
4674 .formats = RT5677_FORMATS,
4675 },
4676 .capture = {
4677 .stream_name = "SLIMBus Capture",
4678 .channels_min = 1,
4679 .channels_max = 2,
4680 .rates = RT5677_STEREO_RATES,
4681 .formats = RT5677_FORMATS,
4682 },
4683 .ops = &rt5677_aif_dai_ops,
4684 },
4685 };
4686
4687 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4688 .probe = rt5677_probe,
4689 .remove = rt5677_remove,
4690 .suspend = rt5677_suspend,
4691 .resume = rt5677_resume,
4692 .set_bias_level = rt5677_set_bias_level,
4693 .idle_bias_off = true,
4694 .controls = rt5677_snd_controls,
4695 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4696 .dapm_widgets = rt5677_dapm_widgets,
4697 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4698 .dapm_routes = rt5677_dapm_routes,
4699 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4700 };
4701
4702 static const struct regmap_config rt5677_regmap_physical = {
4703 .name = "physical",
4704 .reg_bits = 8,
4705 .val_bits = 16,
4706
4707 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4708 RT5677_PR_SPACING),
4709 .readable_reg = rt5677_readable_register,
4710
4711 .cache_type = REGCACHE_NONE,
4712 .ranges = rt5677_ranges,
4713 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4714 };
4715
4716 static const struct regmap_config rt5677_regmap = {
4717 .reg_bits = 8,
4718 .val_bits = 16,
4719
4720 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4721 RT5677_PR_SPACING),
4722
4723 .volatile_reg = rt5677_volatile_register,
4724 .readable_reg = rt5677_readable_register,
4725 .reg_read = rt5677_read,
4726 .reg_write = rt5677_write,
4727
4728 .cache_type = REGCACHE_RBTREE,
4729 .reg_defaults = rt5677_reg,
4730 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4731 .ranges = rt5677_ranges,
4732 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4733 };
4734
4735 static const struct i2c_device_id rt5677_i2c_id[] = {
4736 { "rt5677", 0 },
4737 { }
4738 };
4739 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4740
4741 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4742 {
4743 rt5677->pdata.in1_diff = of_property_read_bool(np,
4744 "realtek,in1-differential");
4745 rt5677->pdata.in2_diff = of_property_read_bool(np,
4746 "realtek,in2-differential");
4747 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4748 "realtek,lout1-differential");
4749 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4750 "realtek,lout2-differential");
4751 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4752 "realtek,lout3-differential");
4753
4754 rt5677->pow_ldo2 = of_get_named_gpio(np,
4755 "realtek,pow-ldo2-gpio", 0);
4756
4757 /*
4758 * POW_LDO2 is optional (it may be statically tied on the board).
4759 * -ENOENT means that the property doesn't exist, i.e. there is no
4760 * GPIO, so is not an error. Any other error code means the property
4761 * exists, but could not be parsed.
4762 */
4763 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4764 (rt5677->pow_ldo2 != -ENOENT))
4765 return rt5677->pow_ldo2;
4766
4767 of_property_read_u8_array(np, "realtek,gpio-config",
4768 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4769
4770 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4771 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4772 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4773
4774 return 0;
4775 }
4776
4777 static struct regmap_irq rt5677_irqs[] = {
4778 [RT5677_IRQ_JD1] = {
4779 .reg_offset = 0,
4780 .mask = RT5677_EN_IRQ_GPIO_JD1,
4781 },
4782 [RT5677_IRQ_JD2] = {
4783 .reg_offset = 0,
4784 .mask = RT5677_EN_IRQ_GPIO_JD2,
4785 },
4786 [RT5677_IRQ_JD3] = {
4787 .reg_offset = 0,
4788 .mask = RT5677_EN_IRQ_GPIO_JD3,
4789 },
4790 };
4791
4792 static struct regmap_irq_chip rt5677_irq_chip = {
4793 .name = "rt5677",
4794 .irqs = rt5677_irqs,
4795 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4796
4797 .num_regs = 1,
4798 .status_base = RT5677_IRQ_CTRL1,
4799 .mask_base = RT5677_IRQ_CTRL1,
4800 .mask_invert = 1,
4801 };
4802
4803 static int rt5677_init_irq(struct i2c_client *i2c)
4804 {
4805 int ret;
4806 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4807
4808 if (!rt5677->pdata.jd1_gpio &&
4809 !rt5677->pdata.jd2_gpio &&
4810 !rt5677->pdata.jd3_gpio)
4811 return 0;
4812
4813 if (!i2c->irq) {
4814 dev_err(&i2c->dev, "No interrupt specified\n");
4815 return -EINVAL;
4816 }
4817
4818 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4819 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4820 &rt5677_irq_chip, &rt5677->irq_data);
4821
4822 if (ret != 0) {
4823 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4824 return ret;
4825 }
4826
4827 return 0;
4828 }
4829
4830 static void rt5677_free_irq(struct i2c_client *i2c)
4831 {
4832 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4833
4834 if (rt5677->irq_data)
4835 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4836 }
4837
4838 static int rt5677_i2c_probe(struct i2c_client *i2c,
4839 const struct i2c_device_id *id)
4840 {
4841 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4842 struct rt5677_priv *rt5677;
4843 int ret;
4844 unsigned int val;
4845
4846 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4847 GFP_KERNEL);
4848 if (rt5677 == NULL)
4849 return -ENOMEM;
4850
4851 i2c_set_clientdata(i2c, rt5677);
4852
4853 if (pdata)
4854 rt5677->pdata = *pdata;
4855
4856 if (i2c->dev.of_node) {
4857 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4858 if (ret) {
4859 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4860 ret);
4861 return ret;
4862 }
4863 } else {
4864 rt5677->pow_ldo2 = -EINVAL;
4865 }
4866
4867 if (gpio_is_valid(rt5677->pow_ldo2)) {
4868 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4869 GPIOF_OUT_INIT_HIGH,
4870 "RT5677 POW_LDO2");
4871 if (ret < 0) {
4872 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4873 rt5677->pow_ldo2, ret);
4874 return ret;
4875 }
4876 /* Wait a while until I2C bus becomes available. The datasheet
4877 * does not specify the exact we should wait but startup
4878 * sequence mentiones at least a few milliseconds.
4879 */
4880 msleep(10);
4881 }
4882
4883 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4884 &rt5677_regmap_physical);
4885 if (IS_ERR(rt5677->regmap_physical)) {
4886 ret = PTR_ERR(rt5677->regmap_physical);
4887 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4888 ret);
4889 return ret;
4890 }
4891
4892 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
4893 if (IS_ERR(rt5677->regmap)) {
4894 ret = PTR_ERR(rt5677->regmap);
4895 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4896 ret);
4897 return ret;
4898 }
4899
4900 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4901 if (val != RT5677_DEVICE_ID) {
4902 dev_err(&i2c->dev,
4903 "Device with ID register %x is not rt5677\n", val);
4904 return -ENODEV;
4905 }
4906
4907 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4908
4909 ret = regmap_register_patch(rt5677->regmap, init_list,
4910 ARRAY_SIZE(init_list));
4911 if (ret != 0)
4912 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4913
4914 if (rt5677->pdata.in1_diff)
4915 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4916 RT5677_IN_DF1, RT5677_IN_DF1);
4917
4918 if (rt5677->pdata.in2_diff)
4919 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4920 RT5677_IN_DF2, RT5677_IN_DF2);
4921
4922 if (rt5677->pdata.lout1_diff)
4923 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4924 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4925
4926 if (rt5677->pdata.lout2_diff)
4927 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4928 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4929
4930 if (rt5677->pdata.lout3_diff)
4931 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4932 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4933
4934 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4935 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4936 RT5677_GPIO5_FUNC_MASK,
4937 RT5677_GPIO5_FUNC_DMIC);
4938 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4939 RT5677_GPIO5_DIR_MASK,
4940 RT5677_GPIO5_DIR_OUT);
4941 }
4942
4943 if (rt5677->pdata.micbias1_vdd_3v3)
4944 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
4945 RT5677_MICBIAS1_CTRL_VDD_MASK,
4946 RT5677_MICBIAS1_CTRL_VDD_3_3V);
4947
4948 rt5677_init_gpio(i2c);
4949 rt5677_init_irq(i2c);
4950
4951 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4952 rt5677_dai, ARRAY_SIZE(rt5677_dai));
4953 }
4954
4955 static int rt5677_i2c_remove(struct i2c_client *i2c)
4956 {
4957 snd_soc_unregister_codec(&i2c->dev);
4958 rt5677_free_irq(i2c);
4959 rt5677_free_gpio(i2c);
4960
4961 return 0;
4962 }
4963
4964 static struct i2c_driver rt5677_i2c_driver = {
4965 .driver = {
4966 .name = "rt5677",
4967 .owner = THIS_MODULE,
4968 },
4969 .probe = rt5677_i2c_probe,
4970 .remove = rt5677_i2c_remove,
4971 .id_table = rt5677_i2c_id,
4972 };
4973 module_i2c_driver(rt5677_i2c_driver);
4974
4975 MODULE_DESCRIPTION("ASoC RT5677 driver");
4976 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4977 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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