2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/of_device.h>
24 #include <sound/core.h>
25 #include <sound/tlv.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
34 #define SGTL5000_DAP_REG_OFFSET 0x0100
35 #define SGTL5000_MAX_REG_OFFSET 0x013A
37 /* default value of sgtl5000 registers */
38 static const struct reg_default sgtl5000_reg_defaults
[] = {
39 { SGTL5000_CHIP_CLK_CTRL
, 0x0008 },
40 { SGTL5000_CHIP_I2S_CTRL
, 0x0010 },
41 { SGTL5000_CHIP_SSS_CTRL
, 0x0008 },
42 { SGTL5000_CHIP_DAC_VOL
, 0x3c3c },
43 { SGTL5000_CHIP_PAD_STRENGTH
, 0x015f },
44 { SGTL5000_CHIP_ANA_HP_CTRL
, 0x1818 },
45 { SGTL5000_CHIP_ANA_CTRL
, 0x0111 },
46 { SGTL5000_CHIP_LINE_OUT_VOL
, 0x0404 },
47 { SGTL5000_CHIP_ANA_POWER
, 0x7060 },
48 { SGTL5000_CHIP_PLL_CTRL
, 0x5000 },
49 { SGTL5000_DAP_BASS_ENHANCE
, 0x0040 },
50 { SGTL5000_DAP_BASS_ENHANCE_CTRL
, 0x051f },
51 { SGTL5000_DAP_SURROUND
, 0x0040 },
52 { SGTL5000_DAP_EQ_BASS_BAND0
, 0x002f },
53 { SGTL5000_DAP_EQ_BASS_BAND1
, 0x002f },
54 { SGTL5000_DAP_EQ_BASS_BAND2
, 0x002f },
55 { SGTL5000_DAP_EQ_BASS_BAND3
, 0x002f },
56 { SGTL5000_DAP_EQ_BASS_BAND4
, 0x002f },
57 { SGTL5000_DAP_MAIN_CHAN
, 0x8000 },
58 { SGTL5000_DAP_AVC_CTRL
, 0x0510 },
59 { SGTL5000_DAP_AVC_THRESHOLD
, 0x1473 },
60 { SGTL5000_DAP_AVC_ATTACK
, 0x0028 },
61 { SGTL5000_DAP_AVC_DECAY
, 0x0050 },
64 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
65 enum sgtl5000_regulator_supplies
{
72 /* vddd is optional supply */
73 static const char *supply_names
[SGTL5000_SUPPLY_NUM
] = {
79 #define LDO_CONSUMER_NAME "VDDD_LDO"
80 #define LDO_VOLTAGE 1200000
82 static struct regulator_consumer_supply ldo_consumer
[] = {
83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME
, NULL
),
86 static struct regulator_init_data ldo_init_data
= {
90 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
91 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
93 .num_consumer_supplies
= 1,
94 .consumer_supplies
= &ldo_consumer
[0],
98 * sgtl5000 internal ldo regulator,
99 * enabled when VDDD not provided
101 struct ldo_regulator
{
102 struct regulator_desc desc
;
103 struct regulator_dev
*dev
;
109 /* sgtl5000 private structure in codec */
110 struct sgtl5000_priv
{
111 int sysclk
; /* sysclk rate */
112 int master
; /* i2s master or not */
113 int fmt
; /* i2s data format */
114 struct regulator_bulk_data supplies
[SGTL5000_SUPPLY_NUM
];
115 struct ldo_regulator
*ldo
;
116 struct regmap
*regmap
;
120 * mic_bias power on/off share the same register bits with
121 * output impedance of mic bias, when power on mic bias, we
122 * need reclaim it to impedance value.
128 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
129 struct snd_kcontrol
*kcontrol
, int event
)
132 case SND_SOC_DAPM_POST_PMU
:
133 /* change mic bias resistor to 4Kohm */
134 snd_soc_update_bits(w
->codec
, SGTL5000_CHIP_MIC_CTRL
,
135 SGTL5000_BIAS_R_MASK
,
136 SGTL5000_BIAS_R_4k
<< SGTL5000_BIAS_R_SHIFT
);
139 case SND_SOC_DAPM_PRE_PMD
:
140 snd_soc_update_bits(w
->codec
, SGTL5000_CHIP_MIC_CTRL
,
141 SGTL5000_BIAS_R_MASK
, 0);
148 * As manual described, ADC/DAC only works when VAG powerup,
149 * So enabled VAG before ADC/DAC up.
150 * In power down case, we need wait 400ms when vag fully ramped down.
152 static int power_vag_event(struct snd_soc_dapm_widget
*w
,
153 struct snd_kcontrol
*kcontrol
, int event
)
156 case SND_SOC_DAPM_PRE_PMU
:
157 snd_soc_update_bits(w
->codec
, SGTL5000_CHIP_ANA_POWER
,
158 SGTL5000_VAG_POWERUP
, SGTL5000_VAG_POWERUP
);
161 case SND_SOC_DAPM_POST_PMD
:
162 snd_soc_update_bits(w
->codec
, SGTL5000_CHIP_ANA_POWER
,
163 SGTL5000_VAG_POWERUP
, 0);
173 /* input sources for ADC */
174 static const char *adc_mux_text
[] = {
178 static const struct soc_enum adc_enum
=
179 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL
, 2, 2, adc_mux_text
);
181 static const struct snd_kcontrol_new adc_mux
=
182 SOC_DAPM_ENUM("Capture Mux", adc_enum
);
184 /* input sources for DAC */
185 static const char *dac_mux_text
[] = {
189 static const struct soc_enum dac_enum
=
190 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL
, 6, 2, dac_mux_text
);
192 static const struct snd_kcontrol_new dac_mux
=
193 SOC_DAPM_ENUM("Headphone Mux", dac_enum
);
195 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets
[] = {
196 SND_SOC_DAPM_INPUT("LINE_IN"),
197 SND_SOC_DAPM_INPUT("MIC_IN"),
199 SND_SOC_DAPM_OUTPUT("HP_OUT"),
200 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
202 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL
, 8, 0,
204 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
206 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER
, 4, 0, NULL
, 0),
207 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER
, 0, 0, NULL
, 0),
209 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM
, 0, 0, &adc_mux
),
210 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM
, 0, 0, &dac_mux
),
212 /* aif for i2s input */
213 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
214 0, SGTL5000_CHIP_DIG_POWER
,
217 /* aif for i2s output */
218 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
219 0, SGTL5000_CHIP_DIG_POWER
,
222 SND_SOC_DAPM_SUPPLY("VAG_POWER", SGTL5000_CHIP_ANA_POWER
, 7, 0,
224 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
226 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER
, 1, 0),
227 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER
, 3, 0),
230 /* routes for sgtl5000 */
231 static const struct snd_soc_dapm_route sgtl5000_dapm_routes
[] = {
232 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
233 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
235 {"ADC", NULL
, "VAG_POWER"},
236 {"ADC", NULL
, "Capture Mux"}, /* adc_mux --> adc */
237 {"AIFOUT", NULL
, "ADC"}, /* adc --> i2s_out */
239 {"DAC", NULL
, "VAG_POWER"},
240 {"DAC", NULL
, "AIFIN"}, /* i2s-->dac,skip audio mux */
241 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
242 {"LO", NULL
, "DAC"}, /* dac --> line_out */
244 {"LINE_IN", NULL
, "VAG_POWER"},
245 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
246 {"HP", NULL
, "Headphone Mux"}, /* hp_mux --> hp */
248 {"LINE_OUT", NULL
, "LO"},
249 {"HP_OUT", NULL
, "HP"},
252 /* custom function to fetch info of PCM playback volume */
253 static int dac_info_volsw(struct snd_kcontrol
*kcontrol
,
254 struct snd_ctl_elem_info
*uinfo
)
256 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
258 uinfo
->value
.integer
.min
= 0;
259 uinfo
->value
.integer
.max
= 0xfc - 0x3c;
264 * custom function to get of PCM playback volume
266 * dac volume register
267 * 15-------------8-7--------------0
268 * | R channel vol | L channel vol |
269 * -------------------------------
271 * PCM volume with 0.5017 dB steps from 0 to -90 dB
273 * register values map to dB
274 * 0x3B and less = Reserved
278 * 0xFC and greater = Muted
280 * register value map to userspace value
282 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
283 * ------------------------------
284 * userspace value 0xc0 0
286 static int dac_get_volsw(struct snd_kcontrol
*kcontrol
,
287 struct snd_ctl_elem_value
*ucontrol
)
289 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
294 reg
= snd_soc_read(codec
, SGTL5000_CHIP_DAC_VOL
);
296 /* get left channel volume */
297 l
= (reg
& SGTL5000_DAC_VOL_LEFT_MASK
) >> SGTL5000_DAC_VOL_LEFT_SHIFT
;
299 /* get right channel volume */
300 r
= (reg
& SGTL5000_DAC_VOL_RIGHT_MASK
) >> SGTL5000_DAC_VOL_RIGHT_SHIFT
;
302 /* make sure value fall in (0x3c,0xfc) */
303 l
= clamp(l
, 0x3c, 0xfc);
304 r
= clamp(r
, 0x3c, 0xfc);
306 /* invert it and map to userspace value */
310 ucontrol
->value
.integer
.value
[0] = l
;
311 ucontrol
->value
.integer
.value
[1] = r
;
317 * custom function to put of PCM playback volume
319 * dac volume register
320 * 15-------------8-7--------------0
321 * | R channel vol | L channel vol |
322 * -------------------------------
324 * PCM volume with 0.5017 dB steps from 0 to -90 dB
326 * register values map to dB
327 * 0x3B and less = Reserved
331 * 0xFC and greater = Muted
333 * userspace value map to register value
335 * userspace value 0xc0 0
336 * ------------------------------
337 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
339 static int dac_put_volsw(struct snd_kcontrol
*kcontrol
,
340 struct snd_ctl_elem_value
*ucontrol
)
342 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
347 l
= ucontrol
->value
.integer
.value
[0];
348 r
= ucontrol
->value
.integer
.value
[1];
350 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
351 l
= clamp(l
, 0, 0xfc - 0x3c);
352 r
= clamp(r
, 0, 0xfc - 0x3c);
354 /* invert it, get the value can be set to register */
358 /* shift to get the register value */
359 reg
= l
<< SGTL5000_DAC_VOL_LEFT_SHIFT
|
360 r
<< SGTL5000_DAC_VOL_RIGHT_SHIFT
;
362 snd_soc_write(codec
, SGTL5000_CHIP_DAC_VOL
, reg
);
367 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate
, -600, 600, 0);
369 /* tlv for mic gain, 0db 20db 30db 40db */
370 static const unsigned int mic_gain_tlv
[] = {
371 TLV_DB_RANGE_HEAD(2),
372 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
373 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
376 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
377 static const DECLARE_TLV_DB_SCALE(headphone_volume
, -5150, 50, 0);
379 static const struct snd_kcontrol_new sgtl5000_snd_controls
[] = {
380 /* SOC_DOUBLE_S8_TLV with invert */
382 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
383 .name
= "PCM Playback Volume",
384 .access
= SNDRV_CTL_ELEM_ACCESS_TLV_READ
|
385 SNDRV_CTL_ELEM_ACCESS_READWRITE
,
386 .info
= dac_info_volsw
,
387 .get
= dac_get_volsw
,
388 .put
= dac_put_volsw
,
391 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL
, 0, 4, 0xf, 0),
392 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
393 SGTL5000_CHIP_ANA_ADC_CTRL
,
394 8, 2, 0, capture_6db_attenuate
),
395 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL
, 1, 1, 0),
397 SOC_DOUBLE_TLV("Headphone Playback Volume",
398 SGTL5000_CHIP_ANA_HP_CTRL
,
402 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL
,
405 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL
,
406 0, 3, 0, mic_gain_tlv
),
409 /* mute the codec used by alsa core */
410 static int sgtl5000_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
412 struct snd_soc_codec
*codec
= codec_dai
->codec
;
413 u16 adcdac_ctrl
= SGTL5000_DAC_MUTE_LEFT
| SGTL5000_DAC_MUTE_RIGHT
;
415 snd_soc_update_bits(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
416 adcdac_ctrl
, mute
? adcdac_ctrl
: 0);
421 /* set codec format */
422 static int sgtl5000_set_dai_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
424 struct snd_soc_codec
*codec
= codec_dai
->codec
;
425 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
428 sgtl5000
->master
= 0;
430 * i2s clock and frame master setting.
432 * - clock and frame slave,
433 * - clock and frame master
435 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
436 case SND_SOC_DAIFMT_CBS_CFS
:
438 case SND_SOC_DAIFMT_CBM_CFM
:
439 i2sctl
|= SGTL5000_I2S_MASTER
;
440 sgtl5000
->master
= 1;
446 /* setting i2s data format */
447 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
448 case SND_SOC_DAIFMT_DSP_A
:
449 i2sctl
|= SGTL5000_I2S_MODE_PCM
;
451 case SND_SOC_DAIFMT_DSP_B
:
452 i2sctl
|= SGTL5000_I2S_MODE_PCM
;
453 i2sctl
|= SGTL5000_I2S_LRALIGN
;
455 case SND_SOC_DAIFMT_I2S
:
456 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
;
458 case SND_SOC_DAIFMT_RIGHT_J
:
459 i2sctl
|= SGTL5000_I2S_MODE_RJ
;
460 i2sctl
|= SGTL5000_I2S_LRPOL
;
462 case SND_SOC_DAIFMT_LEFT_J
:
463 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
;
464 i2sctl
|= SGTL5000_I2S_LRALIGN
;
470 sgtl5000
->fmt
= fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
472 /* Clock inversion */
473 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
474 case SND_SOC_DAIFMT_NB_NF
:
476 case SND_SOC_DAIFMT_IB_NF
:
477 i2sctl
|= SGTL5000_I2S_SCLK_INV
;
483 snd_soc_write(codec
, SGTL5000_CHIP_I2S_CTRL
, i2sctl
);
488 /* set codec sysclk */
489 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
490 int clk_id
, unsigned int freq
, int dir
)
492 struct snd_soc_codec
*codec
= codec_dai
->codec
;
493 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
496 case SGTL5000_SYSCLK
:
497 sgtl5000
->sysclk
= freq
;
507 * set clock according to i2s frame clock,
508 * sgtl5000 provide 2 clock sources.
509 * 1. sys_mclk. sample freq can only configure to
510 * 1/256, 1/384, 1/512 of sys_mclk.
511 * 2. pll. can derive any audio clocks.
513 * clock setting rules:
514 * 1. in slave mode, only sys_mclk can use.
515 * 2. as constraint by sys_mclk, sample freq should
516 * set to 32k, 44.1k and above.
517 * 3. using sys_mclk prefer to pll to save power.
519 static int sgtl5000_set_clock(struct snd_soc_codec
*codec
, int frame_rate
)
521 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
523 int sys_fs
; /* sample freq */
526 * sample freq should be divided by frame clock,
527 * if frame clock lower than 44.1khz, sample feq should set to
530 switch (frame_rate
) {
544 /* set divided factor of frame clock */
545 switch (sys_fs
/ frame_rate
) {
547 clk_ctl
|= SGTL5000_RATE_MODE_DIV_4
<< SGTL5000_RATE_MODE_SHIFT
;
550 clk_ctl
|= SGTL5000_RATE_MODE_DIV_2
<< SGTL5000_RATE_MODE_SHIFT
;
553 clk_ctl
|= SGTL5000_RATE_MODE_DIV_1
<< SGTL5000_RATE_MODE_SHIFT
;
559 /* set the sys_fs according to frame rate */
562 clk_ctl
|= SGTL5000_SYS_FS_32k
<< SGTL5000_SYS_FS_SHIFT
;
565 clk_ctl
|= SGTL5000_SYS_FS_44_1k
<< SGTL5000_SYS_FS_SHIFT
;
568 clk_ctl
|= SGTL5000_SYS_FS_48k
<< SGTL5000_SYS_FS_SHIFT
;
571 clk_ctl
|= SGTL5000_SYS_FS_96k
<< SGTL5000_SYS_FS_SHIFT
;
574 dev_err(codec
->dev
, "frame rate %d not supported\n",
580 * calculate the divider of mclk/sample_freq,
581 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
583 switch (sgtl5000
->sysclk
/ sys_fs
) {
585 clk_ctl
|= SGTL5000_MCLK_FREQ_256FS
<<
586 SGTL5000_MCLK_FREQ_SHIFT
;
589 clk_ctl
|= SGTL5000_MCLK_FREQ_384FS
<<
590 SGTL5000_MCLK_FREQ_SHIFT
;
593 clk_ctl
|= SGTL5000_MCLK_FREQ_512FS
<<
594 SGTL5000_MCLK_FREQ_SHIFT
;
597 /* if mclk not satisify the divider, use pll */
598 if (sgtl5000
->master
) {
599 clk_ctl
|= SGTL5000_MCLK_FREQ_PLL
<<
600 SGTL5000_MCLK_FREQ_SHIFT
;
603 "PLL not supported in slave mode\n");
608 /* if using pll, please check manual 6.4.2 for detail */
609 if ((clk_ctl
& SGTL5000_MCLK_FREQ_MASK
) == SGTL5000_MCLK_FREQ_PLL
) {
613 unsigned int in
, int_div
, frac_div
;
615 if (sgtl5000
->sysclk
> 17000000) {
617 in
= sgtl5000
->sysclk
/ 2;
620 in
= sgtl5000
->sysclk
;
631 pll_ctl
= int_div
<< SGTL5000_PLL_INT_DIV_SHIFT
|
632 frac_div
<< SGTL5000_PLL_FRAC_DIV_SHIFT
;
634 snd_soc_write(codec
, SGTL5000_CHIP_PLL_CTRL
, pll_ctl
);
636 snd_soc_update_bits(codec
,
637 SGTL5000_CHIP_CLK_TOP_CTRL
,
638 SGTL5000_INPUT_FREQ_DIV2
,
639 SGTL5000_INPUT_FREQ_DIV2
);
641 snd_soc_update_bits(codec
,
642 SGTL5000_CHIP_CLK_TOP_CTRL
,
643 SGTL5000_INPUT_FREQ_DIV2
,
647 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
648 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
649 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
);
652 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
653 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
657 /* if using pll, clk_ctrl must be set after pll power up */
658 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
, clk_ctl
);
664 * Set PCM DAI bit size and sample rate.
665 * input: params_rate, params_fmt
667 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream
*substream
,
668 struct snd_pcm_hw_params
*params
,
669 struct snd_soc_dai
*dai
)
671 struct snd_soc_codec
*codec
= dai
->codec
;
672 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
673 int channels
= params_channels(params
);
678 /* sysclk should already set */
679 if (!sgtl5000
->sysclk
) {
680 dev_err(codec
->dev
, "%s: set sysclk first!\n", __func__
);
684 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
685 stereo
= SGTL5000_DAC_STEREO
;
687 stereo
= SGTL5000_ADC_STEREO
;
689 /* set mono to save power */
690 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
, stereo
,
691 channels
== 1 ? 0 : stereo
);
693 /* set codec clock base on lrclk */
694 ret
= sgtl5000_set_clock(codec
, params_rate(params
));
698 /* set i2s data format */
699 switch (params_format(params
)) {
700 case SNDRV_PCM_FORMAT_S16_LE
:
701 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
703 i2s_ctl
|= SGTL5000_I2S_DLEN_16
<< SGTL5000_I2S_DLEN_SHIFT
;
704 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_32FS
<<
705 SGTL5000_I2S_SCLKFREQ_SHIFT
;
707 case SNDRV_PCM_FORMAT_S20_3LE
:
708 i2s_ctl
|= SGTL5000_I2S_DLEN_20
<< SGTL5000_I2S_DLEN_SHIFT
;
709 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
710 SGTL5000_I2S_SCLKFREQ_SHIFT
;
712 case SNDRV_PCM_FORMAT_S24_LE
:
713 i2s_ctl
|= SGTL5000_I2S_DLEN_24
<< SGTL5000_I2S_DLEN_SHIFT
;
714 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
715 SGTL5000_I2S_SCLKFREQ_SHIFT
;
717 case SNDRV_PCM_FORMAT_S32_LE
:
718 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
720 i2s_ctl
|= SGTL5000_I2S_DLEN_32
<< SGTL5000_I2S_DLEN_SHIFT
;
721 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
722 SGTL5000_I2S_SCLKFREQ_SHIFT
;
728 snd_soc_update_bits(codec
, SGTL5000_CHIP_I2S_CTRL
,
729 SGTL5000_I2S_DLEN_MASK
| SGTL5000_I2S_SCLKFREQ_MASK
,
735 #ifdef CONFIG_REGULATOR
736 static int ldo_regulator_is_enabled(struct regulator_dev
*dev
)
738 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
743 static int ldo_regulator_enable(struct regulator_dev
*dev
)
745 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
746 struct snd_soc_codec
*codec
= (struct snd_soc_codec
*)ldo
->codec_data
;
749 if (ldo_regulator_is_enabled(dev
))
752 /* set regulator value firstly */
753 reg
= (1600 - ldo
->voltage
/ 1000) / 50;
754 reg
= clamp(reg
, 0x0, 0xf);
756 /* amend the voltage value, unit: uV */
757 ldo
->voltage
= (1600 - reg
* 50) * 1000;
759 /* set voltage to register */
760 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
761 SGTL5000_LINREG_VDDD_MASK
, reg
);
763 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
764 SGTL5000_LINEREG_D_POWERUP
,
765 SGTL5000_LINEREG_D_POWERUP
);
767 /* when internal ldo enabled, simple digital power can be disabled */
768 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
769 SGTL5000_LINREG_SIMPLE_POWERUP
,
776 static int ldo_regulator_disable(struct regulator_dev
*dev
)
778 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
779 struct snd_soc_codec
*codec
= (struct snd_soc_codec
*)ldo
->codec_data
;
781 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
782 SGTL5000_LINEREG_D_POWERUP
,
785 /* clear voltage info */
786 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
787 SGTL5000_LINREG_VDDD_MASK
, 0);
794 static int ldo_regulator_get_voltage(struct regulator_dev
*dev
)
796 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
801 static struct regulator_ops ldo_regulator_ops
= {
802 .is_enabled
= ldo_regulator_is_enabled
,
803 .enable
= ldo_regulator_enable
,
804 .disable
= ldo_regulator_disable
,
805 .get_voltage
= ldo_regulator_get_voltage
,
808 static int ldo_regulator_register(struct snd_soc_codec
*codec
,
809 struct regulator_init_data
*init_data
,
812 struct ldo_regulator
*ldo
;
813 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
814 struct regulator_config config
= { };
816 ldo
= kzalloc(sizeof(struct ldo_regulator
), GFP_KERNEL
);
819 dev_err(codec
->dev
, "failed to allocate ldo_regulator\n");
823 ldo
->desc
.name
= kstrdup(dev_name(codec
->dev
), GFP_KERNEL
);
824 if (!ldo
->desc
.name
) {
826 dev_err(codec
->dev
, "failed to allocate decs name memory\n");
830 ldo
->desc
.type
= REGULATOR_VOLTAGE
;
831 ldo
->desc
.owner
= THIS_MODULE
;
832 ldo
->desc
.ops
= &ldo_regulator_ops
;
833 ldo
->desc
.n_voltages
= 1;
835 ldo
->codec_data
= codec
;
836 ldo
->voltage
= voltage
;
838 config
.dev
= codec
->dev
;
839 config
.driver_data
= ldo
;
840 config
.init_data
= init_data
;
842 ldo
->dev
= regulator_register(&ldo
->desc
, &config
);
843 if (IS_ERR(ldo
->dev
)) {
844 int ret
= PTR_ERR(ldo
->dev
);
846 dev_err(codec
->dev
, "failed to register regulator\n");
847 kfree(ldo
->desc
.name
);
857 static int ldo_regulator_remove(struct snd_soc_codec
*codec
)
859 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
860 struct ldo_regulator
*ldo
= sgtl5000
->ldo
;
865 regulator_unregister(ldo
->dev
);
866 kfree(ldo
->desc
.name
);
872 static int ldo_regulator_register(struct snd_soc_codec
*codec
,
873 struct regulator_init_data
*init_data
,
876 dev_err(codec
->dev
, "this setup needs regulator support in the kernel\n");
880 static int ldo_regulator_remove(struct snd_soc_codec
*codec
)
888 * common state changes:
890 * off --> standby --> prepare --> on
891 * standby --> prepare --> on
894 * on --> prepare --> standby
896 static int sgtl5000_set_bias_level(struct snd_soc_codec
*codec
,
897 enum snd_soc_bias_level level
)
900 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
903 case SND_SOC_BIAS_ON
:
904 case SND_SOC_BIAS_PREPARE
:
906 case SND_SOC_BIAS_STANDBY
:
907 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
908 ret
= regulator_bulk_enable(
909 ARRAY_SIZE(sgtl5000
->supplies
),
917 case SND_SOC_BIAS_OFF
:
918 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
923 codec
->dapm
.bias_level
= level
;
927 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
928 SNDRV_PCM_FMTBIT_S20_3LE |\
929 SNDRV_PCM_FMTBIT_S24_LE |\
930 SNDRV_PCM_FMTBIT_S32_LE)
932 static const struct snd_soc_dai_ops sgtl5000_ops
= {
933 .hw_params
= sgtl5000_pcm_hw_params
,
934 .digital_mute
= sgtl5000_digital_mute
,
935 .set_fmt
= sgtl5000_set_dai_fmt
,
936 .set_sysclk
= sgtl5000_set_dai_sysclk
,
939 static struct snd_soc_dai_driver sgtl5000_dai
= {
942 .stream_name
= "Playback",
946 * only support 8~48K + 96K,
947 * TODO modify hw_param to support more
949 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
950 .formats
= SGTL5000_FORMATS
,
953 .stream_name
= "Capture",
956 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
957 .formats
= SGTL5000_FORMATS
,
959 .ops
= &sgtl5000_ops
,
960 .symmetric_rates
= 1,
963 static bool sgtl5000_volatile(struct device
*dev
, unsigned int reg
)
966 case SGTL5000_CHIP_ID
:
967 case SGTL5000_CHIP_ADCDAC_CTRL
:
968 case SGTL5000_CHIP_ANA_STATUS
:
975 static bool sgtl5000_readable(struct device
*dev
, unsigned int reg
)
978 case SGTL5000_CHIP_ID
:
979 case SGTL5000_CHIP_DIG_POWER
:
980 case SGTL5000_CHIP_CLK_CTRL
:
981 case SGTL5000_CHIP_I2S_CTRL
:
982 case SGTL5000_CHIP_SSS_CTRL
:
983 case SGTL5000_CHIP_ADCDAC_CTRL
:
984 case SGTL5000_CHIP_DAC_VOL
:
985 case SGTL5000_CHIP_PAD_STRENGTH
:
986 case SGTL5000_CHIP_ANA_ADC_CTRL
:
987 case SGTL5000_CHIP_ANA_HP_CTRL
:
988 case SGTL5000_CHIP_ANA_CTRL
:
989 case SGTL5000_CHIP_LINREG_CTRL
:
990 case SGTL5000_CHIP_REF_CTRL
:
991 case SGTL5000_CHIP_MIC_CTRL
:
992 case SGTL5000_CHIP_LINE_OUT_CTRL
:
993 case SGTL5000_CHIP_LINE_OUT_VOL
:
994 case SGTL5000_CHIP_ANA_POWER
:
995 case SGTL5000_CHIP_PLL_CTRL
:
996 case SGTL5000_CHIP_CLK_TOP_CTRL
:
997 case SGTL5000_CHIP_ANA_STATUS
:
998 case SGTL5000_CHIP_SHORT_CTRL
:
999 case SGTL5000_CHIP_ANA_TEST2
:
1000 case SGTL5000_DAP_CTRL
:
1001 case SGTL5000_DAP_PEQ
:
1002 case SGTL5000_DAP_BASS_ENHANCE
:
1003 case SGTL5000_DAP_BASS_ENHANCE_CTRL
:
1004 case SGTL5000_DAP_AUDIO_EQ
:
1005 case SGTL5000_DAP_SURROUND
:
1006 case SGTL5000_DAP_FLT_COEF_ACCESS
:
1007 case SGTL5000_DAP_COEF_WR_B0_MSB
:
1008 case SGTL5000_DAP_COEF_WR_B0_LSB
:
1009 case SGTL5000_DAP_EQ_BASS_BAND0
:
1010 case SGTL5000_DAP_EQ_BASS_BAND1
:
1011 case SGTL5000_DAP_EQ_BASS_BAND2
:
1012 case SGTL5000_DAP_EQ_BASS_BAND3
:
1013 case SGTL5000_DAP_EQ_BASS_BAND4
:
1014 case SGTL5000_DAP_MAIN_CHAN
:
1015 case SGTL5000_DAP_MIX_CHAN
:
1016 case SGTL5000_DAP_AVC_CTRL
:
1017 case SGTL5000_DAP_AVC_THRESHOLD
:
1018 case SGTL5000_DAP_AVC_ATTACK
:
1019 case SGTL5000_DAP_AVC_DECAY
:
1020 case SGTL5000_DAP_COEF_WR_B1_MSB
:
1021 case SGTL5000_DAP_COEF_WR_B1_LSB
:
1022 case SGTL5000_DAP_COEF_WR_B2_MSB
:
1023 case SGTL5000_DAP_COEF_WR_B2_LSB
:
1024 case SGTL5000_DAP_COEF_WR_A1_MSB
:
1025 case SGTL5000_DAP_COEF_WR_A1_LSB
:
1026 case SGTL5000_DAP_COEF_WR_A2_MSB
:
1027 case SGTL5000_DAP_COEF_WR_A2_LSB
:
1035 #ifdef CONFIG_SUSPEND
1036 static int sgtl5000_suspend(struct snd_soc_codec
*codec
)
1038 sgtl5000_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1044 * restore all sgtl5000 registers,
1045 * since a big hole between dap and regular registers,
1046 * we will restore them respectively.
1048 static int sgtl5000_restore_regs(struct snd_soc_codec
*codec
)
1050 u16
*cache
= codec
->reg_cache
;
1053 /* restore regular registers */
1054 for (reg
= 0; reg
<= SGTL5000_CHIP_SHORT_CTRL
; reg
+= 2) {
1056 /* These regs should restore in particular order */
1057 if (reg
== SGTL5000_CHIP_ANA_POWER
||
1058 reg
== SGTL5000_CHIP_CLK_CTRL
||
1059 reg
== SGTL5000_CHIP_LINREG_CTRL
||
1060 reg
== SGTL5000_CHIP_LINE_OUT_CTRL
||
1061 reg
== SGTL5000_CHIP_REF_CTRL
)
1064 snd_soc_write(codec
, reg
, cache
[reg
]);
1067 /* restore dap registers */
1068 for (reg
= SGTL5000_DAP_REG_OFFSET
; reg
< SGTL5000_MAX_REG_OFFSET
; reg
+= 2)
1069 snd_soc_write(codec
, reg
, cache
[reg
]);
1072 * restore these regs according to the power setting sequence in
1073 * sgtl5000_set_power_regs() and clock setting sequence in
1074 * sgtl5000_set_clock().
1076 * The order of restore is:
1077 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1078 * SGTL5000_CHIP_ANA_POWER PLL bits set
1079 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1080 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1081 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1082 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
1084 snd_soc_write(codec
, SGTL5000_CHIP_LINREG_CTRL
,
1085 cache
[SGTL5000_CHIP_LINREG_CTRL
]);
1087 snd_soc_write(codec
, SGTL5000_CHIP_ANA_POWER
,
1088 cache
[SGTL5000_CHIP_ANA_POWER
]);
1090 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
,
1091 cache
[SGTL5000_CHIP_CLK_CTRL
]);
1093 snd_soc_write(codec
, SGTL5000_CHIP_REF_CTRL
,
1094 cache
[SGTL5000_CHIP_REF_CTRL
]);
1096 snd_soc_write(codec
, SGTL5000_CHIP_LINE_OUT_CTRL
,
1097 cache
[SGTL5000_CHIP_LINE_OUT_CTRL
]);
1101 static int sgtl5000_resume(struct snd_soc_codec
*codec
)
1103 /* Bring the codec back up to standby to enable regulators */
1104 sgtl5000_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1106 /* Restore registers by cached in memory */
1107 sgtl5000_restore_regs(codec
);
1111 #define sgtl5000_suspend NULL
1112 #define sgtl5000_resume NULL
1113 #endif /* CONFIG_SUSPEND */
1116 * sgtl5000 has 3 internal power supplies:
1117 * 1. VAG, normally set to vdda/2
1118 * 2. chargepump, set to different value
1119 * according to voltage of vdda and vddio
1120 * 3. line out VAG, normally set to vddio/2
1122 * and should be set according to:
1123 * 1. vddd provided by external or not
1124 * 2. vdda and vddio voltage value. > 3.1v or not
1125 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1127 static int sgtl5000_set_power_regs(struct snd_soc_codec
*codec
)
1135 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1137 vdda
= regulator_get_voltage(sgtl5000
->supplies
[VDDA
].consumer
);
1138 vddio
= regulator_get_voltage(sgtl5000
->supplies
[VDDIO
].consumer
);
1139 vddd
= regulator_get_voltage(sgtl5000
->supplies
[VDDD
].consumer
);
1142 vddio
= vddio
/ 1000;
1145 if (vdda
<= 0 || vddio
<= 0 || vddd
< 0) {
1146 dev_err(codec
->dev
, "regulator voltage not set correctly\n");
1151 /* according to datasheet, maximum voltage of supplies */
1152 if (vdda
> 3600 || vddio
> 3600 || vddd
> 1980) {
1154 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1161 ana_pwr
= snd_soc_read(codec
, SGTL5000_CHIP_ANA_POWER
);
1162 ana_pwr
|= SGTL5000_DAC_STEREO
|
1163 SGTL5000_ADC_STEREO
|
1164 SGTL5000_REFTOP_POWERUP
;
1165 lreg_ctrl
= snd_soc_read(codec
, SGTL5000_CHIP_LINREG_CTRL
);
1167 if (vddio
< 3100 && vdda
< 3100) {
1168 /* enable internal oscillator used for charge pump */
1169 snd_soc_update_bits(codec
, SGTL5000_CHIP_CLK_TOP_CTRL
,
1170 SGTL5000_INT_OSC_EN
,
1171 SGTL5000_INT_OSC_EN
);
1172 /* Enable VDDC charge pump */
1173 ana_pwr
|= SGTL5000_VDDC_CHRGPMP_POWERUP
;
1174 } else if (vddio
>= 3100 && vdda
>= 3100) {
1176 * if vddio and vddd > 3.1v,
1177 * charge pump should be clean before set ana_pwr
1179 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
1180 SGTL5000_VDDC_CHRGPMP_POWERUP
, 0);
1182 /* VDDC use VDDIO rail */
1183 lreg_ctrl
|= SGTL5000_VDDC_ASSN_OVRD
;
1184 lreg_ctrl
|= SGTL5000_VDDC_MAN_ASSN_VDDIO
<<
1185 SGTL5000_VDDC_MAN_ASSN_SHIFT
;
1188 snd_soc_write(codec
, SGTL5000_CHIP_LINREG_CTRL
, lreg_ctrl
);
1190 snd_soc_write(codec
, SGTL5000_CHIP_ANA_POWER
, ana_pwr
);
1192 /* set voltage to register */
1193 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
1194 SGTL5000_LINREG_VDDD_MASK
, 0x8);
1197 * if vddd linear reg has been enabled,
1198 * simple digital supply should be clear to get
1199 * proper VDDD voltage.
1201 if (ana_pwr
& SGTL5000_LINEREG_D_POWERUP
)
1202 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
1203 SGTL5000_LINREG_SIMPLE_POWERUP
,
1206 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
1207 SGTL5000_LINREG_SIMPLE_POWERUP
|
1208 SGTL5000_STARTUP_POWERUP
,
1212 * set ADC/DAC VAG to vdda / 2,
1213 * should stay in range (0.8v, 1.575v)
1216 if (vag
<= SGTL5000_ANA_GND_BASE
)
1218 else if (vag
>= SGTL5000_ANA_GND_BASE
+ SGTL5000_ANA_GND_STP
*
1219 (SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
))
1220 vag
= SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
;
1222 vag
= (vag
- SGTL5000_ANA_GND_BASE
) / SGTL5000_ANA_GND_STP
;
1224 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1225 SGTL5000_ANA_GND_MASK
, vag
<< SGTL5000_ANA_GND_SHIFT
);
1227 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1229 if (vag
<= SGTL5000_LINE_OUT_GND_BASE
)
1231 else if (vag
>= SGTL5000_LINE_OUT_GND_BASE
+
1232 SGTL5000_LINE_OUT_GND_STP
* SGTL5000_LINE_OUT_GND_MAX
)
1233 vag
= SGTL5000_LINE_OUT_GND_MAX
;
1235 vag
= (vag
- SGTL5000_LINE_OUT_GND_BASE
) /
1236 SGTL5000_LINE_OUT_GND_STP
;
1238 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINE_OUT_CTRL
,
1239 SGTL5000_LINE_OUT_CURRENT_MASK
|
1240 SGTL5000_LINE_OUT_GND_MASK
,
1241 vag
<< SGTL5000_LINE_OUT_GND_SHIFT
|
1242 SGTL5000_LINE_OUT_CURRENT_360u
<<
1243 SGTL5000_LINE_OUT_CURRENT_SHIFT
);
1248 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec
*codec
)
1250 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1253 /* set internal ldo to 1.2v */
1254 ret
= ldo_regulator_register(codec
, &ldo_init_data
, LDO_VOLTAGE
);
1257 "Failed to register vddd internal supplies: %d\n", ret
);
1261 sgtl5000
->supplies
[VDDD
].supply
= LDO_CONSUMER_NAME
;
1263 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(sgtl5000
->supplies
),
1264 sgtl5000
->supplies
);
1267 ldo_regulator_remove(codec
);
1268 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
1272 dev_info(codec
->dev
, "Using internal LDO instead of VDDD\n");
1276 static int sgtl5000_enable_regulators(struct snd_soc_codec
*codec
)
1282 int external_vddd
= 0;
1283 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1285 for (i
= 0; i
< ARRAY_SIZE(sgtl5000
->supplies
); i
++)
1286 sgtl5000
->supplies
[i
].supply
= supply_names
[i
];
1288 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(sgtl5000
->supplies
),
1289 sgtl5000
->supplies
);
1293 ret
= sgtl5000_replace_vddd_with_ldo(codec
);
1298 ret
= regulator_bulk_enable(ARRAY_SIZE(sgtl5000
->supplies
),
1299 sgtl5000
->supplies
);
1301 goto err_regulator_free
;
1303 /* wait for all power rails bring up */
1307 * workaround for revision 0x11 and later,
1308 * roll back to use internal LDO
1311 ret
= regmap_read(sgtl5000
->regmap
, SGTL5000_CHIP_ID
, ®
);
1313 goto err_regulator_disable
;
1315 rev
= (reg
& SGTL5000_REVID_MASK
) >> SGTL5000_REVID_SHIFT
;
1317 if (external_vddd
&& rev
>= 0x11) {
1318 /* disable all regulator first */
1319 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1320 sgtl5000
->supplies
);
1321 /* free VDDD regulator */
1322 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1323 sgtl5000
->supplies
);
1325 ret
= sgtl5000_replace_vddd_with_ldo(codec
);
1329 ret
= regulator_bulk_enable(ARRAY_SIZE(sgtl5000
->supplies
),
1330 sgtl5000
->supplies
);
1332 goto err_regulator_free
;
1334 /* wait for all power rails bring up */
1340 err_regulator_disable
:
1341 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1342 sgtl5000
->supplies
);
1344 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1345 sgtl5000
->supplies
);
1347 ldo_regulator_remove(codec
);
1352 static int sgtl5000_probe(struct snd_soc_codec
*codec
)
1355 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1357 /* setup i2c data ops */
1358 codec
->control_data
= sgtl5000
->regmap
;
1359 ret
= snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
1361 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1365 ret
= sgtl5000_enable_regulators(codec
);
1369 /* power up sgtl5000 */
1370 ret
= sgtl5000_set_power_regs(codec
);
1374 /* enable small pop, introduce 400ms delay in turning off */
1375 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1377 SGTL5000_SMALL_POP
);
1379 /* disable short cut detector */
1380 snd_soc_write(codec
, SGTL5000_CHIP_SHORT_CTRL
, 0);
1383 * set i2s as default input of sound switch
1384 * TODO: add sound switch to control and dapm widge.
1386 snd_soc_write(codec
, SGTL5000_CHIP_SSS_CTRL
,
1387 SGTL5000_DAC_SEL_I2S_IN
<< SGTL5000_DAC_SEL_SHIFT
);
1388 snd_soc_write(codec
, SGTL5000_CHIP_DIG_POWER
,
1389 SGTL5000_ADC_EN
| SGTL5000_DAC_EN
);
1391 /* enable dac volume ramp by default */
1392 snd_soc_write(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
1393 SGTL5000_DAC_VOL_RAMP_EN
|
1394 SGTL5000_DAC_MUTE_RIGHT
|
1395 SGTL5000_DAC_MUTE_LEFT
);
1397 snd_soc_write(codec
, SGTL5000_CHIP_PAD_STRENGTH
, 0x015f);
1399 snd_soc_write(codec
, SGTL5000_CHIP_ANA_CTRL
,
1400 SGTL5000_HP_ZCD_EN
|
1401 SGTL5000_ADC_ZCD_EN
);
1403 snd_soc_write(codec
, SGTL5000_CHIP_MIC_CTRL
, 2);
1408 * Enable DAP in kcontrol and dapm.
1410 snd_soc_write(codec
, SGTL5000_DAP_CTRL
, 0);
1412 /* leading to standby state */
1413 ret
= sgtl5000_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1420 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1421 sgtl5000
->supplies
);
1422 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1423 sgtl5000
->supplies
);
1424 ldo_regulator_remove(codec
);
1429 static int sgtl5000_remove(struct snd_soc_codec
*codec
)
1431 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1433 sgtl5000_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1435 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1436 sgtl5000
->supplies
);
1437 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1438 sgtl5000
->supplies
);
1439 ldo_regulator_remove(codec
);
1444 static struct snd_soc_codec_driver sgtl5000_driver
= {
1445 .probe
= sgtl5000_probe
,
1446 .remove
= sgtl5000_remove
,
1447 .suspend
= sgtl5000_suspend
,
1448 .resume
= sgtl5000_resume
,
1449 .set_bias_level
= sgtl5000_set_bias_level
,
1450 .controls
= sgtl5000_snd_controls
,
1451 .num_controls
= ARRAY_SIZE(sgtl5000_snd_controls
),
1452 .dapm_widgets
= sgtl5000_dapm_widgets
,
1453 .num_dapm_widgets
= ARRAY_SIZE(sgtl5000_dapm_widgets
),
1454 .dapm_routes
= sgtl5000_dapm_routes
,
1455 .num_dapm_routes
= ARRAY_SIZE(sgtl5000_dapm_routes
),
1458 static const struct regmap_config sgtl5000_regmap
= {
1462 .max_register
= SGTL5000_MAX_REG_OFFSET
,
1463 .volatile_reg
= sgtl5000_volatile
,
1464 .readable_reg
= sgtl5000_readable
,
1466 .cache_type
= REGCACHE_RBTREE
,
1467 .reg_defaults
= sgtl5000_reg_defaults
,
1468 .num_reg_defaults
= ARRAY_SIZE(sgtl5000_reg_defaults
),
1472 * Write all the default values from sgtl5000_reg_defaults[] array into the
1473 * sgtl5000 registers, to make sure we always start with the sane registers
1474 * values as stated in the datasheet.
1476 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1477 * we follow this approach to guarantee we always start from the default values
1478 * and avoid problems like, not being able to probe after an audio playback
1479 * followed by a system reset or a 'reboot' command in Linux
1481 static int sgtl5000_fill_defaults(struct sgtl5000_priv
*sgtl5000
)
1483 int i
, ret
, val
, index
;
1485 for (i
= 0; i
< ARRAY_SIZE(sgtl5000_reg_defaults
); i
++) {
1486 val
= sgtl5000_reg_defaults
[i
].def
;
1487 index
= sgtl5000_reg_defaults
[i
].reg
;
1488 ret
= regmap_write(sgtl5000
->regmap
, index
, val
);
1496 static int sgtl5000_i2c_probe(struct i2c_client
*client
,
1497 const struct i2c_device_id
*id
)
1499 struct sgtl5000_priv
*sgtl5000
;
1502 sgtl5000
= devm_kzalloc(&client
->dev
, sizeof(struct sgtl5000_priv
),
1507 sgtl5000
->regmap
= devm_regmap_init_i2c(client
, &sgtl5000_regmap
);
1508 if (IS_ERR(sgtl5000
->regmap
)) {
1509 ret
= PTR_ERR(sgtl5000
->regmap
);
1510 dev_err(&client
->dev
, "Failed to allocate regmap: %d\n", ret
);
1514 /* read chip information */
1515 ret
= regmap_read(sgtl5000
->regmap
, SGTL5000_CHIP_ID
, ®
);
1519 if (((reg
& SGTL5000_PARTID_MASK
) >> SGTL5000_PARTID_SHIFT
) !=
1520 SGTL5000_PARTID_PART_ID
) {
1521 dev_err(&client
->dev
,
1522 "Device with ID register %x is not a sgtl5000\n", reg
);
1526 rev
= (reg
& SGTL5000_REVID_MASK
) >> SGTL5000_REVID_SHIFT
;
1527 dev_info(&client
->dev
, "sgtl5000 revision 0x%x\n", rev
);
1529 i2c_set_clientdata(client
, sgtl5000
);
1531 /* Ensure sgtl5000 will start with sane register values */
1532 ret
= sgtl5000_fill_defaults(sgtl5000
);
1536 ret
= snd_soc_register_codec(&client
->dev
,
1537 &sgtl5000_driver
, &sgtl5000_dai
, 1);
1541 static int sgtl5000_i2c_remove(struct i2c_client
*client
)
1543 snd_soc_unregister_codec(&client
->dev
);
1548 static const struct i2c_device_id sgtl5000_id
[] = {
1553 MODULE_DEVICE_TABLE(i2c
, sgtl5000_id
);
1555 static const struct of_device_id sgtl5000_dt_ids
[] = {
1556 { .compatible
= "fsl,sgtl5000", },
1559 MODULE_DEVICE_TABLE(of
, sgtl5000_dt_ids
);
1561 static struct i2c_driver sgtl5000_i2c_driver
= {
1564 .owner
= THIS_MODULE
,
1565 .of_match_table
= sgtl5000_dt_ids
,
1567 .probe
= sgtl5000_i2c_probe
,
1568 .remove
= sgtl5000_i2c_remove
,
1569 .id_table
= sgtl5000_id
,
1572 module_i2c_driver(sgtl5000_i2c_driver
);
1574 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1575 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1576 MODULE_LICENSE("GPL");