2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* default value of sgtl5000 registers */
39 static const struct reg_default sgtl5000_reg_defaults
[] = {
40 { SGTL5000_CHIP_DIG_POWER
, 0x0000 },
41 { SGTL5000_CHIP_CLK_CTRL
, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL
, 0x0010 },
43 { SGTL5000_CHIP_SSS_CTRL
, 0x0010 },
44 { SGTL5000_CHIP_ADCDAC_CTRL
, 0x020c },
45 { SGTL5000_CHIP_DAC_VOL
, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH
, 0x015f },
47 { SGTL5000_CHIP_ANA_ADC_CTRL
, 0x0000 },
48 { SGTL5000_CHIP_ANA_HP_CTRL
, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL
, 0x0111 },
50 { SGTL5000_CHIP_LINREG_CTRL
, 0x0000 },
51 { SGTL5000_CHIP_REF_CTRL
, 0x0000 },
52 { SGTL5000_CHIP_MIC_CTRL
, 0x0000 },
53 { SGTL5000_CHIP_LINE_OUT_CTRL
, 0x0000 },
54 { SGTL5000_CHIP_LINE_OUT_VOL
, 0x0404 },
55 { SGTL5000_CHIP_ANA_POWER
, 0x7060 },
56 { SGTL5000_CHIP_PLL_CTRL
, 0x5000 },
57 { SGTL5000_CHIP_CLK_TOP_CTRL
, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS
, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL
, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2
, 0x0000 },
61 { SGTL5000_DAP_CTRL
, 0x0000 },
62 { SGTL5000_DAP_PEQ
, 0x0000 },
63 { SGTL5000_DAP_BASS_ENHANCE
, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL
, 0x051f },
65 { SGTL5000_DAP_AUDIO_EQ
, 0x0000 },
66 { SGTL5000_DAP_SURROUND
, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0
, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1
, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2
, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3
, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4
, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN
, 0x8000 },
73 { SGTL5000_DAP_MIX_CHAN
, 0x0000 },
74 { SGTL5000_DAP_AVC_CTRL
, 0x0510 },
75 { SGTL5000_DAP_AVC_THRESHOLD
, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK
, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY
, 0x0050 },
80 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
81 enum sgtl5000_regulator_supplies
{
88 /* vddd is optional supply */
89 static const char *supply_names
[SGTL5000_SUPPLY_NUM
] = {
95 #define LDO_CONSUMER_NAME "VDDD_LDO"
96 #define LDO_VOLTAGE 1200000
98 static struct regulator_consumer_supply ldo_consumer
[] = {
99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME
, NULL
),
102 static struct regulator_init_data ldo_init_data
= {
106 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
107 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
109 .num_consumer_supplies
= 1,
110 .consumer_supplies
= &ldo_consumer
[0],
114 * sgtl5000 internal ldo regulator,
115 * enabled when VDDD not provided
117 struct ldo_regulator
{
118 struct regulator_desc desc
;
119 struct regulator_dev
*dev
;
125 enum sgtl5000_micbias_resistor
{
126 SGTL5000_MICBIAS_OFF
= 0,
127 SGTL5000_MICBIAS_2K
= 2,
128 SGTL5000_MICBIAS_4K
= 4,
129 SGTL5000_MICBIAS_8K
= 8,
132 /* sgtl5000 private structure in codec */
133 struct sgtl5000_priv
{
134 int sysclk
; /* sysclk rate */
135 int master
; /* i2s master or not */
136 int fmt
; /* i2s data format */
137 struct regulator_bulk_data supplies
[SGTL5000_SUPPLY_NUM
];
138 struct ldo_regulator
*ldo
;
139 struct regmap
*regmap
;
147 * mic_bias power on/off share the same register bits with
148 * output impedance of mic bias, when power on mic bias, we
149 * need reclaim it to impedance value.
155 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
156 struct snd_kcontrol
*kcontrol
, int event
)
158 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
159 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
162 case SND_SOC_DAPM_POST_PMU
:
163 /* change mic bias resistor */
164 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
165 SGTL5000_BIAS_R_MASK
,
166 sgtl5000
->micbias_resistor
<< SGTL5000_BIAS_R_SHIFT
);
169 case SND_SOC_DAPM_PRE_PMD
:
170 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
171 SGTL5000_BIAS_R_MASK
, 0);
178 * As manual described, ADC/DAC only works when VAG powerup,
179 * So enabled VAG before ADC/DAC up.
180 * In power down case, we need wait 400ms when vag fully ramped down.
182 static int power_vag_event(struct snd_soc_dapm_widget
*w
,
183 struct snd_kcontrol
*kcontrol
, int event
)
185 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
186 const u32 mask
= SGTL5000_DAC_POWERUP
| SGTL5000_ADC_POWERUP
;
189 case SND_SOC_DAPM_POST_PMU
:
190 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
191 SGTL5000_VAG_POWERUP
, SGTL5000_VAG_POWERUP
);
194 case SND_SOC_DAPM_PRE_PMD
:
196 * Don't clear VAG_POWERUP, when both DAC and ADC are
197 * operational to prevent inadvertently starving the
200 if ((snd_soc_read(codec
, SGTL5000_CHIP_ANA_POWER
) &
202 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
203 SGTL5000_VAG_POWERUP
, 0);
214 /* input sources for ADC */
215 static const char *adc_mux_text
[] = {
219 static SOC_ENUM_SINGLE_DECL(adc_enum
,
220 SGTL5000_CHIP_ANA_CTRL
, 2,
223 static const struct snd_kcontrol_new adc_mux
=
224 SOC_DAPM_ENUM("Capture Mux", adc_enum
);
226 /* input sources for DAC */
227 static const char *dac_mux_text
[] = {
231 static SOC_ENUM_SINGLE_DECL(dac_enum
,
232 SGTL5000_CHIP_ANA_CTRL
, 6,
235 static const struct snd_kcontrol_new dac_mux
=
236 SOC_DAPM_ENUM("Headphone Mux", dac_enum
);
238 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets
[] = {
239 SND_SOC_DAPM_INPUT("LINE_IN"),
240 SND_SOC_DAPM_INPUT("MIC_IN"),
242 SND_SOC_DAPM_OUTPUT("HP_OUT"),
243 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
245 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL
, 8, 0,
247 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
249 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER
, 4, 0, NULL
, 0),
250 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER
, 0, 0, NULL
, 0),
252 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM
, 0, 0, &adc_mux
),
253 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM
, 0, 0, &dac_mux
),
255 /* aif for i2s input */
256 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
257 0, SGTL5000_CHIP_DIG_POWER
,
260 /* aif for i2s output */
261 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
262 0, SGTL5000_CHIP_DIG_POWER
,
265 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER
, 1, 0),
266 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER
, 3, 0),
268 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event
),
269 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event
),
272 /* routes for sgtl5000 */
273 static const struct snd_soc_dapm_route sgtl5000_dapm_routes
[] = {
274 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
275 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
277 {"ADC", NULL
, "Capture Mux"}, /* adc_mux --> adc */
278 {"AIFOUT", NULL
, "ADC"}, /* adc --> i2s_out */
280 {"DAC", NULL
, "AIFIN"}, /* i2s-->dac,skip audio mux */
281 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
282 {"LO", NULL
, "DAC"}, /* dac --> line_out */
284 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
285 {"HP", NULL
, "Headphone Mux"}, /* hp_mux --> hp */
287 {"LINE_OUT", NULL
, "LO"},
288 {"HP_OUT", NULL
, "HP"},
291 /* custom function to fetch info of PCM playback volume */
292 static int dac_info_volsw(struct snd_kcontrol
*kcontrol
,
293 struct snd_ctl_elem_info
*uinfo
)
295 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
297 uinfo
->value
.integer
.min
= 0;
298 uinfo
->value
.integer
.max
= 0xfc - 0x3c;
303 * custom function to get of PCM playback volume
305 * dac volume register
306 * 15-------------8-7--------------0
307 * | R channel vol | L channel vol |
308 * -------------------------------
310 * PCM volume with 0.5017 dB steps from 0 to -90 dB
312 * register values map to dB
313 * 0x3B and less = Reserved
317 * 0xFC and greater = Muted
319 * register value map to userspace value
321 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
322 * ------------------------------
323 * userspace value 0xc0 0
325 static int dac_get_volsw(struct snd_kcontrol
*kcontrol
,
326 struct snd_ctl_elem_value
*ucontrol
)
328 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
333 reg
= snd_soc_read(codec
, SGTL5000_CHIP_DAC_VOL
);
335 /* get left channel volume */
336 l
= (reg
& SGTL5000_DAC_VOL_LEFT_MASK
) >> SGTL5000_DAC_VOL_LEFT_SHIFT
;
338 /* get right channel volume */
339 r
= (reg
& SGTL5000_DAC_VOL_RIGHT_MASK
) >> SGTL5000_DAC_VOL_RIGHT_SHIFT
;
341 /* make sure value fall in (0x3c,0xfc) */
342 l
= clamp(l
, 0x3c, 0xfc);
343 r
= clamp(r
, 0x3c, 0xfc);
345 /* invert it and map to userspace value */
349 ucontrol
->value
.integer
.value
[0] = l
;
350 ucontrol
->value
.integer
.value
[1] = r
;
356 * custom function to put of PCM playback volume
358 * dac volume register
359 * 15-------------8-7--------------0
360 * | R channel vol | L channel vol |
361 * -------------------------------
363 * PCM volume with 0.5017 dB steps from 0 to -90 dB
365 * register values map to dB
366 * 0x3B and less = Reserved
370 * 0xFC and greater = Muted
372 * userspace value map to register value
374 * userspace value 0xc0 0
375 * ------------------------------
376 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
378 static int dac_put_volsw(struct snd_kcontrol
*kcontrol
,
379 struct snd_ctl_elem_value
*ucontrol
)
381 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
386 l
= ucontrol
->value
.integer
.value
[0];
387 r
= ucontrol
->value
.integer
.value
[1];
389 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
390 l
= clamp(l
, 0, 0xfc - 0x3c);
391 r
= clamp(r
, 0, 0xfc - 0x3c);
393 /* invert it, get the value can be set to register */
397 /* shift to get the register value */
398 reg
= l
<< SGTL5000_DAC_VOL_LEFT_SHIFT
|
399 r
<< SGTL5000_DAC_VOL_RIGHT_SHIFT
;
401 snd_soc_write(codec
, SGTL5000_CHIP_DAC_VOL
, reg
);
406 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate
, -600, 600, 0);
408 /* tlv for mic gain, 0db 20db 30db 40db */
409 static const unsigned int mic_gain_tlv
[] = {
410 TLV_DB_RANGE_HEAD(2),
411 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
412 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
415 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
416 static const DECLARE_TLV_DB_SCALE(headphone_volume
, -5150, 50, 0);
418 static const struct snd_kcontrol_new sgtl5000_snd_controls
[] = {
419 /* SOC_DOUBLE_S8_TLV with invert */
421 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
422 .name
= "PCM Playback Volume",
423 .access
= SNDRV_CTL_ELEM_ACCESS_TLV_READ
|
424 SNDRV_CTL_ELEM_ACCESS_READWRITE
,
425 .info
= dac_info_volsw
,
426 .get
= dac_get_volsw
,
427 .put
= dac_put_volsw
,
430 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL
, 0, 4, 0xf, 0),
431 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
432 SGTL5000_CHIP_ANA_ADC_CTRL
,
433 8, 1, 0, capture_6db_attenuate
),
434 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL
, 1, 1, 0),
436 SOC_DOUBLE_TLV("Headphone Playback Volume",
437 SGTL5000_CHIP_ANA_HP_CTRL
,
441 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL
,
444 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL
,
445 0, 3, 0, mic_gain_tlv
),
448 /* mute the codec used by alsa core */
449 static int sgtl5000_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
451 struct snd_soc_codec
*codec
= codec_dai
->codec
;
452 u16 adcdac_ctrl
= SGTL5000_DAC_MUTE_LEFT
| SGTL5000_DAC_MUTE_RIGHT
;
454 snd_soc_update_bits(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
455 adcdac_ctrl
, mute
? adcdac_ctrl
: 0);
460 /* set codec format */
461 static int sgtl5000_set_dai_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
463 struct snd_soc_codec
*codec
= codec_dai
->codec
;
464 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
467 sgtl5000
->master
= 0;
469 * i2s clock and frame master setting.
471 * - clock and frame slave,
472 * - clock and frame master
474 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
475 case SND_SOC_DAIFMT_CBS_CFS
:
477 case SND_SOC_DAIFMT_CBM_CFM
:
478 i2sctl
|= SGTL5000_I2S_MASTER
;
479 sgtl5000
->master
= 1;
485 /* setting i2s data format */
486 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
487 case SND_SOC_DAIFMT_DSP_A
:
488 i2sctl
|= SGTL5000_I2S_MODE_PCM
<< SGTL5000_I2S_MODE_SHIFT
;
490 case SND_SOC_DAIFMT_DSP_B
:
491 i2sctl
|= SGTL5000_I2S_MODE_PCM
<< SGTL5000_I2S_MODE_SHIFT
;
492 i2sctl
|= SGTL5000_I2S_LRALIGN
;
494 case SND_SOC_DAIFMT_I2S
:
495 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
<< SGTL5000_I2S_MODE_SHIFT
;
497 case SND_SOC_DAIFMT_RIGHT_J
:
498 i2sctl
|= SGTL5000_I2S_MODE_RJ
<< SGTL5000_I2S_MODE_SHIFT
;
499 i2sctl
|= SGTL5000_I2S_LRPOL
;
501 case SND_SOC_DAIFMT_LEFT_J
:
502 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
<< SGTL5000_I2S_MODE_SHIFT
;
503 i2sctl
|= SGTL5000_I2S_LRALIGN
;
509 sgtl5000
->fmt
= fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
511 /* Clock inversion */
512 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
513 case SND_SOC_DAIFMT_NB_NF
:
515 case SND_SOC_DAIFMT_IB_NF
:
516 i2sctl
|= SGTL5000_I2S_SCLK_INV
;
522 snd_soc_write(codec
, SGTL5000_CHIP_I2S_CTRL
, i2sctl
);
527 /* set codec sysclk */
528 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
529 int clk_id
, unsigned int freq
, int dir
)
531 struct snd_soc_codec
*codec
= codec_dai
->codec
;
532 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
535 case SGTL5000_SYSCLK
:
536 sgtl5000
->sysclk
= freq
;
546 * set clock according to i2s frame clock,
547 * sgtl5000 provides 2 clock sources:
548 * 1. sys_mclk: sample freq can only be configured to
549 * 1/256, 1/384, 1/512 of sys_mclk.
550 * 2. pll: can derive any audio clocks.
552 * clock setting rules:
553 * 1. in slave mode, only sys_mclk can be used
554 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
556 * 3. usage of sys_mclk is preferred over pll to save power.
558 static int sgtl5000_set_clock(struct snd_soc_codec
*codec
, int frame_rate
)
560 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
562 int sys_fs
; /* sample freq */
565 * sample freq should be divided by frame clock,
566 * if frame clock is lower than 44.1 kHz, sample freq should be set to
567 * 32 kHz or 44.1 kHz.
569 switch (frame_rate
) {
583 /* set divided factor of frame clock */
584 switch (sys_fs
/ frame_rate
) {
586 clk_ctl
|= SGTL5000_RATE_MODE_DIV_4
<< SGTL5000_RATE_MODE_SHIFT
;
589 clk_ctl
|= SGTL5000_RATE_MODE_DIV_2
<< SGTL5000_RATE_MODE_SHIFT
;
592 clk_ctl
|= SGTL5000_RATE_MODE_DIV_1
<< SGTL5000_RATE_MODE_SHIFT
;
598 /* set the sys_fs according to frame rate */
601 clk_ctl
|= SGTL5000_SYS_FS_32k
<< SGTL5000_SYS_FS_SHIFT
;
604 clk_ctl
|= SGTL5000_SYS_FS_44_1k
<< SGTL5000_SYS_FS_SHIFT
;
607 clk_ctl
|= SGTL5000_SYS_FS_48k
<< SGTL5000_SYS_FS_SHIFT
;
610 clk_ctl
|= SGTL5000_SYS_FS_96k
<< SGTL5000_SYS_FS_SHIFT
;
613 dev_err(codec
->dev
, "frame rate %d not supported\n",
619 * calculate the divider of mclk/sample_freq,
620 * factor of freq = 96 kHz can only be 256, since mclk is in the range
623 switch (sgtl5000
->sysclk
/ frame_rate
) {
625 clk_ctl
|= SGTL5000_MCLK_FREQ_256FS
<<
626 SGTL5000_MCLK_FREQ_SHIFT
;
629 clk_ctl
|= SGTL5000_MCLK_FREQ_384FS
<<
630 SGTL5000_MCLK_FREQ_SHIFT
;
633 clk_ctl
|= SGTL5000_MCLK_FREQ_512FS
<<
634 SGTL5000_MCLK_FREQ_SHIFT
;
637 /* if mclk does not satisfy the divider, use pll */
638 if (sgtl5000
->master
) {
639 clk_ctl
|= SGTL5000_MCLK_FREQ_PLL
<<
640 SGTL5000_MCLK_FREQ_SHIFT
;
643 "PLL not supported in slave mode\n");
644 dev_err(codec
->dev
, "%d ratio is not supported. "
645 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
646 sgtl5000
->sysclk
/ frame_rate
);
651 /* if using pll, please check manual 6.4.2 for detail */
652 if ((clk_ctl
& SGTL5000_MCLK_FREQ_MASK
) == SGTL5000_MCLK_FREQ_PLL
) {
656 unsigned int in
, int_div
, frac_div
;
658 if (sgtl5000
->sysclk
> 17000000) {
660 in
= sgtl5000
->sysclk
/ 2;
663 in
= sgtl5000
->sysclk
;
674 pll_ctl
= int_div
<< SGTL5000_PLL_INT_DIV_SHIFT
|
675 frac_div
<< SGTL5000_PLL_FRAC_DIV_SHIFT
;
677 snd_soc_write(codec
, SGTL5000_CHIP_PLL_CTRL
, pll_ctl
);
679 snd_soc_update_bits(codec
,
680 SGTL5000_CHIP_CLK_TOP_CTRL
,
681 SGTL5000_INPUT_FREQ_DIV2
,
682 SGTL5000_INPUT_FREQ_DIV2
);
684 snd_soc_update_bits(codec
,
685 SGTL5000_CHIP_CLK_TOP_CTRL
,
686 SGTL5000_INPUT_FREQ_DIV2
,
690 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
691 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
692 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
);
694 /* if using pll, clk_ctrl must be set after pll power up */
695 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
, clk_ctl
);
697 /* otherwise, clk_ctrl must be set before pll power down */
698 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
, clk_ctl
);
701 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
702 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
710 * Set PCM DAI bit size and sample rate.
711 * input: params_rate, params_fmt
713 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream
*substream
,
714 struct snd_pcm_hw_params
*params
,
715 struct snd_soc_dai
*dai
)
717 struct snd_soc_codec
*codec
= dai
->codec
;
718 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
719 int channels
= params_channels(params
);
724 /* sysclk should already set */
725 if (!sgtl5000
->sysclk
) {
726 dev_err(codec
->dev
, "%s: set sysclk first!\n", __func__
);
730 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
731 stereo
= SGTL5000_DAC_STEREO
;
733 stereo
= SGTL5000_ADC_STEREO
;
735 /* set mono to save power */
736 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
, stereo
,
737 channels
== 1 ? 0 : stereo
);
739 /* set codec clock base on lrclk */
740 ret
= sgtl5000_set_clock(codec
, params_rate(params
));
744 /* set i2s data format */
745 switch (params_width(params
)) {
747 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
749 i2s_ctl
|= SGTL5000_I2S_DLEN_16
<< SGTL5000_I2S_DLEN_SHIFT
;
750 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_32FS
<<
751 SGTL5000_I2S_SCLKFREQ_SHIFT
;
754 i2s_ctl
|= SGTL5000_I2S_DLEN_20
<< SGTL5000_I2S_DLEN_SHIFT
;
755 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
756 SGTL5000_I2S_SCLKFREQ_SHIFT
;
759 i2s_ctl
|= SGTL5000_I2S_DLEN_24
<< SGTL5000_I2S_DLEN_SHIFT
;
760 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
761 SGTL5000_I2S_SCLKFREQ_SHIFT
;
764 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
766 i2s_ctl
|= SGTL5000_I2S_DLEN_32
<< SGTL5000_I2S_DLEN_SHIFT
;
767 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
768 SGTL5000_I2S_SCLKFREQ_SHIFT
;
774 snd_soc_update_bits(codec
, SGTL5000_CHIP_I2S_CTRL
,
775 SGTL5000_I2S_DLEN_MASK
| SGTL5000_I2S_SCLKFREQ_MASK
,
781 #ifdef CONFIG_REGULATOR
782 static int ldo_regulator_is_enabled(struct regulator_dev
*dev
)
784 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
789 static int ldo_regulator_enable(struct regulator_dev
*dev
)
791 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
792 struct snd_soc_codec
*codec
= (struct snd_soc_codec
*)ldo
->codec_data
;
795 if (ldo_regulator_is_enabled(dev
))
798 /* set regulator value firstly */
799 reg
= (1600 - ldo
->voltage
/ 1000) / 50;
800 reg
= clamp(reg
, 0x0, 0xf);
802 /* amend the voltage value, unit: uV */
803 ldo
->voltage
= (1600 - reg
* 50) * 1000;
805 /* set voltage to register */
806 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
807 SGTL5000_LINREG_VDDD_MASK
, reg
);
809 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
810 SGTL5000_LINEREG_D_POWERUP
,
811 SGTL5000_LINEREG_D_POWERUP
);
813 /* when internal ldo is enabled, simple digital power can be disabled */
814 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
815 SGTL5000_LINREG_SIMPLE_POWERUP
,
822 static int ldo_regulator_disable(struct regulator_dev
*dev
)
824 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
825 struct snd_soc_codec
*codec
= (struct snd_soc_codec
*)ldo
->codec_data
;
827 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
828 SGTL5000_LINEREG_D_POWERUP
,
831 /* clear voltage info */
832 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
833 SGTL5000_LINREG_VDDD_MASK
, 0);
840 static int ldo_regulator_get_voltage(struct regulator_dev
*dev
)
842 struct ldo_regulator
*ldo
= rdev_get_drvdata(dev
);
847 static struct regulator_ops ldo_regulator_ops
= {
848 .is_enabled
= ldo_regulator_is_enabled
,
849 .enable
= ldo_regulator_enable
,
850 .disable
= ldo_regulator_disable
,
851 .get_voltage
= ldo_regulator_get_voltage
,
854 static int ldo_regulator_register(struct snd_soc_codec
*codec
,
855 struct regulator_init_data
*init_data
,
858 struct ldo_regulator
*ldo
;
859 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
860 struct regulator_config config
= { };
862 ldo
= kzalloc(sizeof(struct ldo_regulator
), GFP_KERNEL
);
867 ldo
->desc
.name
= kstrdup(dev_name(codec
->dev
), GFP_KERNEL
);
868 if (!ldo
->desc
.name
) {
870 dev_err(codec
->dev
, "failed to allocate decs name memory\n");
874 ldo
->desc
.type
= REGULATOR_VOLTAGE
;
875 ldo
->desc
.owner
= THIS_MODULE
;
876 ldo
->desc
.ops
= &ldo_regulator_ops
;
877 ldo
->desc
.n_voltages
= 1;
879 ldo
->codec_data
= codec
;
880 ldo
->voltage
= voltage
;
882 config
.dev
= codec
->dev
;
883 config
.driver_data
= ldo
;
884 config
.init_data
= init_data
;
886 ldo
->dev
= regulator_register(&ldo
->desc
, &config
);
887 if (IS_ERR(ldo
->dev
)) {
888 int ret
= PTR_ERR(ldo
->dev
);
890 dev_err(codec
->dev
, "failed to register regulator\n");
891 kfree(ldo
->desc
.name
);
901 static int ldo_regulator_remove(struct snd_soc_codec
*codec
)
903 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
904 struct ldo_regulator
*ldo
= sgtl5000
->ldo
;
909 regulator_unregister(ldo
->dev
);
910 kfree(ldo
->desc
.name
);
916 static int ldo_regulator_register(struct snd_soc_codec
*codec
,
917 struct regulator_init_data
*init_data
,
920 dev_err(codec
->dev
, "this setup needs regulator support in the kernel\n");
924 static int ldo_regulator_remove(struct snd_soc_codec
*codec
)
932 * common state changes:
934 * off --> standby --> prepare --> on
935 * standby --> prepare --> on
938 * on --> prepare --> standby
940 static int sgtl5000_set_bias_level(struct snd_soc_codec
*codec
,
941 enum snd_soc_bias_level level
)
944 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
947 case SND_SOC_BIAS_ON
:
948 case SND_SOC_BIAS_PREPARE
:
950 case SND_SOC_BIAS_STANDBY
:
951 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
) {
952 ret
= regulator_bulk_enable(
953 ARRAY_SIZE(sgtl5000
->supplies
),
959 regcache_cache_only(sgtl5000
->regmap
, false);
961 ret
= regcache_sync(sgtl5000
->regmap
);
964 "Failed to restore cache: %d\n", ret
);
966 regcache_cache_only(sgtl5000
->regmap
, true);
967 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
975 case SND_SOC_BIAS_OFF
:
976 regcache_cache_only(sgtl5000
->regmap
, true);
977 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
985 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
986 SNDRV_PCM_FMTBIT_S20_3LE |\
987 SNDRV_PCM_FMTBIT_S24_LE |\
988 SNDRV_PCM_FMTBIT_S32_LE)
990 static const struct snd_soc_dai_ops sgtl5000_ops
= {
991 .hw_params
= sgtl5000_pcm_hw_params
,
992 .digital_mute
= sgtl5000_digital_mute
,
993 .set_fmt
= sgtl5000_set_dai_fmt
,
994 .set_sysclk
= sgtl5000_set_dai_sysclk
,
997 static struct snd_soc_dai_driver sgtl5000_dai
= {
1000 .stream_name
= "Playback",
1004 * only support 8~48K + 96K,
1005 * TODO modify hw_param to support more
1007 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
1008 .formats
= SGTL5000_FORMATS
,
1011 .stream_name
= "Capture",
1014 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
1015 .formats
= SGTL5000_FORMATS
,
1017 .ops
= &sgtl5000_ops
,
1018 .symmetric_rates
= 1,
1021 static bool sgtl5000_volatile(struct device
*dev
, unsigned int reg
)
1024 case SGTL5000_CHIP_ID
:
1025 case SGTL5000_CHIP_ADCDAC_CTRL
:
1026 case SGTL5000_CHIP_ANA_STATUS
:
1033 static bool sgtl5000_readable(struct device
*dev
, unsigned int reg
)
1036 case SGTL5000_CHIP_ID
:
1037 case SGTL5000_CHIP_DIG_POWER
:
1038 case SGTL5000_CHIP_CLK_CTRL
:
1039 case SGTL5000_CHIP_I2S_CTRL
:
1040 case SGTL5000_CHIP_SSS_CTRL
:
1041 case SGTL5000_CHIP_ADCDAC_CTRL
:
1042 case SGTL5000_CHIP_DAC_VOL
:
1043 case SGTL5000_CHIP_PAD_STRENGTH
:
1044 case SGTL5000_CHIP_ANA_ADC_CTRL
:
1045 case SGTL5000_CHIP_ANA_HP_CTRL
:
1046 case SGTL5000_CHIP_ANA_CTRL
:
1047 case SGTL5000_CHIP_LINREG_CTRL
:
1048 case SGTL5000_CHIP_REF_CTRL
:
1049 case SGTL5000_CHIP_MIC_CTRL
:
1050 case SGTL5000_CHIP_LINE_OUT_CTRL
:
1051 case SGTL5000_CHIP_LINE_OUT_VOL
:
1052 case SGTL5000_CHIP_ANA_POWER
:
1053 case SGTL5000_CHIP_PLL_CTRL
:
1054 case SGTL5000_CHIP_CLK_TOP_CTRL
:
1055 case SGTL5000_CHIP_ANA_STATUS
:
1056 case SGTL5000_CHIP_SHORT_CTRL
:
1057 case SGTL5000_CHIP_ANA_TEST2
:
1058 case SGTL5000_DAP_CTRL
:
1059 case SGTL5000_DAP_PEQ
:
1060 case SGTL5000_DAP_BASS_ENHANCE
:
1061 case SGTL5000_DAP_BASS_ENHANCE_CTRL
:
1062 case SGTL5000_DAP_AUDIO_EQ
:
1063 case SGTL5000_DAP_SURROUND
:
1064 case SGTL5000_DAP_FLT_COEF_ACCESS
:
1065 case SGTL5000_DAP_COEF_WR_B0_MSB
:
1066 case SGTL5000_DAP_COEF_WR_B0_LSB
:
1067 case SGTL5000_DAP_EQ_BASS_BAND0
:
1068 case SGTL5000_DAP_EQ_BASS_BAND1
:
1069 case SGTL5000_DAP_EQ_BASS_BAND2
:
1070 case SGTL5000_DAP_EQ_BASS_BAND3
:
1071 case SGTL5000_DAP_EQ_BASS_BAND4
:
1072 case SGTL5000_DAP_MAIN_CHAN
:
1073 case SGTL5000_DAP_MIX_CHAN
:
1074 case SGTL5000_DAP_AVC_CTRL
:
1075 case SGTL5000_DAP_AVC_THRESHOLD
:
1076 case SGTL5000_DAP_AVC_ATTACK
:
1077 case SGTL5000_DAP_AVC_DECAY
:
1078 case SGTL5000_DAP_COEF_WR_B1_MSB
:
1079 case SGTL5000_DAP_COEF_WR_B1_LSB
:
1080 case SGTL5000_DAP_COEF_WR_B2_MSB
:
1081 case SGTL5000_DAP_COEF_WR_B2_LSB
:
1082 case SGTL5000_DAP_COEF_WR_A1_MSB
:
1083 case SGTL5000_DAP_COEF_WR_A1_LSB
:
1084 case SGTL5000_DAP_COEF_WR_A2_MSB
:
1085 case SGTL5000_DAP_COEF_WR_A2_LSB
:
1094 * sgtl5000 has 3 internal power supplies:
1095 * 1. VAG, normally set to vdda/2
1096 * 2. charge pump, set to different value
1097 * according to voltage of vdda and vddio
1098 * 3. line out VAG, normally set to vddio/2
1100 * and should be set according to:
1101 * 1. vddd provided by external or not
1102 * 2. vdda and vddio voltage value. > 3.1v or not
1103 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1105 static int sgtl5000_set_power_regs(struct snd_soc_codec
*codec
)
1113 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1115 vdda
= regulator_get_voltage(sgtl5000
->supplies
[VDDA
].consumer
);
1116 vddio
= regulator_get_voltage(sgtl5000
->supplies
[VDDIO
].consumer
);
1117 vddd
= regulator_get_voltage(sgtl5000
->supplies
[VDDD
].consumer
);
1120 vddio
= vddio
/ 1000;
1123 if (vdda
<= 0 || vddio
<= 0 || vddd
< 0) {
1124 dev_err(codec
->dev
, "regulator voltage not set correctly\n");
1129 /* according to datasheet, maximum voltage of supplies */
1130 if (vdda
> 3600 || vddio
> 3600 || vddd
> 1980) {
1132 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1139 ana_pwr
= snd_soc_read(codec
, SGTL5000_CHIP_ANA_POWER
);
1140 ana_pwr
|= SGTL5000_DAC_STEREO
|
1141 SGTL5000_ADC_STEREO
|
1142 SGTL5000_REFTOP_POWERUP
;
1143 lreg_ctrl
= snd_soc_read(codec
, SGTL5000_CHIP_LINREG_CTRL
);
1145 if (vddio
< 3100 && vdda
< 3100) {
1146 /* enable internal oscillator used for charge pump */
1147 snd_soc_update_bits(codec
, SGTL5000_CHIP_CLK_TOP_CTRL
,
1148 SGTL5000_INT_OSC_EN
,
1149 SGTL5000_INT_OSC_EN
);
1150 /* Enable VDDC charge pump */
1151 ana_pwr
|= SGTL5000_VDDC_CHRGPMP_POWERUP
;
1152 } else if (vddio
>= 3100 && vdda
>= 3100) {
1153 ana_pwr
&= ~SGTL5000_VDDC_CHRGPMP_POWERUP
;
1154 /* VDDC use VDDIO rail */
1155 lreg_ctrl
|= SGTL5000_VDDC_ASSN_OVRD
;
1156 lreg_ctrl
|= SGTL5000_VDDC_MAN_ASSN_VDDIO
<<
1157 SGTL5000_VDDC_MAN_ASSN_SHIFT
;
1160 snd_soc_write(codec
, SGTL5000_CHIP_LINREG_CTRL
, lreg_ctrl
);
1162 snd_soc_write(codec
, SGTL5000_CHIP_ANA_POWER
, ana_pwr
);
1164 /* set voltage to register */
1165 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINREG_CTRL
,
1166 SGTL5000_LINREG_VDDD_MASK
, 0x8);
1169 * if vddd linear reg has been enabled,
1170 * simple digital supply should be clear to get
1171 * proper VDDD voltage.
1173 if (ana_pwr
& SGTL5000_LINEREG_D_POWERUP
)
1174 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
1175 SGTL5000_LINREG_SIMPLE_POWERUP
,
1178 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
1179 SGTL5000_LINREG_SIMPLE_POWERUP
|
1180 SGTL5000_STARTUP_POWERUP
,
1184 * set ADC/DAC VAG to vdda / 2,
1185 * should stay in range (0.8v, 1.575v)
1188 if (vag
<= SGTL5000_ANA_GND_BASE
)
1190 else if (vag
>= SGTL5000_ANA_GND_BASE
+ SGTL5000_ANA_GND_STP
*
1191 (SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
))
1192 vag
= SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
;
1194 vag
= (vag
- SGTL5000_ANA_GND_BASE
) / SGTL5000_ANA_GND_STP
;
1196 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1197 SGTL5000_ANA_GND_MASK
, vag
<< SGTL5000_ANA_GND_SHIFT
);
1199 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1201 if (vag
<= SGTL5000_LINE_OUT_GND_BASE
)
1203 else if (vag
>= SGTL5000_LINE_OUT_GND_BASE
+
1204 SGTL5000_LINE_OUT_GND_STP
* SGTL5000_LINE_OUT_GND_MAX
)
1205 vag
= SGTL5000_LINE_OUT_GND_MAX
;
1207 vag
= (vag
- SGTL5000_LINE_OUT_GND_BASE
) /
1208 SGTL5000_LINE_OUT_GND_STP
;
1210 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINE_OUT_CTRL
,
1211 SGTL5000_LINE_OUT_CURRENT_MASK
|
1212 SGTL5000_LINE_OUT_GND_MASK
,
1213 vag
<< SGTL5000_LINE_OUT_GND_SHIFT
|
1214 SGTL5000_LINE_OUT_CURRENT_360u
<<
1215 SGTL5000_LINE_OUT_CURRENT_SHIFT
);
1220 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec
*codec
)
1222 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1225 /* set internal ldo to 1.2v */
1226 ret
= ldo_regulator_register(codec
, &ldo_init_data
, LDO_VOLTAGE
);
1229 "Failed to register vddd internal supplies: %d\n", ret
);
1233 sgtl5000
->supplies
[VDDD
].supply
= LDO_CONSUMER_NAME
;
1235 dev_info(codec
->dev
, "Using internal LDO instead of VDDD\n");
1239 static int sgtl5000_enable_regulators(struct snd_soc_codec
*codec
)
1243 int external_vddd
= 0;
1244 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1245 struct regulator
*vddd
;
1247 for (i
= 0; i
< ARRAY_SIZE(sgtl5000
->supplies
); i
++)
1248 sgtl5000
->supplies
[i
].supply
= supply_names
[i
];
1250 /* External VDDD only works before revision 0x11 */
1251 if (sgtl5000
->revision
< 0x11) {
1252 vddd
= regulator_get_optional(codec
->dev
, "VDDD");
1254 /* See if it's just not registered yet */
1255 if (PTR_ERR(vddd
) == -EPROBE_DEFER
)
1256 return -EPROBE_DEFER
;
1259 regulator_put(vddd
);
1263 if (!external_vddd
) {
1264 ret
= sgtl5000_replace_vddd_with_ldo(codec
);
1269 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(sgtl5000
->supplies
),
1270 sgtl5000
->supplies
);
1272 goto err_ldo_remove
;
1274 ret
= regulator_bulk_enable(ARRAY_SIZE(sgtl5000
->supplies
),
1275 sgtl5000
->supplies
);
1277 goto err_regulator_free
;
1279 /* wait for all power rails bring up */
1285 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1286 sgtl5000
->supplies
);
1289 ldo_regulator_remove(codec
);
1294 static int sgtl5000_probe(struct snd_soc_codec
*codec
)
1297 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1299 ret
= sgtl5000_enable_regulators(codec
);
1303 /* power up sgtl5000 */
1304 ret
= sgtl5000_set_power_regs(codec
);
1308 /* enable small pop, introduce 400ms delay in turning off */
1309 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1310 SGTL5000_SMALL_POP
, 1);
1312 /* disable short cut detector */
1313 snd_soc_write(codec
, SGTL5000_CHIP_SHORT_CTRL
, 0);
1316 * set i2s as default input of sound switch
1317 * TODO: add sound switch to control and dapm widge.
1319 snd_soc_write(codec
, SGTL5000_CHIP_SSS_CTRL
,
1320 SGTL5000_DAC_SEL_I2S_IN
<< SGTL5000_DAC_SEL_SHIFT
);
1321 snd_soc_write(codec
, SGTL5000_CHIP_DIG_POWER
,
1322 SGTL5000_ADC_EN
| SGTL5000_DAC_EN
);
1324 /* enable dac volume ramp by default */
1325 snd_soc_write(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
1326 SGTL5000_DAC_VOL_RAMP_EN
|
1327 SGTL5000_DAC_MUTE_RIGHT
|
1328 SGTL5000_DAC_MUTE_LEFT
);
1330 snd_soc_write(codec
, SGTL5000_CHIP_PAD_STRENGTH
, 0x015f);
1332 snd_soc_write(codec
, SGTL5000_CHIP_ANA_CTRL
,
1333 SGTL5000_HP_ZCD_EN
|
1334 SGTL5000_ADC_ZCD_EN
);
1336 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
1337 SGTL5000_BIAS_R_MASK
,
1338 sgtl5000
->micbias_resistor
<< SGTL5000_BIAS_R_SHIFT
);
1340 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
1341 SGTL5000_BIAS_R_MASK
,
1342 sgtl5000
->micbias_voltage
<< SGTL5000_BIAS_R_SHIFT
);
1346 * Enable DAP in kcontrol and dapm.
1348 snd_soc_write(codec
, SGTL5000_DAP_CTRL
, 0);
1353 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1354 sgtl5000
->supplies
);
1355 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1356 sgtl5000
->supplies
);
1357 ldo_regulator_remove(codec
);
1362 static int sgtl5000_remove(struct snd_soc_codec
*codec
)
1364 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1366 regulator_bulk_disable(ARRAY_SIZE(sgtl5000
->supplies
),
1367 sgtl5000
->supplies
);
1368 regulator_bulk_free(ARRAY_SIZE(sgtl5000
->supplies
),
1369 sgtl5000
->supplies
);
1370 ldo_regulator_remove(codec
);
1375 static struct snd_soc_codec_driver sgtl5000_driver
= {
1376 .probe
= sgtl5000_probe
,
1377 .remove
= sgtl5000_remove
,
1378 .set_bias_level
= sgtl5000_set_bias_level
,
1379 .suspend_bias_off
= true,
1380 .controls
= sgtl5000_snd_controls
,
1381 .num_controls
= ARRAY_SIZE(sgtl5000_snd_controls
),
1382 .dapm_widgets
= sgtl5000_dapm_widgets
,
1383 .num_dapm_widgets
= ARRAY_SIZE(sgtl5000_dapm_widgets
),
1384 .dapm_routes
= sgtl5000_dapm_routes
,
1385 .num_dapm_routes
= ARRAY_SIZE(sgtl5000_dapm_routes
),
1388 static const struct regmap_config sgtl5000_regmap
= {
1393 .max_register
= SGTL5000_MAX_REG_OFFSET
,
1394 .volatile_reg
= sgtl5000_volatile
,
1395 .readable_reg
= sgtl5000_readable
,
1397 .cache_type
= REGCACHE_RBTREE
,
1398 .reg_defaults
= sgtl5000_reg_defaults
,
1399 .num_reg_defaults
= ARRAY_SIZE(sgtl5000_reg_defaults
),
1403 * Write all the default values from sgtl5000_reg_defaults[] array into the
1404 * sgtl5000 registers, to make sure we always start with the sane registers
1405 * values as stated in the datasheet.
1407 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1408 * we follow this approach to guarantee we always start from the default values
1409 * and avoid problems like, not being able to probe after an audio playback
1410 * followed by a system reset or a 'reboot' command in Linux
1412 static int sgtl5000_fill_defaults(struct sgtl5000_priv
*sgtl5000
)
1414 int i
, ret
, val
, index
;
1416 for (i
= 0; i
< ARRAY_SIZE(sgtl5000_reg_defaults
); i
++) {
1417 val
= sgtl5000_reg_defaults
[i
].def
;
1418 index
= sgtl5000_reg_defaults
[i
].reg
;
1419 ret
= regmap_write(sgtl5000
->regmap
, index
, val
);
1427 static int sgtl5000_i2c_probe(struct i2c_client
*client
,
1428 const struct i2c_device_id
*id
)
1430 struct sgtl5000_priv
*sgtl5000
;
1432 struct device_node
*np
= client
->dev
.of_node
;
1435 sgtl5000
= devm_kzalloc(&client
->dev
, sizeof(*sgtl5000
), GFP_KERNEL
);
1439 sgtl5000
->regmap
= devm_regmap_init_i2c(client
, &sgtl5000_regmap
);
1440 if (IS_ERR(sgtl5000
->regmap
)) {
1441 ret
= PTR_ERR(sgtl5000
->regmap
);
1442 dev_err(&client
->dev
, "Failed to allocate regmap: %d\n", ret
);
1446 sgtl5000
->mclk
= devm_clk_get(&client
->dev
, NULL
);
1447 if (IS_ERR(sgtl5000
->mclk
)) {
1448 ret
= PTR_ERR(sgtl5000
->mclk
);
1449 dev_err(&client
->dev
, "Failed to get mclock: %d\n", ret
);
1450 /* Defer the probe to see if the clk will be provided later */
1452 return -EPROBE_DEFER
;
1456 ret
= clk_prepare_enable(sgtl5000
->mclk
);
1460 /* Need 8 clocks before I2C accesses */
1463 /* read chip information */
1464 ret
= regmap_read(sgtl5000
->regmap
, SGTL5000_CHIP_ID
, ®
);
1468 if (((reg
& SGTL5000_PARTID_MASK
) >> SGTL5000_PARTID_SHIFT
) !=
1469 SGTL5000_PARTID_PART_ID
) {
1470 dev_err(&client
->dev
,
1471 "Device with ID register %x is not a sgtl5000\n", reg
);
1476 rev
= (reg
& SGTL5000_REVID_MASK
) >> SGTL5000_REVID_SHIFT
;
1477 dev_info(&client
->dev
, "sgtl5000 revision 0x%x\n", rev
);
1478 sgtl5000
->revision
= rev
;
1481 if (!of_property_read_u32(np
,
1482 "micbias-resistor-k-ohms", &value
)) {
1484 case SGTL5000_MICBIAS_OFF
:
1485 sgtl5000
->micbias_resistor
= 0;
1487 case SGTL5000_MICBIAS_2K
:
1488 sgtl5000
->micbias_resistor
= 1;
1490 case SGTL5000_MICBIAS_4K
:
1491 sgtl5000
->micbias_resistor
= 2;
1493 case SGTL5000_MICBIAS_8K
:
1494 sgtl5000
->micbias_resistor
= 3;
1497 sgtl5000
->micbias_resistor
= 2;
1498 dev_err(&client
->dev
,
1499 "Unsuitable MicBias resistor\n");
1502 /* default is 4Kohms */
1503 sgtl5000
->micbias_resistor
= 2;
1505 if (!of_property_read_u32(np
,
1506 "micbias-voltage-m-volts", &value
)) {
1508 /* steps of 250mV */
1509 if ((value
>= 1250) && (value
<= 3000))
1510 sgtl5000
->micbias_voltage
= (value
/ 250) - 5;
1512 sgtl5000
->micbias_voltage
= 0;
1513 dev_err(&client
->dev
,
1514 "Unsuitable MicBias resistor\n");
1517 sgtl5000
->micbias_voltage
= 0;
1521 i2c_set_clientdata(client
, sgtl5000
);
1523 /* Ensure sgtl5000 will start with sane register values */
1524 ret
= sgtl5000_fill_defaults(sgtl5000
);
1528 ret
= snd_soc_register_codec(&client
->dev
,
1529 &sgtl5000_driver
, &sgtl5000_dai
, 1);
1536 clk_disable_unprepare(sgtl5000
->mclk
);
1540 static int sgtl5000_i2c_remove(struct i2c_client
*client
)
1542 struct sgtl5000_priv
*sgtl5000
= i2c_get_clientdata(client
);
1544 snd_soc_unregister_codec(&client
->dev
);
1545 clk_disable_unprepare(sgtl5000
->mclk
);
1549 static const struct i2c_device_id sgtl5000_id
[] = {
1554 MODULE_DEVICE_TABLE(i2c
, sgtl5000_id
);
1556 static const struct of_device_id sgtl5000_dt_ids
[] = {
1557 { .compatible
= "fsl,sgtl5000", },
1560 MODULE_DEVICE_TABLE(of
, sgtl5000_dt_ids
);
1562 static struct i2c_driver sgtl5000_i2c_driver
= {
1565 .owner
= THIS_MODULE
,
1566 .of_match_table
= sgtl5000_dt_ids
,
1568 .probe
= sgtl5000_i2c_probe
,
1569 .remove
= sgtl5000_i2c_remove
,
1570 .id_table
= sgtl5000_id
,
1573 module_i2c_driver(sgtl5000_i2c_driver
);
1575 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1576 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1577 MODULE_LICENSE("GPL");