2 * SSM4567 amplifier audio driver
4 * Copyright 2014 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
7 * Based on code copyright/by:
8 * Copyright 2013 Analog Devices Inc.
10 * Licensed under the GPL-2.
13 #include <linux/acpi.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/i2c.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
26 #define SSM4567_REG_POWER_CTRL 0x00
27 #define SSM4567_REG_AMP_SNS_CTRL 0x01
28 #define SSM4567_REG_DAC_CTRL 0x02
29 #define SSM4567_REG_DAC_VOLUME 0x03
30 #define SSM4567_REG_SAI_CTRL_1 0x04
31 #define SSM4567_REG_SAI_CTRL_2 0x05
32 #define SSM4567_REG_SAI_PLACEMENT_1 0x06
33 #define SSM4567_REG_SAI_PLACEMENT_2 0x07
34 #define SSM4567_REG_SAI_PLACEMENT_3 0x08
35 #define SSM4567_REG_SAI_PLACEMENT_4 0x09
36 #define SSM4567_REG_SAI_PLACEMENT_5 0x0a
37 #define SSM4567_REG_SAI_PLACEMENT_6 0x0b
38 #define SSM4567_REG_BATTERY_V_OUT 0x0c
39 #define SSM4567_REG_LIMITER_CTRL_1 0x0d
40 #define SSM4567_REG_LIMITER_CTRL_2 0x0e
41 #define SSM4567_REG_LIMITER_CTRL_3 0x0f
42 #define SSM4567_REG_STATUS_1 0x10
43 #define SSM4567_REG_STATUS_2 0x11
44 #define SSM4567_REG_FAULT_CTRL 0x12
45 #define SSM4567_REG_PDM_CTRL 0x13
46 #define SSM4567_REG_MCLK_RATIO 0x14
47 #define SSM4567_REG_BOOST_CTRL_1 0x15
48 #define SSM4567_REG_BOOST_CTRL_2 0x16
49 #define SSM4567_REG_SOFT_RESET 0xff
52 #define SSM4567_POWER_APWDN_EN BIT(7)
53 #define SSM4567_POWER_BSNS_PWDN BIT(6)
54 #define SSM4567_POWER_VSNS_PWDN BIT(5)
55 #define SSM4567_POWER_ISNS_PWDN BIT(4)
56 #define SSM4567_POWER_BOOST_PWDN BIT(3)
57 #define SSM4567_POWER_AMP_PWDN BIT(2)
58 #define SSM4567_POWER_VBAT_ONLY BIT(1)
59 #define SSM4567_POWER_SPWDN BIT(0)
62 #define SSM4567_DAC_HV BIT(7)
63 #define SSM4567_DAC_MUTE BIT(6)
64 #define SSM4567_DAC_HPF BIT(5)
65 #define SSM4567_DAC_LPM BIT(4)
66 #define SSM4567_DAC_FS_MASK 0x7
67 #define SSM4567_DAC_FS_8000_12000 0x0
68 #define SSM4567_DAC_FS_16000_24000 0x1
69 #define SSM4567_DAC_FS_32000_48000 0x2
70 #define SSM4567_DAC_FS_64000_96000 0x3
71 #define SSM4567_DAC_FS_128000_192000 0x4
74 #define SSM4567_SAI_CTRL_1_BCLK BIT(6)
75 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK (0x3 << 4)
76 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_32 (0x0 << 4)
77 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_48 (0x1 << 4)
78 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_64 (0x2 << 4)
79 #define SSM4567_SAI_CTRL_1_FSYNC BIT(3)
80 #define SSM4567_SAI_CTRL_1_LJ BIT(2)
81 #define SSM4567_SAI_CTRL_1_TDM BIT(1)
82 #define SSM4567_SAI_CTRL_1_PDM BIT(0)
85 #define SSM4567_SAI_CTRL_2_AUTO_SLOT BIT(3)
86 #define SSM4567_SAI_CTRL_2_TDM_SLOT_MASK 0x7
87 #define SSM4567_SAI_CTRL_2_TDM_SLOT(x) (x)
90 struct regmap
*regmap
;
93 static const struct reg_default ssm4567_reg_defaults
[] = {
94 { SSM4567_REG_POWER_CTRL
, 0x81 },
95 { SSM4567_REG_AMP_SNS_CTRL
, 0x09 },
96 { SSM4567_REG_DAC_CTRL
, 0x32 },
97 { SSM4567_REG_DAC_VOLUME
, 0x40 },
98 { SSM4567_REG_SAI_CTRL_1
, 0x00 },
99 { SSM4567_REG_SAI_CTRL_2
, 0x08 },
100 { SSM4567_REG_SAI_PLACEMENT_1
, 0x01 },
101 { SSM4567_REG_SAI_PLACEMENT_2
, 0x20 },
102 { SSM4567_REG_SAI_PLACEMENT_3
, 0x32 },
103 { SSM4567_REG_SAI_PLACEMENT_4
, 0x07 },
104 { SSM4567_REG_SAI_PLACEMENT_5
, 0x07 },
105 { SSM4567_REG_SAI_PLACEMENT_6
, 0x07 },
106 { SSM4567_REG_BATTERY_V_OUT
, 0x00 },
107 { SSM4567_REG_LIMITER_CTRL_1
, 0xa4 },
108 { SSM4567_REG_LIMITER_CTRL_2
, 0x73 },
109 { SSM4567_REG_LIMITER_CTRL_3
, 0x00 },
110 { SSM4567_REG_STATUS_1
, 0x00 },
111 { SSM4567_REG_STATUS_2
, 0x00 },
112 { SSM4567_REG_FAULT_CTRL
, 0x30 },
113 { SSM4567_REG_PDM_CTRL
, 0x40 },
114 { SSM4567_REG_MCLK_RATIO
, 0x11 },
115 { SSM4567_REG_BOOST_CTRL_1
, 0x03 },
116 { SSM4567_REG_BOOST_CTRL_2
, 0x00 },
117 { SSM4567_REG_SOFT_RESET
, 0x00 },
121 static bool ssm4567_readable_reg(struct device
*dev
, unsigned int reg
)
124 case SSM4567_REG_POWER_CTRL
... SSM4567_REG_BOOST_CTRL_2
:
132 static bool ssm4567_writeable_reg(struct device
*dev
, unsigned int reg
)
135 case SSM4567_REG_POWER_CTRL
... SSM4567_REG_SAI_PLACEMENT_6
:
136 case SSM4567_REG_LIMITER_CTRL_1
... SSM4567_REG_LIMITER_CTRL_3
:
137 case SSM4567_REG_FAULT_CTRL
... SSM4567_REG_BOOST_CTRL_2
:
138 /* The datasheet states that soft reset register is read-only,
139 * but logically it is write-only. */
140 case SSM4567_REG_SOFT_RESET
:
147 static bool ssm4567_volatile_reg(struct device
*dev
, unsigned int reg
)
150 case SSM4567_REG_BATTERY_V_OUT
:
151 case SSM4567_REG_STATUS_1
... SSM4567_REG_STATUS_2
:
152 case SSM4567_REG_SOFT_RESET
:
159 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm4567_vol_tlv
, -7125, 2400);
161 static const struct snd_kcontrol_new ssm4567_snd_controls
[] = {
162 SOC_SINGLE_TLV("Master Playback Volume", SSM4567_REG_DAC_VOLUME
, 0,
163 0xff, 1, ssm4567_vol_tlv
),
164 SOC_SINGLE("DAC Low Power Mode Switch", SSM4567_REG_DAC_CTRL
, 4, 1, 0),
165 SOC_SINGLE("DAC High Pass Filter Switch", SSM4567_REG_DAC_CTRL
,
169 static const struct snd_kcontrol_new ssm4567_amplifier_boost_control
=
170 SOC_DAPM_SINGLE("Switch", SSM4567_REG_POWER_CTRL
, 1, 1, 1);
172 static const struct snd_soc_dapm_widget ssm4567_dapm_widgets
[] = {
173 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM4567_REG_POWER_CTRL
, 2, 1),
174 SND_SOC_DAPM_SWITCH("Amplifier Boost", SSM4567_REG_POWER_CTRL
, 3, 1,
175 &ssm4567_amplifier_boost_control
),
177 SND_SOC_DAPM_OUTPUT("OUT"),
180 static const struct snd_soc_dapm_route ssm4567_routes
[] = {
181 { "OUT", NULL
, "Amplifier Boost" },
182 { "Amplifier Boost", "Switch", "DAC" },
183 { "OUT", NULL
, "DAC" },
186 static int ssm4567_hw_params(struct snd_pcm_substream
*substream
,
187 struct snd_pcm_hw_params
*params
, struct snd_soc_dai
*dai
)
189 struct snd_soc_codec
*codec
= dai
->codec
;
190 struct ssm4567
*ssm4567
= snd_soc_codec_get_drvdata(codec
);
191 unsigned int rate
= params_rate(params
);
194 if (rate
>= 8000 && rate
<= 12000)
195 dacfs
= SSM4567_DAC_FS_8000_12000
;
196 else if (rate
>= 16000 && rate
<= 24000)
197 dacfs
= SSM4567_DAC_FS_16000_24000
;
198 else if (rate
>= 32000 && rate
<= 48000)
199 dacfs
= SSM4567_DAC_FS_32000_48000
;
200 else if (rate
>= 64000 && rate
<= 96000)
201 dacfs
= SSM4567_DAC_FS_64000_96000
;
202 else if (rate
>= 128000 && rate
<= 192000)
203 dacfs
= SSM4567_DAC_FS_128000_192000
;
207 return regmap_update_bits(ssm4567
->regmap
, SSM4567_REG_DAC_CTRL
,
208 SSM4567_DAC_FS_MASK
, dacfs
);
211 static int ssm4567_mute(struct snd_soc_dai
*dai
, int mute
)
213 struct ssm4567
*ssm4567
= snd_soc_codec_get_drvdata(dai
->codec
);
216 val
= mute
? SSM4567_DAC_MUTE
: 0;
217 return regmap_update_bits(ssm4567
->regmap
, SSM4567_REG_DAC_CTRL
,
218 SSM4567_DAC_MUTE
, val
);
221 static int ssm4567_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
222 unsigned int rx_mask
, int slots
, int width
)
224 struct ssm4567
*ssm4567
= snd_soc_dai_get_drvdata(dai
);
232 if (rx_mask
&& rx_mask
!= tx_mask
)
235 slot
= __ffs(tx_mask
);
236 if (tx_mask
!= BIT(slot
))
241 blcks
= SSM4567_SAI_CTRL_1_TDM_BLCKS_32
;
244 blcks
= SSM4567_SAI_CTRL_1_TDM_BLCKS_48
;
247 blcks
= SSM4567_SAI_CTRL_1_TDM_BLCKS_64
;
253 ret
= regmap_update_bits(ssm4567
->regmap
, SSM4567_REG_SAI_CTRL_2
,
254 SSM4567_SAI_CTRL_2_AUTO_SLOT
| SSM4567_SAI_CTRL_2_TDM_SLOT_MASK
,
255 SSM4567_SAI_CTRL_2_TDM_SLOT(slot
));
259 return regmap_update_bits(ssm4567
->regmap
, SSM4567_REG_SAI_CTRL_1
,
260 SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK
, blcks
);
263 static int ssm4567_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
265 struct ssm4567
*ssm4567
= snd_soc_dai_get_drvdata(dai
);
266 unsigned int ctrl1
= 0;
269 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
270 case SND_SOC_DAIFMT_CBS_CFS
:
276 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
277 case SND_SOC_DAIFMT_NB_NF
:
280 case SND_SOC_DAIFMT_IB_NF
:
281 ctrl1
|= SSM4567_SAI_CTRL_1_BCLK
;
284 case SND_SOC_DAIFMT_NB_IF
:
285 ctrl1
|= SSM4567_SAI_CTRL_1_FSYNC
;
288 case SND_SOC_DAIFMT_IB_IF
:
289 ctrl1
|= SSM4567_SAI_CTRL_1_BCLK
;
296 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
297 case SND_SOC_DAIFMT_I2S
:
299 case SND_SOC_DAIFMT_LEFT_J
:
300 ctrl1
|= SSM4567_SAI_CTRL_1_LJ
;
301 invert_fclk
= !invert_fclk
;
303 case SND_SOC_DAIFMT_DSP_A
:
304 ctrl1
|= SSM4567_SAI_CTRL_1_TDM
;
306 case SND_SOC_DAIFMT_DSP_B
:
307 ctrl1
|= SSM4567_SAI_CTRL_1_TDM
| SSM4567_SAI_CTRL_1_LJ
;
309 case SND_SOC_DAIFMT_PDM
:
310 ctrl1
|= SSM4567_SAI_CTRL_1_PDM
;
317 ctrl1
|= SSM4567_SAI_CTRL_1_FSYNC
;
319 return regmap_update_bits(ssm4567
->regmap
, SSM4567_REG_SAI_CTRL_1
,
320 SSM4567_SAI_CTRL_1_BCLK
|
321 SSM4567_SAI_CTRL_1_FSYNC
|
322 SSM4567_SAI_CTRL_1_LJ
|
323 SSM4567_SAI_CTRL_1_TDM
|
324 SSM4567_SAI_CTRL_1_PDM
,
328 static int ssm4567_set_power(struct ssm4567
*ssm4567
, bool enable
)
333 ret
= regmap_update_bits(ssm4567
->regmap
,
334 SSM4567_REG_POWER_CTRL
,
335 SSM4567_POWER_SPWDN
, SSM4567_POWER_SPWDN
);
336 regcache_mark_dirty(ssm4567
->regmap
);
339 regcache_cache_only(ssm4567
->regmap
, !enable
);
342 ret
= regmap_update_bits(ssm4567
->regmap
,
343 SSM4567_REG_POWER_CTRL
,
344 SSM4567_POWER_SPWDN
, 0x00);
345 regcache_sync(ssm4567
->regmap
);
351 static int ssm4567_set_bias_level(struct snd_soc_codec
*codec
,
352 enum snd_soc_bias_level level
)
354 struct ssm4567
*ssm4567
= snd_soc_codec_get_drvdata(codec
);
358 case SND_SOC_BIAS_ON
:
360 case SND_SOC_BIAS_PREPARE
:
362 case SND_SOC_BIAS_STANDBY
:
363 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
)
364 ret
= ssm4567_set_power(ssm4567
, true);
366 case SND_SOC_BIAS_OFF
:
367 ret
= ssm4567_set_power(ssm4567
, false);
374 static const struct snd_soc_dai_ops ssm4567_dai_ops
= {
375 .hw_params
= ssm4567_hw_params
,
376 .digital_mute
= ssm4567_mute
,
377 .set_fmt
= ssm4567_set_dai_fmt
,
378 .set_tdm_slot
= ssm4567_set_tdm_slot
,
381 static struct snd_soc_dai_driver ssm4567_dai
= {
382 .name
= "ssm4567-hifi",
384 .stream_name
= "Playback",
387 .rates
= SNDRV_PCM_RATE_8000_192000
,
388 .formats
= SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
|
389 SNDRV_PCM_FMTBIT_S32
,
391 .ops
= &ssm4567_dai_ops
,
394 static struct snd_soc_codec_driver ssm4567_codec_driver
= {
395 .set_bias_level
= ssm4567_set_bias_level
,
396 .idle_bias_off
= true,
398 .controls
= ssm4567_snd_controls
,
399 .num_controls
= ARRAY_SIZE(ssm4567_snd_controls
),
400 .dapm_widgets
= ssm4567_dapm_widgets
,
401 .num_dapm_widgets
= ARRAY_SIZE(ssm4567_dapm_widgets
),
402 .dapm_routes
= ssm4567_routes
,
403 .num_dapm_routes
= ARRAY_SIZE(ssm4567_routes
),
406 static const struct regmap_config ssm4567_regmap_config
= {
410 .max_register
= SSM4567_REG_SOFT_RESET
,
411 .readable_reg
= ssm4567_readable_reg
,
412 .writeable_reg
= ssm4567_writeable_reg
,
413 .volatile_reg
= ssm4567_volatile_reg
,
415 .cache_type
= REGCACHE_RBTREE
,
416 .reg_defaults
= ssm4567_reg_defaults
,
417 .num_reg_defaults
= ARRAY_SIZE(ssm4567_reg_defaults
),
420 static int ssm4567_i2c_probe(struct i2c_client
*i2c
,
421 const struct i2c_device_id
*id
)
423 struct ssm4567
*ssm4567
;
426 ssm4567
= devm_kzalloc(&i2c
->dev
, sizeof(*ssm4567
), GFP_KERNEL
);
430 i2c_set_clientdata(i2c
, ssm4567
);
432 ssm4567
->regmap
= devm_regmap_init_i2c(i2c
, &ssm4567_regmap_config
);
433 if (IS_ERR(ssm4567
->regmap
))
434 return PTR_ERR(ssm4567
->regmap
);
436 ret
= regmap_write(ssm4567
->regmap
, SSM4567_REG_SOFT_RESET
, 0x00);
440 ret
= ssm4567_set_power(ssm4567
, false);
444 return snd_soc_register_codec(&i2c
->dev
, &ssm4567_codec_driver
,
448 static int ssm4567_i2c_remove(struct i2c_client
*client
)
450 snd_soc_unregister_codec(&client
->dev
);
454 static const struct i2c_device_id ssm4567_i2c_ids
[] = {
458 MODULE_DEVICE_TABLE(i2c
, ssm4567_i2c_ids
);
462 static const struct acpi_device_id ssm4567_acpi_match
[] = {
466 MODULE_DEVICE_TABLE(acpi
, ssm4567_acpi_match
);
470 static struct i2c_driver ssm4567_driver
= {
473 .acpi_match_table
= ACPI_PTR(ssm4567_acpi_match
),
475 .probe
= ssm4567_i2c_probe
,
476 .remove
= ssm4567_i2c_remove
,
477 .id_table
= ssm4567_i2c_ids
,
479 module_i2c_driver(ssm4567_driver
);
481 MODULE_DESCRIPTION("ASoC SSM4567 driver");
482 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
483 MODULE_LICENSE("GPL");