sound/soc/codecs/tlv320aic32x4.c

   1 /*
   2  * linux/sound/soc/codecs/tlv320aic32x4.c
   3  *
   4  * Copyright 2011 Vista Silicon S.L.
   5  *
   6  * Author: Javier Martin <javier.martin@vista-silicon.com>
   7  *
   8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  23  * MA 02110-1301, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/gpio.h>
  32 #include <linux/i2c.h>
  33 #include <linux/cdev.h>
  34 #include <linux/slab.h>
  35
  36 #include <sound/tlv320aic32x4.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/pcm_params.h>
  40 #include <sound/soc.h>
  41 #include <sound/soc-dapm.h>
  42 #include <sound/initval.h>
  43 #include <sound/tlv.h>
  44
  45 #include "tlv320aic32x4.h"
  46
  47 struct aic32x4_rate_divs {
  48         u32 mclk;
  49         u32 rate;
  50         u8 p_val;
  51         u8 pll_j;
  52         u16 pll_d;
  53         u16 dosr;
  54         u8 ndac;
  55         u8 mdac;
  56         u8 aosr;
  57         u8 nadc;
  58         u8 madc;
  59         u8 blck_N;
  60 };
  61
  62 struct aic32x4_priv {
  63         struct regmap *regmap;
  64         u32 sysclk;
  65         u32 power_cfg;
  66         u32 micpga_routing;
  67         bool swapdacs;
  68         int rstn_gpio;
  69 };
  70
  71 /* 0dB min, 1dB steps */
  72 static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
  73 /* 0dB min, 0.5dB steps */
  74 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
  75
  76 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
  77         SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
  78                         AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
  79         SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
  80                         AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
  81         SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
  82                         AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
  83         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
  84                         AIC32X4_HPRGAIN, 6, 0x01, 1),
  85         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
  86                         AIC32X4_LORGAIN, 6, 0x01, 1),
  87         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
  88                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
  89
  90         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
  91         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
  92
  93         SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
  94                         AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
  95         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
  96                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
  97
  98         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
  99
 100         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 101         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 102         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 103                         4, 0x07, 0),
 104         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 105                         0, 0x03, 0),
 106         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 107                         6, 0x03, 0),
 108         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 109                         1, 0x1F, 0),
 110         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 111                         0, 0x7F, 0),
 112         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 113                         3, 0x1F, 0),
 114         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 115                         3, 0x1F, 0),
 116         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 117                         0, 0x1F, 0),
 118         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 119                         0, 0x0F, 0),
 120 };
 121
 122 static const struct aic32x4_rate_divs aic32x4_divs[] = {
 123         /* 8k rate */
 124         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
 125         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
 126         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
 127         /* 11.025k rate */
 128         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
 129         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
 130         /* 16k rate */
 131         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
 132         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
 133         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
 134         /* 22.05k rate */
 135         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
 136         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
 137         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
 138         /* 32k rate */
 139         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
 140         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
 141         /* 44.1k rate */
 142         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
 143         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
 144         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
 145         /* 48k rate */
 146         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
 147         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
 148         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
 149 };
 150
 151 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 152         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 153         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 154 };
 155
 156 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 157         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 158         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 159 };
 160
 161 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 162         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 163 };
 164
 165 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 166         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 167 };
 168
 169 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
 170         SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
 171         SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
 172         SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
 173 };
 174
 175 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
 176         SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
 177         SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
 178         SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
 179 };
 180
 181 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 182         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 183         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 184                            &hpl_output_mixer_controls[0],
 185                            ARRAY_SIZE(hpl_output_mixer_controls)),
 186         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 187
 188         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 189                            &lol_output_mixer_controls[0],
 190                            ARRAY_SIZE(lol_output_mixer_controls)),
 191         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 192
 193         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 194         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 195                            &hpr_output_mixer_controls[0],
 196                            ARRAY_SIZE(hpr_output_mixer_controls)),
 197         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 198         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 199                            &lor_output_mixer_controls[0],
 200                            ARRAY_SIZE(lor_output_mixer_controls)),
 201         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 202         SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
 203                            &left_input_mixer_controls[0],
 204                            ARRAY_SIZE(left_input_mixer_controls)),
 205         SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
 206                            &right_input_mixer_controls[0],
 207                            ARRAY_SIZE(right_input_mixer_controls)),
 208         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 209         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 210         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
 211
 212         SND_SOC_DAPM_OUTPUT("HPL"),
 213         SND_SOC_DAPM_OUTPUT("HPR"),
 214         SND_SOC_DAPM_OUTPUT("LOL"),
 215         SND_SOC_DAPM_OUTPUT("LOR"),
 216         SND_SOC_DAPM_INPUT("IN1_L"),
 217         SND_SOC_DAPM_INPUT("IN1_R"),
 218         SND_SOC_DAPM_INPUT("IN2_L"),
 219         SND_SOC_DAPM_INPUT("IN2_R"),
 220         SND_SOC_DAPM_INPUT("IN3_L"),
 221         SND_SOC_DAPM_INPUT("IN3_R"),
 222 };
 223
 224 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 225         /* Left Output */
 226         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 227         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 228
 229         {"HPL Power", NULL, "HPL Output Mixer"},
 230         {"HPL", NULL, "HPL Power"},
 231
 232         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 233
 234         {"LOL Power", NULL, "LOL Output Mixer"},
 235         {"LOL", NULL, "LOL Power"},
 236
 237         /* Right Output */
 238         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 239         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 240
 241         {"HPR Power", NULL, "HPR Output Mixer"},
 242         {"HPR", NULL, "HPR Power"},
 243
 244         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 245
 246         {"LOR Power", NULL, "LOR Output Mixer"},
 247         {"LOR", NULL, "LOR Power"},
 248
 249         /* Left input */
 250         {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
 251         {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
 252         {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
 253
 254         {"Left ADC", NULL, "Left Input Mixer"},
 255
 256         /* Right Input */
 257         {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
 258         {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
 259         {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
 260
 261         {"Right ADC", NULL, "Right Input Mixer"},
 262 };
 263
 264 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 265         {
 266                 .selector_reg = 0,
 267                 .selector_mask  = 0xff,
 268                 .window_start = 0,
 269                 .window_len = 128,
 270                 .range_min = 0,
 271                 .range_max = AIC32X4_RMICPGAVOL,
 272         },
 273 };
 274
 275 static const struct regmap_config aic32x4_regmap = {
 276         .reg_bits = 8,
 277         .val_bits = 8,
 278
 279         .max_register = AIC32X4_RMICPGAVOL,
 280         .ranges = aic32x4_regmap_pages,
 281         .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
 282 };
 283
 284 static inline int aic32x4_get_divs(int mclk, int rate)
 285 {
 286         int i;
 287
 288         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 289                 if ((aic32x4_divs[i].rate == rate)
 290                     && (aic32x4_divs[i].mclk == mclk)) {
 291                         return i;
 292                 }
 293         }
 294         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
 295         return -EINVAL;
 296 }
 297
 298 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 299                                   int clk_id, unsigned int freq, int dir)
 300 {
 301         struct snd_soc_codec *codec = codec_dai->codec;
 302         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 303
 304         switch (freq) {
 305         case AIC32X4_FREQ_12000000:
 306         case AIC32X4_FREQ_24000000:
 307         case AIC32X4_FREQ_25000000:
 308                 aic32x4->sysclk = freq;
 309                 return 0;
 310         }
 311         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
 312         return -EINVAL;
 313 }
 314
 315 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 316 {
 317         struct snd_soc_codec *codec = codec_dai->codec;
 318         u8 iface_reg_1;
 319         u8 iface_reg_2;
 320         u8 iface_reg_3;
 321
 322         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
 323         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
 324         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
 325         iface_reg_2 = 0;
 326         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
 327         iface_reg_3 = iface_reg_3 & ~(1 << 3);
 328
 329         /* set master/slave audio interface */
 330         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 331         case SND_SOC_DAIFMT_CBM_CFM:
 332                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 333                 break;
 334         case SND_SOC_DAIFMT_CBS_CFS:
 335                 break;
 336         default:
 337                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 338                 return -EINVAL;
 339         }
 340
 341         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 342         case SND_SOC_DAIFMT_I2S:
 343                 break;
 344         case SND_SOC_DAIFMT_DSP_A:
 345                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 346                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 347                 iface_reg_2 = 0x01; /* add offset 1 */
 348                 break;
 349         case SND_SOC_DAIFMT_DSP_B:
 350                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 351                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 352                 break;
 353         case SND_SOC_DAIFMT_RIGHT_J:
 354                 iface_reg_1 |=
 355                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 356                 break;
 357         case SND_SOC_DAIFMT_LEFT_J:
 358                 iface_reg_1 |=
 359                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 360                 break;
 361         default:
 362                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 363                 return -EINVAL;
 364         }
 365
 366         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
 367         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
 368         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
 369         return 0;
 370 }
 371
 372 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 373                              struct snd_pcm_hw_params *params,
 374                              struct snd_soc_dai *dai)
 375 {
 376         struct snd_soc_codec *codec = dai->codec;
 377         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 378         u8 data;
 379         int i;
 380
 381         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
 382         if (i < 0) {
 383                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
 384                 return i;
 385         }
 386
 387         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
 388         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
 389         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
 390
 391         /* We will fix R value to 1 and will make P & J=K.D as varialble */
 392         data = snd_soc_read(codec, AIC32X4_PLLPR);
 393         data &= ~(7 << 4);
 394         snd_soc_write(codec, AIC32X4_PLLPR,
 395                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
 396
 397         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 398
 399         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 400         snd_soc_write(codec, AIC32X4_PLLDLSB,
 401                       (aic32x4_divs[i].pll_d & 0xff));
 402
 403         /* NDAC divider value */
 404         data = snd_soc_read(codec, AIC32X4_NDAC);
 405         data &= ~(0x7f);
 406         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
 407
 408         /* MDAC divider value */
 409         data = snd_soc_read(codec, AIC32X4_MDAC);
 410         data &= ~(0x7f);
 411         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
 412
 413         /* DOSR MSB & LSB values */
 414         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 415         snd_soc_write(codec, AIC32X4_DOSRLSB,
 416                       (aic32x4_divs[i].dosr & 0xff));
 417
 418         /* NADC divider value */
 419         data = snd_soc_read(codec, AIC32X4_NADC);
 420         data &= ~(0x7f);
 421         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
 422
 423         /* MADC divider value */
 424         data = snd_soc_read(codec, AIC32X4_MADC);
 425         data &= ~(0x7f);
 426         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
 427
 428         /* AOSR value */
 429         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 430
 431         /* BCLK N divider */
 432         data = snd_soc_read(codec, AIC32X4_BCLKN);
 433         data &= ~(0x7f);
 434         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
 435
 436         data = snd_soc_read(codec, AIC32X4_IFACE1);
 437         data = data & ~(3 << 4);
 438         switch (params_format(params)) {
 439         case SNDRV_PCM_FORMAT_S16_LE:
 440                 break;
 441         case SNDRV_PCM_FORMAT_S20_3LE:
 442                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
 443                 break;
 444         case SNDRV_PCM_FORMAT_S24_LE:
 445                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
 446                 break;
 447         case SNDRV_PCM_FORMAT_S32_LE:
 448                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
 449                 break;
 450         }
 451         snd_soc_write(codec, AIC32X4_IFACE1, data);
 452
 453         if (params_channels(params) == 1) {
 454                 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 455         } else {
 456                 if (aic32x4->swapdacs)
 457                         data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
 458                 else
 459                         data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 460         }
 461         snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
 462                         data);
 463
 464         return 0;
 465 }
 466
 467 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
 468 {
 469         struct snd_soc_codec *codec = dai->codec;
 470         u8 dac_reg;
 471
 472         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
 473         if (mute)
 474                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
 475         else
 476                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
 477         return 0;
 478 }
 479
 480 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 481                                   enum snd_soc_bias_level level)
 482 {
 483         switch (level) {
 484         case SND_SOC_BIAS_ON:
 485                 /* Switch on PLL */
 486                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 487                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
 488
 489                 /* Switch on NDAC Divider */
 490                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 491                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
 492
 493                 /* Switch on MDAC Divider */
 494                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 495                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
 496
 497                 /* Switch on NADC Divider */
 498                 snd_soc_update_bits(codec, AIC32X4_NADC,
 499                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
 500
 501                 /* Switch on MADC Divider */
 502                 snd_soc_update_bits(codec, AIC32X4_MADC,
 503                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
 504
 505                 /* Switch on BCLK_N Divider */
 506                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 507                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 508                 break;
 509         case SND_SOC_BIAS_PREPARE:
 510                 break;
 511         case SND_SOC_BIAS_STANDBY:
 512                 /* Switch off PLL */
 513                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 514                                     AIC32X4_PLLEN, 0);
 515
 516                 /* Switch off NDAC Divider */
 517                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 518                                     AIC32X4_NDACEN, 0);
 519
 520                 /* Switch off MDAC Divider */
 521                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 522                                     AIC32X4_MDACEN, 0);
 523
 524                 /* Switch off NADC Divider */
 525                 snd_soc_update_bits(codec, AIC32X4_NADC,
 526                                     AIC32X4_NADCEN, 0);
 527
 528                 /* Switch off MADC Divider */
 529                 snd_soc_update_bits(codec, AIC32X4_MADC,
 530                                     AIC32X4_MADCEN, 0);
 531
 532                 /* Switch off BCLK_N Divider */
 533                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 534                                     AIC32X4_BCLKEN, 0);
 535                 break;
 536         case SND_SOC_BIAS_OFF:
 537                 break;
 538         }
 539         codec->dapm.bias_level = level;
 540         return 0;
 541 }
 542
 543 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
 544 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 545                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 546
 547 static const struct snd_soc_dai_ops aic32x4_ops = {
 548         .hw_params = aic32x4_hw_params,
 549         .digital_mute = aic32x4_mute,
 550         .set_fmt = aic32x4_set_dai_fmt,
 551         .set_sysclk = aic32x4_set_dai_sysclk,
 552 };
 553
 554 static struct snd_soc_dai_driver aic32x4_dai = {
 555         .name = "tlv320aic32x4-hifi",
 556         .playback = {
 557                      .stream_name = "Playback",
 558                      .channels_min = 1,
 559                      .channels_max = 2,
 560                      .rates = AIC32X4_RATES,
 561                      .formats = AIC32X4_FORMATS,},
 562         .capture = {
 563                     .stream_name = "Capture",
 564                     .channels_min = 1,
 565                     .channels_max = 2,
 566                     .rates = AIC32X4_RATES,
 567                     .formats = AIC32X4_FORMATS,},
 568         .ops = &aic32x4_ops,
 569         .symmetric_rates = 1,
 570 };
 571
 572 static int aic32x4_suspend(struct snd_soc_codec *codec)
 573 {
 574         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 575         return 0;
 576 }
 577
 578 static int aic32x4_resume(struct snd_soc_codec *codec)
 579 {
 580         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 581         return 0;
 582 }
 583
 584 static int aic32x4_probe(struct snd_soc_codec *codec)
 585 {
 586         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 587         u32 tmp_reg;
 588
 589         snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
 590
 591         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 592                 ndelay(10);
 593                 gpio_set_value(aic32x4->rstn_gpio, 1);
 594         }
 595
 596         snd_soc_write(codec, AIC32X4_RESET, 0x01);
 597
 598         /* Power platform configuration */
 599         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 600                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 601                                                       AIC32X4_MICBIAS_2075V);
 602         }
 603         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
 604                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 605         }
 606
 607         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
 608                         AIC32X4_LDOCTLEN : 0;
 609         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
 610
 611         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
 612         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
 613                 tmp_reg |= AIC32X4_LDOIN_18_36;
 614         }
 615         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
 616                 tmp_reg |= AIC32X4_LDOIN2HP;
 617         }
 618         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 619
 620         /* Mic PGA routing */
 621         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
 622                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
 623         else
 624                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K);
 625         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
 626                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
 627         else
 628                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K);
 629
 630         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 631
 632         /*
 633          * Workaround: for an unknown reason, the ADC needs to be powered up
 634          * and down for the first capture to work properly. It seems related to
 635          * a HW BUG or some kind of behavior not documented in the datasheet.
 636          */
 637         tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
 638         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
 639                                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
 640         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
 641
 642         return 0;
 643 }
 644
 645 static int aic32x4_remove(struct snd_soc_codec *codec)
 646 {
 647         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 648         return 0;
 649 }
 650
 651 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
 652         .probe = aic32x4_probe,
 653         .remove = aic32x4_remove,
 654         .suspend = aic32x4_suspend,
 655         .resume = aic32x4_resume,
 656         .set_bias_level = aic32x4_set_bias_level,
 657
 658         .controls = aic32x4_snd_controls,
 659         .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
 660         .dapm_widgets = aic32x4_dapm_widgets,
 661         .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
 662         .dapm_routes = aic32x4_dapm_routes,
 663         .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
 664 };
 665
 666 static int aic32x4_i2c_probe(struct i2c_client *i2c,
 667                              const struct i2c_device_id *id)
 668 {
 669         struct aic32x4_pdata *pdata = i2c->dev.platform_data;
 670         struct aic32x4_priv *aic32x4;
 671         int ret;
 672
 673         aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
 674                                GFP_KERNEL);
 675         if (aic32x4 == NULL)
 676                 return -ENOMEM;
 677
 678         aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap);
 679         if (IS_ERR(aic32x4->regmap))
 680                 return PTR_ERR(aic32x4->regmap);
 681
 682         i2c_set_clientdata(i2c, aic32x4);
 683
 684         if (pdata) {
 685                 aic32x4->power_cfg = pdata->power_cfg;
 686                 aic32x4->swapdacs = pdata->swapdacs;
 687                 aic32x4->micpga_routing = pdata->micpga_routing;
 688                 aic32x4->rstn_gpio = pdata->rstn_gpio;
 689         } else {
 690                 aic32x4->power_cfg = 0;
 691                 aic32x4->swapdacs = false;
 692                 aic32x4->micpga_routing = 0;
 693                 aic32x4->rstn_gpio = -1;
 694         }
 695
 696         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 697                 ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio,
 698                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
 699                 if (ret != 0)
 700                         return ret;
 701         }
 702
 703         ret = snd_soc_register_codec(&i2c->dev,
 704                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
 705         return ret;
 706 }
 707
 708 static int aic32x4_i2c_remove(struct i2c_client *client)
 709 {
 710         snd_soc_unregister_codec(&client->dev);
 711         return 0;
 712 }
 713
 714 static const struct i2c_device_id aic32x4_i2c_id[] = {
 715         { "tlv320aic32x4", 0 },
 716         { }
 717 };
 718 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
 719
 720 static struct i2c_driver aic32x4_i2c_driver = {
 721         .driver = {
 722                 .name = "tlv320aic32x4",
 723                 .owner = THIS_MODULE,
 724         },
 725         .probe =    aic32x4_i2c_probe,
 726         .remove =   aic32x4_i2c_remove,
 727         .id_table = aic32x4_i2c_id,
 728 };
 729
 730 module_i2c_driver(aic32x4_i2c_driver);
 731
 732 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
 733 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
 734 MODULE_LICENSE("GPL");