sound/soc/codecs/tlv320aic32x4.c

   1 /*
   2  * linux/sound/soc/codecs/tlv320aic32x4.c
   3  *
   4  * Copyright 2011 Vista Silicon S.L.
   5  *
   6  * Author: Javier Martin <javier.martin@vista-silicon.com>
   7  *
   8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  23  * MA 02110-1301, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/i2c.h>
  34 #include <linux/cdev.h>
  35 #include <linux/slab.h>
  36 #include <linux/clk.h>
  37
  38 #include <sound/tlv320aic32x4.h>
  39 #include <sound/core.h>
  40 #include <sound/pcm.h>
  41 #include <sound/pcm_params.h>
  42 #include <sound/soc.h>
  43 #include <sound/soc-dapm.h>
  44 #include <sound/initval.h>
  45 #include <sound/tlv.h>
  46
  47 #include "tlv320aic32x4.h"
  48
  49 struct aic32x4_rate_divs {
  50         u32 mclk;
  51         u32 rate;
  52         u8 p_val;
  53         u8 pll_j;
  54         u16 pll_d;
  55         u16 dosr;
  56         u8 ndac;
  57         u8 mdac;
  58         u8 aosr;
  59         u8 nadc;
  60         u8 madc;
  61         u8 blck_N;
  62 };
  63
  64 struct aic32x4_priv {
  65         struct regmap *regmap;
  66         u32 sysclk;
  67         u32 power_cfg;
  68         u32 micpga_routing;
  69         bool swapdacs;
  70         int rstn_gpio;
  71         struct clk *mclk;
  72 };
  73
  74 /* 0dB min, 0.5dB steps */
  75 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
  76 /* -63.5dB min, 0.5dB steps */
  77 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
  78 /* -6dB min, 1dB steps */
  79 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
  80 /* -12dB min, 0.5dB steps */
  81 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
  82
  83 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
  84         SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
  85                         AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
  86         SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
  87                         AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
  88                         tlv_driver_gain),
  89         SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
  90                         AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
  91                         tlv_driver_gain),
  92         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
  93                         AIC32X4_HPRGAIN, 6, 0x01, 1),
  94         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
  95                         AIC32X4_LORGAIN, 6, 0x01, 1),
  96         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
  97                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
  98
  99         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
 100         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
 101
 102         SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
 103                         AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
 104         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
 105                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
 106
 107         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
 108
 109         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 110         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 111         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 112                         4, 0x07, 0),
 113         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 114                         0, 0x03, 0),
 115         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 116                         6, 0x03, 0),
 117         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 118                         1, 0x1F, 0),
 119         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 120                         0, 0x7F, 0),
 121         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 122                         3, 0x1F, 0),
 123         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 124                         3, 0x1F, 0),
 125         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 126                         0, 0x1F, 0),
 127         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 128                         0, 0x0F, 0),
 129 };
 130
 131 static const struct aic32x4_rate_divs aic32x4_divs[] = {
 132         /* 8k rate */
 133         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
 134         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
 135         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
 136         /* 11.025k rate */
 137         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
 138         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
 139         /* 16k rate */
 140         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
 141         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
 142         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
 143         /* 22.05k rate */
 144         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
 145         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
 146         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
 147         /* 32k rate */
 148         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
 149         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
 150         /* 44.1k rate */
 151         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
 152         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
 153         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
 154         /* 48k rate */
 155         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
 156         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
 157         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
 158 };
 159
 160 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 161         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 162         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 163 };
 164
 165 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 166         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 167         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 168 };
 169
 170 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 171         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 172 };
 173
 174 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 175         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 176 };
 177
 178 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
 179         SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
 180         SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
 181         SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
 182 };
 183
 184 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
 185         SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
 186         SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
 187         SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
 188 };
 189
 190 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 191         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 192         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 193                            &hpl_output_mixer_controls[0],
 194                            ARRAY_SIZE(hpl_output_mixer_controls)),
 195         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 196
 197         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 198                            &lol_output_mixer_controls[0],
 199                            ARRAY_SIZE(lol_output_mixer_controls)),
 200         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 201
 202         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 203         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 204                            &hpr_output_mixer_controls[0],
 205                            ARRAY_SIZE(hpr_output_mixer_controls)),
 206         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 207         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 208                            &lor_output_mixer_controls[0],
 209                            ARRAY_SIZE(lor_output_mixer_controls)),
 210         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 211         SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
 212                            &left_input_mixer_controls[0],
 213                            ARRAY_SIZE(left_input_mixer_controls)),
 214         SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
 215                            &right_input_mixer_controls[0],
 216                            ARRAY_SIZE(right_input_mixer_controls)),
 217         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 218         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 219         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
 220
 221         SND_SOC_DAPM_OUTPUT("HPL"),
 222         SND_SOC_DAPM_OUTPUT("HPR"),
 223         SND_SOC_DAPM_OUTPUT("LOL"),
 224         SND_SOC_DAPM_OUTPUT("LOR"),
 225         SND_SOC_DAPM_INPUT("IN1_L"),
 226         SND_SOC_DAPM_INPUT("IN1_R"),
 227         SND_SOC_DAPM_INPUT("IN2_L"),
 228         SND_SOC_DAPM_INPUT("IN2_R"),
 229         SND_SOC_DAPM_INPUT("IN3_L"),
 230         SND_SOC_DAPM_INPUT("IN3_R"),
 231 };
 232
 233 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 234         /* Left Output */
 235         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 236         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 237
 238         {"HPL Power", NULL, "HPL Output Mixer"},
 239         {"HPL", NULL, "HPL Power"},
 240
 241         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 242
 243         {"LOL Power", NULL, "LOL Output Mixer"},
 244         {"LOL", NULL, "LOL Power"},
 245
 246         /* Right Output */
 247         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 248         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 249
 250         {"HPR Power", NULL, "HPR Output Mixer"},
 251         {"HPR", NULL, "HPR Power"},
 252
 253         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 254
 255         {"LOR Power", NULL, "LOR Output Mixer"},
 256         {"LOR", NULL, "LOR Power"},
 257
 258         /* Left input */
 259         {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
 260         {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
 261         {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
 262
 263         {"Left ADC", NULL, "Left Input Mixer"},
 264
 265         /* Right Input */
 266         {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
 267         {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
 268         {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
 269
 270         {"Right ADC", NULL, "Right Input Mixer"},
 271 };
 272
 273 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 274         {
 275                 .selector_reg = 0,
 276                 .selector_mask  = 0xff,
 277                 .window_start = 0,
 278                 .window_len = 128,
 279                 .range_min = 0,
 280                 .range_max = AIC32X4_RMICPGAVOL,
 281         },
 282 };
 283
 284 static const struct regmap_config aic32x4_regmap = {
 285         .reg_bits = 8,
 286         .val_bits = 8,
 287
 288         .max_register = AIC32X4_RMICPGAVOL,
 289         .ranges = aic32x4_regmap_pages,
 290         .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
 291 };
 292
 293 static inline int aic32x4_get_divs(int mclk, int rate)
 294 {
 295         int i;
 296
 297         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 298                 if ((aic32x4_divs[i].rate == rate)
 299                     && (aic32x4_divs[i].mclk == mclk)) {
 300                         return i;
 301                 }
 302         }
 303         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
 304         return -EINVAL;
 305 }
 306
 307 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 308                                   int clk_id, unsigned int freq, int dir)
 309 {
 310         struct snd_soc_codec *codec = codec_dai->codec;
 311         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 312
 313         switch (freq) {
 314         case AIC32X4_FREQ_12000000:
 315         case AIC32X4_FREQ_24000000:
 316         case AIC32X4_FREQ_25000000:
 317                 aic32x4->sysclk = freq;
 318                 return 0;
 319         }
 320         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
 321         return -EINVAL;
 322 }
 323
 324 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 325 {
 326         struct snd_soc_codec *codec = codec_dai->codec;
 327         u8 iface_reg_1;
 328         u8 iface_reg_2;
 329         u8 iface_reg_3;
 330
 331         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
 332         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
 333         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
 334         iface_reg_2 = 0;
 335         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
 336         iface_reg_3 = iface_reg_3 & ~(1 << 3);
 337
 338         /* set master/slave audio interface */
 339         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 340         case SND_SOC_DAIFMT_CBM_CFM:
 341                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 342                 break;
 343         case SND_SOC_DAIFMT_CBS_CFS:
 344                 break;
 345         default:
 346                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 347                 return -EINVAL;
 348         }
 349
 350         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 351         case SND_SOC_DAIFMT_I2S:
 352                 break;
 353         case SND_SOC_DAIFMT_DSP_A:
 354                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 355                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 356                 iface_reg_2 = 0x01; /* add offset 1 */
 357                 break;
 358         case SND_SOC_DAIFMT_DSP_B:
 359                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 360                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 361                 break;
 362         case SND_SOC_DAIFMT_RIGHT_J:
 363                 iface_reg_1 |=
 364                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 365                 break;
 366         case SND_SOC_DAIFMT_LEFT_J:
 367                 iface_reg_1 |=
 368                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 369                 break;
 370         default:
 371                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 372                 return -EINVAL;
 373         }
 374
 375         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
 376         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
 377         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
 378         return 0;
 379 }
 380
 381 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 382                              struct snd_pcm_hw_params *params,
 383                              struct snd_soc_dai *dai)
 384 {
 385         struct snd_soc_codec *codec = dai->codec;
 386         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 387         u8 data;
 388         int i;
 389
 390         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
 391         if (i < 0) {
 392                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
 393                 return i;
 394         }
 395
 396         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
 397         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
 398         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
 399
 400         /* We will fix R value to 1 and will make P & J=K.D as varialble */
 401         data = snd_soc_read(codec, AIC32X4_PLLPR);
 402         data &= ~(7 << 4);
 403         snd_soc_write(codec, AIC32X4_PLLPR,
 404                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
 405
 406         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 407
 408         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 409         snd_soc_write(codec, AIC32X4_PLLDLSB,
 410                       (aic32x4_divs[i].pll_d & 0xff));
 411
 412         /* NDAC divider value */
 413         data = snd_soc_read(codec, AIC32X4_NDAC);
 414         data &= ~(0x7f);
 415         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
 416
 417         /* MDAC divider value */
 418         data = snd_soc_read(codec, AIC32X4_MDAC);
 419         data &= ~(0x7f);
 420         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
 421
 422         /* DOSR MSB & LSB values */
 423         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 424         snd_soc_write(codec, AIC32X4_DOSRLSB,
 425                       (aic32x4_divs[i].dosr & 0xff));
 426
 427         /* NADC divider value */
 428         data = snd_soc_read(codec, AIC32X4_NADC);
 429         data &= ~(0x7f);
 430         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
 431
 432         /* MADC divider value */
 433         data = snd_soc_read(codec, AIC32X4_MADC);
 434         data &= ~(0x7f);
 435         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
 436
 437         /* AOSR value */
 438         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 439
 440         /* BCLK N divider */
 441         data = snd_soc_read(codec, AIC32X4_BCLKN);
 442         data &= ~(0x7f);
 443         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
 444
 445         data = snd_soc_read(codec, AIC32X4_IFACE1);
 446         data = data & ~(3 << 4);
 447         switch (params_format(params)) {
 448         case SNDRV_PCM_FORMAT_S16_LE:
 449                 break;
 450         case SNDRV_PCM_FORMAT_S20_3LE:
 451                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
 452                 break;
 453         case SNDRV_PCM_FORMAT_S24_LE:
 454                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
 455                 break;
 456         case SNDRV_PCM_FORMAT_S32_LE:
 457                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
 458                 break;
 459         }
 460         snd_soc_write(codec, AIC32X4_IFACE1, data);
 461
 462         if (params_channels(params) == 1) {
 463                 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 464         } else {
 465                 if (aic32x4->swapdacs)
 466                         data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
 467                 else
 468                         data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 469         }
 470         snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
 471                         data);
 472
 473         return 0;
 474 }
 475
 476 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
 477 {
 478         struct snd_soc_codec *codec = dai->codec;
 479         u8 dac_reg;
 480
 481         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
 482         if (mute)
 483                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
 484         else
 485                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
 486         return 0;
 487 }
 488
 489 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 490                                   enum snd_soc_bias_level level)
 491 {
 492         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 493         int ret;
 494
 495         switch (level) {
 496         case SND_SOC_BIAS_ON:
 497                 /* Switch on master clock */
 498                 ret = clk_prepare_enable(aic32x4->mclk);
 499                 if (ret) {
 500                         dev_err(codec->dev, "Failed to enable master clock\n");
 501                         return ret;
 502                 }
 503
 504                 /* Switch on PLL */
 505                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 506                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
 507
 508                 /* Switch on NDAC Divider */
 509                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 510                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
 511
 512                 /* Switch on MDAC Divider */
 513                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 514                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
 515
 516                 /* Switch on NADC Divider */
 517                 snd_soc_update_bits(codec, AIC32X4_NADC,
 518                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
 519
 520                 /* Switch on MADC Divider */
 521                 snd_soc_update_bits(codec, AIC32X4_MADC,
 522                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
 523
 524                 /* Switch on BCLK_N Divider */
 525                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 526                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 527                 break;
 528         case SND_SOC_BIAS_PREPARE:
 529                 break;
 530         case SND_SOC_BIAS_STANDBY:
 531                 /* Switch off PLL */
 532                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 533                                     AIC32X4_PLLEN, 0);
 534
 535                 /* Switch off NDAC Divider */
 536                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 537                                     AIC32X4_NDACEN, 0);
 538
 539                 /* Switch off MDAC Divider */
 540                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 541                                     AIC32X4_MDACEN, 0);
 542
 543                 /* Switch off NADC Divider */
 544                 snd_soc_update_bits(codec, AIC32X4_NADC,
 545                                     AIC32X4_NADCEN, 0);
 546
 547                 /* Switch off MADC Divider */
 548                 snd_soc_update_bits(codec, AIC32X4_MADC,
 549                                     AIC32X4_MADCEN, 0);
 550
 551                 /* Switch off BCLK_N Divider */
 552                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 553                                     AIC32X4_BCLKEN, 0);
 554
 555                 /* Switch off master clock */
 556                 clk_disable_unprepare(aic32x4->mclk);
 557                 break;
 558         case SND_SOC_BIAS_OFF:
 559                 break;
 560         }
 561         codec->dapm.bias_level = level;
 562         return 0;
 563 }
 564
 565 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
 566 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 567                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 568
 569 static const struct snd_soc_dai_ops aic32x4_ops = {
 570         .hw_params = aic32x4_hw_params,
 571         .digital_mute = aic32x4_mute,
 572         .set_fmt = aic32x4_set_dai_fmt,
 573         .set_sysclk = aic32x4_set_dai_sysclk,
 574 };
 575
 576 static struct snd_soc_dai_driver aic32x4_dai = {
 577         .name = "tlv320aic32x4-hifi",
 578         .playback = {
 579                      .stream_name = "Playback",
 580                      .channels_min = 1,
 581                      .channels_max = 2,
 582                      .rates = AIC32X4_RATES,
 583                      .formats = AIC32X4_FORMATS,},
 584         .capture = {
 585                     .stream_name = "Capture",
 586                     .channels_min = 1,
 587                     .channels_max = 2,
 588                     .rates = AIC32X4_RATES,
 589                     .formats = AIC32X4_FORMATS,},
 590         .ops = &aic32x4_ops,
 591         .symmetric_rates = 1,
 592 };
 593
 594 static int aic32x4_suspend(struct snd_soc_codec *codec)
 595 {
 596         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 597         return 0;
 598 }
 599
 600 static int aic32x4_resume(struct snd_soc_codec *codec)
 601 {
 602         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 603         return 0;
 604 }
 605
 606 static int aic32x4_probe(struct snd_soc_codec *codec)
 607 {
 608         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 609         u32 tmp_reg;
 610
 611         snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
 612
 613         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 614                 ndelay(10);
 615                 gpio_set_value(aic32x4->rstn_gpio, 1);
 616         }
 617
 618         snd_soc_write(codec, AIC32X4_RESET, 0x01);
 619
 620         /* Power platform configuration */
 621         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 622                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 623                                                       AIC32X4_MICBIAS_2075V);
 624         }
 625         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
 626                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 627         }
 628
 629         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
 630                         AIC32X4_LDOCTLEN : 0;
 631         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
 632
 633         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
 634         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
 635                 tmp_reg |= AIC32X4_LDOIN_18_36;
 636         }
 637         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
 638                 tmp_reg |= AIC32X4_LDOIN2HP;
 639         }
 640         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 641
 642         /* Mic PGA routing */
 643         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
 644                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
 645         else
 646                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K);
 647         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
 648                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
 649         else
 650                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K);
 651
 652         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 653
 654         /*
 655          * Workaround: for an unknown reason, the ADC needs to be powered up
 656          * and down for the first capture to work properly. It seems related to
 657          * a HW BUG or some kind of behavior not documented in the datasheet.
 658          */
 659         tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
 660         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
 661                                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
 662         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
 663
 664         return 0;
 665 }
 666
 667 static int aic32x4_remove(struct snd_soc_codec *codec)
 668 {
 669         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 670         return 0;
 671 }
 672
 673 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
 674         .probe = aic32x4_probe,
 675         .remove = aic32x4_remove,
 676         .suspend = aic32x4_suspend,
 677         .resume = aic32x4_resume,
 678         .set_bias_level = aic32x4_set_bias_level,
 679
 680         .controls = aic32x4_snd_controls,
 681         .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
 682         .dapm_widgets = aic32x4_dapm_widgets,
 683         .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
 684         .dapm_routes = aic32x4_dapm_routes,
 685         .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
 686 };
 687
 688 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
 689                 struct device_node *np)
 690 {
 691         aic32x4->swapdacs = false;
 692         aic32x4->micpga_routing = 0;
 693         aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
 694
 695         return 0;
 696 }
 697
 698 static int aic32x4_i2c_probe(struct i2c_client *i2c,
 699                              const struct i2c_device_id *id)
 700 {
 701         struct aic32x4_pdata *pdata = i2c->dev.platform_data;
 702         struct aic32x4_priv *aic32x4;
 703         struct device_node *np = i2c->dev.of_node;
 704         int ret;
 705
 706         aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
 707                                GFP_KERNEL);
 708         if (aic32x4 == NULL)
 709                 return -ENOMEM;
 710
 711         aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap);
 712         if (IS_ERR(aic32x4->regmap))
 713                 return PTR_ERR(aic32x4->regmap);
 714
 715         i2c_set_clientdata(i2c, aic32x4);
 716
 717         if (pdata) {
 718                 aic32x4->power_cfg = pdata->power_cfg;
 719                 aic32x4->swapdacs = pdata->swapdacs;
 720                 aic32x4->micpga_routing = pdata->micpga_routing;
 721                 aic32x4->rstn_gpio = pdata->rstn_gpio;
 722         } else if (np) {
 723                 ret = aic32x4_parse_dt(aic32x4, np);
 724                 if (ret) {
 725                         dev_err(&i2c->dev, "Failed to parse DT node\n");
 726                         return ret;
 727                 }
 728         } else {
 729                 aic32x4->power_cfg = 0;
 730                 aic32x4->swapdacs = false;
 731                 aic32x4->micpga_routing = 0;
 732                 aic32x4->rstn_gpio = -1;
 733         }
 734
 735         aic32x4->mclk = devm_clk_get(&i2c->dev, "mclk");
 736         if (IS_ERR(aic32x4->mclk)) {
 737                 dev_err(&i2c->dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
 738                 return PTR_ERR(aic32x4->mclk);
 739         }
 740
 741         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 742                 ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio,
 743                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
 744                 if (ret != 0)
 745                         return ret;
 746         }
 747
 748         ret = snd_soc_register_codec(&i2c->dev,
 749                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
 750         return ret;
 751 }
 752
 753 static int aic32x4_i2c_remove(struct i2c_client *client)
 754 {
 755         snd_soc_unregister_codec(&client->dev);
 756         return 0;
 757 }
 758
 759 static const struct i2c_device_id aic32x4_i2c_id[] = {
 760         { "tlv320aic32x4", 0 },
 761         { }
 762 };
 763 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
 764
 765 static const struct of_device_id aic32x4_of_id[] = {
 766         { .compatible = "ti,tlv320aic32x4", },
 767         { /* senitel */ }
 768 };
 769 MODULE_DEVICE_TABLE(of, aic32x4_of_id);
 770
 771 static struct i2c_driver aic32x4_i2c_driver = {
 772         .driver = {
 773                 .name = "tlv320aic32x4",
 774                 .owner = THIS_MODULE,
 775                 .of_match_table = aic32x4_of_id,
 776         },
 777         .probe =    aic32x4_i2c_probe,
 778         .remove =   aic32x4_i2c_remove,
 779         .id_table = aic32x4_i2c_id,
 780 };
 781
 782 module_i2c_driver(aic32x4_i2c_driver);
 783
 784 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
 785 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
 786 MODULE_LICENSE("GPL");