sound/soc/codecs/tlv320aic32x4.c

   1 /*
   2  * linux/sound/soc/codecs/tlv320aic32x4.c
   3  *
   4  * Copyright 2011 Vista Silicon S.L.
   5  *
   6  * Author: Javier Martin <javier.martin@vista-silicon.com>
   7  *
   8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  23  * MA 02110-1301, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/i2c.h>
  34 #include <linux/cdev.h>
  35 #include <linux/slab.h>
  36 #include <linux/clk.h>
  37 #include <linux/regulator/consumer.h>
  38
  39 #include <sound/tlv320aic32x4.h>
  40 #include <sound/core.h>
  41 #include <sound/pcm.h>
  42 #include <sound/pcm_params.h>
  43 #include <sound/soc.h>
  44 #include <sound/soc-dapm.h>
  45 #include <sound/initval.h>
  46 #include <sound/tlv.h>
  47
  48 #include "tlv320aic32x4.h"
  49
  50 struct aic32x4_rate_divs {
  51         u32 mclk;
  52         u32 rate;
  53         u8 p_val;
  54         u8 pll_j;
  55         u16 pll_d;
  56         u16 dosr;
  57         u8 ndac;
  58         u8 mdac;
  59         u8 aosr;
  60         u8 nadc;
  61         u8 madc;
  62         u8 blck_N;
  63 };
  64
  65 struct aic32x4_priv {
  66         struct regmap *regmap;
  67         u32 sysclk;
  68         u32 power_cfg;
  69         u32 micpga_routing;
  70         bool swapdacs;
  71         int rstn_gpio;
  72         struct clk *mclk;
  73
  74         struct regulator *supply_ldo;
  75         struct regulator *supply_iov;
  76         struct regulator *supply_dv;
  77         struct regulator *supply_av;
  78 };
  79
  80 /* 0dB min, 0.5dB steps */
  81 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
  82 /* -63.5dB min, 0.5dB steps */
  83 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
  84 /* -6dB min, 1dB steps */
  85 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
  86 /* -12dB min, 0.5dB steps */
  87 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
  88
  89 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
  90         SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
  91                         AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
  92         SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
  93                         AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
  94                         tlv_driver_gain),
  95         SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
  96                         AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
  97                         tlv_driver_gain),
  98         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
  99                         AIC32X4_HPRGAIN, 6, 0x01, 1),
 100         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
 101                         AIC32X4_LORGAIN, 6, 0x01, 1),
 102         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
 103                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
 104
 105         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
 106         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
 107
 108         SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
 109                         AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
 110         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
 111                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
 112
 113         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
 114
 115         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 116         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 117         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 118                         4, 0x07, 0),
 119         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 120                         0, 0x03, 0),
 121         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 122                         6, 0x03, 0),
 123         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 124                         1, 0x1F, 0),
 125         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 126                         0, 0x7F, 0),
 127         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 128                         3, 0x1F, 0),
 129         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 130                         3, 0x1F, 0),
 131         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 132                         0, 0x1F, 0),
 133         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 134                         0, 0x0F, 0),
 135 };
 136
 137 static const struct aic32x4_rate_divs aic32x4_divs[] = {
 138         /* 8k rate */
 139         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
 140         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
 141         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
 142         /* 11.025k rate */
 143         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
 144         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
 145         /* 16k rate */
 146         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
 147         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
 148         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
 149         /* 22.05k rate */
 150         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
 151         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
 152         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
 153         /* 32k rate */
 154         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
 155         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
 156         /* 44.1k rate */
 157         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
 158         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
 159         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
 160         /* 48k rate */
 161         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
 162         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
 163         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
 164 };
 165
 166 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 167         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 168         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 169 };
 170
 171 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 172         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 173         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 174 };
 175
 176 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 177         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 178 };
 179
 180 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 181         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 182 };
 183
 184 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
 185         SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
 186         SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
 187         SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
 188 };
 189
 190 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
 191         SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
 192         SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
 193         SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
 194 };
 195
 196 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 197         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 198         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 199                            &hpl_output_mixer_controls[0],
 200                            ARRAY_SIZE(hpl_output_mixer_controls)),
 201         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 202
 203         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 204                            &lol_output_mixer_controls[0],
 205                            ARRAY_SIZE(lol_output_mixer_controls)),
 206         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 207
 208         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 209         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 210                            &hpr_output_mixer_controls[0],
 211                            ARRAY_SIZE(hpr_output_mixer_controls)),
 212         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 213         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 214                            &lor_output_mixer_controls[0],
 215                            ARRAY_SIZE(lor_output_mixer_controls)),
 216         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 217         SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
 218                            &left_input_mixer_controls[0],
 219                            ARRAY_SIZE(left_input_mixer_controls)),
 220         SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
 221                            &right_input_mixer_controls[0],
 222                            ARRAY_SIZE(right_input_mixer_controls)),
 223         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 224         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 225         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
 226
 227         SND_SOC_DAPM_OUTPUT("HPL"),
 228         SND_SOC_DAPM_OUTPUT("HPR"),
 229         SND_SOC_DAPM_OUTPUT("LOL"),
 230         SND_SOC_DAPM_OUTPUT("LOR"),
 231         SND_SOC_DAPM_INPUT("IN1_L"),
 232         SND_SOC_DAPM_INPUT("IN1_R"),
 233         SND_SOC_DAPM_INPUT("IN2_L"),
 234         SND_SOC_DAPM_INPUT("IN2_R"),
 235         SND_SOC_DAPM_INPUT("IN3_L"),
 236         SND_SOC_DAPM_INPUT("IN3_R"),
 237 };
 238
 239 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 240         /* Left Output */
 241         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 242         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 243
 244         {"HPL Power", NULL, "HPL Output Mixer"},
 245         {"HPL", NULL, "HPL Power"},
 246
 247         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 248
 249         {"LOL Power", NULL, "LOL Output Mixer"},
 250         {"LOL", NULL, "LOL Power"},
 251
 252         /* Right Output */
 253         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 254         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 255
 256         {"HPR Power", NULL, "HPR Output Mixer"},
 257         {"HPR", NULL, "HPR Power"},
 258
 259         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 260
 261         {"LOR Power", NULL, "LOR Output Mixer"},
 262         {"LOR", NULL, "LOR Power"},
 263
 264         /* Left input */
 265         {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
 266         {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
 267         {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
 268
 269         {"Left ADC", NULL, "Left Input Mixer"},
 270
 271         /* Right Input */
 272         {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
 273         {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
 274         {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
 275
 276         {"Right ADC", NULL, "Right Input Mixer"},
 277 };
 278
 279 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 280         {
 281                 .selector_reg = 0,
 282                 .selector_mask  = 0xff,
 283                 .window_start = 0,
 284                 .window_len = 128,
 285                 .range_min = 0,
 286                 .range_max = AIC32X4_RMICPGAVOL,
 287         },
 288 };
 289
 290 static const struct regmap_config aic32x4_regmap = {
 291         .reg_bits = 8,
 292         .val_bits = 8,
 293
 294         .max_register = AIC32X4_RMICPGAVOL,
 295         .ranges = aic32x4_regmap_pages,
 296         .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
 297 };
 298
 299 static inline int aic32x4_get_divs(int mclk, int rate)
 300 {
 301         int i;
 302
 303         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 304                 if ((aic32x4_divs[i].rate == rate)
 305                     && (aic32x4_divs[i].mclk == mclk)) {
 306                         return i;
 307                 }
 308         }
 309         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
 310         return -EINVAL;
 311 }
 312
 313 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 314                                   int clk_id, unsigned int freq, int dir)
 315 {
 316         struct snd_soc_codec *codec = codec_dai->codec;
 317         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 318
 319         switch (freq) {
 320         case AIC32X4_FREQ_12000000:
 321         case AIC32X4_FREQ_24000000:
 322         case AIC32X4_FREQ_25000000:
 323                 aic32x4->sysclk = freq;
 324                 return 0;
 325         }
 326         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
 327         return -EINVAL;
 328 }
 329
 330 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 331 {
 332         struct snd_soc_codec *codec = codec_dai->codec;
 333         u8 iface_reg_1;
 334         u8 iface_reg_2;
 335         u8 iface_reg_3;
 336
 337         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
 338         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
 339         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
 340         iface_reg_2 = 0;
 341         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
 342         iface_reg_3 = iface_reg_3 & ~(1 << 3);
 343
 344         /* set master/slave audio interface */
 345         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 346         case SND_SOC_DAIFMT_CBM_CFM:
 347                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 348                 break;
 349         case SND_SOC_DAIFMT_CBS_CFS:
 350                 break;
 351         default:
 352                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 353                 return -EINVAL;
 354         }
 355
 356         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 357         case SND_SOC_DAIFMT_I2S:
 358                 break;
 359         case SND_SOC_DAIFMT_DSP_A:
 360                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 361                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 362                 iface_reg_2 = 0x01; /* add offset 1 */
 363                 break;
 364         case SND_SOC_DAIFMT_DSP_B:
 365                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 366                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 367                 break;
 368         case SND_SOC_DAIFMT_RIGHT_J:
 369                 iface_reg_1 |=
 370                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 371                 break;
 372         case SND_SOC_DAIFMT_LEFT_J:
 373                 iface_reg_1 |=
 374                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 375                 break;
 376         default:
 377                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 378                 return -EINVAL;
 379         }
 380
 381         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
 382         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
 383         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
 384         return 0;
 385 }
 386
 387 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 388                              struct snd_pcm_hw_params *params,
 389                              struct snd_soc_dai *dai)
 390 {
 391         struct snd_soc_codec *codec = dai->codec;
 392         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 393         u8 data;
 394         int i;
 395
 396         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
 397         if (i < 0) {
 398                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
 399                 return i;
 400         }
 401
 402         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
 403         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
 404         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
 405
 406         /* We will fix R value to 1 and will make P & J=K.D as varialble */
 407         data = snd_soc_read(codec, AIC32X4_PLLPR);
 408         data &= ~(7 << 4);
 409         snd_soc_write(codec, AIC32X4_PLLPR,
 410                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
 411
 412         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 413
 414         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 415         snd_soc_write(codec, AIC32X4_PLLDLSB,
 416                       (aic32x4_divs[i].pll_d & 0xff));
 417
 418         /* NDAC divider value */
 419         data = snd_soc_read(codec, AIC32X4_NDAC);
 420         data &= ~(0x7f);
 421         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
 422
 423         /* MDAC divider value */
 424         data = snd_soc_read(codec, AIC32X4_MDAC);
 425         data &= ~(0x7f);
 426         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
 427
 428         /* DOSR MSB & LSB values */
 429         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 430         snd_soc_write(codec, AIC32X4_DOSRLSB,
 431                       (aic32x4_divs[i].dosr & 0xff));
 432
 433         /* NADC divider value */
 434         data = snd_soc_read(codec, AIC32X4_NADC);
 435         data &= ~(0x7f);
 436         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
 437
 438         /* MADC divider value */
 439         data = snd_soc_read(codec, AIC32X4_MADC);
 440         data &= ~(0x7f);
 441         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
 442
 443         /* AOSR value */
 444         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 445
 446         /* BCLK N divider */
 447         data = snd_soc_read(codec, AIC32X4_BCLKN);
 448         data &= ~(0x7f);
 449         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
 450
 451         data = snd_soc_read(codec, AIC32X4_IFACE1);
 452         data = data & ~(3 << 4);
 453         switch (params_width(params)) {
 454         case 16:
 455                 break;
 456         case 20:
 457                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
 458                 break;
 459         case 24:
 460                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
 461                 break;
 462         case 32:
 463                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
 464                 break;
 465         }
 466         snd_soc_write(codec, AIC32X4_IFACE1, data);
 467
 468         if (params_channels(params) == 1) {
 469                 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 470         } else {
 471                 if (aic32x4->swapdacs)
 472                         data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
 473                 else
 474                         data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 475         }
 476         snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
 477                         data);
 478
 479         return 0;
 480 }
 481
 482 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
 483 {
 484         struct snd_soc_codec *codec = dai->codec;
 485         u8 dac_reg;
 486
 487         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
 488         if (mute)
 489                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
 490         else
 491                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
 492         return 0;
 493 }
 494
 495 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 496                                   enum snd_soc_bias_level level)
 497 {
 498         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 499         int ret;
 500
 501         switch (level) {
 502         case SND_SOC_BIAS_ON:
 503                 /* Switch on master clock */
 504                 ret = clk_prepare_enable(aic32x4->mclk);
 505                 if (ret) {
 506                         dev_err(codec->dev, "Failed to enable master clock\n");
 507                         return ret;
 508                 }
 509
 510                 /* Switch on PLL */
 511                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 512                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
 513
 514                 /* Switch on NDAC Divider */
 515                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 516                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
 517
 518                 /* Switch on MDAC Divider */
 519                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 520                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
 521
 522                 /* Switch on NADC Divider */
 523                 snd_soc_update_bits(codec, AIC32X4_NADC,
 524                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
 525
 526                 /* Switch on MADC Divider */
 527                 snd_soc_update_bits(codec, AIC32X4_MADC,
 528                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
 529
 530                 /* Switch on BCLK_N Divider */
 531                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 532                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 533                 break;
 534         case SND_SOC_BIAS_PREPARE:
 535                 break;
 536         case SND_SOC_BIAS_STANDBY:
 537                 /* Switch off BCLK_N Divider */
 538                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 539                                     AIC32X4_BCLKEN, 0);
 540
 541                 /* Switch off MADC Divider */
 542                 snd_soc_update_bits(codec, AIC32X4_MADC,
 543                                     AIC32X4_MADCEN, 0);
 544
 545                 /* Switch off NADC Divider */
 546                 snd_soc_update_bits(codec, AIC32X4_NADC,
 547                                     AIC32X4_NADCEN, 0);
 548
 549                 /* Switch off MDAC Divider */
 550                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 551                                     AIC32X4_MDACEN, 0);
 552
 553                 /* Switch off NDAC Divider */
 554                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 555                                     AIC32X4_NDACEN, 0);
 556
 557                 /* Switch off PLL */
 558                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 559                                     AIC32X4_PLLEN, 0);
 560
 561                 /* Switch off master clock */
 562                 clk_disable_unprepare(aic32x4->mclk);
 563                 break;
 564         case SND_SOC_BIAS_OFF:
 565                 break;
 566         }
 567         return 0;
 568 }
 569
 570 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
 571 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 572                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 573
 574 static const struct snd_soc_dai_ops aic32x4_ops = {
 575         .hw_params = aic32x4_hw_params,
 576         .digital_mute = aic32x4_mute,
 577         .set_fmt = aic32x4_set_dai_fmt,
 578         .set_sysclk = aic32x4_set_dai_sysclk,
 579 };
 580
 581 static struct snd_soc_dai_driver aic32x4_dai = {
 582         .name = "tlv320aic32x4-hifi",
 583         .playback = {
 584                      .stream_name = "Playback",
 585                      .channels_min = 1,
 586                      .channels_max = 2,
 587                      .rates = AIC32X4_RATES,
 588                      .formats = AIC32X4_FORMATS,},
 589         .capture = {
 590                     .stream_name = "Capture",
 591                     .channels_min = 1,
 592                     .channels_max = 2,
 593                     .rates = AIC32X4_RATES,
 594                     .formats = AIC32X4_FORMATS,},
 595         .ops = &aic32x4_ops,
 596         .symmetric_rates = 1,
 597 };
 598
 599 static int aic32x4_probe(struct snd_soc_codec *codec)
 600 {
 601         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 602         u32 tmp_reg;
 603
 604         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 605                 ndelay(10);
 606                 gpio_set_value(aic32x4->rstn_gpio, 1);
 607         }
 608
 609         snd_soc_write(codec, AIC32X4_RESET, 0x01);
 610
 611         /* Power platform configuration */
 612         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 613                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 614                                                       AIC32X4_MICBIAS_2075V);
 615         }
 616         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
 617                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 618
 619         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
 620                         AIC32X4_LDOCTLEN : 0;
 621         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
 622
 623         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
 624         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
 625                 tmp_reg |= AIC32X4_LDOIN_18_36;
 626         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
 627                 tmp_reg |= AIC32X4_LDOIN2HP;
 628         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 629
 630         /* Mic PGA routing */
 631         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
 632                 snd_soc_write(codec, AIC32X4_LMICPGANIN,
 633                                 AIC32X4_LMICPGANIN_IN2R_10K);
 634         else
 635                 snd_soc_write(codec, AIC32X4_LMICPGANIN,
 636                                 AIC32X4_LMICPGANIN_CM1L_10K);
 637         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
 638                 snd_soc_write(codec, AIC32X4_RMICPGANIN,
 639                                 AIC32X4_RMICPGANIN_IN1L_10K);
 640         else
 641                 snd_soc_write(codec, AIC32X4_RMICPGANIN,
 642                                 AIC32X4_RMICPGANIN_CM1R_10K);
 643
 644         /*
 645          * Workaround: for an unknown reason, the ADC needs to be powered up
 646          * and down for the first capture to work properly. It seems related to
 647          * a HW BUG or some kind of behavior not documented in the datasheet.
 648          */
 649         tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
 650         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
 651                                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
 652         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
 653
 654         return 0;
 655 }
 656
 657 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
 658         .probe = aic32x4_probe,
 659         .set_bias_level = aic32x4_set_bias_level,
 660         .suspend_bias_off = true,
 661
 662         .controls = aic32x4_snd_controls,
 663         .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
 664         .dapm_widgets = aic32x4_dapm_widgets,
 665         .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
 666         .dapm_routes = aic32x4_dapm_routes,
 667         .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
 668 };
 669
 670 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
 671                 struct device_node *np)
 672 {
 673         aic32x4->swapdacs = false;
 674         aic32x4->micpga_routing = 0;
 675         aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
 676
 677         return 0;
 678 }
 679
 680 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
 681 {
 682         regulator_disable(aic32x4->supply_iov);
 683
 684         if (!IS_ERR(aic32x4->supply_ldo))
 685                 regulator_disable(aic32x4->supply_ldo);
 686
 687         if (!IS_ERR(aic32x4->supply_dv))
 688                 regulator_disable(aic32x4->supply_dv);
 689
 690         if (!IS_ERR(aic32x4->supply_av))
 691                 regulator_disable(aic32x4->supply_av);
 692 }
 693
 694 static int aic32x4_setup_regulators(struct device *dev,
 695                 struct aic32x4_priv *aic32x4)
 696 {
 697         int ret = 0;
 698
 699         aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
 700         aic32x4->supply_iov = devm_regulator_get(dev, "iov");
 701         aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
 702         aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
 703
 704         /* Check if the regulator requirements are fulfilled */
 705
 706         if (IS_ERR(aic32x4->supply_iov)) {
 707                 dev_err(dev, "Missing supply 'iov'\n");
 708                 return PTR_ERR(aic32x4->supply_iov);
 709         }
 710
 711         if (IS_ERR(aic32x4->supply_ldo)) {
 712                 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
 713                         return -EPROBE_DEFER;
 714
 715                 if (IS_ERR(aic32x4->supply_dv)) {
 716                         dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
 717                         return PTR_ERR(aic32x4->supply_dv);
 718                 }
 719                 if (IS_ERR(aic32x4->supply_av)) {
 720                         dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
 721                         return PTR_ERR(aic32x4->supply_av);
 722                 }
 723         } else {
 724                 if (IS_ERR(aic32x4->supply_dv) &&
 725                                 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
 726                         return -EPROBE_DEFER;
 727                 if (IS_ERR(aic32x4->supply_av) &&
 728                                 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
 729                         return -EPROBE_DEFER;
 730         }
 731
 732         ret = regulator_enable(aic32x4->supply_iov);
 733         if (ret) {
 734                 dev_err(dev, "Failed to enable regulator iov\n");
 735                 return ret;
 736         }
 737
 738         if (!IS_ERR(aic32x4->supply_ldo)) {
 739                 ret = regulator_enable(aic32x4->supply_ldo);
 740                 if (ret) {
 741                         dev_err(dev, "Failed to enable regulator ldo\n");
 742                         goto error_ldo;
 743                 }
 744         }
 745
 746         if (!IS_ERR(aic32x4->supply_dv)) {
 747                 ret = regulator_enable(aic32x4->supply_dv);
 748                 if (ret) {
 749                         dev_err(dev, "Failed to enable regulator dv\n");
 750                         goto error_dv;
 751                 }
 752         }
 753
 754         if (!IS_ERR(aic32x4->supply_av)) {
 755                 ret = regulator_enable(aic32x4->supply_av);
 756                 if (ret) {
 757                         dev_err(dev, "Failed to enable regulator av\n");
 758                         goto error_av;
 759                 }
 760         }
 761
 762         if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
 763                 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
 764
 765         return 0;
 766
 767 error_av:
 768         if (!IS_ERR(aic32x4->supply_dv))
 769                 regulator_disable(aic32x4->supply_dv);
 770
 771 error_dv:
 772         if (!IS_ERR(aic32x4->supply_ldo))
 773                 regulator_disable(aic32x4->supply_ldo);
 774
 775 error_ldo:
 776         regulator_disable(aic32x4->supply_iov);
 777         return ret;
 778 }
 779
 780 static int aic32x4_i2c_probe(struct i2c_client *i2c,
 781                              const struct i2c_device_id *id)
 782 {
 783         struct aic32x4_pdata *pdata = i2c->dev.platform_data;
 784         struct aic32x4_priv *aic32x4;
 785         struct device_node *np = i2c->dev.of_node;
 786         int ret;
 787
 788         aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
 789                                GFP_KERNEL);
 790         if (aic32x4 == NULL)
 791                 return -ENOMEM;
 792
 793         aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap);
 794         if (IS_ERR(aic32x4->regmap))
 795                 return PTR_ERR(aic32x4->regmap);
 796
 797         i2c_set_clientdata(i2c, aic32x4);
 798
 799         if (pdata) {
 800                 aic32x4->power_cfg = pdata->power_cfg;
 801                 aic32x4->swapdacs = pdata->swapdacs;
 802                 aic32x4->micpga_routing = pdata->micpga_routing;
 803                 aic32x4->rstn_gpio = pdata->rstn_gpio;
 804         } else if (np) {
 805                 ret = aic32x4_parse_dt(aic32x4, np);
 806                 if (ret) {
 807                         dev_err(&i2c->dev, "Failed to parse DT node\n");
 808                         return ret;
 809                 }
 810         } else {
 811                 aic32x4->power_cfg = 0;
 812                 aic32x4->swapdacs = false;
 813                 aic32x4->micpga_routing = 0;
 814                 aic32x4->rstn_gpio = -1;
 815         }
 816
 817         aic32x4->mclk = devm_clk_get(&i2c->dev, "mclk");
 818         if (IS_ERR(aic32x4->mclk)) {
 819                 dev_err(&i2c->dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
 820                 return PTR_ERR(aic32x4->mclk);
 821         }
 822
 823         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 824                 ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio,
 825                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
 826                 if (ret != 0)
 827                         return ret;
 828         }
 829
 830         ret = aic32x4_setup_regulators(&i2c->dev, aic32x4);
 831         if (ret) {
 832                 dev_err(&i2c->dev, "Failed to setup regulators\n");
 833                 return ret;
 834         }
 835
 836         ret = snd_soc_register_codec(&i2c->dev,
 837                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
 838         if (ret) {
 839                 dev_err(&i2c->dev, "Failed to register codec\n");
 840                 aic32x4_disable_regulators(aic32x4);
 841                 return ret;
 842         }
 843
 844         i2c_set_clientdata(i2c, aic32x4);
 845
 846         return 0;
 847 }
 848
 849 static int aic32x4_i2c_remove(struct i2c_client *client)
 850 {
 851         struct aic32x4_priv *aic32x4 = i2c_get_clientdata(client);
 852
 853         aic32x4_disable_regulators(aic32x4);
 854
 855         snd_soc_unregister_codec(&client->dev);
 856         return 0;
 857 }
 858
 859 static const struct i2c_device_id aic32x4_i2c_id[] = {
 860         { "tlv320aic32x4", 0 },
 861         { }
 862 };
 863 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
 864
 865 static const struct of_device_id aic32x4_of_id[] = {
 866         { .compatible = "ti,tlv320aic32x4", },
 867         { /* senitel */ }
 868 };
 869 MODULE_DEVICE_TABLE(of, aic32x4_of_id);
 870
 871 static struct i2c_driver aic32x4_i2c_driver = {
 872         .driver = {
 873                 .name = "tlv320aic32x4",
 874                 .owner = THIS_MODULE,
 875                 .of_match_table = aic32x4_of_id,
 876         },
 877         .probe =    aic32x4_i2c_probe,
 878         .remove =   aic32x4_i2c_remove,
 879         .id_table = aic32x4_i2c_id,
 880 };
 881
 882 module_i2c_driver(aic32x4_i2c_driver);
 883
 884 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
 885 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
 886 MODULE_LICENSE("GPL");