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ASoC: tlv320aic3x: Sanitize output controls
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 /* codec private data */
65 struct aic3x_priv {
66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
70 unsigned int sysclk;
71 int master;
72 int gpio_reset;
73 #define AIC3X_MODEL_3X 0
74 #define AIC3X_MODEL_33 1
75 #define AIC3X_MODEL_3007 2
76 u16 model;
77 };
78
79 /*
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
84 */
85 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
112 };
113
114 /*
115 * read aic3x register cache
116 */
117 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
118 unsigned int reg)
119 {
120 u8 *cache = codec->reg_cache;
121 if (reg >= AIC3X_CACHEREGNUM)
122 return -1;
123 return cache[reg];
124 }
125
126 /*
127 * write aic3x register cache
128 */
129 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
130 u8 reg, u8 value)
131 {
132 u8 *cache = codec->reg_cache;
133 if (reg >= AIC3X_CACHEREGNUM)
134 return;
135 cache[reg] = value;
136 }
137
138 /*
139 * write to the aic3x register space
140 */
141 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
142 unsigned int value)
143 {
144 u8 data[2];
145
146 /* data is
147 * D15..D8 aic3x register offset
148 * D7...D0 register data
149 */
150 data[0] = reg & 0xff;
151 data[1] = value & 0xff;
152
153 aic3x_write_reg_cache(codec, data[0], data[1]);
154 if (codec->hw_write(codec->control_data, data, 2) == 2)
155 return 0;
156 else
157 return -EIO;
158 }
159
160 /*
161 * read from the aic3x register space
162 */
163 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
164 u8 *value)
165 {
166 *value = reg & 0xff;
167
168 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
169
170 aic3x_write_reg_cache(codec, reg, *value);
171 return 0;
172 }
173
174 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
175 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
176 .info = snd_soc_info_volsw, \
177 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
178 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
179
180 /*
181 * All input lines are connected when !0xf and disconnected with 0xf bit field,
182 * so we have to use specific dapm_put call for input mixer
183 */
184 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
185 struct snd_ctl_elem_value *ucontrol)
186 {
187 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
188 struct soc_mixer_control *mc =
189 (struct soc_mixer_control *)kcontrol->private_value;
190 unsigned int reg = mc->reg;
191 unsigned int shift = mc->shift;
192 int max = mc->max;
193 unsigned int mask = (1 << fls(max)) - 1;
194 unsigned int invert = mc->invert;
195 unsigned short val, val_mask;
196 int ret;
197 struct snd_soc_dapm_path *path;
198 int found = 0;
199
200 val = (ucontrol->value.integer.value[0] & mask);
201
202 mask = 0xf;
203 if (val)
204 val = mask;
205
206 if (invert)
207 val = mask - val;
208 val_mask = mask << shift;
209 val = val << shift;
210
211 mutex_lock(&widget->codec->mutex);
212
213 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
214 /* find dapm widget path assoc with kcontrol */
215 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
216 if (path->kcontrol != kcontrol)
217 continue;
218
219 /* found, now check type */
220 found = 1;
221 if (val)
222 /* new connection */
223 path->connect = invert ? 0 : 1;
224 else
225 /* old connection must be powered down */
226 path->connect = invert ? 1 : 0;
227 break;
228 }
229
230 if (found)
231 snd_soc_dapm_sync(widget->codec);
232 }
233
234 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
235
236 mutex_unlock(&widget->codec->mutex);
237 return ret;
238 }
239
240 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
241 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
242 static const char *aic3x_left_hpcom_mux[] =
243 { "differential of HPLOUT", "constant VCM", "single-ended" };
244 static const char *aic3x_right_hpcom_mux[] =
245 { "differential of HPROUT", "constant VCM", "single-ended",
246 "differential of HPLCOM", "external feedback" };
247 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
248 static const char *aic3x_adc_hpf[] =
249 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
250
251 #define LDAC_ENUM 0
252 #define RDAC_ENUM 1
253 #define LHPCOM_ENUM 2
254 #define RHPCOM_ENUM 3
255 #define LINE1L_ENUM 4
256 #define LINE1R_ENUM 5
257 #define LINE2L_ENUM 6
258 #define LINE2R_ENUM 7
259 #define ADC_HPF_ENUM 8
260
261 static const struct soc_enum aic3x_enum[] = {
262 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
263 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
264 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
265 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
266 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
267 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
268 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
269 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
270 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
271 };
272
273 /*
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
275 */
276 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
279 /*
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
287 */
288 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
289
290 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
291 /* Output */
292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
294
295 /*
296 * Output controls that map to output mixer switches. Note these are
297 * only for swapped L-to-R and R-to-L routes. See below stereo controls
298 * for direct L-to-L and R-to-R routes.
299 */
300 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
301 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
303 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
305 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306
307 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
308 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
310 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
312 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313
314 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
315 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
317 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
319 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320
321 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
322 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
324 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
326 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327
328 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
329 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
331 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
333 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334
335 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
336 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
338 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
340 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341
342 /* Stereo output controls for direct L-to-L and R-to-R routes */
343 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
344 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
347 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
348 0, 118, 1, output_stage_tlv),
349 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
350 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
351 0, 118, 1, output_stage_tlv),
352
353 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
354 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
355 0, 118, 1, output_stage_tlv),
356 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
357 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
358 0, 118, 1, output_stage_tlv),
359 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
360 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
361 0, 118, 1, output_stage_tlv),
362
363 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
364 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
365 0, 118, 1, output_stage_tlv),
366 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
367 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
368 0, 118, 1, output_stage_tlv),
369 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
370 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
371 0, 118, 1, output_stage_tlv),
372
373 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
374 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
375 0, 118, 1, output_stage_tlv),
376 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
377 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
378 0, 118, 1, output_stage_tlv),
379 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
380 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
381 0, 118, 1, output_stage_tlv),
382
383 /* Output pin mute controls */
384 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
385 0x01, 0),
386 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
387 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
388 0x01, 0),
389 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
390 0x01, 0),
391
392 /*
393 * Note: enable Automatic input Gain Controller with care. It can
394 * adjust PGA to max value when ADC is on and will never go back.
395 */
396 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
397
398 /* Input */
399 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
400 0, 119, 0, adc_tlv),
401 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
402
403 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
404 };
405
406 /*
407 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
408 */
409 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
410
411 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
412 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
413
414 /* Left DAC Mux */
415 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
416 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
417
418 /* Right DAC Mux */
419 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
420 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
421
422 /* Left HPCOM Mux */
423 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
424 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
425
426 /* Right HPCOM Mux */
427 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
428 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
429
430 /* Left Line Mixer */
431 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
432 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
438 };
439
440 /* Right Line Mixer */
441 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
442 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
448 };
449
450 /* Mono Mixer */
451 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
452 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
458 };
459
460 /* Left HP Mixer */
461 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
462 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
468 };
469
470 /* Right HP Mixer */
471 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
472 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
478 };
479
480 /* Left HPCOM Mixer */
481 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
482 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
483 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
484 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
488 };
489
490 /* Right HPCOM Mixer */
491 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
492 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
493 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
498 };
499
500 /* Left PGA Mixer */
501 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
502 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
503 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
504 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
505 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
506 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
507 };
508
509 /* Right PGA Mixer */
510 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
511 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
512 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
513 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
514 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
515 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
516 };
517
518 /* Left Line1 Mux */
519 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
520 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
521
522 /* Right Line1 Mux */
523 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
524 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
525
526 /* Left Line2 Mux */
527 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
528 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
529
530 /* Right Line2 Mux */
531 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
532 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
533
534 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
535 /* Left DAC to Left Outputs */
536 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
537 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_left_dac_mux_controls),
539 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_left_hpcom_mux_controls),
541 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
542 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
543 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
544
545 /* Right DAC to Right Outputs */
546 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
547 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
548 &aic3x_right_dac_mux_controls),
549 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_hpcom_mux_controls),
551 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
552 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
553 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
554
555 /* Mono Output */
556 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
557
558 /* Inputs to Left ADC */
559 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
560 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
561 &aic3x_left_pga_mixer_controls[0],
562 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
563 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
564 &aic3x_left_line1_mux_controls),
565 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_left_line1_mux_controls),
567 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
568 &aic3x_left_line2_mux_controls),
569
570 /* Inputs to Right ADC */
571 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
572 LINE1R_2_RADC_CTRL, 2, 0),
573 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
574 &aic3x_right_pga_mixer_controls[0],
575 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
576 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_right_line1_mux_controls),
578 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_right_line1_mux_controls),
580 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
581 &aic3x_right_line2_mux_controls),
582
583 /*
584 * Not a real mic bias widget but similar function. This is for dynamic
585 * control of GPIO1 digital mic modulator clock output function when
586 * using digital mic.
587 */
588 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
589 AIC3X_GPIO1_REG, 4, 0xf,
590 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
591 AIC3X_GPIO1_FUNC_DISABLED),
592
593 /*
594 * Also similar function like mic bias. Selects digital mic with
595 * configurable oversampling rate instead of ADC converter.
596 */
597 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
598 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
599 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
600 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
602 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
603
604 /* Mic Bias */
605 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
606 MICBIAS_CTRL, 6, 3, 1, 0),
607 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
608 MICBIAS_CTRL, 6, 3, 2, 0),
609 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
610 MICBIAS_CTRL, 6, 3, 3, 0),
611
612 /* Output mixers */
613 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_left_line_mixer_controls[0],
615 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
616 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
617 &aic3x_right_line_mixer_controls[0],
618 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
619 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
620 &aic3x_mono_mixer_controls[0],
621 ARRAY_SIZE(aic3x_mono_mixer_controls)),
622 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
623 &aic3x_left_hp_mixer_controls[0],
624 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
625 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
626 &aic3x_right_hp_mixer_controls[0],
627 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
628 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
629 &aic3x_left_hpcom_mixer_controls[0],
630 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
631 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
632 &aic3x_right_hpcom_mixer_controls[0],
633 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
634
635 SND_SOC_DAPM_OUTPUT("LLOUT"),
636 SND_SOC_DAPM_OUTPUT("RLOUT"),
637 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
638 SND_SOC_DAPM_OUTPUT("HPLOUT"),
639 SND_SOC_DAPM_OUTPUT("HPROUT"),
640 SND_SOC_DAPM_OUTPUT("HPLCOM"),
641 SND_SOC_DAPM_OUTPUT("HPRCOM"),
642
643 SND_SOC_DAPM_INPUT("MIC3L"),
644 SND_SOC_DAPM_INPUT("MIC3R"),
645 SND_SOC_DAPM_INPUT("LINE1L"),
646 SND_SOC_DAPM_INPUT("LINE1R"),
647 SND_SOC_DAPM_INPUT("LINE2L"),
648 SND_SOC_DAPM_INPUT("LINE2R"),
649 };
650
651 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
652 /* Class-D outputs */
653 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
654 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
655
656 SND_SOC_DAPM_OUTPUT("SPOP"),
657 SND_SOC_DAPM_OUTPUT("SPOM"),
658 };
659
660 static const struct snd_soc_dapm_route intercon[] = {
661 /* Left Input */
662 {"Left Line1L Mux", "single-ended", "LINE1L"},
663 {"Left Line1L Mux", "differential", "LINE1L"},
664
665 {"Left Line2L Mux", "single-ended", "LINE2L"},
666 {"Left Line2L Mux", "differential", "LINE2L"},
667
668 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
669 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
670 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
671 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
672 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
673
674 {"Left ADC", NULL, "Left PGA Mixer"},
675 {"Left ADC", NULL, "GPIO1 dmic modclk"},
676
677 /* Right Input */
678 {"Right Line1R Mux", "single-ended", "LINE1R"},
679 {"Right Line1R Mux", "differential", "LINE1R"},
680
681 {"Right Line2R Mux", "single-ended", "LINE2R"},
682 {"Right Line2R Mux", "differential", "LINE2R"},
683
684 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
685 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
686 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
687 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
688 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
689
690 {"Right ADC", NULL, "Right PGA Mixer"},
691 {"Right ADC", NULL, "GPIO1 dmic modclk"},
692
693 /*
694 * Logical path between digital mic enable and GPIO1 modulator clock
695 * output function
696 */
697 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
698 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
699 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
700
701 /* Left DAC Output */
702 {"Left DAC Mux", "DAC_L1", "Left DAC"},
703 {"Left DAC Mux", "DAC_L2", "Left DAC"},
704 {"Left DAC Mux", "DAC_L3", "Left DAC"},
705
706 /* Right DAC Output */
707 {"Right DAC Mux", "DAC_R1", "Right DAC"},
708 {"Right DAC Mux", "DAC_R2", "Right DAC"},
709 {"Right DAC Mux", "DAC_R3", "Right DAC"},
710
711 /* Left Line Output */
712 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
713 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
714 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
715 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
716 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
717 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
718
719 {"Left Line Out", NULL, "Left Line Mixer"},
720 {"Left Line Out", NULL, "Left DAC Mux"},
721 {"LLOUT", NULL, "Left Line Out"},
722
723 /* Right Line Output */
724 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
725 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
726 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
727 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
728 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
729 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
730
731 {"Right Line Out", NULL, "Right Line Mixer"},
732 {"Right Line Out", NULL, "Right DAC Mux"},
733 {"RLOUT", NULL, "Right Line Out"},
734
735 /* Mono Output */
736 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
737 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
738 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
739 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
740 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
741 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
742
743 {"Mono Out", NULL, "Mono Mixer"},
744 {"MONO_LOUT", NULL, "Mono Out"},
745
746 /* Left HP Output */
747 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
748 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
749 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
750 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
751 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
752 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
753
754 {"Left HP Out", NULL, "Left HP Mixer"},
755 {"Left HP Out", NULL, "Left DAC Mux"},
756 {"HPLOUT", NULL, "Left HP Out"},
757
758 /* Right HP Output */
759 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
760 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
761 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
762 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
763 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
764 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
765
766 {"Right HP Out", NULL, "Right HP Mixer"},
767 {"Right HP Out", NULL, "Right DAC Mux"},
768 {"HPROUT", NULL, "Right HP Out"},
769
770 /* Left HPCOM Output */
771 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
772 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
773 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
774 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
775 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
776 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
777
778 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
779 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
780 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
781 {"Left HP Com", NULL, "Left HPCOM Mux"},
782 {"HPLCOM", NULL, "Left HP Com"},
783
784 /* Right HPCOM Output */
785 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
786 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
787 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
788 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
789 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
790 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
791
792 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
793 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
794 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
795 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
796 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
797 {"Right HP Com", NULL, "Right HPCOM Mux"},
798 {"HPRCOM", NULL, "Right HP Com"},
799 };
800
801 static const struct snd_soc_dapm_route intercon_3007[] = {
802 /* Class-D outputs */
803 {"Left Class-D Out", NULL, "Left Line Out"},
804 {"Right Class-D Out", NULL, "Left Line Out"},
805 {"SPOP", NULL, "Left Class-D Out"},
806 {"SPOM", NULL, "Right Class-D Out"},
807 };
808
809 static int aic3x_add_widgets(struct snd_soc_codec *codec)
810 {
811 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
812
813 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
814 ARRAY_SIZE(aic3x_dapm_widgets));
815
816 /* set up audio path interconnects */
817 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
818
819 if (aic3x->model == AIC3X_MODEL_3007) {
820 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
821 ARRAY_SIZE(aic3007_dapm_widgets));
822 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
823 }
824
825 return 0;
826 }
827
828 static int aic3x_hw_params(struct snd_pcm_substream *substream,
829 struct snd_pcm_hw_params *params,
830 struct snd_soc_dai *dai)
831 {
832 struct snd_soc_pcm_runtime *rtd = substream->private_data;
833 struct snd_soc_codec *codec =rtd->codec;
834 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
835 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
836 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
837 u16 d, pll_d = 1;
838 u8 reg;
839 int clk;
840
841 /* select data word length */
842 data =
843 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
844 switch (params_format(params)) {
845 case SNDRV_PCM_FORMAT_S16_LE:
846 break;
847 case SNDRV_PCM_FORMAT_S20_3LE:
848 data |= (0x01 << 4);
849 break;
850 case SNDRV_PCM_FORMAT_S24_LE:
851 data |= (0x02 << 4);
852 break;
853 case SNDRV_PCM_FORMAT_S32_LE:
854 data |= (0x03 << 4);
855 break;
856 }
857 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
858
859 /* Fsref can be 44100 or 48000 */
860 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
861
862 /* Try to find a value for Q which allows us to bypass the PLL and
863 * generate CODEC_CLK directly. */
864 for (pll_q = 2; pll_q < 18; pll_q++)
865 if (aic3x->sysclk / (128 * pll_q) == fsref) {
866 bypass_pll = 1;
867 break;
868 }
869
870 if (bypass_pll) {
871 pll_q &= 0xf;
872 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
873 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
874 /* disable PLL if it is bypassed */
875 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
876 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
877
878 } else {
879 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
880 /* enable PLL when it is used */
881 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
882 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
883 }
884
885 /* Route Left DAC to left channel input and
886 * right DAC to right channel input */
887 data = (LDAC2LCH | RDAC2RCH);
888 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
889 if (params_rate(params) >= 64000)
890 data |= DUAL_RATE_MODE;
891 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
892
893 /* codec sample rate select */
894 data = (fsref * 20) / params_rate(params);
895 if (params_rate(params) < 64000)
896 data /= 2;
897 data /= 5;
898 data -= 2;
899 data |= (data << 4);
900 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
901
902 if (bypass_pll)
903 return 0;
904
905 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
906 * one wins the game. Try with d==0 first, next with d!=0.
907 * Constraints for j are according to the datasheet.
908 * The sysclk is divided by 1000 to prevent integer overflows.
909 */
910
911 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
912
913 for (r = 1; r <= 16; r++)
914 for (p = 1; p <= 8; p++) {
915 for (j = 4; j <= 55; j++) {
916 /* This is actually 1000*((j+(d/10000))*r)/p
917 * The term had to be converted to get
918 * rid of the division by 10000; d = 0 here
919 */
920 int tmp_clk = (1000 * j * r) / p;
921
922 /* Check whether this values get closer than
923 * the best ones we had before
924 */
925 if (abs(codec_clk - tmp_clk) <
926 abs(codec_clk - last_clk)) {
927 pll_j = j; pll_d = 0;
928 pll_r = r; pll_p = p;
929 last_clk = tmp_clk;
930 }
931
932 /* Early exit for exact matches */
933 if (tmp_clk == codec_clk)
934 goto found;
935 }
936 }
937
938 /* try with d != 0 */
939 for (p = 1; p <= 8; p++) {
940 j = codec_clk * p / 1000;
941
942 if (j < 4 || j > 11)
943 continue;
944
945 /* do not use codec_clk here since we'd loose precision */
946 d = ((2048 * p * fsref) - j * aic3x->sysclk)
947 * 100 / (aic3x->sysclk/100);
948
949 clk = (10000 * j + d) / (10 * p);
950
951 /* check whether this values get closer than the best
952 * ones we had before */
953 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
954 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
955 last_clk = clk;
956 }
957
958 /* Early exit for exact matches */
959 if (clk == codec_clk)
960 goto found;
961 }
962
963 if (last_clk == 0) {
964 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
965 return -EINVAL;
966 }
967
968 found:
969 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
970 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
971 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
972 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
973 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
974 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
975 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
976
977 return 0;
978 }
979
980 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
981 {
982 struct snd_soc_codec *codec = dai->codec;
983 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
984 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
985
986 if (mute) {
987 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
988 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
989 } else {
990 aic3x_write(codec, LDAC_VOL, ldac_reg);
991 aic3x_write(codec, RDAC_VOL, rdac_reg);
992 }
993
994 return 0;
995 }
996
997 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
998 int clk_id, unsigned int freq, int dir)
999 {
1000 struct snd_soc_codec *codec = codec_dai->codec;
1001 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1002
1003 aic3x->sysclk = freq;
1004 return 0;
1005 }
1006
1007 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1008 unsigned int fmt)
1009 {
1010 struct snd_soc_codec *codec = codec_dai->codec;
1011 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1012 u8 iface_areg, iface_breg;
1013 int delay = 0;
1014
1015 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1016 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1017
1018 /* set master/slave audio interface */
1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1020 case SND_SOC_DAIFMT_CBM_CFM:
1021 aic3x->master = 1;
1022 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1023 break;
1024 case SND_SOC_DAIFMT_CBS_CFS:
1025 aic3x->master = 0;
1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
1031 /*
1032 * match both interface format and signal polarities since they
1033 * are fixed
1034 */
1035 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1036 SND_SOC_DAIFMT_INV_MASK)) {
1037 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1038 break;
1039 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1040 delay = 1;
1041 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1042 iface_breg |= (0x01 << 6);
1043 break;
1044 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1045 iface_breg |= (0x02 << 6);
1046 break;
1047 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1048 iface_breg |= (0x03 << 6);
1049 break;
1050 default:
1051 return -EINVAL;
1052 }
1053
1054 /* set iface */
1055 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1056 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1057 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1058
1059 return 0;
1060 }
1061
1062 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1063 enum snd_soc_bias_level level)
1064 {
1065 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1066 u8 reg;
1067
1068 switch (level) {
1069 case SND_SOC_BIAS_ON:
1070 break;
1071 case SND_SOC_BIAS_PREPARE:
1072 if (aic3x->master) {
1073 /* enable pll */
1074 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1075 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1076 reg | PLL_ENABLE);
1077 }
1078 break;
1079 case SND_SOC_BIAS_STANDBY:
1080 /* fall through and disable pll */
1081 case SND_SOC_BIAS_OFF:
1082 if (aic3x->master) {
1083 /* disable pll */
1084 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1085 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1086 reg & ~PLL_ENABLE);
1087 }
1088 break;
1089 }
1090 codec->bias_level = level;
1091
1092 return 0;
1093 }
1094
1095 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1096 {
1097 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1098 u8 bit = gpio ? 3: 0;
1099 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1100 aic3x_write(codec, reg, val | (!!state << bit));
1101 }
1102 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1103
1104 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1105 {
1106 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1107 u8 val, bit = gpio ? 2: 1;
1108
1109 aic3x_read(codec, reg, &val);
1110 return (val >> bit) & 1;
1111 }
1112 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1113
1114 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1115 int headset_debounce, int button_debounce)
1116 {
1117 u8 val;
1118
1119 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1120 << AIC3X_HEADSET_DETECT_SHIFT) |
1121 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1122 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1123 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1124 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1125
1126 if (detect & AIC3X_HEADSET_DETECT_MASK)
1127 val |= AIC3X_HEADSET_DETECT_ENABLED;
1128
1129 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1130 }
1131 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1132
1133 int aic3x_headset_detected(struct snd_soc_codec *codec)
1134 {
1135 u8 val;
1136 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1137 return (val >> 4) & 1;
1138 }
1139 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1140
1141 int aic3x_button_pressed(struct snd_soc_codec *codec)
1142 {
1143 u8 val;
1144 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1145 return (val >> 5) & 1;
1146 }
1147 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1148
1149 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1150 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1151 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1152
1153 static struct snd_soc_dai_ops aic3x_dai_ops = {
1154 .hw_params = aic3x_hw_params,
1155 .digital_mute = aic3x_mute,
1156 .set_sysclk = aic3x_set_dai_sysclk,
1157 .set_fmt = aic3x_set_dai_fmt,
1158 };
1159
1160 static struct snd_soc_dai_driver aic3x_dai = {
1161 .name = "tlv320aic3x-hifi",
1162 .playback = {
1163 .stream_name = "Playback",
1164 .channels_min = 1,
1165 .channels_max = 2,
1166 .rates = AIC3X_RATES,
1167 .formats = AIC3X_FORMATS,},
1168 .capture = {
1169 .stream_name = "Capture",
1170 .channels_min = 1,
1171 .channels_max = 2,
1172 .rates = AIC3X_RATES,
1173 .formats = AIC3X_FORMATS,},
1174 .ops = &aic3x_dai_ops,
1175 .symmetric_rates = 1,
1176 };
1177
1178 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1179 {
1180 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1181
1182 return 0;
1183 }
1184
1185 static int aic3x_resume(struct snd_soc_codec *codec)
1186 {
1187 int i;
1188 u8 data[2];
1189 u8 *cache = codec->reg_cache;
1190
1191 /* Sync reg_cache with the hardware */
1192 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1193 data[0] = i;
1194 data[1] = cache[i];
1195 codec->hw_write(codec->control_data, data, 2);
1196 }
1197
1198 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1199
1200 return 0;
1201 }
1202
1203 /*
1204 * initialise the AIC3X driver
1205 * register the mixer and dsp interfaces with the kernel
1206 */
1207 static int aic3x_init(struct snd_soc_codec *codec)
1208 {
1209 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1210 int reg;
1211
1212 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1213 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1214
1215 /* DAC default volume and mute */
1216 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1217 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1218
1219 /* DAC to HP default volume and route to Output mixer */
1220 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1221 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1222 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1223 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1224 /* DAC to Line Out default volume and route to Output mixer */
1225 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1226 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1227 /* DAC to Mono Line Out default volume and route to Output mixer */
1228 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1229 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1230
1231 /* unmute all outputs */
1232 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1233 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1234 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1235 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1236 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1237 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1238 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1239 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1240 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1241 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1242 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1243 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1244 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1245 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1246
1247 /* ADC default volume and unmute */
1248 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1249 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1250 /* By default route Line1 to ADC PGA mixer */
1251 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1252 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1253
1254 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1255 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1256 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1257 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1258 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1259 /* PGA to Line Out default volume, disconnect from Output Mixer */
1260 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1261 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1262 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1263 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1264 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1265
1266 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1267 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1268 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1269 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1270 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1271 /* Line2 Line Out default volume, disconnect from Output Mixer */
1272 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1273 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1274 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1275 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1276 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1277
1278 if (aic3x->model == AIC3X_MODEL_3007) {
1279 /* Class-D speaker driver init; datasheet p. 46 */
1280 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1281 aic3x_write(codec, 0xD, 0x0D);
1282 aic3x_write(codec, 0x8, 0x5C);
1283 aic3x_write(codec, 0x8, 0x5D);
1284 aic3x_write(codec, 0x8, 0x5C);
1285 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x00);
1286 aic3x_write(codec, CLASSD_CTRL, 0);
1287 }
1288
1289 /* off, with power on */
1290 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1291
1292 return 0;
1293 }
1294
1295 static int aic3x_probe(struct snd_soc_codec *codec)
1296 {
1297 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1298
1299 codec->hw_write = (hw_write_t) i2c_master_send;
1300 codec->control_data = aic3x->control_data;
1301
1302 aic3x_init(codec);
1303
1304 if (aic3x->setup) {
1305 /* setup GPIO functions */
1306 aic3x_write(codec, AIC3X_GPIO1_REG,
1307 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1308 aic3x_write(codec, AIC3X_GPIO2_REG,
1309 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1310 }
1311
1312 snd_soc_add_controls(codec, aic3x_snd_controls,
1313 ARRAY_SIZE(aic3x_snd_controls));
1314 if (aic3x->model == AIC3X_MODEL_3007)
1315 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1316
1317 aic3x_add_widgets(codec);
1318
1319 return 0;
1320 }
1321
1322 static int aic3x_remove(struct snd_soc_codec *codec)
1323 {
1324 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1325 return 0;
1326 }
1327
1328 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1329 .read = aic3x_read_reg_cache,
1330 .write = aic3x_write,
1331 .set_bias_level = aic3x_set_bias_level,
1332 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1333 .reg_word_size = sizeof(u8),
1334 .reg_cache_default = aic3x_reg,
1335 .probe = aic3x_probe,
1336 .remove = aic3x_remove,
1337 .suspend = aic3x_suspend,
1338 .resume = aic3x_resume,
1339 };
1340
1341 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1342 /*
1343 * AIC3X 2 wire address can be up to 4 devices with device addresses
1344 * 0x18, 0x19, 0x1A, 0x1B
1345 */
1346
1347 static const struct i2c_device_id aic3x_i2c_id[] = {
1348 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1349 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1350 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1351 { }
1352 };
1353 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1354
1355 /*
1356 * If the i2c layer weren't so broken, we could pass this kind of data
1357 * around
1358 */
1359 static int aic3x_i2c_probe(struct i2c_client *i2c,
1360 const struct i2c_device_id *id)
1361 {
1362 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1363 struct aic3x_setup_data *setup = pdata->setup;
1364 struct aic3x_priv *aic3x;
1365 int ret, i;
1366 const struct i2c_device_id *tbl;
1367
1368 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1369 if (aic3x == NULL) {
1370 dev_err(&i2c->dev, "failed to create private data\n");
1371 return -ENOMEM;
1372 }
1373
1374 aic3x->control_data = i2c;
1375 aic3x->setup = setup;
1376 i2c_set_clientdata(i2c, aic3x);
1377
1378 aic3x->gpio_reset = -1;
1379 if (pdata && pdata->gpio_reset >= 0) {
1380 ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
1381 if (ret != 0)
1382 goto err_gpio;
1383 aic3x->gpio_reset = pdata->gpio_reset;
1384 gpio_direction_output(aic3x->gpio_reset, 0);
1385 }
1386
1387 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1388 if (!strcmp(tbl->name, id->name))
1389 break;
1390 }
1391 aic3x->model = tbl - aic3x_i2c_id;
1392
1393 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1394 aic3x->supplies[i].supply = aic3x_supply_names[i];
1395
1396 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1397 aic3x->supplies);
1398 if (ret != 0) {
1399 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1400 goto err_get;
1401 }
1402
1403 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1404 aic3x->supplies);
1405 if (ret != 0) {
1406 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1407 goto err_enable;
1408 }
1409
1410 if (aic3x->gpio_reset >= 0) {
1411 udelay(1);
1412 gpio_set_value(aic3x->gpio_reset, 1);
1413 }
1414
1415 ret = snd_soc_register_codec(&i2c->dev,
1416 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1417 if (ret < 0)
1418 goto err_enable;
1419 return ret;
1420
1421 err_enable:
1422 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1423 err_get:
1424 if (aic3x->gpio_reset >= 0)
1425 gpio_free(aic3x->gpio_reset);
1426 err_gpio:
1427 kfree(aic3x);
1428 return ret;
1429 }
1430
1431 static int aic3x_i2c_remove(struct i2c_client *client)
1432 {
1433 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1434
1435 if (aic3x->gpio_reset >= 0) {
1436 gpio_set_value(aic3x->gpio_reset, 0);
1437 gpio_free(aic3x->gpio_reset);
1438 }
1439 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1440 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1441
1442 snd_soc_unregister_codec(&client->dev);
1443 kfree(i2c_get_clientdata(client));
1444 return 0;
1445 }
1446
1447 /* machine i2c codec control layer */
1448 static struct i2c_driver aic3x_i2c_driver = {
1449 .driver = {
1450 .name = "tlv320aic3x-codec",
1451 .owner = THIS_MODULE,
1452 },
1453 .probe = aic3x_i2c_probe,
1454 .remove = aic3x_i2c_remove,
1455 .id_table = aic3x_i2c_id,
1456 };
1457
1458 static inline void aic3x_i2c_init(void)
1459 {
1460 int ret;
1461
1462 ret = i2c_add_driver(&aic3x_i2c_driver);
1463 if (ret)
1464 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1465 __func__, ret);
1466 }
1467
1468 static inline void aic3x_i2c_exit(void)
1469 {
1470 i2c_del_driver(&aic3x_i2c_driver);
1471 }
1472 #endif
1473
1474 static int __init aic3x_modinit(void)
1475 {
1476 int ret = 0;
1477 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1478 ret = i2c_add_driver(&aic3x_i2c_driver);
1479 if (ret != 0) {
1480 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1481 ret);
1482 }
1483 #endif
1484 return ret;
1485 }
1486 module_init(aic3x_modinit);
1487
1488 static void __exit aic3x_exit(void)
1489 {
1490 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1491 i2c_del_driver(&aic3x_i2c_driver);
1492 #endif
1493 }
1494 module_exit(aic3x_exit);
1495
1496 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1497 MODULE_AUTHOR("Vladimir Barinov");
1498 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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