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Merge branch 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48
49 #include "tlv320aic3x.h"
50
51 #define AIC3X_VERSION "0.2"
52
53 /* codec private data */
54 struct aic3x_priv {
55 unsigned int sysclk;
56 int master;
57 };
58
59 /*
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
64 */
65 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
92 };
93
94 /*
95 * read aic3x register cache
96 */
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
98 unsigned int reg)
99 {
100 u8 *cache = codec->reg_cache;
101 if (reg >= AIC3X_CACHEREGNUM)
102 return -1;
103 return cache[reg];
104 }
105
106 /*
107 * write aic3x register cache
108 */
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
110 u8 reg, u8 value)
111 {
112 u8 *cache = codec->reg_cache;
113 if (reg >= AIC3X_CACHEREGNUM)
114 return;
115 cache[reg] = value;
116 }
117
118 /*
119 * write to the aic3x register space
120 */
121 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
122 unsigned int value)
123 {
124 u8 data[2];
125
126 /* data is
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
129 */
130 data[0] = reg & 0xff;
131 data[1] = value & 0xff;
132
133 aic3x_write_reg_cache(codec, data[0], data[1]);
134 if (codec->hw_write(codec->control_data, data, 2) == 2)
135 return 0;
136 else
137 return -EIO;
138 }
139
140 /*
141 * read from the aic3x register space
142 */
143 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
144 u8 *value)
145 {
146 *value = reg & 0xff;
147 if (codec->hw_read(codec->control_data, value, 1) != 1)
148 return -EIO;
149
150 aic3x_write_reg_cache(codec, reg, *value);
151 return 0;
152 }
153
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
159
160 /*
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
163 */
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166 {
167 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
168 int reg = kcontrol->private_value & 0xff;
169 int shift = (kcontrol->private_value >> 8) & 0x0f;
170 int mask = (kcontrol->private_value >> 16) & 0xff;
171 int invert = (kcontrol->private_value >> 24) & 0x01;
172 unsigned short val, val_mask;
173 int ret;
174 struct snd_soc_dapm_path *path;
175 int found = 0;
176
177 val = (ucontrol->value.integer.value[0] & mask);
178
179 mask = 0xf;
180 if (val)
181 val = mask;
182
183 if (invert)
184 val = mask - val;
185 val_mask = mask << shift;
186 val = val << shift;
187
188 mutex_lock(&widget->codec->mutex);
189
190 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
193 if (path->kcontrol != kcontrol)
194 continue;
195
196 /* found, now check type */
197 found = 1;
198 if (val)
199 /* new connection */
200 path->connect = invert ? 0 : 1;
201 else
202 /* old connection must be powered down */
203 path->connect = invert ? 1 : 0;
204 break;
205 }
206
207 if (found)
208 snd_soc_dapm_sync(widget->codec);
209 }
210
211 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
212
213 mutex_unlock(&widget->codec->mutex);
214 return ret;
215 }
216
217 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
227
228 #define LDAC_ENUM 0
229 #define RDAC_ENUM 1
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_ENUM 4
233 #define LINE1R_ENUM 5
234 #define LINE2L_ENUM 6
235 #define LINE2R_ENUM 7
236 #define ADC_HPF_ENUM 8
237
238 static const struct soc_enum aic3x_enum[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
241 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
242 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
248 };
249
250 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
251 /* Output */
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
253
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
255 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
256 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
257 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
258 SOC_DOUBLE_R("LineL DAC Playback Volume", DACL1_2_LLOPM_VOL,
259 DACR1_2_LLOPM_VOL, 0, 0x7f, 1),
260 SOC_SINGLE("LineL Left PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
261 0, 0x7f, 1),
262 SOC_SINGLE("LineR Right PGA Bypass Playback Volume", PGAR_2_RLOPM_VOL,
263 0, 0x7f, 1),
264 SOC_DOUBLE_R("LineL Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
265 LINE2R_2_LLOPM_VOL, 0, 0x7f, 1),
266 SOC_DOUBLE_R("LineR Line2 Bypass Playback Volume", LINE2L_2_RLOPM_VOL,
267 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
268
269 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
270 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
271 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
272 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
273 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
274 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
275 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
276
277 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
278 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
279 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
280 0x01, 0),
281 SOC_DOUBLE_R("HP Right PGA Bypass Playback Volume", PGAR_2_HPLOUT_VOL,
282 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
283 SOC_SINGLE("HPL PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
284 0, 0x7f, 1),
285 SOC_SINGLE("HPR PGA Bypass Playback Volume", PGAL_2_HPROUT_VOL,
286 0, 0x7f, 1),
287 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
288 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
289
290 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
291 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
292 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
293 0x01, 0),
294 SOC_SINGLE("HPLCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
295 0, 0x7f, 1),
296 SOC_SINGLE("HPRCOM PGA Bypass Playback Volume", PGAL_2_HPRCOM_VOL,
297 0, 0x7f, 1),
298 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
299 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
300
301 /*
302 * Note: enable Automatic input Gain Controller with care. It can
303 * adjust PGA to max value when ADC is on and will never go back.
304 */
305 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
306
307 /* Input */
308 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
309 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
310
311 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
312 };
313
314 /* add non dapm controls */
315 static int aic3x_add_controls(struct snd_soc_codec *codec)
316 {
317 int err, i;
318
319 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
320 err = snd_ctl_add(codec->card,
321 snd_soc_cnew(&aic3x_snd_controls[i],
322 codec, NULL));
323 if (err < 0)
324 return err;
325 }
326
327 return 0;
328 }
329
330 /* Left DAC Mux */
331 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
332 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
333
334 /* Right DAC Mux */
335 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
336 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
337
338 /* Left HPCOM Mux */
339 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
340 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
341
342 /* Right HPCOM Mux */
343 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
344 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
345
346 /* Left DAC_L1 Mixer */
347 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
348 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
349 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
350 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
351 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
352 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
353 };
354
355 /* Right DAC_R1 Mixer */
356 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
357 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
358 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
359 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
360 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
361 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
362 };
363
364 /* Left PGA Mixer */
365 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
366 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
367 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
368 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
369 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
370 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
371 };
372
373 /* Right PGA Mixer */
374 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
375 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
376 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
377 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
378 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
379 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
380 };
381
382 /* Left Line1 Mux */
383 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
384 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
385
386 /* Right Line1 Mux */
387 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
388 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
389
390 /* Left Line2 Mux */
391 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
392 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
393
394 /* Right Line2 Mux */
395 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
396 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
397
398 /* Left PGA Bypass Mixer */
399 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
400 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
401 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
407 };
408
409 /* Right PGA Bypass Mixer */
410 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
411 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
418 };
419
420 /* Left Line2 Bypass Mixer */
421 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
422 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
427 };
428
429 /* Right Line2 Bypass Mixer */
430 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
431 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
436 };
437
438 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
439 /* Left DAC to Left Outputs */
440 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
441 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
442 &aic3x_left_dac_mux_controls),
443 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
444 &aic3x_left_dac_mixer_controls[0],
445 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
446 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
447 &aic3x_left_hpcom_mux_controls),
448 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
449 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
450 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
451
452 /* Right DAC to Right Outputs */
453 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
454 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
455 &aic3x_right_dac_mux_controls),
456 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
457 &aic3x_right_dac_mixer_controls[0],
458 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
459 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
460 &aic3x_right_hpcom_mux_controls),
461 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
462 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
463 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
464
465 /* Mono Output */
466 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
467
468 /* Inputs to Left ADC */
469 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
470 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
471 &aic3x_left_pga_mixer_controls[0],
472 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
473 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
474 &aic3x_left_line1_mux_controls),
475 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
476 &aic3x_left_line1_mux_controls),
477 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
478 &aic3x_left_line2_mux_controls),
479
480 /* Inputs to Right ADC */
481 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
482 LINE1R_2_RADC_CTRL, 2, 0),
483 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
484 &aic3x_right_pga_mixer_controls[0],
485 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
486 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
487 &aic3x_right_line1_mux_controls),
488 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
489 &aic3x_right_line1_mux_controls),
490 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
491 &aic3x_right_line2_mux_controls),
492
493 /*
494 * Not a real mic bias widget but similar function. This is for dynamic
495 * control of GPIO1 digital mic modulator clock output function when
496 * using digital mic.
497 */
498 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
499 AIC3X_GPIO1_REG, 4, 0xf,
500 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
501 AIC3X_GPIO1_FUNC_DISABLED),
502
503 /*
504 * Also similar function like mic bias. Selects digital mic with
505 * configurable oversampling rate instead of ADC converter.
506 */
507 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
508 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
509 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
510 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
511 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
512 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
513
514 /* Mic Bias */
515 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
516 MICBIAS_CTRL, 6, 3, 1, 0),
517 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
518 MICBIAS_CTRL, 6, 3, 2, 0),
519 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
520 MICBIAS_CTRL, 6, 3, 3, 0),
521
522 /* Left PGA to Left Output bypass */
523 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
524 &aic3x_left_pga_bp_mixer_controls[0],
525 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
526
527 /* Right PGA to Right Output bypass */
528 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
529 &aic3x_right_pga_bp_mixer_controls[0],
530 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
531
532 /* Left Line2 to Left Output bypass */
533 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
534 &aic3x_left_line2_bp_mixer_controls[0],
535 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
536
537 /* Right Line2 to Right Output bypass */
538 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
539 &aic3x_right_line2_bp_mixer_controls[0],
540 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
541
542 SND_SOC_DAPM_OUTPUT("LLOUT"),
543 SND_SOC_DAPM_OUTPUT("RLOUT"),
544 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
545 SND_SOC_DAPM_OUTPUT("HPLOUT"),
546 SND_SOC_DAPM_OUTPUT("HPROUT"),
547 SND_SOC_DAPM_OUTPUT("HPLCOM"),
548 SND_SOC_DAPM_OUTPUT("HPRCOM"),
549
550 SND_SOC_DAPM_INPUT("MIC3L"),
551 SND_SOC_DAPM_INPUT("MIC3R"),
552 SND_SOC_DAPM_INPUT("LINE1L"),
553 SND_SOC_DAPM_INPUT("LINE1R"),
554 SND_SOC_DAPM_INPUT("LINE2L"),
555 SND_SOC_DAPM_INPUT("LINE2R"),
556 };
557
558 static const struct snd_soc_dapm_route intercon[] = {
559 /* Left Output */
560 {"Left DAC Mux", "DAC_L1", "Left DAC"},
561 {"Left DAC Mux", "DAC_L2", "Left DAC"},
562 {"Left DAC Mux", "DAC_L3", "Left DAC"},
563
564 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
565 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
566 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
567 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
568 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
569 {"Left Line Out", NULL, "Left DAC Mux"},
570 {"Left HP Out", NULL, "Left DAC Mux"},
571
572 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
573 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
574 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
575
576 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
577 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
578 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
579 {"Left HP Com", NULL, "Left HPCOM Mux"},
580
581 {"LLOUT", NULL, "Left Line Out"},
582 {"LLOUT", NULL, "Left Line Out"},
583 {"HPLOUT", NULL, "Left HP Out"},
584 {"HPLCOM", NULL, "Left HP Com"},
585
586 /* Right Output */
587 {"Right DAC Mux", "DAC_R1", "Right DAC"},
588 {"Right DAC Mux", "DAC_R2", "Right DAC"},
589 {"Right DAC Mux", "DAC_R3", "Right DAC"},
590
591 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
592 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
593 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
594 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
595 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
596 {"Right Line Out", NULL, "Right DAC Mux"},
597 {"Right HP Out", NULL, "Right DAC Mux"},
598
599 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
600 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
601 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
602 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
603 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
604
605 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
606 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
607 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
608 {"Right HP Com", NULL, "Right HPCOM Mux"},
609
610 {"RLOUT", NULL, "Right Line Out"},
611 {"RLOUT", NULL, "Right Line Out"},
612 {"HPROUT", NULL, "Right HP Out"},
613 {"HPRCOM", NULL, "Right HP Com"},
614
615 /* Mono Output */
616 {"MONO_LOUT", NULL, "Mono Out"},
617 {"MONO_LOUT", NULL, "Mono Out"},
618
619 /* Left Input */
620 {"Left Line1L Mux", "single-ended", "LINE1L"},
621 {"Left Line1L Mux", "differential", "LINE1L"},
622
623 {"Left Line2L Mux", "single-ended", "LINE2L"},
624 {"Left Line2L Mux", "differential", "LINE2L"},
625
626 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
627 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
628 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
629 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
630 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
631
632 {"Left ADC", NULL, "Left PGA Mixer"},
633 {"Left ADC", NULL, "GPIO1 dmic modclk"},
634
635 /* Right Input */
636 {"Right Line1R Mux", "single-ended", "LINE1R"},
637 {"Right Line1R Mux", "differential", "LINE1R"},
638
639 {"Right Line2R Mux", "single-ended", "LINE2R"},
640 {"Right Line2R Mux", "differential", "LINE2R"},
641
642 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
643 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
644 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
645 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
646 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
647
648 {"Right ADC", NULL, "Right PGA Mixer"},
649 {"Right ADC", NULL, "GPIO1 dmic modclk"},
650
651 /* Left PGA Bypass */
652 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
653 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
654 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
655 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
656 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
657 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
658 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
659
660 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
661 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
662 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
663
664 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
665 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
666 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
667
668 /* Right PGA Bypass */
669 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
670 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
671 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
672 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
673 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
674 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
675 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
676
677 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
678 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
679 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
680 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
681 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
682
683 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
684 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
685 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
686
687 /* Left Line2 Bypass */
688 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
689 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
690 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
691 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
692 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
693
694 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
695 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
696 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
697
698 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
699 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
700 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
701
702 /* Right Line2 Bypass */
703 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
704 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
705 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
706 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
707 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
708
709 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
710 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
711 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
712 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
713 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
714
715 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
716 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
717 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
718
719 /*
720 * Logical path between digital mic enable and GPIO1 modulator clock
721 * output function
722 */
723 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
724 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
725 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
726 };
727
728 static int aic3x_add_widgets(struct snd_soc_codec *codec)
729 {
730 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
731 ARRAY_SIZE(aic3x_dapm_widgets));
732
733 /* set up audio path interconnects */
734 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
735
736 snd_soc_dapm_new_widgets(codec);
737 return 0;
738 }
739
740 static int aic3x_hw_params(struct snd_pcm_substream *substream,
741 struct snd_pcm_hw_params *params,
742 struct snd_soc_dai *dai)
743 {
744 struct snd_soc_pcm_runtime *rtd = substream->private_data;
745 struct snd_soc_device *socdev = rtd->socdev;
746 struct snd_soc_codec *codec = socdev->codec;
747 struct aic3x_priv *aic3x = codec->private_data;
748 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
749 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
750 u16 pll_d = 1;
751
752 /* select data word length */
753 data =
754 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
755 switch (params_format(params)) {
756 case SNDRV_PCM_FORMAT_S16_LE:
757 break;
758 case SNDRV_PCM_FORMAT_S20_3LE:
759 data |= (0x01 << 4);
760 break;
761 case SNDRV_PCM_FORMAT_S24_LE:
762 data |= (0x02 << 4);
763 break;
764 case SNDRV_PCM_FORMAT_S32_LE:
765 data |= (0x03 << 4);
766 break;
767 }
768 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
769
770 /* Fsref can be 44100 or 48000 */
771 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
772
773 /* Try to find a value for Q which allows us to bypass the PLL and
774 * generate CODEC_CLK directly. */
775 for (pll_q = 2; pll_q < 18; pll_q++)
776 if (aic3x->sysclk / (128 * pll_q) == fsref) {
777 bypass_pll = 1;
778 break;
779 }
780
781 if (bypass_pll) {
782 pll_q &= 0xf;
783 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
784 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
785 } else
786 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
787
788 /* Route Left DAC to left channel input and
789 * right DAC to right channel input */
790 data = (LDAC2LCH | RDAC2RCH);
791 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
792 if (params_rate(params) >= 64000)
793 data |= DUAL_RATE_MODE;
794 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
795
796 /* codec sample rate select */
797 data = (fsref * 20) / params_rate(params);
798 if (params_rate(params) < 64000)
799 data /= 2;
800 data /= 5;
801 data -= 2;
802 data |= (data << 4);
803 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
804
805 if (bypass_pll)
806 return 0;
807
808 /* Use PLL
809 * find an apropriate setup for j, d, r and p by iterating over
810 * p and r - j and d are calculated for each fraction.
811 * Up to 128 values are probed, the closest one wins the game.
812 * The sysclk is divided by 1000 to prevent integer overflows.
813 */
814 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
815
816 for (r = 1; r <= 16; r++)
817 for (p = 1; p <= 8; p++) {
818 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
819 u8 j = tmp / 10000;
820 u16 d = tmp % 10000;
821
822 if (j > 63)
823 continue;
824
825 if (d != 0 && aic3x->sysclk < 10000000)
826 continue;
827
828 /* This is actually 1000 * ((j + (d/10000)) * r) / p
829 * The term had to be converted to get rid of the
830 * division by 10000 */
831 clk = ((10000 * j * r) + (d * r)) / (10 * p);
832
833 /* check whether this values get closer than the best
834 * ones we had before */
835 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
836 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
837 last_clk = clk;
838 }
839
840 /* Early exit for exact matches */
841 if (clk == codec_clk)
842 break;
843 }
844
845 if (last_clk == 0) {
846 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
847 return -EINVAL;
848 }
849
850 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
851 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
852 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
853 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
854 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
855 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
856 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
857
858 return 0;
859 }
860
861 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
862 {
863 struct snd_soc_codec *codec = dai->codec;
864 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
865 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
866
867 if (mute) {
868 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
869 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
870 } else {
871 aic3x_write(codec, LDAC_VOL, ldac_reg);
872 aic3x_write(codec, RDAC_VOL, rdac_reg);
873 }
874
875 return 0;
876 }
877
878 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
879 int clk_id, unsigned int freq, int dir)
880 {
881 struct snd_soc_codec *codec = codec_dai->codec;
882 struct aic3x_priv *aic3x = codec->private_data;
883
884 aic3x->sysclk = freq;
885 return 0;
886 }
887
888 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
889 unsigned int fmt)
890 {
891 struct snd_soc_codec *codec = codec_dai->codec;
892 struct aic3x_priv *aic3x = codec->private_data;
893 u8 iface_areg, iface_breg;
894 int delay = 0;
895
896 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
897 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
898
899 /* set master/slave audio interface */
900 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
901 case SND_SOC_DAIFMT_CBM_CFM:
902 aic3x->master = 1;
903 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
904 break;
905 case SND_SOC_DAIFMT_CBS_CFS:
906 aic3x->master = 0;
907 break;
908 default:
909 return -EINVAL;
910 }
911
912 /*
913 * match both interface format and signal polarities since they
914 * are fixed
915 */
916 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
917 SND_SOC_DAIFMT_INV_MASK)) {
918 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
919 break;
920 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
921 delay = 1;
922 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
923 iface_breg |= (0x01 << 6);
924 break;
925 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
926 iface_breg |= (0x02 << 6);
927 break;
928 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
929 iface_breg |= (0x03 << 6);
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 /* set iface */
936 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
937 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
938 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
939
940 return 0;
941 }
942
943 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
944 enum snd_soc_bias_level level)
945 {
946 struct aic3x_priv *aic3x = codec->private_data;
947 u8 reg;
948
949 switch (level) {
950 case SND_SOC_BIAS_ON:
951 /* all power is driven by DAPM system */
952 if (aic3x->master) {
953 /* enable pll */
954 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
955 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
956 reg | PLL_ENABLE);
957 }
958 break;
959 case SND_SOC_BIAS_PREPARE:
960 break;
961 case SND_SOC_BIAS_STANDBY:
962 /*
963 * all power is driven by DAPM system,
964 * so output power is safe if bypass was set
965 */
966 if (aic3x->master) {
967 /* disable pll */
968 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
969 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
970 reg & ~PLL_ENABLE);
971 }
972 break;
973 case SND_SOC_BIAS_OFF:
974 /* force all power off */
975 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
976 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
977 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
978 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
979
980 reg = aic3x_read_reg_cache(codec, DAC_PWR);
981 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
982
983 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
984 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
985 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
986 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
987
988 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
989 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
990 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
991 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
992
993 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
994 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
995
996 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
997 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
998 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
999 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1000
1001 if (aic3x->master) {
1002 /* disable pll */
1003 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1004 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1005 reg & ~PLL_ENABLE);
1006 }
1007 break;
1008 }
1009 codec->bias_level = level;
1010
1011 return 0;
1012 }
1013
1014 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1015 {
1016 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1017 u8 bit = gpio ? 3: 0;
1018 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1019 aic3x_write(codec, reg, val | (!!state << bit));
1020 }
1021 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1022
1023 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1024 {
1025 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1026 u8 val, bit = gpio ? 2: 1;
1027
1028 aic3x_read(codec, reg, &val);
1029 return (val >> bit) & 1;
1030 }
1031 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1032
1033 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1034 int headset_debounce, int button_debounce)
1035 {
1036 u8 val;
1037
1038 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1039 << AIC3X_HEADSET_DETECT_SHIFT) |
1040 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1041 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1042 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1043 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1044
1045 if (detect & AIC3X_HEADSET_DETECT_MASK)
1046 val |= AIC3X_HEADSET_DETECT_ENABLED;
1047
1048 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1049 }
1050 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1051
1052 int aic3x_headset_detected(struct snd_soc_codec *codec)
1053 {
1054 u8 val;
1055 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1056 return (val >> 4) & 1;
1057 }
1058 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1059
1060 int aic3x_button_pressed(struct snd_soc_codec *codec)
1061 {
1062 u8 val;
1063 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1064 return (val >> 5) & 1;
1065 }
1066 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1067
1068 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1069 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1070 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1071
1072 struct snd_soc_dai aic3x_dai = {
1073 .name = "tlv320aic3x",
1074 .playback = {
1075 .stream_name = "Playback",
1076 .channels_min = 1,
1077 .channels_max = 2,
1078 .rates = AIC3X_RATES,
1079 .formats = AIC3X_FORMATS,},
1080 .capture = {
1081 .stream_name = "Capture",
1082 .channels_min = 1,
1083 .channels_max = 2,
1084 .rates = AIC3X_RATES,
1085 .formats = AIC3X_FORMATS,},
1086 .ops = {
1087 .hw_params = aic3x_hw_params,
1088 .digital_mute = aic3x_mute,
1089 .set_sysclk = aic3x_set_dai_sysclk,
1090 .set_fmt = aic3x_set_dai_fmt,
1091 }
1092 };
1093 EXPORT_SYMBOL_GPL(aic3x_dai);
1094
1095 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1096 {
1097 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1098 struct snd_soc_codec *codec = socdev->codec;
1099
1100 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1101
1102 return 0;
1103 }
1104
1105 static int aic3x_resume(struct platform_device *pdev)
1106 {
1107 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1108 struct snd_soc_codec *codec = socdev->codec;
1109 int i;
1110 u8 data[2];
1111 u8 *cache = codec->reg_cache;
1112
1113 /* Sync reg_cache with the hardware */
1114 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1115 data[0] = i;
1116 data[1] = cache[i];
1117 codec->hw_write(codec->control_data, data, 2);
1118 }
1119
1120 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1121
1122 return 0;
1123 }
1124
1125 /*
1126 * initialise the AIC3X driver
1127 * register the mixer and dsp interfaces with the kernel
1128 */
1129 static int aic3x_init(struct snd_soc_device *socdev)
1130 {
1131 struct snd_soc_codec *codec = socdev->codec;
1132 struct aic3x_setup_data *setup = socdev->codec_data;
1133 int reg, ret = 0;
1134
1135 codec->name = "tlv320aic3x";
1136 codec->owner = THIS_MODULE;
1137 codec->read = aic3x_read_reg_cache;
1138 codec->write = aic3x_write;
1139 codec->set_bias_level = aic3x_set_bias_level;
1140 codec->dai = &aic3x_dai;
1141 codec->num_dai = 1;
1142 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1143 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1144 if (codec->reg_cache == NULL)
1145 return -ENOMEM;
1146
1147 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1148 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1149
1150 /* register pcms */
1151 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1152 if (ret < 0) {
1153 printk(KERN_ERR "aic3x: failed to create pcms\n");
1154 goto pcm_err;
1155 }
1156
1157 /* DAC default volume and mute */
1158 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1159 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1160
1161 /* DAC to HP default volume and route to Output mixer */
1162 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1163 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1164 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1165 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1166 /* DAC to Line Out default volume and route to Output mixer */
1167 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1168 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1169 /* DAC to Mono Line Out default volume and route to Output mixer */
1170 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1171 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1172
1173 /* unmute all outputs */
1174 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1175 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1176 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1177 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1178 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1179 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1180 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1181 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1182 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1183 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1184 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1185 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1186 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1187 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1188
1189 /* ADC default volume and unmute */
1190 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1191 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1192 /* By default route Line1 to ADC PGA mixer */
1193 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1194 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1195
1196 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1197 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1198 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1199 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1200 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1201 /* PGA to Line Out default volume, disconnect from Output Mixer */
1202 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1203 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1204 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1205 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1206 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1207
1208 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1209 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1210 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1211 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1212 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1213 /* Line2 Line Out default volume, disconnect from Output Mixer */
1214 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1215 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1216 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1217 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1218 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1219
1220 /* off, with power on */
1221 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1222
1223 /* setup GPIO functions */
1224 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1225 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1226
1227 aic3x_add_controls(codec);
1228 aic3x_add_widgets(codec);
1229 ret = snd_soc_init_card(socdev);
1230 if (ret < 0) {
1231 printk(KERN_ERR "aic3x: failed to register card\n");
1232 goto card_err;
1233 }
1234
1235 return ret;
1236
1237 card_err:
1238 snd_soc_free_pcms(socdev);
1239 snd_soc_dapm_free(socdev);
1240 pcm_err:
1241 kfree(codec->reg_cache);
1242 return ret;
1243 }
1244
1245 static struct snd_soc_device *aic3x_socdev;
1246
1247 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1248 /*
1249 * AIC3X 2 wire address can be up to 4 devices with device addresses
1250 * 0x18, 0x19, 0x1A, 0x1B
1251 */
1252
1253 /*
1254 * If the i2c layer weren't so broken, we could pass this kind of data
1255 * around
1256 */
1257 static int aic3x_i2c_probe(struct i2c_client *i2c,
1258 const struct i2c_device_id *id)
1259 {
1260 struct snd_soc_device *socdev = aic3x_socdev;
1261 struct snd_soc_codec *codec = socdev->codec;
1262 int ret;
1263
1264 i2c_set_clientdata(i2c, codec);
1265 codec->control_data = i2c;
1266
1267 ret = aic3x_init(socdev);
1268 if (ret < 0)
1269 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1270 return ret;
1271 }
1272
1273 static int aic3x_i2c_remove(struct i2c_client *client)
1274 {
1275 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1276 kfree(codec->reg_cache);
1277 return 0;
1278 }
1279
1280 static const struct i2c_device_id aic3x_i2c_id[] = {
1281 { "tlv320aic3x", 0 },
1282 { }
1283 };
1284 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1285
1286 /* machine i2c codec control layer */
1287 static struct i2c_driver aic3x_i2c_driver = {
1288 .driver = {
1289 .name = "aic3x I2C Codec",
1290 .owner = THIS_MODULE,
1291 },
1292 .probe = aic3x_i2c_probe,
1293 .remove = aic3x_i2c_remove,
1294 .id_table = aic3x_i2c_id,
1295 };
1296
1297 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1298 {
1299 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1300 return (len == 1);
1301 }
1302
1303 static int aic3x_add_i2c_device(struct platform_device *pdev,
1304 const struct aic3x_setup_data *setup)
1305 {
1306 struct i2c_board_info info;
1307 struct i2c_adapter *adapter;
1308 struct i2c_client *client;
1309 int ret;
1310
1311 ret = i2c_add_driver(&aic3x_i2c_driver);
1312 if (ret != 0) {
1313 dev_err(&pdev->dev, "can't add i2c driver\n");
1314 return ret;
1315 }
1316
1317 memset(&info, 0, sizeof(struct i2c_board_info));
1318 info.addr = setup->i2c_address;
1319 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1320
1321 adapter = i2c_get_adapter(setup->i2c_bus);
1322 if (!adapter) {
1323 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1324 setup->i2c_bus);
1325 goto err_driver;
1326 }
1327
1328 client = i2c_new_device(adapter, &info);
1329 i2c_put_adapter(adapter);
1330 if (!client) {
1331 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1332 (unsigned int)info.addr);
1333 goto err_driver;
1334 }
1335
1336 return 0;
1337
1338 err_driver:
1339 i2c_del_driver(&aic3x_i2c_driver);
1340 return -ENODEV;
1341 }
1342 #endif
1343
1344 static int aic3x_probe(struct platform_device *pdev)
1345 {
1346 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1347 struct aic3x_setup_data *setup;
1348 struct snd_soc_codec *codec;
1349 struct aic3x_priv *aic3x;
1350 int ret = 0;
1351
1352 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1353
1354 setup = socdev->codec_data;
1355 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1356 if (codec == NULL)
1357 return -ENOMEM;
1358
1359 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1360 if (aic3x == NULL) {
1361 kfree(codec);
1362 return -ENOMEM;
1363 }
1364
1365 codec->private_data = aic3x;
1366 socdev->codec = codec;
1367 mutex_init(&codec->mutex);
1368 INIT_LIST_HEAD(&codec->dapm_widgets);
1369 INIT_LIST_HEAD(&codec->dapm_paths);
1370
1371 aic3x_socdev = socdev;
1372 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1373 if (setup->i2c_address) {
1374 codec->hw_write = (hw_write_t) i2c_master_send;
1375 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1376 ret = aic3x_add_i2c_device(pdev, setup);
1377 }
1378 #else
1379 /* Add other interfaces here */
1380 #endif
1381
1382 if (ret != 0) {
1383 kfree(codec->private_data);
1384 kfree(codec);
1385 }
1386 return ret;
1387 }
1388
1389 static int aic3x_remove(struct platform_device *pdev)
1390 {
1391 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1392 struct snd_soc_codec *codec = socdev->codec;
1393
1394 /* power down chip */
1395 if (codec->control_data)
1396 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1397
1398 snd_soc_free_pcms(socdev);
1399 snd_soc_dapm_free(socdev);
1400 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1401 i2c_unregister_device(codec->control_data);
1402 i2c_del_driver(&aic3x_i2c_driver);
1403 #endif
1404 kfree(codec->private_data);
1405 kfree(codec);
1406
1407 return 0;
1408 }
1409
1410 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1411 .probe = aic3x_probe,
1412 .remove = aic3x_remove,
1413 .suspend = aic3x_suspend,
1414 .resume = aic3x_resume,
1415 };
1416 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1417
1418 static int __init aic3x_modinit(void)
1419 {
1420 return snd_soc_register_dai(&aic3x_dai);
1421 }
1422 module_init(aic3x_modinit);
1423
1424 static void __exit aic3x_exit(void)
1425 {
1426 snd_soc_unregister_dai(&aic3x_dai);
1427 }
1428 module_exit(aic3x_exit);
1429
1430 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1431 MODULE_AUTHOR("Vladimir Barinov");
1432 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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