2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
50 #include "tlv320aic3x.h"
52 #define AIC3X_VERSION "0.2"
54 /* codec private data */
61 * AIC3X register cache
62 * We can't read the AIC3X register space when we are
63 * using 2 wire for device control, so we cache them instead.
64 * There is no point in caching the reset register
66 static const u8 aic3x_reg
[AIC3X_CACHEREGNUM
] = {
67 0x00, 0x00, 0x00, 0x10, /* 0 */
68 0x04, 0x00, 0x00, 0x00, /* 4 */
69 0x00, 0x00, 0x00, 0x01, /* 8 */
70 0x00, 0x00, 0x00, 0x80, /* 12 */
71 0x80, 0xff, 0xff, 0x78, /* 16 */
72 0x78, 0x78, 0x78, 0x78, /* 20 */
73 0x78, 0x00, 0x00, 0xfe, /* 24 */
74 0x00, 0x00, 0xfe, 0x00, /* 28 */
75 0x18, 0x18, 0x00, 0x00, /* 32 */
76 0x00, 0x00, 0x00, 0x00, /* 36 */
77 0x00, 0x00, 0x00, 0x80, /* 40 */
78 0x80, 0x00, 0x00, 0x00, /* 44 */
79 0x00, 0x00, 0x00, 0x04, /* 48 */
80 0x00, 0x00, 0x00, 0x00, /* 52 */
81 0x00, 0x00, 0x04, 0x00, /* 56 */
82 0x00, 0x00, 0x00, 0x00, /* 60 */
83 0x00, 0x04, 0x00, 0x00, /* 64 */
84 0x00, 0x00, 0x00, 0x00, /* 68 */
85 0x04, 0x00, 0x00, 0x00, /* 72 */
86 0x00, 0x00, 0x00, 0x00, /* 76 */
87 0x00, 0x00, 0x00, 0x00, /* 80 */
88 0x00, 0x00, 0x00, 0x00, /* 84 */
89 0x00, 0x00, 0x00, 0x00, /* 88 */
90 0x00, 0x00, 0x00, 0x00, /* 92 */
91 0x00, 0x00, 0x00, 0x00, /* 96 */
92 0x00, 0x00, 0x02, /* 100 */
96 * read aic3x register cache
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec
*codec
,
101 u8
*cache
= codec
->reg_cache
;
102 if (reg
>= AIC3X_CACHEREGNUM
)
108 * write aic3x register cache
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec
*codec
,
113 u8
*cache
= codec
->reg_cache
;
114 if (reg
>= AIC3X_CACHEREGNUM
)
120 * write to the aic3x register space
122 static int aic3x_write(struct snd_soc_codec
*codec
, unsigned int reg
,
128 * D15..D8 aic3x register offset
129 * D7...D0 register data
131 data
[0] = reg
& 0xff;
132 data
[1] = value
& 0xff;
134 aic3x_write_reg_cache(codec
, data
[0], data
[1]);
135 if (codec
->hw_write(codec
->control_data
, data
, 2) == 2)
142 * read from the aic3x register space
144 static int aic3x_read(struct snd_soc_codec
*codec
, unsigned int reg
,
148 if (codec
->hw_read(codec
->control_data
, value
, 1) != 1)
151 aic3x_write_reg_cache(codec
, reg
, *value
);
155 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
157 .info = snd_soc_info_volsw, \
158 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
159 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
162 * All input lines are connected when !0xf and disconnected with 0xf bit field,
163 * so we have to use specific dapm_put call for input mixer
165 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
166 struct snd_ctl_elem_value
*ucontrol
)
168 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
169 struct soc_mixer_control
*mc
=
170 (struct soc_mixer_control
*)kcontrol
->private_value
;
171 unsigned int reg
= mc
->reg
;
172 unsigned int shift
= mc
->shift
;
174 unsigned int mask
= (1 << fls(max
)) - 1;
175 unsigned int invert
= mc
->invert
;
176 unsigned short val
, val_mask
;
178 struct snd_soc_dapm_path
*path
;
181 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
189 val_mask
= mask
<< shift
;
192 mutex_lock(&widget
->codec
->mutex
);
194 if (snd_soc_test_bits(widget
->codec
, reg
, val_mask
, val
)) {
195 /* find dapm widget path assoc with kcontrol */
196 list_for_each_entry(path
, &widget
->codec
->dapm_paths
, list
) {
197 if (path
->kcontrol
!= kcontrol
)
200 /* found, now check type */
204 path
->connect
= invert
? 0 : 1;
206 /* old connection must be powered down */
207 path
->connect
= invert
? 1 : 0;
212 snd_soc_dapm_sync(widget
->codec
);
215 ret
= snd_soc_update_bits(widget
->codec
, reg
, val_mask
, val
);
217 mutex_unlock(&widget
->codec
->mutex
);
221 static const char *aic3x_left_dac_mux
[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
222 static const char *aic3x_right_dac_mux
[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
223 static const char *aic3x_left_hpcom_mux
[] =
224 { "differential of HPLOUT", "constant VCM", "single-ended" };
225 static const char *aic3x_right_hpcom_mux
[] =
226 { "differential of HPROUT", "constant VCM", "single-ended",
227 "differential of HPLCOM", "external feedback" };
228 static const char *aic3x_linein_mode_mux
[] = { "single-ended", "differential" };
229 static const char *aic3x_adc_hpf
[] =
230 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
234 #define LHPCOM_ENUM 2
235 #define RHPCOM_ENUM 3
236 #define LINE1L_ENUM 4
237 #define LINE1R_ENUM 5
238 #define LINE2L_ENUM 6
239 #define LINE2R_ENUM 7
240 #define ADC_HPF_ENUM 8
242 static const struct soc_enum aic3x_enum
[] = {
243 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 6, 3, aic3x_left_dac_mux
),
244 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 4, 3, aic3x_right_dac_mux
),
245 SOC_ENUM_SINGLE(HPLCOM_CFG
, 4, 3, aic3x_left_hpcom_mux
),
246 SOC_ENUM_SINGLE(HPRCOM_CFG
, 3, 5, aic3x_right_hpcom_mux
),
247 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
248 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
249 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
250 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
251 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL
, 6, 4, 4, aic3x_adc_hpf
),
255 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
257 static DECLARE_TLV_DB_SCALE(dac_tlv
, -6350, 50, 0);
258 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
259 static DECLARE_TLV_DB_SCALE(adc_tlv
, 0, 50, 0);
261 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
262 * Step size is approximately 0.5 dB over most of the scale but increasing
263 * near the very low levels.
264 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
265 * but having increasing dB difference below that (and where it doesn't count
266 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
267 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
269 static DECLARE_TLV_DB_SCALE(output_stage_tlv
, -5900, 50, 1);
271 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
273 SOC_DOUBLE_R_TLV("PCM Playback Volume",
274 LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1, dac_tlv
),
276 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
277 DACL1_2_LLOPM_VOL
, DACR1_2_RLOPM_VOL
,
278 0, 118, 1, output_stage_tlv
),
279 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL
, 3, 0x01, 0),
280 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL
, 3, 0x01, 0),
281 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
282 DACL1_2_LLOPM_VOL
, DACR1_2_LLOPM_VOL
,
283 0, 118, 1, output_stage_tlv
),
284 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
285 PGAL_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
286 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
287 PGAR_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
288 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
289 LINE2L_2_LLOPM_VOL
, LINE2R_2_LLOPM_VOL
,
290 0, 118, 1, output_stage_tlv
),
291 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
292 LINE2L_2_RLOPM_VOL
, LINE2R_2_RLOPM_VOL
,
293 0, 118, 1, output_stage_tlv
),
295 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
296 DACL1_2_MONOLOPM_VOL
, DACR1_2_MONOLOPM_VOL
,
297 0, 118, 1, output_stage_tlv
),
298 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
299 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
300 PGAL_2_MONOLOPM_VOL
, PGAR_2_MONOLOPM_VOL
,
301 0, 118, 1, output_stage_tlv
),
302 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
303 LINE2L_2_MONOLOPM_VOL
, LINE2R_2_MONOLOPM_VOL
,
304 0, 118, 1, output_stage_tlv
),
306 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
307 DACL1_2_HPLOUT_VOL
, DACR1_2_HPROUT_VOL
,
308 0, 118, 1, output_stage_tlv
),
309 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
311 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
312 PGAR_2_HPLOUT_VOL
, PGAR_2_HPROUT_VOL
,
313 0, 118, 1, output_stage_tlv
),
314 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
315 PGAL_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
316 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
317 PGAL_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
318 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
319 LINE2L_2_HPLOUT_VOL
, LINE2R_2_HPROUT_VOL
,
320 0, 118, 1, output_stage_tlv
),
322 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
323 DACL1_2_HPLCOM_VOL
, DACR1_2_HPRCOM_VOL
,
324 0, 118, 1, output_stage_tlv
),
325 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
327 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
328 PGAL_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
329 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
330 PGAL_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
331 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
332 LINE2L_2_HPLCOM_VOL
, LINE2R_2_HPRCOM_VOL
,
333 0, 118, 1, output_stage_tlv
),
336 * Note: enable Automatic input Gain Controller with care. It can
337 * adjust PGA to max value when ADC is on and will never go back.
339 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
342 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL
, RADC_VOL
,
344 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
346 SOC_ENUM("ADC HPF Cut-off", aic3x_enum
[ADC_HPF_ENUM
]),
350 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
351 SOC_DAPM_ENUM("Route", aic3x_enum
[LDAC_ENUM
]);
354 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
355 SOC_DAPM_ENUM("Route", aic3x_enum
[RDAC_ENUM
]);
358 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
359 SOC_DAPM_ENUM("Route", aic3x_enum
[LHPCOM_ENUM
]);
361 /* Right HPCOM Mux */
362 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
363 SOC_DAPM_ENUM("Route", aic3x_enum
[RHPCOM_ENUM
]);
365 /* Left DAC_L1 Mixer */
366 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls
[] = {
367 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
368 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL
, 7, 1, 0),
369 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
370 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
371 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
374 /* Right DAC_R1 Mixer */
375 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls
[] = {
376 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL
, 7, 1, 0),
377 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
378 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
379 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
380 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
384 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
385 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
386 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
387 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
388 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
389 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
392 /* Right PGA Mixer */
393 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
394 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
395 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
396 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
397 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
398 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
402 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls
=
403 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1L_ENUM
]);
405 /* Right Line1 Mux */
406 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls
=
407 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1R_ENUM
]);
410 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
411 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2L_ENUM
]);
413 /* Right Line2 Mux */
414 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
415 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2R_ENUM
]);
417 /* Left PGA Bypass Mixer */
418 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls
[] = {
419 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
420 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL
, 7, 1, 0),
421 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
422 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
423 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL
, 7, 1, 0),
424 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
425 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL
, 7, 1, 0),
428 /* Right PGA Bypass Mixer */
429 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls
[] = {
430 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL
, 7, 1, 0),
431 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
432 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
433 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL
, 7, 1, 0),
434 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
435 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL
, 7, 1, 0),
436 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
439 /* Left Line2 Bypass Mixer */
440 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls
[] = {
441 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
442 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL
, 7, 1, 0),
443 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
444 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
445 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
448 /* Right Line2 Bypass Mixer */
449 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls
[] = {
450 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL
, 7, 1, 0),
451 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
452 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
453 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
454 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
457 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
458 /* Left DAC to Left Outputs */
459 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
460 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
461 &aic3x_left_dac_mux_controls
),
462 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM
, 0, 0,
463 &aic3x_left_dac_mixer_controls
[0],
464 ARRAY_SIZE(aic3x_left_dac_mixer_controls
)),
465 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
466 &aic3x_left_hpcom_mux_controls
),
467 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
468 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
469 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
471 /* Right DAC to Right Outputs */
472 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
473 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
474 &aic3x_right_dac_mux_controls
),
475 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM
, 0, 0,
476 &aic3x_right_dac_mixer_controls
[0],
477 ARRAY_SIZE(aic3x_right_dac_mixer_controls
)),
478 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
479 &aic3x_right_hpcom_mux_controls
),
480 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
481 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
482 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
485 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
487 /* Inputs to Left ADC */
488 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
489 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
490 &aic3x_left_pga_mixer_controls
[0],
491 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
492 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
493 &aic3x_left_line1_mux_controls
),
494 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM
, 0, 0,
495 &aic3x_left_line1_mux_controls
),
496 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
497 &aic3x_left_line2_mux_controls
),
499 /* Inputs to Right ADC */
500 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
501 LINE1R_2_RADC_CTRL
, 2, 0),
502 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
503 &aic3x_right_pga_mixer_controls
[0],
504 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
505 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM
, 0, 0,
506 &aic3x_right_line1_mux_controls
),
507 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
508 &aic3x_right_line1_mux_controls
),
509 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
510 &aic3x_right_line2_mux_controls
),
513 * Not a real mic bias widget but similar function. This is for dynamic
514 * control of GPIO1 digital mic modulator clock output function when
517 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
518 AIC3X_GPIO1_REG
, 4, 0xf,
519 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
520 AIC3X_GPIO1_FUNC_DISABLED
),
523 * Also similar function like mic bias. Selects digital mic with
524 * configurable oversampling rate instead of ADC converter.
526 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
527 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
528 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
529 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
530 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
531 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
534 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2V",
535 MICBIAS_CTRL
, 6, 3, 1, 0),
536 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2.5V",
537 MICBIAS_CTRL
, 6, 3, 2, 0),
538 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias AVDD",
539 MICBIAS_CTRL
, 6, 3, 3, 0),
541 /* Left PGA to Left Output bypass */
542 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
543 &aic3x_left_pga_bp_mixer_controls
[0],
544 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls
)),
546 /* Right PGA to Right Output bypass */
547 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
548 &aic3x_right_pga_bp_mixer_controls
[0],
549 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls
)),
551 /* Left Line2 to Left Output bypass */
552 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
553 &aic3x_left_line2_bp_mixer_controls
[0],
554 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls
)),
556 /* Right Line2 to Right Output bypass */
557 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
558 &aic3x_right_line2_bp_mixer_controls
[0],
559 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls
)),
561 SND_SOC_DAPM_OUTPUT("LLOUT"),
562 SND_SOC_DAPM_OUTPUT("RLOUT"),
563 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
564 SND_SOC_DAPM_OUTPUT("HPLOUT"),
565 SND_SOC_DAPM_OUTPUT("HPROUT"),
566 SND_SOC_DAPM_OUTPUT("HPLCOM"),
567 SND_SOC_DAPM_OUTPUT("HPRCOM"),
569 SND_SOC_DAPM_INPUT("MIC3L"),
570 SND_SOC_DAPM_INPUT("MIC3R"),
571 SND_SOC_DAPM_INPUT("LINE1L"),
572 SND_SOC_DAPM_INPUT("LINE1R"),
573 SND_SOC_DAPM_INPUT("LINE2L"),
574 SND_SOC_DAPM_INPUT("LINE2R"),
577 static const struct snd_soc_dapm_route intercon
[] = {
579 {"Left DAC Mux", "DAC_L1", "Left DAC"},
580 {"Left DAC Mux", "DAC_L2", "Left DAC"},
581 {"Left DAC Mux", "DAC_L3", "Left DAC"},
583 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
584 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
585 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
586 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
587 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
588 {"Left Line Out", NULL
, "Left DAC Mux"},
589 {"Left HP Out", NULL
, "Left DAC Mux"},
591 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
592 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
593 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
595 {"Left Line Out", NULL
, "Left DAC_L1 Mixer"},
596 {"Mono Out", NULL
, "Left DAC_L1 Mixer"},
597 {"Left HP Out", NULL
, "Left DAC_L1 Mixer"},
598 {"Left HP Com", NULL
, "Left HPCOM Mux"},
600 {"LLOUT", NULL
, "Left Line Out"},
601 {"LLOUT", NULL
, "Left Line Out"},
602 {"HPLOUT", NULL
, "Left HP Out"},
603 {"HPLCOM", NULL
, "Left HP Com"},
606 {"Right DAC Mux", "DAC_R1", "Right DAC"},
607 {"Right DAC Mux", "DAC_R2", "Right DAC"},
608 {"Right DAC Mux", "DAC_R3", "Right DAC"},
610 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
611 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
612 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
613 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
614 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
615 {"Right Line Out", NULL
, "Right DAC Mux"},
616 {"Right HP Out", NULL
, "Right DAC Mux"},
618 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
619 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
620 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
621 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
622 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
624 {"Right Line Out", NULL
, "Right DAC_R1 Mixer"},
625 {"Mono Out", NULL
, "Right DAC_R1 Mixer"},
626 {"Right HP Out", NULL
, "Right DAC_R1 Mixer"},
627 {"Right HP Com", NULL
, "Right HPCOM Mux"},
629 {"RLOUT", NULL
, "Right Line Out"},
630 {"RLOUT", NULL
, "Right Line Out"},
631 {"HPROUT", NULL
, "Right HP Out"},
632 {"HPRCOM", NULL
, "Right HP Com"},
635 {"MONO_LOUT", NULL
, "Mono Out"},
636 {"MONO_LOUT", NULL
, "Mono Out"},
639 {"Left Line1L Mux", "single-ended", "LINE1L"},
640 {"Left Line1L Mux", "differential", "LINE1L"},
642 {"Left Line2L Mux", "single-ended", "LINE2L"},
643 {"Left Line2L Mux", "differential", "LINE2L"},
645 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
646 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
647 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
648 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
649 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
651 {"Left ADC", NULL
, "Left PGA Mixer"},
652 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
655 {"Right Line1R Mux", "single-ended", "LINE1R"},
656 {"Right Line1R Mux", "differential", "LINE1R"},
658 {"Right Line2R Mux", "single-ended", "LINE2R"},
659 {"Right Line2R Mux", "differential", "LINE2R"},
661 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
662 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
663 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
664 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
665 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
667 {"Right ADC", NULL
, "Right PGA Mixer"},
668 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
670 /* Left PGA Bypass */
671 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
672 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
673 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
674 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
675 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
676 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
677 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
679 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
680 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
681 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
683 {"Left Line Out", NULL
, "Left PGA Bypass Mixer"},
684 {"Mono Out", NULL
, "Left PGA Bypass Mixer"},
685 {"Left HP Out", NULL
, "Left PGA Bypass Mixer"},
687 /* Right PGA Bypass */
688 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
689 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
690 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
691 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
692 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
693 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
694 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
696 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
697 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
698 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
699 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
700 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
702 {"Right Line Out", NULL
, "Right PGA Bypass Mixer"},
703 {"Mono Out", NULL
, "Right PGA Bypass Mixer"},
704 {"Right HP Out", NULL
, "Right PGA Bypass Mixer"},
706 /* Left Line2 Bypass */
707 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
708 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
709 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
710 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
711 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
713 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
714 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
715 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
717 {"Left Line Out", NULL
, "Left Line2 Bypass Mixer"},
718 {"Mono Out", NULL
, "Left Line2 Bypass Mixer"},
719 {"Left HP Out", NULL
, "Left Line2 Bypass Mixer"},
721 /* Right Line2 Bypass */
722 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
723 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
724 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
725 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
726 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
728 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
729 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
730 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
731 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
732 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
734 {"Right Line Out", NULL
, "Right Line2 Bypass Mixer"},
735 {"Mono Out", NULL
, "Right Line2 Bypass Mixer"},
736 {"Right HP Out", NULL
, "Right Line2 Bypass Mixer"},
739 * Logical path between digital mic enable and GPIO1 modulator clock
742 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
743 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
744 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
747 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
749 snd_soc_dapm_new_controls(codec
, aic3x_dapm_widgets
,
750 ARRAY_SIZE(aic3x_dapm_widgets
));
752 /* set up audio path interconnects */
753 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
755 snd_soc_dapm_new_widgets(codec
);
759 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
760 struct snd_pcm_hw_params
*params
,
761 struct snd_soc_dai
*dai
)
763 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
764 struct snd_soc_device
*socdev
= rtd
->socdev
;
765 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
766 struct aic3x_priv
*aic3x
= codec
->private_data
;
767 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
768 u8 data
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
771 /* select data word length */
773 aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
774 switch (params_format(params
)) {
775 case SNDRV_PCM_FORMAT_S16_LE
:
777 case SNDRV_PCM_FORMAT_S20_3LE
:
780 case SNDRV_PCM_FORMAT_S24_LE
:
783 case SNDRV_PCM_FORMAT_S32_LE
:
787 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
789 /* Fsref can be 44100 or 48000 */
790 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
792 /* Try to find a value for Q which allows us to bypass the PLL and
793 * generate CODEC_CLK directly. */
794 for (pll_q
= 2; pll_q
< 18; pll_q
++)
795 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
802 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
803 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
805 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
807 /* Route Left DAC to left channel input and
808 * right DAC to right channel input */
809 data
= (LDAC2LCH
| RDAC2RCH
);
810 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
811 if (params_rate(params
) >= 64000)
812 data
|= DUAL_RATE_MODE
;
813 aic3x_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
815 /* codec sample rate select */
816 data
= (fsref
* 20) / params_rate(params
);
817 if (params_rate(params
) < 64000)
822 aic3x_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
828 * find an apropriate setup for j, d, r and p by iterating over
829 * p and r - j and d are calculated for each fraction.
830 * Up to 128 values are probed, the closest one wins the game.
831 * The sysclk is divided by 1000 to prevent integer overflows.
833 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
835 for (r
= 1; r
<= 16; r
++)
836 for (p
= 1; p
<= 8; p
++) {
837 int clk
, tmp
= (codec_clk
* pll_r
* 10) / pll_p
;
844 if (d
!= 0 && aic3x
->sysclk
< 10000000)
847 /* This is actually 1000 * ((j + (d/10000)) * r) / p
848 * The term had to be converted to get rid of the
849 * division by 10000 */
850 clk
= ((10000 * j
* r
) + (d
* r
)) / (10 * p
);
852 /* check whether this values get closer than the best
853 * ones we had before */
854 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
855 pll_j
= j
; pll_d
= d
; pll_r
= r
; pll_p
= p
;
859 /* Early exit for exact matches */
860 if (clk
== codec_clk
)
865 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
869 data
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
870 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, data
| (pll_p
<< PLLP_SHIFT
));
871 aic3x_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
, pll_r
<< PLLR_SHIFT
);
872 aic3x_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
873 aic3x_write(codec
, AIC3X_PLL_PROGC_REG
, (pll_d
>> 6) << PLLD_MSB_SHIFT
);
874 aic3x_write(codec
, AIC3X_PLL_PROGD_REG
,
875 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
880 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
882 struct snd_soc_codec
*codec
= dai
->codec
;
883 u8 ldac_reg
= aic3x_read_reg_cache(codec
, LDAC_VOL
) & ~MUTE_ON
;
884 u8 rdac_reg
= aic3x_read_reg_cache(codec
, RDAC_VOL
) & ~MUTE_ON
;
887 aic3x_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
888 aic3x_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
890 aic3x_write(codec
, LDAC_VOL
, ldac_reg
);
891 aic3x_write(codec
, RDAC_VOL
, rdac_reg
);
897 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
898 int clk_id
, unsigned int freq
, int dir
)
900 struct snd_soc_codec
*codec
= codec_dai
->codec
;
901 struct aic3x_priv
*aic3x
= codec
->private_data
;
903 aic3x
->sysclk
= freq
;
907 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
910 struct snd_soc_codec
*codec
= codec_dai
->codec
;
911 struct aic3x_priv
*aic3x
= codec
->private_data
;
912 u8 iface_areg
, iface_breg
;
915 iface_areg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
916 iface_breg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
918 /* set master/slave audio interface */
919 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
920 case SND_SOC_DAIFMT_CBM_CFM
:
922 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
924 case SND_SOC_DAIFMT_CBS_CFS
:
932 * match both interface format and signal polarities since they
935 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
936 SND_SOC_DAIFMT_INV_MASK
)) {
937 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
939 case (SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
):
941 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
942 iface_breg
|= (0x01 << 6);
944 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
945 iface_breg
|= (0x02 << 6);
947 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
948 iface_breg
|= (0x03 << 6);
955 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
956 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
957 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLC
, delay
);
962 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
963 enum snd_soc_bias_level level
)
965 struct aic3x_priv
*aic3x
= codec
->private_data
;
969 case SND_SOC_BIAS_ON
:
970 /* all power is driven by DAPM system */
973 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
974 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
978 case SND_SOC_BIAS_PREPARE
:
980 case SND_SOC_BIAS_STANDBY
:
982 * all power is driven by DAPM system,
983 * so output power is safe if bypass was set
987 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
988 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
992 case SND_SOC_BIAS_OFF
:
993 /* force all power off */
994 reg
= aic3x_read_reg_cache(codec
, LINE1L_2_LADC_CTRL
);
995 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, reg
& ~LADC_PWR_ON
);
996 reg
= aic3x_read_reg_cache(codec
, LINE1R_2_RADC_CTRL
);
997 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, reg
& ~RADC_PWR_ON
);
999 reg
= aic3x_read_reg_cache(codec
, DAC_PWR
);
1000 aic3x_write(codec
, DAC_PWR
, reg
& ~(LDAC_PWR_ON
| RDAC_PWR_ON
));
1002 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
1003 aic3x_write(codec
, HPLOUT_CTRL
, reg
& ~HPLOUT_PWR_ON
);
1004 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
1005 aic3x_write(codec
, HPROUT_CTRL
, reg
& ~HPROUT_PWR_ON
);
1007 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
1008 aic3x_write(codec
, HPLCOM_CTRL
, reg
& ~HPLCOM_PWR_ON
);
1009 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
1010 aic3x_write(codec
, HPRCOM_CTRL
, reg
& ~HPRCOM_PWR_ON
);
1012 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
1013 aic3x_write(codec
, MONOLOPM_CTRL
, reg
& ~MONOLOPM_PWR_ON
);
1015 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
1016 aic3x_write(codec
, LLOPM_CTRL
, reg
& ~LLOPM_PWR_ON
);
1017 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
1018 aic3x_write(codec
, RLOPM_CTRL
, reg
& ~RLOPM_PWR_ON
);
1020 if (aic3x
->master
) {
1022 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
1023 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
1028 codec
->bias_level
= level
;
1033 void aic3x_set_gpio(struct snd_soc_codec
*codec
, int gpio
, int state
)
1035 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1036 u8 bit
= gpio
? 3: 0;
1037 u8 val
= aic3x_read_reg_cache(codec
, reg
) & ~(1 << bit
);
1038 aic3x_write(codec
, reg
, val
| (!!state
<< bit
));
1040 EXPORT_SYMBOL_GPL(aic3x_set_gpio
);
1042 int aic3x_get_gpio(struct snd_soc_codec
*codec
, int gpio
)
1044 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1045 u8 val
, bit
= gpio
? 2: 1;
1047 aic3x_read(codec
, reg
, &val
);
1048 return (val
>> bit
) & 1;
1050 EXPORT_SYMBOL_GPL(aic3x_get_gpio
);
1052 void aic3x_set_headset_detection(struct snd_soc_codec
*codec
, int detect
,
1053 int headset_debounce
, int button_debounce
)
1057 val
= ((detect
& AIC3X_HEADSET_DETECT_MASK
)
1058 << AIC3X_HEADSET_DETECT_SHIFT
) |
1059 ((headset_debounce
& AIC3X_HEADSET_DEBOUNCE_MASK
)
1060 << AIC3X_HEADSET_DEBOUNCE_SHIFT
) |
1061 ((button_debounce
& AIC3X_BUTTON_DEBOUNCE_MASK
)
1062 << AIC3X_BUTTON_DEBOUNCE_SHIFT
);
1064 if (detect
& AIC3X_HEADSET_DETECT_MASK
)
1065 val
|= AIC3X_HEADSET_DETECT_ENABLED
;
1067 aic3x_write(codec
, AIC3X_HEADSET_DETECT_CTRL_A
, val
);
1069 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection
);
1071 int aic3x_headset_detected(struct snd_soc_codec
*codec
)
1074 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1075 return (val
>> 4) & 1;
1077 EXPORT_SYMBOL_GPL(aic3x_headset_detected
);
1079 int aic3x_button_pressed(struct snd_soc_codec
*codec
)
1082 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1083 return (val
>> 5) & 1;
1085 EXPORT_SYMBOL_GPL(aic3x_button_pressed
);
1087 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1088 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1089 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1091 struct snd_soc_dai aic3x_dai
= {
1092 .name
= "tlv320aic3x",
1094 .stream_name
= "Playback",
1097 .rates
= AIC3X_RATES
,
1098 .formats
= AIC3X_FORMATS
,},
1100 .stream_name
= "Capture",
1103 .rates
= AIC3X_RATES
,
1104 .formats
= AIC3X_FORMATS
,},
1106 .hw_params
= aic3x_hw_params
,
1107 .digital_mute
= aic3x_mute
,
1108 .set_sysclk
= aic3x_set_dai_sysclk
,
1109 .set_fmt
= aic3x_set_dai_fmt
,
1112 EXPORT_SYMBOL_GPL(aic3x_dai
);
1114 static int aic3x_suspend(struct platform_device
*pdev
, pm_message_t state
)
1116 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1117 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1119 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1124 static int aic3x_resume(struct platform_device
*pdev
)
1126 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1127 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1130 u8
*cache
= codec
->reg_cache
;
1132 /* Sync reg_cache with the hardware */
1133 for (i
= 0; i
< ARRAY_SIZE(aic3x_reg
); i
++) {
1136 codec
->hw_write(codec
->control_data
, data
, 2);
1139 aic3x_set_bias_level(codec
, codec
->suspend_bias_level
);
1145 * initialise the AIC3X driver
1146 * register the mixer and dsp interfaces with the kernel
1148 static int aic3x_init(struct snd_soc_device
*socdev
)
1150 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1151 struct aic3x_setup_data
*setup
= socdev
->codec_data
;
1154 codec
->name
= "tlv320aic3x";
1155 codec
->owner
= THIS_MODULE
;
1156 codec
->read
= aic3x_read_reg_cache
;
1157 codec
->write
= aic3x_write
;
1158 codec
->set_bias_level
= aic3x_set_bias_level
;
1159 codec
->dai
= &aic3x_dai
;
1161 codec
->reg_cache_size
= ARRAY_SIZE(aic3x_reg
);
1162 codec
->reg_cache
= kmemdup(aic3x_reg
, sizeof(aic3x_reg
), GFP_KERNEL
);
1163 if (codec
->reg_cache
== NULL
)
1166 aic3x_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1167 aic3x_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1170 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1172 printk(KERN_ERR
"aic3x: failed to create pcms\n");
1176 /* DAC default volume and mute */
1177 aic3x_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1178 aic3x_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1180 /* DAC to HP default volume and route to Output mixer */
1181 aic3x_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1182 aic3x_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1183 aic3x_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1184 aic3x_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1185 /* DAC to Line Out default volume and route to Output mixer */
1186 aic3x_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1187 aic3x_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1188 /* DAC to Mono Line Out default volume and route to Output mixer */
1189 aic3x_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1190 aic3x_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1192 /* unmute all outputs */
1193 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
1194 aic3x_write(codec
, LLOPM_CTRL
, reg
| UNMUTE
);
1195 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
1196 aic3x_write(codec
, RLOPM_CTRL
, reg
| UNMUTE
);
1197 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
1198 aic3x_write(codec
, MONOLOPM_CTRL
, reg
| UNMUTE
);
1199 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
1200 aic3x_write(codec
, HPLOUT_CTRL
, reg
| UNMUTE
);
1201 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
1202 aic3x_write(codec
, HPROUT_CTRL
, reg
| UNMUTE
);
1203 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
1204 aic3x_write(codec
, HPLCOM_CTRL
, reg
| UNMUTE
);
1205 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
1206 aic3x_write(codec
, HPRCOM_CTRL
, reg
| UNMUTE
);
1208 /* ADC default volume and unmute */
1209 aic3x_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1210 aic3x_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1211 /* By default route Line1 to ADC PGA mixer */
1212 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1213 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1215 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1216 aic3x_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1217 aic3x_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1218 aic3x_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1219 aic3x_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1220 /* PGA to Line Out default volume, disconnect from Output Mixer */
1221 aic3x_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1222 aic3x_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1223 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1224 aic3x_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1225 aic3x_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1227 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1228 aic3x_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1229 aic3x_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1230 aic3x_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1231 aic3x_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1232 /* Line2 Line Out default volume, disconnect from Output Mixer */
1233 aic3x_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1234 aic3x_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1235 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1236 aic3x_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1237 aic3x_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1239 /* off, with power on */
1240 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1242 /* setup GPIO functions */
1243 aic3x_write(codec
, AIC3X_GPIO1_REG
, (setup
->gpio_func
[0] & 0xf) << 4);
1244 aic3x_write(codec
, AIC3X_GPIO2_REG
, (setup
->gpio_func
[1] & 0xf) << 4);
1246 snd_soc_add_controls(codec
, aic3x_snd_controls
,
1247 ARRAY_SIZE(aic3x_snd_controls
));
1248 aic3x_add_widgets(codec
);
1249 ret
= snd_soc_init_card(socdev
);
1251 printk(KERN_ERR
"aic3x: failed to register card\n");
1258 snd_soc_free_pcms(socdev
);
1259 snd_soc_dapm_free(socdev
);
1261 kfree(codec
->reg_cache
);
1265 static struct snd_soc_device
*aic3x_socdev
;
1267 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1269 * AIC3X 2 wire address can be up to 4 devices with device addresses
1270 * 0x18, 0x19, 0x1A, 0x1B
1274 * If the i2c layer weren't so broken, we could pass this kind of data
1277 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1278 const struct i2c_device_id
*id
)
1280 struct snd_soc_device
*socdev
= aic3x_socdev
;
1281 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1284 i2c_set_clientdata(i2c
, codec
);
1285 codec
->control_data
= i2c
;
1287 ret
= aic3x_init(socdev
);
1289 printk(KERN_ERR
"aic3x: failed to initialise AIC3X\n");
1293 static int aic3x_i2c_remove(struct i2c_client
*client
)
1295 struct snd_soc_codec
*codec
= i2c_get_clientdata(client
);
1296 kfree(codec
->reg_cache
);
1300 static const struct i2c_device_id aic3x_i2c_id
[] = {
1301 { "tlv320aic3x", 0 },
1304 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1306 /* machine i2c codec control layer */
1307 static struct i2c_driver aic3x_i2c_driver
= {
1309 .name
= "aic3x I2C Codec",
1310 .owner
= THIS_MODULE
,
1312 .probe
= aic3x_i2c_probe
,
1313 .remove
= aic3x_i2c_remove
,
1314 .id_table
= aic3x_i2c_id
,
1317 static int aic3x_i2c_read(struct i2c_client
*client
, u8
*value
, int len
)
1319 value
[0] = i2c_smbus_read_byte_data(client
, value
[0]);
1323 static int aic3x_add_i2c_device(struct platform_device
*pdev
,
1324 const struct aic3x_setup_data
*setup
)
1326 struct i2c_board_info info
;
1327 struct i2c_adapter
*adapter
;
1328 struct i2c_client
*client
;
1331 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1333 dev_err(&pdev
->dev
, "can't add i2c driver\n");
1337 memset(&info
, 0, sizeof(struct i2c_board_info
));
1338 info
.addr
= setup
->i2c_address
;
1339 strlcpy(info
.type
, "tlv320aic3x", I2C_NAME_SIZE
);
1341 adapter
= i2c_get_adapter(setup
->i2c_bus
);
1343 dev_err(&pdev
->dev
, "can't get i2c adapter %d\n",
1348 client
= i2c_new_device(adapter
, &info
);
1349 i2c_put_adapter(adapter
);
1351 dev_err(&pdev
->dev
, "can't add i2c device at 0x%x\n",
1352 (unsigned int)info
.addr
);
1359 i2c_del_driver(&aic3x_i2c_driver
);
1364 static int aic3x_probe(struct platform_device
*pdev
)
1366 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1367 struct aic3x_setup_data
*setup
;
1368 struct snd_soc_codec
*codec
;
1369 struct aic3x_priv
*aic3x
;
1372 printk(KERN_INFO
"AIC3X Audio Codec %s\n", AIC3X_VERSION
);
1374 setup
= socdev
->codec_data
;
1375 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1379 aic3x
= kzalloc(sizeof(struct aic3x_priv
), GFP_KERNEL
);
1380 if (aic3x
== NULL
) {
1385 codec
->private_data
= aic3x
;
1386 socdev
->card
->codec
= codec
;
1387 mutex_init(&codec
->mutex
);
1388 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1389 INIT_LIST_HEAD(&codec
->dapm_paths
);
1391 aic3x_socdev
= socdev
;
1392 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1393 if (setup
->i2c_address
) {
1394 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1395 codec
->hw_read
= (hw_read_t
) aic3x_i2c_read
;
1396 ret
= aic3x_add_i2c_device(pdev
, setup
);
1399 /* Add other interfaces here */
1403 kfree(codec
->private_data
);
1409 static int aic3x_remove(struct platform_device
*pdev
)
1411 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1412 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1414 /* power down chip */
1415 if (codec
->control_data
)
1416 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1418 snd_soc_free_pcms(socdev
);
1419 snd_soc_dapm_free(socdev
);
1420 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1421 i2c_unregister_device(codec
->control_data
);
1422 i2c_del_driver(&aic3x_i2c_driver
);
1424 kfree(codec
->private_data
);
1430 struct snd_soc_codec_device soc_codec_dev_aic3x
= {
1431 .probe
= aic3x_probe
,
1432 .remove
= aic3x_remove
,
1433 .suspend
= aic3x_suspend
,
1434 .resume
= aic3x_resume
,
1436 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x
);
1438 static int __init
aic3x_modinit(void)
1440 return snd_soc_register_dai(&aic3x_dai
);
1442 module_init(aic3x_modinit
);
1444 static void __exit
aic3x_exit(void)
1446 snd_soc_unregister_dai(&aic3x_dai
);
1448 module_exit(aic3x_exit
);
1450 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1451 MODULE_AUTHOR("Vladimir Barinov");
1452 MODULE_LICENSE("GPL");