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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/slab.h>
44 #include <sound/core.h>
45 #include <sound/pcm.h>
46 #include <sound/pcm_params.h>
47 #include <sound/soc.h>
48 #include <sound/initval.h>
49 #include <sound/tlv.h>
50 #include <sound/tlv320aic3x.h>
51
52 #include "tlv320aic3x.h"
53
54 #define AIC3X_NUM_SUPPLIES 4
55 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
56 "IOVDD", /* I/O Voltage */
57 "DVDD", /* Digital Core Voltage */
58 "AVDD", /* Analog DAC Voltage */
59 "DRVDD", /* ADC Analog and Output Driver Voltage */
60 };
61
62 static LIST_HEAD(reset_list);
63
64 struct aic3x_priv;
65
66 struct aic3x_disable_nb {
67 struct notifier_block nb;
68 struct aic3x_priv *aic3x;
69 };
70
71 /* codec private data */
72 struct aic3x_priv {
73 struct snd_soc_codec *codec;
74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
76 enum snd_soc_control_type control_type;
77 struct aic3x_setup_data *setup;
78 unsigned int sysclk;
79 struct list_head list;
80 int master;
81 int gpio_reset;
82 int power;
83 #define AIC3X_MODEL_3X 0
84 #define AIC3X_MODEL_33 1
85 #define AIC3X_MODEL_3007 2
86 u16 model;
87 };
88
89 /*
90 * AIC3X register cache
91 * We can't read the AIC3X register space when we are
92 * using 2 wire for device control, so we cache them instead.
93 * There is no point in caching the reset register
94 */
95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
96 0x00, 0x00, 0x00, 0x10, /* 0 */
97 0x04, 0x00, 0x00, 0x00, /* 4 */
98 0x00, 0x00, 0x00, 0x01, /* 8 */
99 0x00, 0x00, 0x00, 0x80, /* 12 */
100 0x80, 0xff, 0xff, 0x78, /* 16 */
101 0x78, 0x78, 0x78, 0x78, /* 20 */
102 0x78, 0x00, 0x00, 0xfe, /* 24 */
103 0x00, 0x00, 0xfe, 0x00, /* 28 */
104 0x18, 0x18, 0x00, 0x00, /* 32 */
105 0x00, 0x00, 0x00, 0x00, /* 36 */
106 0x00, 0x00, 0x00, 0x80, /* 40 */
107 0x80, 0x00, 0x00, 0x00, /* 44 */
108 0x00, 0x00, 0x00, 0x04, /* 48 */
109 0x00, 0x00, 0x00, 0x00, /* 52 */
110 0x00, 0x00, 0x04, 0x00, /* 56 */
111 0x00, 0x00, 0x00, 0x00, /* 60 */
112 0x00, 0x04, 0x00, 0x00, /* 64 */
113 0x00, 0x00, 0x00, 0x00, /* 68 */
114 0x04, 0x00, 0x00, 0x00, /* 72 */
115 0x00, 0x00, 0x00, 0x00, /* 76 */
116 0x00, 0x00, 0x00, 0x00, /* 80 */
117 0x00, 0x00, 0x00, 0x00, /* 84 */
118 0x00, 0x00, 0x00, 0x00, /* 88 */
119 0x00, 0x00, 0x00, 0x00, /* 92 */
120 0x00, 0x00, 0x00, 0x00, /* 96 */
121 0x00, 0x00, 0x02, /* 100 */
122 };
123
124 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
125 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
126 .info = snd_soc_info_volsw, \
127 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
128 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
129
130 /*
131 * All input lines are connected when !0xf and disconnected with 0xf bit field,
132 * so we have to use specific dapm_put call for input mixer
133 */
134 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
135 struct snd_ctl_elem_value *ucontrol)
136 {
137 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
138 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
139 struct soc_mixer_control *mc =
140 (struct soc_mixer_control *)kcontrol->private_value;
141 unsigned int reg = mc->reg;
142 unsigned int shift = mc->shift;
143 int max = mc->max;
144 unsigned int mask = (1 << fls(max)) - 1;
145 unsigned int invert = mc->invert;
146 unsigned short val, val_mask;
147 int ret;
148 struct snd_soc_dapm_path *path;
149 int found = 0;
150
151 val = (ucontrol->value.integer.value[0] & mask);
152
153 mask = 0xf;
154 if (val)
155 val = mask;
156
157 if (invert)
158 val = mask - val;
159 val_mask = mask << shift;
160 val = val << shift;
161
162 mutex_lock(&widget->codec->mutex);
163
164 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
165 /* find dapm widget path assoc with kcontrol */
166 list_for_each_entry(path, &widget->dapm->card->paths, list) {
167 if (path->kcontrol != kcontrol)
168 continue;
169
170 /* found, now check type */
171 found = 1;
172 if (val)
173 /* new connection */
174 path->connect = invert ? 0 : 1;
175 else
176 /* old connection must be powered down */
177 path->connect = invert ? 1 : 0;
178
179 dapm_mark_dirty(path->source, "tlv320aic3x source");
180 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
181
182 break;
183 }
184
185 if (found)
186 snd_soc_dapm_sync(widget->dapm);
187 }
188
189 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
190
191 mutex_unlock(&widget->codec->mutex);
192 return ret;
193 }
194
195 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
196 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
197 static const char *aic3x_left_hpcom_mux[] =
198 { "differential of HPLOUT", "constant VCM", "single-ended" };
199 static const char *aic3x_right_hpcom_mux[] =
200 { "differential of HPROUT", "constant VCM", "single-ended",
201 "differential of HPLCOM", "external feedback" };
202 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
203 static const char *aic3x_adc_hpf[] =
204 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
205
206 #define LDAC_ENUM 0
207 #define RDAC_ENUM 1
208 #define LHPCOM_ENUM 2
209 #define RHPCOM_ENUM 3
210 #define LINE1L_2_L_ENUM 4
211 #define LINE1L_2_R_ENUM 5
212 #define LINE1R_2_L_ENUM 6
213 #define LINE1R_2_R_ENUM 7
214 #define LINE2L_ENUM 8
215 #define LINE2R_ENUM 9
216 #define ADC_HPF_ENUM 10
217
218 static const struct soc_enum aic3x_enum[] = {
219 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
220 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
221 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
222 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
223 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
224 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
225 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
226 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
227 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
229 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
230 };
231
232 /*
233 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
234 */
235 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
236 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
237 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
238 /*
239 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
240 * Step size is approximately 0.5 dB over most of the scale but increasing
241 * near the very low levels.
242 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
243 * but having increasing dB difference below that (and where it doesn't count
244 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
245 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
246 */
247 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
248
249 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
250 /* Output */
251 SOC_DOUBLE_R_TLV("PCM Playback Volume",
252 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
253
254 /*
255 * Output controls that map to output mixer switches. Note these are
256 * only for swapped L-to-R and R-to-L routes. See below stereo controls
257 * for direct L-to-L and R-to-R routes.
258 */
259 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
260 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
261 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
262 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
263 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
264 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
265
266 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
267 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
268 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
269 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
270 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
271 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
272
273 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
274 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
276 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
278 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
279
280 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
281 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
283 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
285 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
286
287 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
288 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
290 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
292 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
293
294 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
295 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
297 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
299 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
300
301 /* Stereo output controls for direct L-to-L and R-to-R routes */
302 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
303 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
304 0, 118, 1, output_stage_tlv),
305 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
306 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
307 0, 118, 1, output_stage_tlv),
308 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
309 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
310 0, 118, 1, output_stage_tlv),
311
312 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
313 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
314 0, 118, 1, output_stage_tlv),
315 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
316 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
317 0, 118, 1, output_stage_tlv),
318 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
319 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
320 0, 118, 1, output_stage_tlv),
321
322 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
323 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
324 0, 118, 1, output_stage_tlv),
325 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
326 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
327 0, 118, 1, output_stage_tlv),
328 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
329 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
330 0, 118, 1, output_stage_tlv),
331
332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
334 0, 118, 1, output_stage_tlv),
335 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
336 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
337 0, 118, 1, output_stage_tlv),
338 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
339 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
340 0, 118, 1, output_stage_tlv),
341
342 /* Output pin mute controls */
343 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
344 0x01, 0),
345 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
346 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
347 0x01, 0),
348 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
349 0x01, 0),
350
351 /*
352 * Note: enable Automatic input Gain Controller with care. It can
353 * adjust PGA to max value when ADC is on and will never go back.
354 */
355 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
356
357 /* Input */
358 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
359 0, 119, 0, adc_tlv),
360 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
361
362 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
363 };
364
365 /*
366 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
367 */
368 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
369
370 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
371 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
372
373 /* Left DAC Mux */
374 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
375 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
376
377 /* Right DAC Mux */
378 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
379 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
380
381 /* Left HPCOM Mux */
382 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
383 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
384
385 /* Right HPCOM Mux */
386 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
387 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
388
389 /* Left Line Mixer */
390 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
391 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
397 };
398
399 /* Right Line Mixer */
400 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
401 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
402 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
407 };
408
409 /* Mono Mixer */
410 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
411 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
417 };
418
419 /* Left HP Mixer */
420 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
427 };
428
429 /* Right HP Mixer */
430 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
437 };
438
439 /* Left HPCOM Mixer */
440 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
447 };
448
449 /* Right HPCOM Mixer */
450 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
457 };
458
459 /* Left PGA Mixer */
460 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
461 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
462 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
463 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
464 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
465 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
466 };
467
468 /* Right PGA Mixer */
469 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
470 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
471 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
472 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
473 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
474 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
475 };
476
477 /* Left Line1 Mux */
478 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
479 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
480 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
481 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
482
483 /* Right Line1 Mux */
484 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
485 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
486 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
487 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
488
489 /* Left Line2 Mux */
490 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
491 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
492
493 /* Right Line2 Mux */
494 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
495 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
496
497 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
498 /* Left DAC to Left Outputs */
499 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
500 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
501 &aic3x_left_dac_mux_controls),
502 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
503 &aic3x_left_hpcom_mux_controls),
504 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
505 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
506 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
507
508 /* Right DAC to Right Outputs */
509 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
510 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
511 &aic3x_right_dac_mux_controls),
512 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
513 &aic3x_right_hpcom_mux_controls),
514 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
517
518 /* Mono Output */
519 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
520
521 /* Inputs to Left ADC */
522 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
523 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
524 &aic3x_left_pga_mixer_controls[0],
525 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
526 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
527 &aic3x_left_line1l_mux_controls),
528 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
529 &aic3x_left_line1r_mux_controls),
530 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
531 &aic3x_left_line2_mux_controls),
532
533 /* Inputs to Right ADC */
534 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
535 LINE1R_2_RADC_CTRL, 2, 0),
536 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
537 &aic3x_right_pga_mixer_controls[0],
538 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
539 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_right_line1l_mux_controls),
541 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
542 &aic3x_right_line1r_mux_controls),
543 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
544 &aic3x_right_line2_mux_controls),
545
546 /*
547 * Not a real mic bias widget but similar function. This is for dynamic
548 * control of GPIO1 digital mic modulator clock output function when
549 * using digital mic.
550 */
551 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
552 AIC3X_GPIO1_REG, 4, 0xf,
553 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
554 AIC3X_GPIO1_FUNC_DISABLED),
555
556 /*
557 * Also similar function like mic bias. Selects digital mic with
558 * configurable oversampling rate instead of ADC converter.
559 */
560 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
561 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
562 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
563 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
565 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
566
567 /* Mic Bias */
568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
569 MICBIAS_CTRL, 6, 3, 1, 0),
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
571 MICBIAS_CTRL, 6, 3, 2, 0),
572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
573 MICBIAS_CTRL, 6, 3, 3, 0),
574
575 /* Output mixers */
576 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
577 &aic3x_left_line_mixer_controls[0],
578 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
579 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
580 &aic3x_right_line_mixer_controls[0],
581 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
582 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
583 &aic3x_mono_mixer_controls[0],
584 ARRAY_SIZE(aic3x_mono_mixer_controls)),
585 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
586 &aic3x_left_hp_mixer_controls[0],
587 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
588 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
589 &aic3x_right_hp_mixer_controls[0],
590 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
591 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
592 &aic3x_left_hpcom_mixer_controls[0],
593 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
594 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
595 &aic3x_right_hpcom_mixer_controls[0],
596 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
597
598 SND_SOC_DAPM_OUTPUT("LLOUT"),
599 SND_SOC_DAPM_OUTPUT("RLOUT"),
600 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
601 SND_SOC_DAPM_OUTPUT("HPLOUT"),
602 SND_SOC_DAPM_OUTPUT("HPROUT"),
603 SND_SOC_DAPM_OUTPUT("HPLCOM"),
604 SND_SOC_DAPM_OUTPUT("HPRCOM"),
605
606 SND_SOC_DAPM_INPUT("MIC3L"),
607 SND_SOC_DAPM_INPUT("MIC3R"),
608 SND_SOC_DAPM_INPUT("LINE1L"),
609 SND_SOC_DAPM_INPUT("LINE1R"),
610 SND_SOC_DAPM_INPUT("LINE2L"),
611 SND_SOC_DAPM_INPUT("LINE2R"),
612
613 /*
614 * Virtual output pin to detection block inside codec. This can be
615 * used to keep codec bias on if gpio or detection features are needed.
616 * Force pin on or construct a path with an input jack and mic bias
617 * widgets.
618 */
619 SND_SOC_DAPM_OUTPUT("Detection"),
620 };
621
622 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
623 /* Class-D outputs */
624 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
625 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
626
627 SND_SOC_DAPM_OUTPUT("SPOP"),
628 SND_SOC_DAPM_OUTPUT("SPOM"),
629 };
630
631 static const struct snd_soc_dapm_route intercon[] = {
632 /* Left Input */
633 {"Left Line1L Mux", "single-ended", "LINE1L"},
634 {"Left Line1L Mux", "differential", "LINE1L"},
635
636 {"Left Line2L Mux", "single-ended", "LINE2L"},
637 {"Left Line2L Mux", "differential", "LINE2L"},
638
639 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
640 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
641 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
642 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
643 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
644
645 {"Left ADC", NULL, "Left PGA Mixer"},
646 {"Left ADC", NULL, "GPIO1 dmic modclk"},
647
648 /* Right Input */
649 {"Right Line1R Mux", "single-ended", "LINE1R"},
650 {"Right Line1R Mux", "differential", "LINE1R"},
651
652 {"Right Line2R Mux", "single-ended", "LINE2R"},
653 {"Right Line2R Mux", "differential", "LINE2R"},
654
655 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
656 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
657 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
658 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
659 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
660
661 {"Right ADC", NULL, "Right PGA Mixer"},
662 {"Right ADC", NULL, "GPIO1 dmic modclk"},
663
664 /*
665 * Logical path between digital mic enable and GPIO1 modulator clock
666 * output function
667 */
668 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
669 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
670 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
671
672 /* Left DAC Output */
673 {"Left DAC Mux", "DAC_L1", "Left DAC"},
674 {"Left DAC Mux", "DAC_L2", "Left DAC"},
675 {"Left DAC Mux", "DAC_L3", "Left DAC"},
676
677 /* Right DAC Output */
678 {"Right DAC Mux", "DAC_R1", "Right DAC"},
679 {"Right DAC Mux", "DAC_R2", "Right DAC"},
680 {"Right DAC Mux", "DAC_R3", "Right DAC"},
681
682 /* Left Line Output */
683 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
684 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
685 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
686 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
687 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
688 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
689
690 {"Left Line Out", NULL, "Left Line Mixer"},
691 {"Left Line Out", NULL, "Left DAC Mux"},
692 {"LLOUT", NULL, "Left Line Out"},
693
694 /* Right Line Output */
695 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
696 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
697 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
698 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
699 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
700 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
701
702 {"Right Line Out", NULL, "Right Line Mixer"},
703 {"Right Line Out", NULL, "Right DAC Mux"},
704 {"RLOUT", NULL, "Right Line Out"},
705
706 /* Mono Output */
707 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
708 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
709 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
710 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
711 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
712 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
713
714 {"Mono Out", NULL, "Mono Mixer"},
715 {"MONO_LOUT", NULL, "Mono Out"},
716
717 /* Left HP Output */
718 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
719 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
720 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
721 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
722 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
723 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
724
725 {"Left HP Out", NULL, "Left HP Mixer"},
726 {"Left HP Out", NULL, "Left DAC Mux"},
727 {"HPLOUT", NULL, "Left HP Out"},
728
729 /* Right HP Output */
730 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
731 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
732 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
733 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
734 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
735 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
736
737 {"Right HP Out", NULL, "Right HP Mixer"},
738 {"Right HP Out", NULL, "Right DAC Mux"},
739 {"HPROUT", NULL, "Right HP Out"},
740
741 /* Left HPCOM Output */
742 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
743 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
744 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
745 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
746 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
747 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
748
749 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
750 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
751 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
752 {"Left HP Com", NULL, "Left HPCOM Mux"},
753 {"HPLCOM", NULL, "Left HP Com"},
754
755 /* Right HPCOM Output */
756 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
757 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
758 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
759 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
760 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
761 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
762
763 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
764 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
765 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
766 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
767 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
768 {"Right HP Com", NULL, "Right HPCOM Mux"},
769 {"HPRCOM", NULL, "Right HP Com"},
770 };
771
772 static const struct snd_soc_dapm_route intercon_3007[] = {
773 /* Class-D outputs */
774 {"Left Class-D Out", NULL, "Left Line Out"},
775 {"Right Class-D Out", NULL, "Left Line Out"},
776 {"SPOP", NULL, "Left Class-D Out"},
777 {"SPOM", NULL, "Right Class-D Out"},
778 };
779
780 static int aic3x_add_widgets(struct snd_soc_codec *codec)
781 {
782 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
783 struct snd_soc_dapm_context *dapm = &codec->dapm;
784
785 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
786 ARRAY_SIZE(aic3x_dapm_widgets));
787
788 /* set up audio path interconnects */
789 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
790
791 if (aic3x->model == AIC3X_MODEL_3007) {
792 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
793 ARRAY_SIZE(aic3007_dapm_widgets));
794 snd_soc_dapm_add_routes(dapm, intercon_3007,
795 ARRAY_SIZE(intercon_3007));
796 }
797
798 return 0;
799 }
800
801 static int aic3x_hw_params(struct snd_pcm_substream *substream,
802 struct snd_pcm_hw_params *params,
803 struct snd_soc_dai *dai)
804 {
805 struct snd_soc_codec *codec = dai->codec;
806 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
807 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
808 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
809 u16 d, pll_d = 1;
810 int clk;
811
812 /* select data word length */
813 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
814 switch (params_format(params)) {
815 case SNDRV_PCM_FORMAT_S16_LE:
816 break;
817 case SNDRV_PCM_FORMAT_S20_3LE:
818 data |= (0x01 << 4);
819 break;
820 case SNDRV_PCM_FORMAT_S24_LE:
821 data |= (0x02 << 4);
822 break;
823 case SNDRV_PCM_FORMAT_S32_LE:
824 data |= (0x03 << 4);
825 break;
826 }
827 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
828
829 /* Fsref can be 44100 or 48000 */
830 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
831
832 /* Try to find a value for Q which allows us to bypass the PLL and
833 * generate CODEC_CLK directly. */
834 for (pll_q = 2; pll_q < 18; pll_q++)
835 if (aic3x->sysclk / (128 * pll_q) == fsref) {
836 bypass_pll = 1;
837 break;
838 }
839
840 if (bypass_pll) {
841 pll_q &= 0xf;
842 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
843 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
844 /* disable PLL if it is bypassed */
845 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
846
847 } else {
848 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
849 /* enable PLL when it is used */
850 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
851 PLL_ENABLE, PLL_ENABLE);
852 }
853
854 /* Route Left DAC to left channel input and
855 * right DAC to right channel input */
856 data = (LDAC2LCH | RDAC2RCH);
857 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
858 if (params_rate(params) >= 64000)
859 data |= DUAL_RATE_MODE;
860 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
861
862 /* codec sample rate select */
863 data = (fsref * 20) / params_rate(params);
864 if (params_rate(params) < 64000)
865 data /= 2;
866 data /= 5;
867 data -= 2;
868 data |= (data << 4);
869 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
870
871 if (bypass_pll)
872 return 0;
873
874 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
875 * one wins the game. Try with d==0 first, next with d!=0.
876 * Constraints for j are according to the datasheet.
877 * The sysclk is divided by 1000 to prevent integer overflows.
878 */
879
880 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
881
882 for (r = 1; r <= 16; r++)
883 for (p = 1; p <= 8; p++) {
884 for (j = 4; j <= 55; j++) {
885 /* This is actually 1000*((j+(d/10000))*r)/p
886 * The term had to be converted to get
887 * rid of the division by 10000; d = 0 here
888 */
889 int tmp_clk = (1000 * j * r) / p;
890
891 /* Check whether this values get closer than
892 * the best ones we had before
893 */
894 if (abs(codec_clk - tmp_clk) <
895 abs(codec_clk - last_clk)) {
896 pll_j = j; pll_d = 0;
897 pll_r = r; pll_p = p;
898 last_clk = tmp_clk;
899 }
900
901 /* Early exit for exact matches */
902 if (tmp_clk == codec_clk)
903 goto found;
904 }
905 }
906
907 /* try with d != 0 */
908 for (p = 1; p <= 8; p++) {
909 j = codec_clk * p / 1000;
910
911 if (j < 4 || j > 11)
912 continue;
913
914 /* do not use codec_clk here since we'd loose precision */
915 d = ((2048 * p * fsref) - j * aic3x->sysclk)
916 * 100 / (aic3x->sysclk/100);
917
918 clk = (10000 * j + d) / (10 * p);
919
920 /* check whether this values get closer than the best
921 * ones we had before */
922 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
923 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
924 last_clk = clk;
925 }
926
927 /* Early exit for exact matches */
928 if (clk == codec_clk)
929 goto found;
930 }
931
932 if (last_clk == 0) {
933 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
934 return -EINVAL;
935 }
936
937 found:
938 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
939 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
940 pll_r << PLLR_SHIFT);
941 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
942 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
943 (pll_d >> 6) << PLLD_MSB_SHIFT);
944 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
945 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
946
947 return 0;
948 }
949
950 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
951 {
952 struct snd_soc_codec *codec = dai->codec;
953 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
954 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
955
956 if (mute) {
957 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
958 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
959 } else {
960 snd_soc_write(codec, LDAC_VOL, ldac_reg);
961 snd_soc_write(codec, RDAC_VOL, rdac_reg);
962 }
963
964 return 0;
965 }
966
967 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
968 int clk_id, unsigned int freq, int dir)
969 {
970 struct snd_soc_codec *codec = codec_dai->codec;
971 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
972
973 aic3x->sysclk = freq;
974 return 0;
975 }
976
977 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
978 unsigned int fmt)
979 {
980 struct snd_soc_codec *codec = codec_dai->codec;
981 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
982 u8 iface_areg, iface_breg;
983 int delay = 0;
984
985 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
986 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
987
988 /* set master/slave audio interface */
989 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
990 case SND_SOC_DAIFMT_CBM_CFM:
991 aic3x->master = 1;
992 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
993 break;
994 case SND_SOC_DAIFMT_CBS_CFS:
995 aic3x->master = 0;
996 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
997 break;
998 default:
999 return -EINVAL;
1000 }
1001
1002 /*
1003 * match both interface format and signal polarities since they
1004 * are fixed
1005 */
1006 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1007 SND_SOC_DAIFMT_INV_MASK)) {
1008 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1009 break;
1010 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1011 delay = 1;
1012 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1013 iface_breg |= (0x01 << 6);
1014 break;
1015 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1016 iface_breg |= (0x02 << 6);
1017 break;
1018 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1019 iface_breg |= (0x03 << 6);
1020 break;
1021 default:
1022 return -EINVAL;
1023 }
1024
1025 /* set iface */
1026 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1027 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1028 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1029
1030 return 0;
1031 }
1032
1033 static int aic3x_init_3007(struct snd_soc_codec *codec)
1034 {
1035 u8 tmp1, tmp2, *cache = codec->reg_cache;
1036
1037 /*
1038 * There is no need to cache writes to undocumented page 0xD but
1039 * respective page 0 register cache entries must be preserved
1040 */
1041 tmp1 = cache[0xD];
1042 tmp2 = cache[0x8];
1043 /* Class-D speaker driver init; datasheet p. 46 */
1044 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1045 snd_soc_write(codec, 0xD, 0x0D);
1046 snd_soc_write(codec, 0x8, 0x5C);
1047 snd_soc_write(codec, 0x8, 0x5D);
1048 snd_soc_write(codec, 0x8, 0x5C);
1049 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1050 cache[0xD] = tmp1;
1051 cache[0x8] = tmp2;
1052
1053 return 0;
1054 }
1055
1056 static int aic3x_regulator_event(struct notifier_block *nb,
1057 unsigned long event, void *data)
1058 {
1059 struct aic3x_disable_nb *disable_nb =
1060 container_of(nb, struct aic3x_disable_nb, nb);
1061 struct aic3x_priv *aic3x = disable_nb->aic3x;
1062
1063 if (event & REGULATOR_EVENT_DISABLE) {
1064 /*
1065 * Put codec to reset and require cache sync as at least one
1066 * of the supplies was disabled
1067 */
1068 if (gpio_is_valid(aic3x->gpio_reset))
1069 gpio_set_value(aic3x->gpio_reset, 0);
1070 aic3x->codec->cache_sync = 1;
1071 }
1072
1073 return 0;
1074 }
1075
1076 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1077 {
1078 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1079 int i, ret;
1080 u8 *cache = codec->reg_cache;
1081
1082 if (power) {
1083 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1084 aic3x->supplies);
1085 if (ret)
1086 goto out;
1087 aic3x->power = 1;
1088 /*
1089 * Reset release and cache sync is necessary only if some
1090 * supply was off or if there were cached writes
1091 */
1092 if (!codec->cache_sync)
1093 goto out;
1094
1095 if (gpio_is_valid(aic3x->gpio_reset)) {
1096 udelay(1);
1097 gpio_set_value(aic3x->gpio_reset, 1);
1098 }
1099
1100 /* Sync reg_cache with the hardware */
1101 codec->cache_only = 0;
1102 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
1103 snd_soc_write(codec, i, cache[i]);
1104 if (aic3x->model == AIC3X_MODEL_3007)
1105 aic3x_init_3007(codec);
1106 codec->cache_sync = 0;
1107 } else {
1108 /*
1109 * Do soft reset to this codec instance in order to clear
1110 * possible VDD leakage currents in case the supply regulators
1111 * remain on
1112 */
1113 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1114 codec->cache_sync = 1;
1115 aic3x->power = 0;
1116 /* HW writes are needless when bias is off */
1117 codec->cache_only = 1;
1118 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1119 aic3x->supplies);
1120 }
1121 out:
1122 return ret;
1123 }
1124
1125 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1126 enum snd_soc_bias_level level)
1127 {
1128 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1129
1130 switch (level) {
1131 case SND_SOC_BIAS_ON:
1132 break;
1133 case SND_SOC_BIAS_PREPARE:
1134 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1135 aic3x->master) {
1136 /* enable pll */
1137 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1138 PLL_ENABLE, PLL_ENABLE);
1139 }
1140 break;
1141 case SND_SOC_BIAS_STANDBY:
1142 if (!aic3x->power)
1143 aic3x_set_power(codec, 1);
1144 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1145 aic3x->master) {
1146 /* disable pll */
1147 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1148 PLL_ENABLE, 0);
1149 }
1150 break;
1151 case SND_SOC_BIAS_OFF:
1152 if (aic3x->power)
1153 aic3x_set_power(codec, 0);
1154 break;
1155 }
1156 codec->dapm.bias_level = level;
1157
1158 return 0;
1159 }
1160
1161 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1162 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1163 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1164
1165 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1166 .hw_params = aic3x_hw_params,
1167 .digital_mute = aic3x_mute,
1168 .set_sysclk = aic3x_set_dai_sysclk,
1169 .set_fmt = aic3x_set_dai_fmt,
1170 };
1171
1172 static struct snd_soc_dai_driver aic3x_dai = {
1173 .name = "tlv320aic3x-hifi",
1174 .playback = {
1175 .stream_name = "Playback",
1176 .channels_min = 1,
1177 .channels_max = 2,
1178 .rates = AIC3X_RATES,
1179 .formats = AIC3X_FORMATS,},
1180 .capture = {
1181 .stream_name = "Capture",
1182 .channels_min = 1,
1183 .channels_max = 2,
1184 .rates = AIC3X_RATES,
1185 .formats = AIC3X_FORMATS,},
1186 .ops = &aic3x_dai_ops,
1187 .symmetric_rates = 1,
1188 };
1189
1190 static int aic3x_suspend(struct snd_soc_codec *codec)
1191 {
1192 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1193
1194 return 0;
1195 }
1196
1197 static int aic3x_resume(struct snd_soc_codec *codec)
1198 {
1199 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1200
1201 return 0;
1202 }
1203
1204 /*
1205 * initialise the AIC3X driver
1206 * register the mixer and dsp interfaces with the kernel
1207 */
1208 static int aic3x_init(struct snd_soc_codec *codec)
1209 {
1210 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1211
1212 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1213 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1214
1215 /* DAC default volume and mute */
1216 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1217 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1218
1219 /* DAC to HP default volume and route to Output mixer */
1220 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1221 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1222 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1223 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1224 /* DAC to Line Out default volume and route to Output mixer */
1225 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1226 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1227 /* DAC to Mono Line Out default volume and route to Output mixer */
1228 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1229 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1230
1231 /* unmute all outputs */
1232 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1233 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1234 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1235 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1236 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1237 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1238 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1239
1240 /* ADC default volume and unmute */
1241 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1242 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1243 /* By default route Line1 to ADC PGA mixer */
1244 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1245 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1246
1247 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1248 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1249 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1250 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1251 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1252 /* PGA to Line Out default volume, disconnect from Output Mixer */
1253 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1254 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1255 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1256 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1257 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1258
1259 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1260 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1261 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1262 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1263 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1264 /* Line2 Line Out default volume, disconnect from Output Mixer */
1265 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1266 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1267 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1268 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1269 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1270
1271 if (aic3x->model == AIC3X_MODEL_3007) {
1272 aic3x_init_3007(codec);
1273 snd_soc_write(codec, CLASSD_CTRL, 0);
1274 }
1275
1276 return 0;
1277 }
1278
1279 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1280 {
1281 struct aic3x_priv *a;
1282
1283 list_for_each_entry(a, &reset_list, list) {
1284 if (gpio_is_valid(aic3x->gpio_reset) &&
1285 aic3x->gpio_reset == a->gpio_reset)
1286 return true;
1287 }
1288
1289 return false;
1290 }
1291
1292 static int aic3x_probe(struct snd_soc_codec *codec)
1293 {
1294 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1295 int ret, i;
1296
1297 INIT_LIST_HEAD(&aic3x->list);
1298 aic3x->codec = codec;
1299
1300 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1301 if (ret != 0) {
1302 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1303 return ret;
1304 }
1305
1306 if (gpio_is_valid(aic3x->gpio_reset) &&
1307 !aic3x_is_shared_reset(aic3x)) {
1308 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1309 if (ret != 0)
1310 goto err_gpio;
1311 gpio_direction_output(aic3x->gpio_reset, 0);
1312 }
1313
1314 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1315 aic3x->supplies[i].supply = aic3x_supply_names[i];
1316
1317 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1318 aic3x->supplies);
1319 if (ret != 0) {
1320 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1321 goto err_get;
1322 }
1323 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1324 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1325 aic3x->disable_nb[i].aic3x = aic3x;
1326 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1327 &aic3x->disable_nb[i].nb);
1328 if (ret) {
1329 dev_err(codec->dev,
1330 "Failed to request regulator notifier: %d\n",
1331 ret);
1332 goto err_notif;
1333 }
1334 }
1335
1336 codec->cache_only = 1;
1337 aic3x_init(codec);
1338
1339 if (aic3x->setup) {
1340 /* setup GPIO functions */
1341 snd_soc_write(codec, AIC3X_GPIO1_REG,
1342 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1343 snd_soc_write(codec, AIC3X_GPIO2_REG,
1344 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1345 }
1346
1347 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
1348 ARRAY_SIZE(aic3x_snd_controls));
1349 if (aic3x->model == AIC3X_MODEL_3007)
1350 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1351
1352 aic3x_add_widgets(codec);
1353 list_add(&aic3x->list, &reset_list);
1354
1355 return 0;
1356
1357 err_notif:
1358 while (i--)
1359 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1360 &aic3x->disable_nb[i].nb);
1361 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1362 err_get:
1363 if (gpio_is_valid(aic3x->gpio_reset) &&
1364 !aic3x_is_shared_reset(aic3x))
1365 gpio_free(aic3x->gpio_reset);
1366 err_gpio:
1367 return ret;
1368 }
1369
1370 static int aic3x_remove(struct snd_soc_codec *codec)
1371 {
1372 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1373 int i;
1374
1375 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1376 list_del(&aic3x->list);
1377 if (gpio_is_valid(aic3x->gpio_reset) &&
1378 !aic3x_is_shared_reset(aic3x)) {
1379 gpio_set_value(aic3x->gpio_reset, 0);
1380 gpio_free(aic3x->gpio_reset);
1381 }
1382 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1383 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1384 &aic3x->disable_nb[i].nb);
1385 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1386
1387 return 0;
1388 }
1389
1390 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1391 .set_bias_level = aic3x_set_bias_level,
1392 .idle_bias_off = true,
1393 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1394 .reg_word_size = sizeof(u8),
1395 .reg_cache_default = aic3x_reg,
1396 .probe = aic3x_probe,
1397 .remove = aic3x_remove,
1398 .suspend = aic3x_suspend,
1399 .resume = aic3x_resume,
1400 };
1401
1402 /*
1403 * AIC3X 2 wire address can be up to 4 devices with device addresses
1404 * 0x18, 0x19, 0x1A, 0x1B
1405 */
1406
1407 static const struct i2c_device_id aic3x_i2c_id[] = {
1408 { "tlv320aic3x", AIC3X_MODEL_3X },
1409 { "tlv320aic33", AIC3X_MODEL_33 },
1410 { "tlv320aic3007", AIC3X_MODEL_3007 },
1411 { }
1412 };
1413 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1414
1415 /*
1416 * If the i2c layer weren't so broken, we could pass this kind of data
1417 * around
1418 */
1419 static int aic3x_i2c_probe(struct i2c_client *i2c,
1420 const struct i2c_device_id *id)
1421 {
1422 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1423 struct aic3x_priv *aic3x;
1424 int ret;
1425
1426 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1427 if (aic3x == NULL) {
1428 dev_err(&i2c->dev, "failed to create private data\n");
1429 return -ENOMEM;
1430 }
1431
1432 aic3x->control_type = SND_SOC_I2C;
1433
1434 i2c_set_clientdata(i2c, aic3x);
1435 if (pdata) {
1436 aic3x->gpio_reset = pdata->gpio_reset;
1437 aic3x->setup = pdata->setup;
1438 } else {
1439 aic3x->gpio_reset = -1;
1440 }
1441
1442 aic3x->model = id->driver_data;
1443
1444 ret = snd_soc_register_codec(&i2c->dev,
1445 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1446 return ret;
1447 }
1448
1449 static int aic3x_i2c_remove(struct i2c_client *client)
1450 {
1451 snd_soc_unregister_codec(&client->dev);
1452 return 0;
1453 }
1454
1455 /* machine i2c codec control layer */
1456 static struct i2c_driver aic3x_i2c_driver = {
1457 .driver = {
1458 .name = "tlv320aic3x-codec",
1459 .owner = THIS_MODULE,
1460 },
1461 .probe = aic3x_i2c_probe,
1462 .remove = aic3x_i2c_remove,
1463 .id_table = aic3x_i2c_id,
1464 };
1465
1466 static int __init aic3x_modinit(void)
1467 {
1468 int ret = 0;
1469 ret = i2c_add_driver(&aic3x_i2c_driver);
1470 if (ret != 0) {
1471 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1472 ret);
1473 }
1474 return ret;
1475 }
1476 module_init(aic3x_modinit);
1477
1478 static void __exit aic3x_exit(void)
1479 {
1480 i2c_del_driver(&aic3x_i2c_driver);
1481 }
1482 module_exit(aic3x_exit);
1483
1484 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1485 MODULE_AUTHOR("Vladimir Barinov");
1486 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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