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ASoC: tlv320aic3x: Add TDM support
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/of.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 static LIST_HEAD(reset_list);
65
66 struct aic3x_priv;
67
68 struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71 };
72
73 /* codec private data */
74 struct aic3x_priv {
75 struct snd_soc_codec *codec;
76 struct regmap *regmap;
77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
79 struct aic3x_setup_data *setup;
80 unsigned int sysclk;
81 unsigned int dai_fmt;
82 unsigned int tdm_delay;
83 struct list_head list;
84 int master;
85 int gpio_reset;
86 int power;
87 #define AIC3X_MODEL_3X 0
88 #define AIC3X_MODEL_33 1
89 #define AIC3X_MODEL_3007 2
90 u16 model;
91
92 /* Selects the micbias voltage */
93 enum aic3x_micbias_voltage micbias_vg;
94 };
95
96 static const struct reg_default aic3x_reg[] = {
97 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
98 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
99 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
100 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
101 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
102 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
103 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
104 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
105 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
106 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
107 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
108 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
109 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
110 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
111 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
112 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
113 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
114 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
115 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
116 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
117 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
118 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
119 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
120 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
121 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
122 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
123 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
124 { 108, 0x00 }, { 109, 0x00 },
125 };
126
127 static const struct regmap_config aic3x_regmap = {
128 .reg_bits = 8,
129 .val_bits = 8,
130
131 .max_register = DAC_ICC_ADJ,
132 .reg_defaults = aic3x_reg,
133 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
134 .cache_type = REGCACHE_RBTREE,
135 };
136
137 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
138 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
139 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
140
141 /*
142 * All input lines are connected when !0xf and disconnected with 0xf bit field,
143 * so we have to use specific dapm_put call for input mixer
144 */
145 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
146 struct snd_ctl_elem_value *ucontrol)
147 {
148 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
149 struct soc_mixer_control *mc =
150 (struct soc_mixer_control *)kcontrol->private_value;
151 unsigned int reg = mc->reg;
152 unsigned int shift = mc->shift;
153 int max = mc->max;
154 unsigned int mask = (1 << fls(max)) - 1;
155 unsigned int invert = mc->invert;
156 unsigned short val;
157 struct snd_soc_dapm_update update;
158 int connect, change;
159
160 val = (ucontrol->value.integer.value[0] & mask);
161
162 mask = 0xf;
163 if (val)
164 val = mask;
165
166 connect = !!val;
167
168 if (invert)
169 val = mask - val;
170
171 mask <<= shift;
172 val <<= shift;
173
174 change = snd_soc_test_bits(codec, reg, mask, val);
175 if (change) {
176 update.kcontrol = kcontrol;
177 update.reg = reg;
178 update.mask = mask;
179 update.val = val;
180
181 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
182 &update);
183 }
184
185 return change;
186 }
187
188 /*
189 * mic bias power on/off share the same register bits with
190 * output voltage of mic bias. when power on mic bias, we
191 * need reclaim it to voltage value.
192 * 0x0 = Powered off
193 * 0x1 = MICBIAS output is powered to 2.0V,
194 * 0x2 = MICBIAS output is powered to 2.5V
195 * 0x3 = MICBIAS output is connected to AVDD
196 */
197 static int mic_bias_event(struct snd_soc_dapm_widget *w,
198 struct snd_kcontrol *kcontrol, int event)
199 {
200 struct snd_soc_codec *codec = w->codec;
201 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
202
203 switch (event) {
204 case SND_SOC_DAPM_POST_PMU:
205 /* change mic bias voltage to user defined */
206 snd_soc_update_bits(codec, MICBIAS_CTRL,
207 MICBIAS_LEVEL_MASK,
208 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
209 break;
210
211 case SND_SOC_DAPM_PRE_PMD:
212 snd_soc_update_bits(codec, MICBIAS_CTRL,
213 MICBIAS_LEVEL_MASK, 0);
214 break;
215 }
216 return 0;
217 }
218
219 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
220 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
221 static const char *aic3x_left_hpcom_mux[] =
222 { "differential of HPLOUT", "constant VCM", "single-ended" };
223 static const char *aic3x_right_hpcom_mux[] =
224 { "differential of HPROUT", "constant VCM", "single-ended",
225 "differential of HPLCOM", "external feedback" };
226 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
227 static const char *aic3x_adc_hpf[] =
228 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
229
230 #define LDAC_ENUM 0
231 #define RDAC_ENUM 1
232 #define LHPCOM_ENUM 2
233 #define RHPCOM_ENUM 3
234 #define LINE1L_2_L_ENUM 4
235 #define LINE1L_2_R_ENUM 5
236 #define LINE1R_2_L_ENUM 6
237 #define LINE1R_2_R_ENUM 7
238 #define LINE2L_ENUM 8
239 #define LINE2R_ENUM 9
240 #define ADC_HPF_ENUM 10
241
242 static const struct soc_enum aic3x_enum[] = {
243 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
245 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
246 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
247 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
252 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
253 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
254 };
255
256 static const char *aic3x_agc_level[] =
257 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
258 static const struct soc_enum aic3x_agc_level_enum[] = {
259 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
260 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
261 };
262
263 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
264 static const struct soc_enum aic3x_agc_attack_enum[] = {
265 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
266 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
267 };
268
269 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
270 static const struct soc_enum aic3x_agc_decay_enum[] = {
271 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
272 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
273 };
274
275 /*
276 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
277 */
278 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
279 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
280 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
281 /*
282 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
283 * Step size is approximately 0.5 dB over most of the scale but increasing
284 * near the very low levels.
285 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
286 * but having increasing dB difference below that (and where it doesn't count
287 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
288 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
289 */
290 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
291
292 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
293 /* Output */
294 SOC_DOUBLE_R_TLV("PCM Playback Volume",
295 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
296
297 /*
298 * Output controls that map to output mixer switches. Note these are
299 * only for swapped L-to-R and R-to-L routes. See below stereo controls
300 * for direct L-to-L and R-to-R routes.
301 */
302 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
303 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
305 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
307 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
308
309 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
310 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
312 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
314 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
315
316 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
317 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
319 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
321 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
322
323 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
324 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
326 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
328 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
329
330 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
331 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
333 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
335 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
336
337 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
338 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
340 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
342 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
343
344 /* Stereo output controls for direct L-to-L and R-to-R routes */
345 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
346 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
347 0, 118, 1, output_stage_tlv),
348 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
349 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
350 0, 118, 1, output_stage_tlv),
351 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
352 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
353 0, 118, 1, output_stage_tlv),
354
355 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
356 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
357 0, 118, 1, output_stage_tlv),
358 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
359 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
360 0, 118, 1, output_stage_tlv),
361 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
362 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
363 0, 118, 1, output_stage_tlv),
364
365 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
366 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
367 0, 118, 1, output_stage_tlv),
368 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
369 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
370 0, 118, 1, output_stage_tlv),
371 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
372 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
373 0, 118, 1, output_stage_tlv),
374
375 /* Output pin mute controls */
376 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
377 0x01, 0),
378 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
379 0x01, 0),
380 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
381 0x01, 0),
382
383 /*
384 * Note: enable Automatic input Gain Controller with care. It can
385 * adjust PGA to max value when ADC is on and will never go back.
386 */
387 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
388 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
389 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
390 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
391 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
392 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
393 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
394
395 /* De-emphasis */
396 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
397
398 /* Input */
399 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
400 0, 119, 0, adc_tlv),
401 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
402
403 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
404 };
405
406 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
407 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
408 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
409 0, 118, 1, output_stage_tlv),
410 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
411 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
412 0, 118, 1, output_stage_tlv),
413 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
414 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
415 0, 118, 1, output_stage_tlv),
416
417 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
418 };
419
420 /*
421 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
422 */
423 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
424
425 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
426 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
427
428 /* Left DAC Mux */
429 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
430 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
431
432 /* Right DAC Mux */
433 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
434 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
435
436 /* Left HPCOM Mux */
437 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
438 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
439
440 /* Right HPCOM Mux */
441 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
442 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
443
444 /* Left Line Mixer */
445 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
452 };
453
454 /* Right Line Mixer */
455 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
462 };
463
464 /* Mono Mixer */
465 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
472 };
473
474 /* Left HP Mixer */
475 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
482 };
483
484 /* Right HP Mixer */
485 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
486 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
492 };
493
494 /* Left HPCOM Mixer */
495 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
496 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
502 };
503
504 /* Right HPCOM Mixer */
505 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
506 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
510 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
512 };
513
514 /* Left PGA Mixer */
515 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
516 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
517 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
518 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
519 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
520 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
521 };
522
523 /* Right PGA Mixer */
524 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
525 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
526 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
527 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
528 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
529 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
530 };
531
532 /* Left Line1 Mux */
533 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
534 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
535 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
536 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
537
538 /* Right Line1 Mux */
539 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
540 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
541 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
542 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
543
544 /* Left Line2 Mux */
545 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
546 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
547
548 /* Right Line2 Mux */
549 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
550 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
551
552 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
553 /* Left DAC to Left Outputs */
554 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
555 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
556 &aic3x_left_dac_mux_controls),
557 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
558 &aic3x_left_hpcom_mux_controls),
559 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
560 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
561 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
562
563 /* Right DAC to Right Outputs */
564 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
565 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_right_dac_mux_controls),
567 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
568 &aic3x_right_hpcom_mux_controls),
569 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
570 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
571 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
572
573 /* Inputs to Left ADC */
574 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
575 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
576 &aic3x_left_pga_mixer_controls[0],
577 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
578 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_left_line1l_mux_controls),
580 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
581 &aic3x_left_line1r_mux_controls),
582 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
583 &aic3x_left_line2_mux_controls),
584
585 /* Inputs to Right ADC */
586 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
587 LINE1R_2_RADC_CTRL, 2, 0),
588 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
589 &aic3x_right_pga_mixer_controls[0],
590 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
591 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
592 &aic3x_right_line1l_mux_controls),
593 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
594 &aic3x_right_line1r_mux_controls),
595 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
596 &aic3x_right_line2_mux_controls),
597
598 /*
599 * Not a real mic bias widget but similar function. This is for dynamic
600 * control of GPIO1 digital mic modulator clock output function when
601 * using digital mic.
602 */
603 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
604 AIC3X_GPIO1_REG, 4, 0xf,
605 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
606 AIC3X_GPIO1_FUNC_DISABLED),
607
608 /*
609 * Also similar function like mic bias. Selects digital mic with
610 * configurable oversampling rate instead of ADC converter.
611 */
612 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
613 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
614 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
615 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
616 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
617 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
618
619 /* Mic Bias */
620 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
621 mic_bias_event,
622 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
623
624 /* Output mixers */
625 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
626 &aic3x_left_line_mixer_controls[0],
627 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
628 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
629 &aic3x_right_line_mixer_controls[0],
630 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
631 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
632 &aic3x_left_hp_mixer_controls[0],
633 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
634 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
635 &aic3x_right_hp_mixer_controls[0],
636 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
637 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
638 &aic3x_left_hpcom_mixer_controls[0],
639 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
640 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
641 &aic3x_right_hpcom_mixer_controls[0],
642 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
643
644 SND_SOC_DAPM_OUTPUT("LLOUT"),
645 SND_SOC_DAPM_OUTPUT("RLOUT"),
646 SND_SOC_DAPM_OUTPUT("HPLOUT"),
647 SND_SOC_DAPM_OUTPUT("HPROUT"),
648 SND_SOC_DAPM_OUTPUT("HPLCOM"),
649 SND_SOC_DAPM_OUTPUT("HPRCOM"),
650
651 SND_SOC_DAPM_INPUT("MIC3L"),
652 SND_SOC_DAPM_INPUT("MIC3R"),
653 SND_SOC_DAPM_INPUT("LINE1L"),
654 SND_SOC_DAPM_INPUT("LINE1R"),
655 SND_SOC_DAPM_INPUT("LINE2L"),
656 SND_SOC_DAPM_INPUT("LINE2R"),
657
658 /*
659 * Virtual output pin to detection block inside codec. This can be
660 * used to keep codec bias on if gpio or detection features are needed.
661 * Force pin on or construct a path with an input jack and mic bias
662 * widgets.
663 */
664 SND_SOC_DAPM_OUTPUT("Detection"),
665 };
666
667 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
668 /* Mono Output */
669 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
670
671 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
672 &aic3x_mono_mixer_controls[0],
673 ARRAY_SIZE(aic3x_mono_mixer_controls)),
674
675 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
676 };
677
678 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
679 /* Class-D outputs */
680 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
681 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
682
683 SND_SOC_DAPM_OUTPUT("SPOP"),
684 SND_SOC_DAPM_OUTPUT("SPOM"),
685 };
686
687 static const struct snd_soc_dapm_route intercon[] = {
688 /* Left Input */
689 {"Left Line1L Mux", "single-ended", "LINE1L"},
690 {"Left Line1L Mux", "differential", "LINE1L"},
691 {"Left Line1R Mux", "single-ended", "LINE1R"},
692 {"Left Line1R Mux", "differential", "LINE1R"},
693
694 {"Left Line2L Mux", "single-ended", "LINE2L"},
695 {"Left Line2L Mux", "differential", "LINE2L"},
696
697 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
698 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
699 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
700 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
701 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
702
703 {"Left ADC", NULL, "Left PGA Mixer"},
704 {"Left ADC", NULL, "GPIO1 dmic modclk"},
705
706 /* Right Input */
707 {"Right Line1R Mux", "single-ended", "LINE1R"},
708 {"Right Line1R Mux", "differential", "LINE1R"},
709 {"Right Line1L Mux", "single-ended", "LINE1L"},
710 {"Right Line1L Mux", "differential", "LINE1L"},
711
712 {"Right Line2R Mux", "single-ended", "LINE2R"},
713 {"Right Line2R Mux", "differential", "LINE2R"},
714
715 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
716 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
717 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
718 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
719 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
720
721 {"Right ADC", NULL, "Right PGA Mixer"},
722 {"Right ADC", NULL, "GPIO1 dmic modclk"},
723
724 /*
725 * Logical path between digital mic enable and GPIO1 modulator clock
726 * output function
727 */
728 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
729 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
730 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
731
732 /* Left DAC Output */
733 {"Left DAC Mux", "DAC_L1", "Left DAC"},
734 {"Left DAC Mux", "DAC_L2", "Left DAC"},
735 {"Left DAC Mux", "DAC_L3", "Left DAC"},
736
737 /* Right DAC Output */
738 {"Right DAC Mux", "DAC_R1", "Right DAC"},
739 {"Right DAC Mux", "DAC_R2", "Right DAC"},
740 {"Right DAC Mux", "DAC_R3", "Right DAC"},
741
742 /* Left Line Output */
743 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
744 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
745 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
746 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
747 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
748 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
749
750 {"Left Line Out", NULL, "Left Line Mixer"},
751 {"Left Line Out", NULL, "Left DAC Mux"},
752 {"LLOUT", NULL, "Left Line Out"},
753
754 /* Right Line Output */
755 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
756 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
757 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
758 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
759 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
760 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
761
762 {"Right Line Out", NULL, "Right Line Mixer"},
763 {"Right Line Out", NULL, "Right DAC Mux"},
764 {"RLOUT", NULL, "Right Line Out"},
765
766 /* Left HP Output */
767 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
768 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
769 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
770 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
771 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
772 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
773
774 {"Left HP Out", NULL, "Left HP Mixer"},
775 {"Left HP Out", NULL, "Left DAC Mux"},
776 {"HPLOUT", NULL, "Left HP Out"},
777
778 /* Right HP Output */
779 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
780 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
781 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
782 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
783 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
784 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
785
786 {"Right HP Out", NULL, "Right HP Mixer"},
787 {"Right HP Out", NULL, "Right DAC Mux"},
788 {"HPROUT", NULL, "Right HP Out"},
789
790 /* Left HPCOM Output */
791 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
792 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
793 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
794 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
795 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
796 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
797
798 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
799 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
800 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
801 {"Left HP Com", NULL, "Left HPCOM Mux"},
802 {"HPLCOM", NULL, "Left HP Com"},
803
804 /* Right HPCOM Output */
805 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
806 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
807 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
808 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
809 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
810 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
811
812 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
813 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
814 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
815 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
816 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
817 {"Right HP Com", NULL, "Right HPCOM Mux"},
818 {"HPRCOM", NULL, "Right HP Com"},
819 };
820
821 static const struct snd_soc_dapm_route intercon_mono[] = {
822 /* Mono Output */
823 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
824 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
825 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
826 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
827 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
828 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
829 {"Mono Out", NULL, "Mono Mixer"},
830 {"MONO_LOUT", NULL, "Mono Out"},
831 };
832
833 static const struct snd_soc_dapm_route intercon_3007[] = {
834 /* Class-D outputs */
835 {"Left Class-D Out", NULL, "Left Line Out"},
836 {"Right Class-D Out", NULL, "Left Line Out"},
837 {"SPOP", NULL, "Left Class-D Out"},
838 {"SPOM", NULL, "Right Class-D Out"},
839 };
840
841 static int aic3x_add_widgets(struct snd_soc_codec *codec)
842 {
843 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
844 struct snd_soc_dapm_context *dapm = &codec->dapm;
845
846 switch (aic3x->model) {
847 case AIC3X_MODEL_3X:
848 case AIC3X_MODEL_33:
849 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
850 ARRAY_SIZE(aic3x_dapm_mono_widgets));
851 snd_soc_dapm_add_routes(dapm, intercon_mono,
852 ARRAY_SIZE(intercon_mono));
853 break;
854 case AIC3X_MODEL_3007:
855 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
856 ARRAY_SIZE(aic3007_dapm_widgets));
857 snd_soc_dapm_add_routes(dapm, intercon_3007,
858 ARRAY_SIZE(intercon_3007));
859 break;
860 }
861
862 return 0;
863 }
864
865 static int aic3x_hw_params(struct snd_pcm_substream *substream,
866 struct snd_pcm_hw_params *params,
867 struct snd_soc_dai *dai)
868 {
869 struct snd_soc_codec *codec = dai->codec;
870 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
871 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
872 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
873 u16 d, pll_d = 1;
874 int clk;
875
876 /* select data word length */
877 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
878 switch (params_width(params)) {
879 case 16:
880 break;
881 case 20:
882 data |= (0x01 << 4);
883 break;
884 case 24:
885 data |= (0x02 << 4);
886 break;
887 case 32:
888 data |= (0x03 << 4);
889 break;
890 }
891 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
892
893 /* Fsref can be 44100 or 48000 */
894 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
895
896 /* Try to find a value for Q which allows us to bypass the PLL and
897 * generate CODEC_CLK directly. */
898 for (pll_q = 2; pll_q < 18; pll_q++)
899 if (aic3x->sysclk / (128 * pll_q) == fsref) {
900 bypass_pll = 1;
901 break;
902 }
903
904 if (bypass_pll) {
905 pll_q &= 0xf;
906 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
907 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
908 /* disable PLL if it is bypassed */
909 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
910
911 } else {
912 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
913 /* enable PLL when it is used */
914 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
915 PLL_ENABLE, PLL_ENABLE);
916 }
917
918 /* Route Left DAC to left channel input and
919 * right DAC to right channel input */
920 data = (LDAC2LCH | RDAC2RCH);
921 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
922 if (params_rate(params) >= 64000)
923 data |= DUAL_RATE_MODE;
924 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
925
926 /* codec sample rate select */
927 data = (fsref * 20) / params_rate(params);
928 if (params_rate(params) < 64000)
929 data /= 2;
930 data /= 5;
931 data -= 2;
932 data |= (data << 4);
933 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
934
935 if (bypass_pll)
936 return 0;
937
938 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
939 * one wins the game. Try with d==0 first, next with d!=0.
940 * Constraints for j are according to the datasheet.
941 * The sysclk is divided by 1000 to prevent integer overflows.
942 */
943
944 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
945
946 for (r = 1; r <= 16; r++)
947 for (p = 1; p <= 8; p++) {
948 for (j = 4; j <= 55; j++) {
949 /* This is actually 1000*((j+(d/10000))*r)/p
950 * The term had to be converted to get
951 * rid of the division by 10000; d = 0 here
952 */
953 int tmp_clk = (1000 * j * r) / p;
954
955 /* Check whether this values get closer than
956 * the best ones we had before
957 */
958 if (abs(codec_clk - tmp_clk) <
959 abs(codec_clk - last_clk)) {
960 pll_j = j; pll_d = 0;
961 pll_r = r; pll_p = p;
962 last_clk = tmp_clk;
963 }
964
965 /* Early exit for exact matches */
966 if (tmp_clk == codec_clk)
967 goto found;
968 }
969 }
970
971 /* try with d != 0 */
972 for (p = 1; p <= 8; p++) {
973 j = codec_clk * p / 1000;
974
975 if (j < 4 || j > 11)
976 continue;
977
978 /* do not use codec_clk here since we'd loose precision */
979 d = ((2048 * p * fsref) - j * aic3x->sysclk)
980 * 100 / (aic3x->sysclk/100);
981
982 clk = (10000 * j + d) / (10 * p);
983
984 /* check whether this values get closer than the best
985 * ones we had before */
986 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
987 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
988 last_clk = clk;
989 }
990
991 /* Early exit for exact matches */
992 if (clk == codec_clk)
993 goto found;
994 }
995
996 if (last_clk == 0) {
997 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
998 return -EINVAL;
999 }
1000
1001 found:
1002 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1003 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1004 pll_r << PLLR_SHIFT);
1005 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1006 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1007 (pll_d >> 6) << PLLD_MSB_SHIFT);
1008 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1009 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1010
1011 return 0;
1012 }
1013
1014 static int aic3x_prepare(struct snd_pcm_substream *substream,
1015 struct snd_soc_dai *dai)
1016 {
1017 struct snd_soc_codec *codec = dai->codec;
1018 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1019 int delay = 0;
1020
1021 /* TDM slot selection only valid in DSP_A/_B mode */
1022 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1023 delay += (aic3x->tdm_delay + 1);
1024 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1025 delay += aic3x->tdm_delay;
1026
1027 /* Configure data delay */
1028 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, aic3x->tdm_delay);
1029
1030 return 0;
1031 }
1032
1033 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1034 {
1035 struct snd_soc_codec *codec = dai->codec;
1036 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1037 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1038
1039 if (mute) {
1040 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1041 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1042 } else {
1043 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1044 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1045 }
1046
1047 return 0;
1048 }
1049
1050 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1051 int clk_id, unsigned int freq, int dir)
1052 {
1053 struct snd_soc_codec *codec = codec_dai->codec;
1054 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1055
1056 /* set clock on MCLK or GPIO2 or BCLK */
1057 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1058 clk_id << PLLCLK_IN_SHIFT);
1059 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1060 clk_id << CLKDIV_IN_SHIFT);
1061
1062 aic3x->sysclk = freq;
1063 return 0;
1064 }
1065
1066 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1067 unsigned int fmt)
1068 {
1069 struct snd_soc_codec *codec = codec_dai->codec;
1070 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1071 u8 iface_areg, iface_breg;
1072
1073 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1074 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1075
1076 /* set master/slave audio interface */
1077 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1078 case SND_SOC_DAIFMT_CBM_CFM:
1079 aic3x->master = 1;
1080 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1081 break;
1082 case SND_SOC_DAIFMT_CBS_CFS:
1083 aic3x->master = 0;
1084 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089
1090 /*
1091 * match both interface format and signal polarities since they
1092 * are fixed
1093 */
1094 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1095 SND_SOC_DAIFMT_INV_MASK)) {
1096 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1097 break;
1098 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1099 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1100 iface_breg |= (0x01 << 6);
1101 break;
1102 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1103 iface_breg |= (0x02 << 6);
1104 break;
1105 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1106 iface_breg |= (0x03 << 6);
1107 break;
1108 default:
1109 return -EINVAL;
1110 }
1111
1112 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1113
1114 /* set iface */
1115 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1116 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1117
1118 return 0;
1119 }
1120
1121 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1122 unsigned int tx_mask, unsigned int rx_mask,
1123 int slots, int slot_width)
1124 {
1125 struct snd_soc_codec *codec = codec_dai->codec;
1126 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1127 unsigned int lsb;
1128
1129 if (tx_mask != rx_mask) {
1130 dev_err(codec->dev, "tx and rx masks must be symmetric\n");
1131 return -EINVAL;
1132 }
1133
1134 if (unlikely(!tx_mask)) {
1135 dev_err(codec->dev, "tx and rx masks need to be non 0\n");
1136 return -EINVAL;
1137 }
1138
1139 /* TDM based on DSP mode requires slots to be adjacent */
1140 lsb = __ffs(tx_mask);
1141 if ((lsb + 1) != __fls(tx_mask)) {
1142 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n");
1143 return -EINVAL;
1144 }
1145
1146 aic3x->tdm_delay = lsb * slot_width;
1147
1148 /* DOUT in high-impedance on inactive bit clocks */
1149 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
1150 DOUT_TRISTATE, DOUT_TRISTATE);
1151
1152 return 0;
1153 }
1154
1155 static int aic3x_regulator_event(struct notifier_block *nb,
1156 unsigned long event, void *data)
1157 {
1158 struct aic3x_disable_nb *disable_nb =
1159 container_of(nb, struct aic3x_disable_nb, nb);
1160 struct aic3x_priv *aic3x = disable_nb->aic3x;
1161
1162 if (event & REGULATOR_EVENT_DISABLE) {
1163 /*
1164 * Put codec to reset and require cache sync as at least one
1165 * of the supplies was disabled
1166 */
1167 if (gpio_is_valid(aic3x->gpio_reset))
1168 gpio_set_value(aic3x->gpio_reset, 0);
1169 regcache_mark_dirty(aic3x->regmap);
1170 }
1171
1172 return 0;
1173 }
1174
1175 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1176 {
1177 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1178 unsigned int pll_c, pll_d;
1179 int ret;
1180
1181 if (power) {
1182 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1183 aic3x->supplies);
1184 if (ret)
1185 goto out;
1186 aic3x->power = 1;
1187
1188 if (gpio_is_valid(aic3x->gpio_reset)) {
1189 udelay(1);
1190 gpio_set_value(aic3x->gpio_reset, 1);
1191 }
1192
1193 /* Sync reg_cache with the hardware */
1194 regcache_cache_only(aic3x->regmap, false);
1195 regcache_sync(aic3x->regmap);
1196
1197 /* Rewrite paired PLL D registers in case cached sync skipped
1198 * writing one of them and thus caused other one also not
1199 * being written
1200 */
1201 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1202 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1203 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1204 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1205 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1206 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1207 }
1208 } else {
1209 /*
1210 * Do soft reset to this codec instance in order to clear
1211 * possible VDD leakage currents in case the supply regulators
1212 * remain on
1213 */
1214 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1215 regcache_mark_dirty(aic3x->regmap);
1216 aic3x->power = 0;
1217 /* HW writes are needless when bias is off */
1218 regcache_cache_only(aic3x->regmap, true);
1219 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1220 aic3x->supplies);
1221 }
1222 out:
1223 return ret;
1224 }
1225
1226 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1227 enum snd_soc_bias_level level)
1228 {
1229 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1230
1231 switch (level) {
1232 case SND_SOC_BIAS_ON:
1233 break;
1234 case SND_SOC_BIAS_PREPARE:
1235 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1236 aic3x->master) {
1237 /* enable pll */
1238 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1239 PLL_ENABLE, PLL_ENABLE);
1240 }
1241 break;
1242 case SND_SOC_BIAS_STANDBY:
1243 if (!aic3x->power)
1244 aic3x_set_power(codec, 1);
1245 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1246 aic3x->master) {
1247 /* disable pll */
1248 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1249 PLL_ENABLE, 0);
1250 }
1251 break;
1252 case SND_SOC_BIAS_OFF:
1253 if (aic3x->power)
1254 aic3x_set_power(codec, 0);
1255 break;
1256 }
1257 codec->dapm.bias_level = level;
1258
1259 return 0;
1260 }
1261
1262 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1263 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1264 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1265 SNDRV_PCM_FMTBIT_S32_LE)
1266
1267 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1268 .hw_params = aic3x_hw_params,
1269 .prepare = aic3x_prepare,
1270 .digital_mute = aic3x_mute,
1271 .set_sysclk = aic3x_set_dai_sysclk,
1272 .set_fmt = aic3x_set_dai_fmt,
1273 .set_tdm_slot = aic3x_set_dai_tdm_slot,
1274 };
1275
1276 static struct snd_soc_dai_driver aic3x_dai = {
1277 .name = "tlv320aic3x-hifi",
1278 .playback = {
1279 .stream_name = "Playback",
1280 .channels_min = 2,
1281 .channels_max = 2,
1282 .rates = AIC3X_RATES,
1283 .formats = AIC3X_FORMATS,},
1284 .capture = {
1285 .stream_name = "Capture",
1286 .channels_min = 2,
1287 .channels_max = 2,
1288 .rates = AIC3X_RATES,
1289 .formats = AIC3X_FORMATS,},
1290 .ops = &aic3x_dai_ops,
1291 .symmetric_rates = 1,
1292 };
1293
1294 static void aic3x_mono_init(struct snd_soc_codec *codec)
1295 {
1296 /* DAC to Mono Line Out default volume and route to Output mixer */
1297 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1298 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1299
1300 /* unmute all outputs */
1301 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1302
1303 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1304 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1305 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1306
1307 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1308 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1309 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1310 }
1311
1312 /*
1313 * initialise the AIC3X driver
1314 * register the mixer and dsp interfaces with the kernel
1315 */
1316 static int aic3x_init(struct snd_soc_codec *codec)
1317 {
1318 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1319
1320 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1321 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1322
1323 /* DAC default volume and mute */
1324 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1325 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1326
1327 /* DAC to HP default volume and route to Output mixer */
1328 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1329 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1330 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1331 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1332 /* DAC to Line Out default volume and route to Output mixer */
1333 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1334 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1335
1336 /* unmute all outputs */
1337 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1338 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1339 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1340 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1341 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1342 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1343
1344 /* ADC default volume and unmute */
1345 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1346 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1347 /* By default route Line1 to ADC PGA mixer */
1348 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1349 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1350
1351 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1352 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1353 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1354 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1355 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1356 /* PGA to Line Out default volume, disconnect from Output Mixer */
1357 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1358 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1359
1360 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1361 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1362 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1363 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1364 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1365 /* Line2 Line Out default volume, disconnect from Output Mixer */
1366 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1367 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1368
1369 switch (aic3x->model) {
1370 case AIC3X_MODEL_3X:
1371 case AIC3X_MODEL_33:
1372 aic3x_mono_init(codec);
1373 break;
1374 case AIC3X_MODEL_3007:
1375 snd_soc_write(codec, CLASSD_CTRL, 0);
1376 break;
1377 }
1378
1379 return 0;
1380 }
1381
1382 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1383 {
1384 struct aic3x_priv *a;
1385
1386 list_for_each_entry(a, &reset_list, list) {
1387 if (gpio_is_valid(aic3x->gpio_reset) &&
1388 aic3x->gpio_reset == a->gpio_reset)
1389 return true;
1390 }
1391
1392 return false;
1393 }
1394
1395 static int aic3x_probe(struct snd_soc_codec *codec)
1396 {
1397 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1398 int ret, i;
1399
1400 INIT_LIST_HEAD(&aic3x->list);
1401 aic3x->codec = codec;
1402
1403 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1404 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1405 aic3x->disable_nb[i].aic3x = aic3x;
1406 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1407 &aic3x->disable_nb[i].nb);
1408 if (ret) {
1409 dev_err(codec->dev,
1410 "Failed to request regulator notifier: %d\n",
1411 ret);
1412 goto err_notif;
1413 }
1414 }
1415
1416 regcache_mark_dirty(aic3x->regmap);
1417 aic3x_init(codec);
1418
1419 if (aic3x->setup) {
1420 /* setup GPIO functions */
1421 snd_soc_write(codec, AIC3X_GPIO1_REG,
1422 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1423 snd_soc_write(codec, AIC3X_GPIO2_REG,
1424 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1425 }
1426
1427 switch (aic3x->model) {
1428 case AIC3X_MODEL_3X:
1429 case AIC3X_MODEL_33:
1430 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1431 ARRAY_SIZE(aic3x_mono_controls));
1432 break;
1433 case AIC3X_MODEL_3007:
1434 snd_soc_add_codec_controls(codec,
1435 &aic3x_classd_amp_gain_ctrl, 1);
1436 break;
1437 }
1438
1439 /* set mic bias voltage */
1440 switch (aic3x->micbias_vg) {
1441 case AIC3X_MICBIAS_2_0V:
1442 case AIC3X_MICBIAS_2_5V:
1443 case AIC3X_MICBIAS_AVDDV:
1444 snd_soc_update_bits(codec, MICBIAS_CTRL,
1445 MICBIAS_LEVEL_MASK,
1446 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1447 break;
1448 case AIC3X_MICBIAS_OFF:
1449 /*
1450 * noting to do. target won't enter here. This is just to avoid
1451 * compile time warning "warning: enumeration value
1452 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1453 */
1454 break;
1455 }
1456
1457 aic3x_add_widgets(codec);
1458
1459 return 0;
1460
1461 err_notif:
1462 while (i--)
1463 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1464 &aic3x->disable_nb[i].nb);
1465 return ret;
1466 }
1467
1468 static int aic3x_remove(struct snd_soc_codec *codec)
1469 {
1470 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1471 int i;
1472
1473 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1474 list_del(&aic3x->list);
1475 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1476 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1477 &aic3x->disable_nb[i].nb);
1478
1479 return 0;
1480 }
1481
1482 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1483 .set_bias_level = aic3x_set_bias_level,
1484 .idle_bias_off = true,
1485 .probe = aic3x_probe,
1486 .remove = aic3x_remove,
1487 .controls = aic3x_snd_controls,
1488 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1489 .dapm_widgets = aic3x_dapm_widgets,
1490 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1491 .dapm_routes = intercon,
1492 .num_dapm_routes = ARRAY_SIZE(intercon),
1493 };
1494
1495 /*
1496 * AIC3X 2 wire address can be up to 4 devices with device addresses
1497 * 0x18, 0x19, 0x1A, 0x1B
1498 */
1499
1500 static const struct i2c_device_id aic3x_i2c_id[] = {
1501 { "tlv320aic3x", AIC3X_MODEL_3X },
1502 { "tlv320aic33", AIC3X_MODEL_33 },
1503 { "tlv320aic3007", AIC3X_MODEL_3007 },
1504 { "tlv320aic3106", AIC3X_MODEL_3X },
1505 { }
1506 };
1507 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1508
1509 static const struct reg_default aic3007_class_d[] = {
1510 /* Class-D speaker driver init; datasheet p. 46 */
1511 { AIC3X_PAGE_SELECT, 0x0D },
1512 { 0xD, 0x0D },
1513 { 0x8, 0x5C },
1514 { 0x8, 0x5D },
1515 { 0x8, 0x5C },
1516 { AIC3X_PAGE_SELECT, 0x00 },
1517 };
1518
1519 /*
1520 * If the i2c layer weren't so broken, we could pass this kind of data
1521 * around
1522 */
1523 static int aic3x_i2c_probe(struct i2c_client *i2c,
1524 const struct i2c_device_id *id)
1525 {
1526 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1527 struct aic3x_priv *aic3x;
1528 struct aic3x_setup_data *ai3x_setup;
1529 struct device_node *np = i2c->dev.of_node;
1530 int ret, i;
1531 u32 value;
1532
1533 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1534 if (!aic3x)
1535 return -ENOMEM;
1536
1537 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1538 if (IS_ERR(aic3x->regmap)) {
1539 ret = PTR_ERR(aic3x->regmap);
1540 return ret;
1541 }
1542
1543 regcache_cache_only(aic3x->regmap, true);
1544
1545 i2c_set_clientdata(i2c, aic3x);
1546 if (pdata) {
1547 aic3x->gpio_reset = pdata->gpio_reset;
1548 aic3x->setup = pdata->setup;
1549 aic3x->micbias_vg = pdata->micbias_vg;
1550 } else if (np) {
1551 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1552 GFP_KERNEL);
1553 if (!ai3x_setup)
1554 return -ENOMEM;
1555
1556 ret = of_get_named_gpio(np, "gpio-reset", 0);
1557 if (ret >= 0)
1558 aic3x->gpio_reset = ret;
1559 else
1560 aic3x->gpio_reset = -1;
1561
1562 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1563 ai3x_setup->gpio_func, 2) >= 0) {
1564 aic3x->setup = ai3x_setup;
1565 }
1566
1567 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1568 switch (value) {
1569 case 1 :
1570 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1571 break;
1572 case 2 :
1573 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1574 break;
1575 case 3 :
1576 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1577 break;
1578 default :
1579 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1580 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1581 "found in DT\n");
1582 }
1583 } else {
1584 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1585 }
1586
1587 } else {
1588 aic3x->gpio_reset = -1;
1589 }
1590
1591 aic3x->model = id->driver_data;
1592
1593 if (gpio_is_valid(aic3x->gpio_reset) &&
1594 !aic3x_is_shared_reset(aic3x)) {
1595 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1596 if (ret != 0)
1597 goto err;
1598 gpio_direction_output(aic3x->gpio_reset, 0);
1599 }
1600
1601 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1602 aic3x->supplies[i].supply = aic3x_supply_names[i];
1603
1604 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1605 aic3x->supplies);
1606 if (ret != 0) {
1607 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1608 goto err_gpio;
1609 }
1610
1611 if (aic3x->model == AIC3X_MODEL_3007) {
1612 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1613 ARRAY_SIZE(aic3007_class_d));
1614 if (ret != 0)
1615 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1616 ret);
1617 }
1618
1619 ret = snd_soc_register_codec(&i2c->dev,
1620 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1621
1622 if (ret != 0)
1623 goto err_gpio;
1624
1625 list_add(&aic3x->list, &reset_list);
1626
1627 return 0;
1628
1629 err_gpio:
1630 if (gpio_is_valid(aic3x->gpio_reset) &&
1631 !aic3x_is_shared_reset(aic3x))
1632 gpio_free(aic3x->gpio_reset);
1633 err:
1634 return ret;
1635 }
1636
1637 static int aic3x_i2c_remove(struct i2c_client *client)
1638 {
1639 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1640
1641 snd_soc_unregister_codec(&client->dev);
1642 if (gpio_is_valid(aic3x->gpio_reset) &&
1643 !aic3x_is_shared_reset(aic3x)) {
1644 gpio_set_value(aic3x->gpio_reset, 0);
1645 gpio_free(aic3x->gpio_reset);
1646 }
1647 return 0;
1648 }
1649
1650 #if defined(CONFIG_OF)
1651 static const struct of_device_id tlv320aic3x_of_match[] = {
1652 { .compatible = "ti,tlv320aic3x", },
1653 { .compatible = "ti,tlv320aic33" },
1654 { .compatible = "ti,tlv320aic3007" },
1655 { .compatible = "ti,tlv320aic3106" },
1656 {},
1657 };
1658 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1659 #endif
1660
1661 /* machine i2c codec control layer */
1662 static struct i2c_driver aic3x_i2c_driver = {
1663 .driver = {
1664 .name = "tlv320aic3x-codec",
1665 .owner = THIS_MODULE,
1666 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1667 },
1668 .probe = aic3x_i2c_probe,
1669 .remove = aic3x_i2c_remove,
1670 .id_table = aic3x_i2c_id,
1671 };
1672
1673 module_i2c_driver(aic3x_i2c_driver);
1674
1675 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1676 MODULE_AUTHOR("Vladimir Barinov");
1677 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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