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Merge branch 'for-3.2' into for-3.3
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/initval.h>
50 #include <sound/tlv.h>
51 #include <sound/tlv320aic3x.h>
52
53 #include "tlv320aic3x.h"
54
55 #define AIC3X_NUM_SUPPLIES 4
56 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61 };
62
63 static LIST_HEAD(reset_list);
64
65 struct aic3x_priv;
66
67 struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70 };
71
72 /* codec private data */
73 struct aic3x_priv {
74 struct snd_soc_codec *codec;
75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 unsigned int sysclk;
80 struct list_head list;
81 int master;
82 int gpio_reset;
83 int power;
84 #define AIC3X_MODEL_3X 0
85 #define AIC3X_MODEL_33 1
86 #define AIC3X_MODEL_3007 2
87 u16 model;
88 };
89
90 /*
91 * AIC3X register cache
92 * We can't read the AIC3X register space when we are
93 * using 2 wire for device control, so we cache them instead.
94 * There is no point in caching the reset register
95 */
96 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
97 0x00, 0x00, 0x00, 0x10, /* 0 */
98 0x04, 0x00, 0x00, 0x00, /* 4 */
99 0x00, 0x00, 0x00, 0x01, /* 8 */
100 0x00, 0x00, 0x00, 0x80, /* 12 */
101 0x80, 0xff, 0xff, 0x78, /* 16 */
102 0x78, 0x78, 0x78, 0x78, /* 20 */
103 0x78, 0x00, 0x00, 0xfe, /* 24 */
104 0x00, 0x00, 0xfe, 0x00, /* 28 */
105 0x18, 0x18, 0x00, 0x00, /* 32 */
106 0x00, 0x00, 0x00, 0x00, /* 36 */
107 0x00, 0x00, 0x00, 0x80, /* 40 */
108 0x80, 0x00, 0x00, 0x00, /* 44 */
109 0x00, 0x00, 0x00, 0x04, /* 48 */
110 0x00, 0x00, 0x00, 0x00, /* 52 */
111 0x00, 0x00, 0x04, 0x00, /* 56 */
112 0x00, 0x00, 0x00, 0x00, /* 60 */
113 0x00, 0x04, 0x00, 0x00, /* 64 */
114 0x00, 0x00, 0x00, 0x00, /* 68 */
115 0x04, 0x00, 0x00, 0x00, /* 72 */
116 0x00, 0x00, 0x00, 0x00, /* 76 */
117 0x00, 0x00, 0x00, 0x00, /* 80 */
118 0x00, 0x00, 0x00, 0x00, /* 84 */
119 0x00, 0x00, 0x00, 0x00, /* 88 */
120 0x00, 0x00, 0x00, 0x00, /* 92 */
121 0x00, 0x00, 0x00, 0x00, /* 96 */
122 0x00, 0x00, 0x02, /* 100 */
123 };
124
125 /*
126 * read from the aic3x register space. Only use for this function is if
127 * wanting to read volatile bits from those registers that has both read-only
128 * and read/write bits. All other cases should use snd_soc_read.
129 */
130 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
131 u8 *value)
132 {
133 u8 *cache = codec->reg_cache;
134
135 if (codec->cache_only)
136 return -EINVAL;
137 if (reg >= AIC3X_CACHEREGNUM)
138 return -1;
139
140 codec->cache_bypass = 1;
141 *value = snd_soc_read(codec, reg);
142 codec->cache_bypass = 0;
143
144 cache[reg] = *value;
145
146 return 0;
147 }
148
149 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
150 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
151 .info = snd_soc_info_volsw, \
152 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
153 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
154
155 /*
156 * All input lines are connected when !0xf and disconnected with 0xf bit field,
157 * so we have to use specific dapm_put call for input mixer
158 */
159 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
160 struct snd_ctl_elem_value *ucontrol)
161 {
162 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
163 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
164 struct soc_mixer_control *mc =
165 (struct soc_mixer_control *)kcontrol->private_value;
166 unsigned int reg = mc->reg;
167 unsigned int shift = mc->shift;
168 int max = mc->max;
169 unsigned int mask = (1 << fls(max)) - 1;
170 unsigned int invert = mc->invert;
171 unsigned short val, val_mask;
172 int ret;
173 struct snd_soc_dapm_path *path;
174 int found = 0;
175
176 val = (ucontrol->value.integer.value[0] & mask);
177
178 mask = 0xf;
179 if (val)
180 val = mask;
181
182 if (invert)
183 val = mask - val;
184 val_mask = mask << shift;
185 val = val << shift;
186
187 mutex_lock(&widget->codec->mutex);
188
189 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
190 /* find dapm widget path assoc with kcontrol */
191 list_for_each_entry(path, &widget->dapm->card->paths, list) {
192 if (path->kcontrol != kcontrol)
193 continue;
194
195 /* found, now check type */
196 found = 1;
197 if (val)
198 /* new connection */
199 path->connect = invert ? 0 : 1;
200 else
201 /* old connection must be powered down */
202 path->connect = invert ? 1 : 0;
203
204 dapm_mark_dirty(path->source, "tlv320aic3x source");
205 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
206
207 break;
208 }
209
210 if (found)
211 snd_soc_dapm_sync(widget->dapm);
212 }
213
214 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
215
216 mutex_unlock(&widget->codec->mutex);
217 return ret;
218 }
219
220 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
221 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
222 static const char *aic3x_left_hpcom_mux[] =
223 { "differential of HPLOUT", "constant VCM", "single-ended" };
224 static const char *aic3x_right_hpcom_mux[] =
225 { "differential of HPROUT", "constant VCM", "single-ended",
226 "differential of HPLCOM", "external feedback" };
227 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
228 static const char *aic3x_adc_hpf[] =
229 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
230
231 #define LDAC_ENUM 0
232 #define RDAC_ENUM 1
233 #define LHPCOM_ENUM 2
234 #define RHPCOM_ENUM 3
235 #define LINE1L_2_L_ENUM 4
236 #define LINE1L_2_R_ENUM 5
237 #define LINE1R_2_L_ENUM 6
238 #define LINE1R_2_R_ENUM 7
239 #define LINE2L_ENUM 8
240 #define LINE2R_ENUM 9
241 #define ADC_HPF_ENUM 10
242
243 static const struct soc_enum aic3x_enum[] = {
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
245 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
246 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
247 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
248 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
252 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
253 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
254 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
255 };
256
257 /*
258 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
259 */
260 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
261 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
262 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
263 /*
264 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
265 * Step size is approximately 0.5 dB over most of the scale but increasing
266 * near the very low levels.
267 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
268 * but having increasing dB difference below that (and where it doesn't count
269 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
270 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
271 */
272 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
273
274 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
275 /* Output */
276 SOC_DOUBLE_R_TLV("PCM Playback Volume",
277 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
278
279 /*
280 * Output controls that map to output mixer switches. Note these are
281 * only for swapped L-to-R and R-to-L routes. See below stereo controls
282 * for direct L-to-L and R-to-R routes.
283 */
284 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
285 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
287 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
288 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
289 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
290
291 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
292 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
294 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
295 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
296 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
297
298 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
299 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
300 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
301 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
303 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
304
305 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
306 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
308 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
310 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
311
312 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
313 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
314 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
315 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
317 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
318
319 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
320 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
321 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
322 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
324 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
325
326 /* Stereo output controls for direct L-to-L and R-to-R routes */
327 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
328 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
329 0, 118, 1, output_stage_tlv),
330 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
331 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
332 0, 118, 1, output_stage_tlv),
333 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
334 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
335 0, 118, 1, output_stage_tlv),
336
337 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
338 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
339 0, 118, 1, output_stage_tlv),
340 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
341 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
342 0, 118, 1, output_stage_tlv),
343 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
344 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346
347 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
348 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
349 0, 118, 1, output_stage_tlv),
350 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
351 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
352 0, 118, 1, output_stage_tlv),
353 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
354 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
355 0, 118, 1, output_stage_tlv),
356
357 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
358 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
359 0, 118, 1, output_stage_tlv),
360 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
361 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
362 0, 118, 1, output_stage_tlv),
363 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
364 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
365 0, 118, 1, output_stage_tlv),
366
367 /* Output pin mute controls */
368 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
369 0x01, 0),
370 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
371 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
372 0x01, 0),
373 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
374 0x01, 0),
375
376 /*
377 * Note: enable Automatic input Gain Controller with care. It can
378 * adjust PGA to max value when ADC is on and will never go back.
379 */
380 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
381
382 /* Input */
383 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
384 0, 119, 0, adc_tlv),
385 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
386
387 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
388 };
389
390 /*
391 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
392 */
393 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
394
395 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
396 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
397
398 /* Left DAC Mux */
399 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
400 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
401
402 /* Right DAC Mux */
403 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
404 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
405
406 /* Left HPCOM Mux */
407 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
408 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
409
410 /* Right HPCOM Mux */
411 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
412 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
413
414 /* Left Line Mixer */
415 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
416 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
422 };
423
424 /* Right Line Mixer */
425 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
426 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
432 };
433
434 /* Mono Mixer */
435 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
436 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
442 };
443
444 /* Left HP Mixer */
445 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
452 };
453
454 /* Right HP Mixer */
455 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
462 };
463
464 /* Left HPCOM Mixer */
465 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
472 };
473
474 /* Right HPCOM Mixer */
475 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
482 };
483
484 /* Left PGA Mixer */
485 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
486 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
487 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
488 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
489 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
490 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
491 };
492
493 /* Right PGA Mixer */
494 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
495 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
496 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
497 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
498 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
499 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
500 };
501
502 /* Left Line1 Mux */
503 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
504 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
505 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
506 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
507
508 /* Right Line1 Mux */
509 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
510 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
511 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
512 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
513
514 /* Left Line2 Mux */
515 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
516 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
517
518 /* Right Line2 Mux */
519 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
520 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
521
522 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
523 /* Left DAC to Left Outputs */
524 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
525 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
526 &aic3x_left_dac_mux_controls),
527 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
528 &aic3x_left_hpcom_mux_controls),
529 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
531 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
532
533 /* Right DAC to Right Outputs */
534 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
535 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
536 &aic3x_right_dac_mux_controls),
537 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_right_hpcom_mux_controls),
539 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
540 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
541 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
542
543 /* Mono Output */
544 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
545
546 /* Inputs to Left ADC */
547 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
548 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
549 &aic3x_left_pga_mixer_controls[0],
550 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
551 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
552 &aic3x_left_line1l_mux_controls),
553 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
554 &aic3x_left_line1r_mux_controls),
555 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
556 &aic3x_left_line2_mux_controls),
557
558 /* Inputs to Right ADC */
559 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
560 LINE1R_2_RADC_CTRL, 2, 0),
561 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
562 &aic3x_right_pga_mixer_controls[0],
563 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
564 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
565 &aic3x_right_line1l_mux_controls),
566 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
567 &aic3x_right_line1r_mux_controls),
568 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
569 &aic3x_right_line2_mux_controls),
570
571 /*
572 * Not a real mic bias widget but similar function. This is for dynamic
573 * control of GPIO1 digital mic modulator clock output function when
574 * using digital mic.
575 */
576 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
577 AIC3X_GPIO1_REG, 4, 0xf,
578 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
579 AIC3X_GPIO1_FUNC_DISABLED),
580
581 /*
582 * Also similar function like mic bias. Selects digital mic with
583 * configurable oversampling rate instead of ADC converter.
584 */
585 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
586 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
587 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
588 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
589 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
590 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
591
592 /* Mic Bias */
593 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
594 MICBIAS_CTRL, 6, 3, 1, 0),
595 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
596 MICBIAS_CTRL, 6, 3, 2, 0),
597 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
598 MICBIAS_CTRL, 6, 3, 3, 0),
599
600 /* Output mixers */
601 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_left_line_mixer_controls[0],
603 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
604 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
605 &aic3x_right_line_mixer_controls[0],
606 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
607 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
608 &aic3x_mono_mixer_controls[0],
609 ARRAY_SIZE(aic3x_mono_mixer_controls)),
610 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
611 &aic3x_left_hp_mixer_controls[0],
612 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
613 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_right_hp_mixer_controls[0],
615 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
616 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
617 &aic3x_left_hpcom_mixer_controls[0],
618 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
619 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
620 &aic3x_right_hpcom_mixer_controls[0],
621 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
622
623 SND_SOC_DAPM_OUTPUT("LLOUT"),
624 SND_SOC_DAPM_OUTPUT("RLOUT"),
625 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
626 SND_SOC_DAPM_OUTPUT("HPLOUT"),
627 SND_SOC_DAPM_OUTPUT("HPROUT"),
628 SND_SOC_DAPM_OUTPUT("HPLCOM"),
629 SND_SOC_DAPM_OUTPUT("HPRCOM"),
630
631 SND_SOC_DAPM_INPUT("MIC3L"),
632 SND_SOC_DAPM_INPUT("MIC3R"),
633 SND_SOC_DAPM_INPUT("LINE1L"),
634 SND_SOC_DAPM_INPUT("LINE1R"),
635 SND_SOC_DAPM_INPUT("LINE2L"),
636 SND_SOC_DAPM_INPUT("LINE2R"),
637
638 /*
639 * Virtual output pin to detection block inside codec. This can be
640 * used to keep codec bias on if gpio or detection features are needed.
641 * Force pin on or construct a path with an input jack and mic bias
642 * widgets.
643 */
644 SND_SOC_DAPM_OUTPUT("Detection"),
645 };
646
647 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
648 /* Class-D outputs */
649 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
650 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
651
652 SND_SOC_DAPM_OUTPUT("SPOP"),
653 SND_SOC_DAPM_OUTPUT("SPOM"),
654 };
655
656 static const struct snd_soc_dapm_route intercon[] = {
657 /* Left Input */
658 {"Left Line1L Mux", "single-ended", "LINE1L"},
659 {"Left Line1L Mux", "differential", "LINE1L"},
660
661 {"Left Line2L Mux", "single-ended", "LINE2L"},
662 {"Left Line2L Mux", "differential", "LINE2L"},
663
664 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
665 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
666 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
667 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
668 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
669
670 {"Left ADC", NULL, "Left PGA Mixer"},
671 {"Left ADC", NULL, "GPIO1 dmic modclk"},
672
673 /* Right Input */
674 {"Right Line1R Mux", "single-ended", "LINE1R"},
675 {"Right Line1R Mux", "differential", "LINE1R"},
676
677 {"Right Line2R Mux", "single-ended", "LINE2R"},
678 {"Right Line2R Mux", "differential", "LINE2R"},
679
680 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
681 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
682 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
683 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
684 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
685
686 {"Right ADC", NULL, "Right PGA Mixer"},
687 {"Right ADC", NULL, "GPIO1 dmic modclk"},
688
689 /*
690 * Logical path between digital mic enable and GPIO1 modulator clock
691 * output function
692 */
693 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
694 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
695 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
696
697 /* Left DAC Output */
698 {"Left DAC Mux", "DAC_L1", "Left DAC"},
699 {"Left DAC Mux", "DAC_L2", "Left DAC"},
700 {"Left DAC Mux", "DAC_L3", "Left DAC"},
701
702 /* Right DAC Output */
703 {"Right DAC Mux", "DAC_R1", "Right DAC"},
704 {"Right DAC Mux", "DAC_R2", "Right DAC"},
705 {"Right DAC Mux", "DAC_R3", "Right DAC"},
706
707 /* Left Line Output */
708 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
709 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
710 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
711 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
712 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
713 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
714
715 {"Left Line Out", NULL, "Left Line Mixer"},
716 {"Left Line Out", NULL, "Left DAC Mux"},
717 {"LLOUT", NULL, "Left Line Out"},
718
719 /* Right Line Output */
720 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
721 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
722 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
723 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
724 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
725 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
726
727 {"Right Line Out", NULL, "Right Line Mixer"},
728 {"Right Line Out", NULL, "Right DAC Mux"},
729 {"RLOUT", NULL, "Right Line Out"},
730
731 /* Mono Output */
732 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
733 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
734 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
735 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
736 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
737 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
738
739 {"Mono Out", NULL, "Mono Mixer"},
740 {"MONO_LOUT", NULL, "Mono Out"},
741
742 /* Left HP Output */
743 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
744 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
745 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
746 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
747 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
748 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
749
750 {"Left HP Out", NULL, "Left HP Mixer"},
751 {"Left HP Out", NULL, "Left DAC Mux"},
752 {"HPLOUT", NULL, "Left HP Out"},
753
754 /* Right HP Output */
755 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
756 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
757 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
758 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
759 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
760 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
761
762 {"Right HP Out", NULL, "Right HP Mixer"},
763 {"Right HP Out", NULL, "Right DAC Mux"},
764 {"HPROUT", NULL, "Right HP Out"},
765
766 /* Left HPCOM Output */
767 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
768 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
769 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
770 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
771 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
772 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
773
774 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
775 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
776 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
777 {"Left HP Com", NULL, "Left HPCOM Mux"},
778 {"HPLCOM", NULL, "Left HP Com"},
779
780 /* Right HPCOM Output */
781 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
782 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
783 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
784 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
785 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
786 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
787
788 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
789 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
790 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
791 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
792 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
793 {"Right HP Com", NULL, "Right HPCOM Mux"},
794 {"HPRCOM", NULL, "Right HP Com"},
795 };
796
797 static const struct snd_soc_dapm_route intercon_3007[] = {
798 /* Class-D outputs */
799 {"Left Class-D Out", NULL, "Left Line Out"},
800 {"Right Class-D Out", NULL, "Left Line Out"},
801 {"SPOP", NULL, "Left Class-D Out"},
802 {"SPOM", NULL, "Right Class-D Out"},
803 };
804
805 static int aic3x_add_widgets(struct snd_soc_codec *codec)
806 {
807 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
808 struct snd_soc_dapm_context *dapm = &codec->dapm;
809
810 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
811 ARRAY_SIZE(aic3x_dapm_widgets));
812
813 /* set up audio path interconnects */
814 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
815
816 if (aic3x->model == AIC3X_MODEL_3007) {
817 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
818 ARRAY_SIZE(aic3007_dapm_widgets));
819 snd_soc_dapm_add_routes(dapm, intercon_3007,
820 ARRAY_SIZE(intercon_3007));
821 }
822
823 return 0;
824 }
825
826 static int aic3x_hw_params(struct snd_pcm_substream *substream,
827 struct snd_pcm_hw_params *params,
828 struct snd_soc_dai *dai)
829 {
830 struct snd_soc_pcm_runtime *rtd = substream->private_data;
831 struct snd_soc_codec *codec =rtd->codec;
832 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
833 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
834 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
835 u16 d, pll_d = 1;
836 int clk;
837
838 /* select data word length */
839 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
840 switch (params_format(params)) {
841 case SNDRV_PCM_FORMAT_S16_LE:
842 break;
843 case SNDRV_PCM_FORMAT_S20_3LE:
844 data |= (0x01 << 4);
845 break;
846 case SNDRV_PCM_FORMAT_S24_LE:
847 data |= (0x02 << 4);
848 break;
849 case SNDRV_PCM_FORMAT_S32_LE:
850 data |= (0x03 << 4);
851 break;
852 }
853 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
854
855 /* Fsref can be 44100 or 48000 */
856 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
857
858 /* Try to find a value for Q which allows us to bypass the PLL and
859 * generate CODEC_CLK directly. */
860 for (pll_q = 2; pll_q < 18; pll_q++)
861 if (aic3x->sysclk / (128 * pll_q) == fsref) {
862 bypass_pll = 1;
863 break;
864 }
865
866 if (bypass_pll) {
867 pll_q &= 0xf;
868 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
869 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
870 /* disable PLL if it is bypassed */
871 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
872
873 } else {
874 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
875 /* enable PLL when it is used */
876 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
877 PLL_ENABLE, PLL_ENABLE);
878 }
879
880 /* Route Left DAC to left channel input and
881 * right DAC to right channel input */
882 data = (LDAC2LCH | RDAC2RCH);
883 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
884 if (params_rate(params) >= 64000)
885 data |= DUAL_RATE_MODE;
886 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
887
888 /* codec sample rate select */
889 data = (fsref * 20) / params_rate(params);
890 if (params_rate(params) < 64000)
891 data /= 2;
892 data /= 5;
893 data -= 2;
894 data |= (data << 4);
895 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
896
897 if (bypass_pll)
898 return 0;
899
900 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
901 * one wins the game. Try with d==0 first, next with d!=0.
902 * Constraints for j are according to the datasheet.
903 * The sysclk is divided by 1000 to prevent integer overflows.
904 */
905
906 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
907
908 for (r = 1; r <= 16; r++)
909 for (p = 1; p <= 8; p++) {
910 for (j = 4; j <= 55; j++) {
911 /* This is actually 1000*((j+(d/10000))*r)/p
912 * The term had to be converted to get
913 * rid of the division by 10000; d = 0 here
914 */
915 int tmp_clk = (1000 * j * r) / p;
916
917 /* Check whether this values get closer than
918 * the best ones we had before
919 */
920 if (abs(codec_clk - tmp_clk) <
921 abs(codec_clk - last_clk)) {
922 pll_j = j; pll_d = 0;
923 pll_r = r; pll_p = p;
924 last_clk = tmp_clk;
925 }
926
927 /* Early exit for exact matches */
928 if (tmp_clk == codec_clk)
929 goto found;
930 }
931 }
932
933 /* try with d != 0 */
934 for (p = 1; p <= 8; p++) {
935 j = codec_clk * p / 1000;
936
937 if (j < 4 || j > 11)
938 continue;
939
940 /* do not use codec_clk here since we'd loose precision */
941 d = ((2048 * p * fsref) - j * aic3x->sysclk)
942 * 100 / (aic3x->sysclk/100);
943
944 clk = (10000 * j + d) / (10 * p);
945
946 /* check whether this values get closer than the best
947 * ones we had before */
948 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
949 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
950 last_clk = clk;
951 }
952
953 /* Early exit for exact matches */
954 if (clk == codec_clk)
955 goto found;
956 }
957
958 if (last_clk == 0) {
959 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
960 return -EINVAL;
961 }
962
963 found:
964 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
965 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
966 data | (pll_p << PLLP_SHIFT));
967 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
968 pll_r << PLLR_SHIFT);
969 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
970 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
971 (pll_d >> 6) << PLLD_MSB_SHIFT);
972 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
973 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
974
975 return 0;
976 }
977
978 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
979 {
980 struct snd_soc_codec *codec = dai->codec;
981 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
982 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
983
984 if (mute) {
985 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
986 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
987 } else {
988 snd_soc_write(codec, LDAC_VOL, ldac_reg);
989 snd_soc_write(codec, RDAC_VOL, rdac_reg);
990 }
991
992 return 0;
993 }
994
995 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
996 int clk_id, unsigned int freq, int dir)
997 {
998 struct snd_soc_codec *codec = codec_dai->codec;
999 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1000
1001 aic3x->sysclk = freq;
1002 return 0;
1003 }
1004
1005 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1006 unsigned int fmt)
1007 {
1008 struct snd_soc_codec *codec = codec_dai->codec;
1009 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1010 u8 iface_areg, iface_breg;
1011 int delay = 0;
1012
1013 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1014 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1015
1016 /* set master/slave audio interface */
1017 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1018 case SND_SOC_DAIFMT_CBM_CFM:
1019 aic3x->master = 1;
1020 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1021 break;
1022 case SND_SOC_DAIFMT_CBS_CFS:
1023 aic3x->master = 0;
1024 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 /*
1031 * match both interface format and signal polarities since they
1032 * are fixed
1033 */
1034 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1035 SND_SOC_DAIFMT_INV_MASK)) {
1036 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1037 break;
1038 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1039 delay = 1;
1040 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1041 iface_breg |= (0x01 << 6);
1042 break;
1043 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1044 iface_breg |= (0x02 << 6);
1045 break;
1046 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1047 iface_breg |= (0x03 << 6);
1048 break;
1049 default:
1050 return -EINVAL;
1051 }
1052
1053 /* set iface */
1054 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1055 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1056 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1057
1058 return 0;
1059 }
1060
1061 static int aic3x_init_3007(struct snd_soc_codec *codec)
1062 {
1063 u8 tmp1, tmp2, *cache = codec->reg_cache;
1064
1065 /*
1066 * There is no need to cache writes to undocumented page 0xD but
1067 * respective page 0 register cache entries must be preserved
1068 */
1069 tmp1 = cache[0xD];
1070 tmp2 = cache[0x8];
1071 /* Class-D speaker driver init; datasheet p. 46 */
1072 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1073 snd_soc_write(codec, 0xD, 0x0D);
1074 snd_soc_write(codec, 0x8, 0x5C);
1075 snd_soc_write(codec, 0x8, 0x5D);
1076 snd_soc_write(codec, 0x8, 0x5C);
1077 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1078 cache[0xD] = tmp1;
1079 cache[0x8] = tmp2;
1080
1081 return 0;
1082 }
1083
1084 static int aic3x_regulator_event(struct notifier_block *nb,
1085 unsigned long event, void *data)
1086 {
1087 struct aic3x_disable_nb *disable_nb =
1088 container_of(nb, struct aic3x_disable_nb, nb);
1089 struct aic3x_priv *aic3x = disable_nb->aic3x;
1090
1091 if (event & REGULATOR_EVENT_DISABLE) {
1092 /*
1093 * Put codec to reset and require cache sync as at least one
1094 * of the supplies was disabled
1095 */
1096 if (gpio_is_valid(aic3x->gpio_reset))
1097 gpio_set_value(aic3x->gpio_reset, 0);
1098 aic3x->codec->cache_sync = 1;
1099 }
1100
1101 return 0;
1102 }
1103
1104 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1105 {
1106 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1107 int i, ret;
1108 u8 *cache = codec->reg_cache;
1109
1110 if (power) {
1111 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1112 aic3x->supplies);
1113 if (ret)
1114 goto out;
1115 aic3x->power = 1;
1116 /*
1117 * Reset release and cache sync is necessary only if some
1118 * supply was off or if there were cached writes
1119 */
1120 if (!codec->cache_sync)
1121 goto out;
1122
1123 if (gpio_is_valid(aic3x->gpio_reset)) {
1124 udelay(1);
1125 gpio_set_value(aic3x->gpio_reset, 1);
1126 }
1127
1128 /* Sync reg_cache with the hardware */
1129 codec->cache_only = 0;
1130 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
1131 snd_soc_write(codec, i, cache[i]);
1132 if (aic3x->model == AIC3X_MODEL_3007)
1133 aic3x_init_3007(codec);
1134 codec->cache_sync = 0;
1135 } else {
1136 /*
1137 * Do soft reset to this codec instance in order to clear
1138 * possible VDD leakage currents in case the supply regulators
1139 * remain on
1140 */
1141 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1142 codec->cache_sync = 1;
1143 aic3x->power = 0;
1144 /* HW writes are needless when bias is off */
1145 codec->cache_only = 1;
1146 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1147 aic3x->supplies);
1148 }
1149 out:
1150 return ret;
1151 }
1152
1153 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1154 enum snd_soc_bias_level level)
1155 {
1156 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1157
1158 switch (level) {
1159 case SND_SOC_BIAS_ON:
1160 break;
1161 case SND_SOC_BIAS_PREPARE:
1162 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1163 aic3x->master) {
1164 /* enable pll */
1165 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1166 PLL_ENABLE, PLL_ENABLE);
1167 }
1168 break;
1169 case SND_SOC_BIAS_STANDBY:
1170 if (!aic3x->power)
1171 aic3x_set_power(codec, 1);
1172 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1173 aic3x->master) {
1174 /* disable pll */
1175 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1176 PLL_ENABLE, 0);
1177 }
1178 break;
1179 case SND_SOC_BIAS_OFF:
1180 if (aic3x->power)
1181 aic3x_set_power(codec, 0);
1182 break;
1183 }
1184 codec->dapm.bias_level = level;
1185
1186 return 0;
1187 }
1188
1189 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1190 {
1191 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1192 u8 bit = gpio ? 3: 0;
1193 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1194 snd_soc_write(codec, reg, val | (!!state << bit));
1195 }
1196 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1197
1198 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1199 {
1200 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1201 u8 val = 0, bit = gpio ? 2 : 1;
1202
1203 aic3x_read(codec, reg, &val);
1204 return (val >> bit) & 1;
1205 }
1206 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1207
1208 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1209 int headset_debounce, int button_debounce)
1210 {
1211 u8 val;
1212
1213 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1214 << AIC3X_HEADSET_DETECT_SHIFT) |
1215 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1216 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1217 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1218 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1219
1220 if (detect & AIC3X_HEADSET_DETECT_MASK)
1221 val |= AIC3X_HEADSET_DETECT_ENABLED;
1222
1223 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1224 }
1225 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1226
1227 int aic3x_headset_detected(struct snd_soc_codec *codec)
1228 {
1229 u8 val = 0;
1230 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1231 return (val >> 4) & 1;
1232 }
1233 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1234
1235 int aic3x_button_pressed(struct snd_soc_codec *codec)
1236 {
1237 u8 val = 0;
1238 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1239 return (val >> 5) & 1;
1240 }
1241 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1242
1243 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1244 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1245 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1246
1247 static struct snd_soc_dai_ops aic3x_dai_ops = {
1248 .hw_params = aic3x_hw_params,
1249 .digital_mute = aic3x_mute,
1250 .set_sysclk = aic3x_set_dai_sysclk,
1251 .set_fmt = aic3x_set_dai_fmt,
1252 };
1253
1254 static struct snd_soc_dai_driver aic3x_dai = {
1255 .name = "tlv320aic3x-hifi",
1256 .playback = {
1257 .stream_name = "Playback",
1258 .channels_min = 1,
1259 .channels_max = 2,
1260 .rates = AIC3X_RATES,
1261 .formats = AIC3X_FORMATS,},
1262 .capture = {
1263 .stream_name = "Capture",
1264 .channels_min = 1,
1265 .channels_max = 2,
1266 .rates = AIC3X_RATES,
1267 .formats = AIC3X_FORMATS,},
1268 .ops = &aic3x_dai_ops,
1269 .symmetric_rates = 1,
1270 };
1271
1272 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1273 {
1274 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1275
1276 return 0;
1277 }
1278
1279 static int aic3x_resume(struct snd_soc_codec *codec)
1280 {
1281 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1282
1283 return 0;
1284 }
1285
1286 /*
1287 * initialise the AIC3X driver
1288 * register the mixer and dsp interfaces with the kernel
1289 */
1290 static int aic3x_init(struct snd_soc_codec *codec)
1291 {
1292 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1293
1294 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1295 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1296
1297 /* DAC default volume and mute */
1298 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1299 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1300
1301 /* DAC to HP default volume and route to Output mixer */
1302 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1303 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1304 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1305 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1306 /* DAC to Line Out default volume and route to Output mixer */
1307 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1308 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1309 /* DAC to Mono Line Out default volume and route to Output mixer */
1310 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1311 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1312
1313 /* unmute all outputs */
1314 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1315 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1316 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1317 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1318 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1319 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1320 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1321
1322 /* ADC default volume and unmute */
1323 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1324 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1325 /* By default route Line1 to ADC PGA mixer */
1326 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1327 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1328
1329 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1330 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1331 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1332 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1333 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1334 /* PGA to Line Out default volume, disconnect from Output Mixer */
1335 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1336 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1337 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1338 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1339 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1340
1341 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1342 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1343 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1344 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1345 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1346 /* Line2 Line Out default volume, disconnect from Output Mixer */
1347 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1348 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1349 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1350 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1351 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1352
1353 if (aic3x->model == AIC3X_MODEL_3007) {
1354 aic3x_init_3007(codec);
1355 snd_soc_write(codec, CLASSD_CTRL, 0);
1356 }
1357
1358 return 0;
1359 }
1360
1361 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1362 {
1363 struct aic3x_priv *a;
1364
1365 list_for_each_entry(a, &reset_list, list) {
1366 if (gpio_is_valid(aic3x->gpio_reset) &&
1367 aic3x->gpio_reset == a->gpio_reset)
1368 return true;
1369 }
1370
1371 return false;
1372 }
1373
1374 static int aic3x_probe(struct snd_soc_codec *codec)
1375 {
1376 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1377 int ret, i;
1378
1379 INIT_LIST_HEAD(&aic3x->list);
1380 aic3x->codec = codec;
1381 codec->dapm.idle_bias_off = 1;
1382
1383 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1384 if (ret != 0) {
1385 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1386 return ret;
1387 }
1388
1389 if (gpio_is_valid(aic3x->gpio_reset) &&
1390 !aic3x_is_shared_reset(aic3x)) {
1391 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1392 if (ret != 0)
1393 goto err_gpio;
1394 gpio_direction_output(aic3x->gpio_reset, 0);
1395 }
1396
1397 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1398 aic3x->supplies[i].supply = aic3x_supply_names[i];
1399
1400 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1401 aic3x->supplies);
1402 if (ret != 0) {
1403 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1404 goto err_get;
1405 }
1406 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1407 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1408 aic3x->disable_nb[i].aic3x = aic3x;
1409 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1410 &aic3x->disable_nb[i].nb);
1411 if (ret) {
1412 dev_err(codec->dev,
1413 "Failed to request regulator notifier: %d\n",
1414 ret);
1415 goto err_notif;
1416 }
1417 }
1418
1419 codec->cache_only = 1;
1420 aic3x_init(codec);
1421
1422 if (aic3x->setup) {
1423 /* setup GPIO functions */
1424 snd_soc_write(codec, AIC3X_GPIO1_REG,
1425 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1426 snd_soc_write(codec, AIC3X_GPIO2_REG,
1427 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1428 }
1429
1430 snd_soc_add_controls(codec, aic3x_snd_controls,
1431 ARRAY_SIZE(aic3x_snd_controls));
1432 if (aic3x->model == AIC3X_MODEL_3007)
1433 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1434
1435 aic3x_add_widgets(codec);
1436 list_add(&aic3x->list, &reset_list);
1437
1438 return 0;
1439
1440 err_notif:
1441 while (i--)
1442 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1443 &aic3x->disable_nb[i].nb);
1444 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1445 err_get:
1446 if (gpio_is_valid(aic3x->gpio_reset) &&
1447 !aic3x_is_shared_reset(aic3x))
1448 gpio_free(aic3x->gpio_reset);
1449 err_gpio:
1450 return ret;
1451 }
1452
1453 static int aic3x_remove(struct snd_soc_codec *codec)
1454 {
1455 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1456 int i;
1457
1458 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1459 list_del(&aic3x->list);
1460 if (gpio_is_valid(aic3x->gpio_reset) &&
1461 !aic3x_is_shared_reset(aic3x)) {
1462 gpio_set_value(aic3x->gpio_reset, 0);
1463 gpio_free(aic3x->gpio_reset);
1464 }
1465 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1466 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1467 &aic3x->disable_nb[i].nb);
1468 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1469
1470 return 0;
1471 }
1472
1473 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1474 .set_bias_level = aic3x_set_bias_level,
1475 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1476 .reg_word_size = sizeof(u8),
1477 .reg_cache_default = aic3x_reg,
1478 .probe = aic3x_probe,
1479 .remove = aic3x_remove,
1480 .suspend = aic3x_suspend,
1481 .resume = aic3x_resume,
1482 };
1483
1484 /*
1485 * AIC3X 2 wire address can be up to 4 devices with device addresses
1486 * 0x18, 0x19, 0x1A, 0x1B
1487 */
1488
1489 static const struct i2c_device_id aic3x_i2c_id[] = {
1490 { "tlv320aic3x", AIC3X_MODEL_3X },
1491 { "tlv320aic33", AIC3X_MODEL_33 },
1492 { "tlv320aic3007", AIC3X_MODEL_3007 },
1493 { }
1494 };
1495 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1496
1497 /*
1498 * If the i2c layer weren't so broken, we could pass this kind of data
1499 * around
1500 */
1501 static int aic3x_i2c_probe(struct i2c_client *i2c,
1502 const struct i2c_device_id *id)
1503 {
1504 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1505 struct aic3x_priv *aic3x;
1506 int ret;
1507
1508 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1509 if (aic3x == NULL) {
1510 dev_err(&i2c->dev, "failed to create private data\n");
1511 return -ENOMEM;
1512 }
1513
1514 aic3x->control_type = SND_SOC_I2C;
1515
1516 i2c_set_clientdata(i2c, aic3x);
1517 if (pdata) {
1518 aic3x->gpio_reset = pdata->gpio_reset;
1519 aic3x->setup = pdata->setup;
1520 } else {
1521 aic3x->gpio_reset = -1;
1522 }
1523
1524 aic3x->model = id->driver_data;
1525
1526 ret = snd_soc_register_codec(&i2c->dev,
1527 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1528 if (ret < 0)
1529 kfree(aic3x);
1530 return ret;
1531 }
1532
1533 static int aic3x_i2c_remove(struct i2c_client *client)
1534 {
1535 snd_soc_unregister_codec(&client->dev);
1536 kfree(i2c_get_clientdata(client));
1537 return 0;
1538 }
1539
1540 /* machine i2c codec control layer */
1541 static struct i2c_driver aic3x_i2c_driver = {
1542 .driver = {
1543 .name = "tlv320aic3x-codec",
1544 .owner = THIS_MODULE,
1545 },
1546 .probe = aic3x_i2c_probe,
1547 .remove = aic3x_i2c_remove,
1548 .id_table = aic3x_i2c_id,
1549 };
1550
1551 static int __init aic3x_modinit(void)
1552 {
1553 int ret = 0;
1554 ret = i2c_add_driver(&aic3x_i2c_driver);
1555 if (ret != 0) {
1556 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1557 ret);
1558 }
1559 return ret;
1560 }
1561 module_init(aic3x_modinit);
1562
1563 static void __exit aic3x_exit(void)
1564 {
1565 i2c_del_driver(&aic3x_i2c_driver);
1566 }
1567 module_exit(aic3x_exit);
1568
1569 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1570 MODULE_AUTHOR("Vladimir Barinov");
1571 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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