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ASoC: tlv320aic3x: Convert SOC_ENUM_SINGLE/DOUBLE arrays to individual
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/of.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 static LIST_HEAD(reset_list);
65
66 struct aic3x_priv;
67
68 struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71 };
72
73 /* codec private data */
74 struct aic3x_priv {
75 struct snd_soc_codec *codec;
76 struct regmap *regmap;
77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
79 struct aic3x_setup_data *setup;
80 unsigned int sysclk;
81 unsigned int dai_fmt;
82 unsigned int tdm_delay;
83 struct list_head list;
84 int master;
85 int gpio_reset;
86 int power;
87 #define AIC3X_MODEL_3X 0
88 #define AIC3X_MODEL_33 1
89 #define AIC3X_MODEL_3007 2
90 u16 model;
91
92 /* Selects the micbias voltage */
93 enum aic3x_micbias_voltage micbias_vg;
94 };
95
96 static const struct reg_default aic3x_reg[] = {
97 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
98 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
99 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
100 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
101 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
102 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
103 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
104 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
105 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
106 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
107 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
108 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
109 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
110 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
111 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
112 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
113 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
114 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
115 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
116 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
117 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
118 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
119 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
120 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
121 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
122 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
123 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
124 { 108, 0x00 }, { 109, 0x00 },
125 };
126
127 static const struct regmap_config aic3x_regmap = {
128 .reg_bits = 8,
129 .val_bits = 8,
130
131 .max_register = DAC_ICC_ADJ,
132 .reg_defaults = aic3x_reg,
133 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
134 .cache_type = REGCACHE_RBTREE,
135 };
136
137 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
138 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
139 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
140
141 /*
142 * All input lines are connected when !0xf and disconnected with 0xf bit field,
143 * so we have to use specific dapm_put call for input mixer
144 */
145 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
146 struct snd_ctl_elem_value *ucontrol)
147 {
148 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
149 struct soc_mixer_control *mc =
150 (struct soc_mixer_control *)kcontrol->private_value;
151 unsigned int reg = mc->reg;
152 unsigned int shift = mc->shift;
153 int max = mc->max;
154 unsigned int mask = (1 << fls(max)) - 1;
155 unsigned int invert = mc->invert;
156 unsigned short val;
157 struct snd_soc_dapm_update update;
158 int connect, change;
159
160 val = (ucontrol->value.integer.value[0] & mask);
161
162 mask = 0xf;
163 if (val)
164 val = mask;
165
166 connect = !!val;
167
168 if (invert)
169 val = mask - val;
170
171 mask <<= shift;
172 val <<= shift;
173
174 change = snd_soc_test_bits(codec, reg, mask, val);
175 if (change) {
176 update.kcontrol = kcontrol;
177 update.reg = reg;
178 update.mask = mask;
179 update.val = val;
180
181 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
182 &update);
183 }
184
185 return change;
186 }
187
188 /*
189 * mic bias power on/off share the same register bits with
190 * output voltage of mic bias. when power on mic bias, we
191 * need reclaim it to voltage value.
192 * 0x0 = Powered off
193 * 0x1 = MICBIAS output is powered to 2.0V,
194 * 0x2 = MICBIAS output is powered to 2.5V
195 * 0x3 = MICBIAS output is connected to AVDD
196 */
197 static int mic_bias_event(struct snd_soc_dapm_widget *w,
198 struct snd_kcontrol *kcontrol, int event)
199 {
200 struct snd_soc_codec *codec = w->codec;
201 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
202
203 switch (event) {
204 case SND_SOC_DAPM_POST_PMU:
205 /* change mic bias voltage to user defined */
206 snd_soc_update_bits(codec, MICBIAS_CTRL,
207 MICBIAS_LEVEL_MASK,
208 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
209 break;
210
211 case SND_SOC_DAPM_PRE_PMD:
212 snd_soc_update_bits(codec, MICBIAS_CTRL,
213 MICBIAS_LEVEL_MASK, 0);
214 break;
215 }
216 return 0;
217 }
218
219 static const char * const aic3x_left_dac_mux[] = {
220 "DAC_L1", "DAC_L3", "DAC_L2" };
221 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
222 aic3x_left_dac_mux);
223
224 static const char * const aic3x_right_dac_mux[] = {
225 "DAC_R1", "DAC_R3", "DAC_R2" };
226 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
227 aic3x_right_dac_mux);
228
229 static const char * const aic3x_left_hpcom_mux[] = {
230 "differential of HPLOUT", "constant VCM", "single-ended" };
231 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
232 aic3x_left_hpcom_mux);
233
234 static const char * const aic3x_right_hpcom_mux[] = {
235 "differential of HPROUT", "constant VCM", "single-ended",
236 "differential of HPLCOM", "external feedback" };
237 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
238 aic3x_right_hpcom_mux);
239
240 static const char * const aic3x_linein_mode_mux[] = {
241 "single-ended", "differential" };
242 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
243 aic3x_linein_mode_mux);
244 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
245 aic3x_linein_mode_mux);
246 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
247 aic3x_linein_mode_mux);
248 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
249 aic3x_linein_mode_mux);
250 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
251 aic3x_linein_mode_mux);
252 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
253 aic3x_linein_mode_mux);
254
255 static const char * const aic3x_adc_hpf[] = {
256 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
257 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
258 aic3x_adc_hpf);
259
260 static const char * const aic3x_agc_level[] = {
261 "-5.5dB", "-8dB", "-10dB", "-12dB",
262 "-14dB", "-17dB", "-20dB", "-24dB" };
263 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
264 aic3x_agc_level);
265 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
266 aic3x_agc_level);
267
268 static const char * const aic3x_agc_attack[] = {
269 "8ms", "11ms", "16ms", "20ms" };
270 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
271 aic3x_agc_attack);
272 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
273 aic3x_agc_attack);
274
275 static const char * const aic3x_agc_decay[] = {
276 "100ms", "200ms", "400ms", "500ms" };
277 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
278 aic3x_agc_decay);
279 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
280 aic3x_agc_decay);
281
282 /*
283 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
284 */
285 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
286 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
287 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
288 /*
289 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
290 * Step size is approximately 0.5 dB over most of the scale but increasing
291 * near the very low levels.
292 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
293 * but having increasing dB difference below that (and where it doesn't count
294 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
295 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
296 */
297 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
298
299 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
300 /* Output */
301 SOC_DOUBLE_R_TLV("PCM Playback Volume",
302 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
303
304 /*
305 * Output controls that map to output mixer switches. Note these are
306 * only for swapped L-to-R and R-to-L routes. See below stereo controls
307 * for direct L-to-L and R-to-R routes.
308 */
309 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
310 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
312 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
313 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
314 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
315
316 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
317 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
319 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
320 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
321 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
322
323 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
324 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
326 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
327 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
328 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
329
330 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
331 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
333 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
334 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
335 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
336
337 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
338 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
340 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
341 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
342 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
343
344 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
345 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
346 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
347 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
348 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
349 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350
351 /* Stereo output controls for direct L-to-L and R-to-R routes */
352 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
353 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
354 0, 118, 1, output_stage_tlv),
355 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
356 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
357 0, 118, 1, output_stage_tlv),
358 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
359 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
360 0, 118, 1, output_stage_tlv),
361
362 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
363 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
364 0, 118, 1, output_stage_tlv),
365 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
366 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
367 0, 118, 1, output_stage_tlv),
368 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
369 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
370 0, 118, 1, output_stage_tlv),
371
372 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
373 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
374 0, 118, 1, output_stage_tlv),
375 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
376 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
377 0, 118, 1, output_stage_tlv),
378 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
379 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
380 0, 118, 1, output_stage_tlv),
381
382 /* Output pin mute controls */
383 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
384 0x01, 0),
385 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
386 0x01, 0),
387 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
388 0x01, 0),
389
390 /*
391 * Note: enable Automatic input Gain Controller with care. It can
392 * adjust PGA to max value when ADC is on and will never go back.
393 */
394 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
395 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
396 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
397 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
398 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
399 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
400 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
401
402 /* De-emphasis */
403 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
404
405 /* Input */
406 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
407 0, 119, 0, adc_tlv),
408 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
409
410 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
411 };
412
413 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
414 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
415 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
416 0, 118, 1, output_stage_tlv),
417 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
418 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
419 0, 118, 1, output_stage_tlv),
420 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
421 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
422 0, 118, 1, output_stage_tlv),
423
424 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
425 };
426
427 /*
428 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
429 */
430 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
431
432 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
433 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
434
435 /* Left DAC Mux */
436 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
437 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
438
439 /* Right DAC Mux */
440 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
441 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
442
443 /* Left HPCOM Mux */
444 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
445 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
446
447 /* Right HPCOM Mux */
448 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
449 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
450
451 /* Left Line Mixer */
452 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
453 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
459 };
460
461 /* Right Line Mixer */
462 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
463 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
469 };
470
471 /* Mono Mixer */
472 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
473 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
479 };
480
481 /* Left HP Mixer */
482 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
483 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
484 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
489 };
490
491 /* Right HP Mixer */
492 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
493 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
499 };
500
501 /* Left HPCOM Mixer */
502 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
503 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
504 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
509 };
510
511 /* Right HPCOM Mixer */
512 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
513 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
514 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
515 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
516 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
519 };
520
521 /* Left PGA Mixer */
522 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
523 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
524 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
525 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
526 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
527 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
528 };
529
530 /* Right PGA Mixer */
531 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
532 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
533 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
534 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
535 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
536 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
537 };
538
539 /* Left Line1 Mux */
540 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
541 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
542 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
543 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
544
545 /* Right Line1 Mux */
546 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
547 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
548 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
549 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
550
551 /* Left Line2 Mux */
552 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
553 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
554
555 /* Right Line2 Mux */
556 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
557 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
558
559 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
560 /* Left DAC to Left Outputs */
561 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
562 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
563 &aic3x_left_dac_mux_controls),
564 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
565 &aic3x_left_hpcom_mux_controls),
566 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
567 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
568 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
569
570 /* Right DAC to Right Outputs */
571 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
572 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
573 &aic3x_right_dac_mux_controls),
574 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
575 &aic3x_right_hpcom_mux_controls),
576 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
577 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
578 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
579
580 /* Inputs to Left ADC */
581 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
582 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
583 &aic3x_left_pga_mixer_controls[0],
584 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
585 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
586 &aic3x_left_line1l_mux_controls),
587 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
588 &aic3x_left_line1r_mux_controls),
589 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
590 &aic3x_left_line2_mux_controls),
591
592 /* Inputs to Right ADC */
593 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
594 LINE1R_2_RADC_CTRL, 2, 0),
595 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
596 &aic3x_right_pga_mixer_controls[0],
597 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
598 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
599 &aic3x_right_line1l_mux_controls),
600 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
601 &aic3x_right_line1r_mux_controls),
602 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
603 &aic3x_right_line2_mux_controls),
604
605 /*
606 * Not a real mic bias widget but similar function. This is for dynamic
607 * control of GPIO1 digital mic modulator clock output function when
608 * using digital mic.
609 */
610 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
611 AIC3X_GPIO1_REG, 4, 0xf,
612 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
613 AIC3X_GPIO1_FUNC_DISABLED),
614
615 /*
616 * Also similar function like mic bias. Selects digital mic with
617 * configurable oversampling rate instead of ADC converter.
618 */
619 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
620 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
621 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
622 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
623 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
624 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
625
626 /* Mic Bias */
627 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
628 mic_bias_event,
629 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
630
631 /* Output mixers */
632 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
633 &aic3x_left_line_mixer_controls[0],
634 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
635 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
636 &aic3x_right_line_mixer_controls[0],
637 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
638 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
639 &aic3x_left_hp_mixer_controls[0],
640 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
641 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
642 &aic3x_right_hp_mixer_controls[0],
643 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
644 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
645 &aic3x_left_hpcom_mixer_controls[0],
646 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
647 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
648 &aic3x_right_hpcom_mixer_controls[0],
649 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
650
651 SND_SOC_DAPM_OUTPUT("LLOUT"),
652 SND_SOC_DAPM_OUTPUT("RLOUT"),
653 SND_SOC_DAPM_OUTPUT("HPLOUT"),
654 SND_SOC_DAPM_OUTPUT("HPROUT"),
655 SND_SOC_DAPM_OUTPUT("HPLCOM"),
656 SND_SOC_DAPM_OUTPUT("HPRCOM"),
657
658 SND_SOC_DAPM_INPUT("MIC3L"),
659 SND_SOC_DAPM_INPUT("MIC3R"),
660 SND_SOC_DAPM_INPUT("LINE1L"),
661 SND_SOC_DAPM_INPUT("LINE1R"),
662 SND_SOC_DAPM_INPUT("LINE2L"),
663 SND_SOC_DAPM_INPUT("LINE2R"),
664
665 /*
666 * Virtual output pin to detection block inside codec. This can be
667 * used to keep codec bias on if gpio or detection features are needed.
668 * Force pin on or construct a path with an input jack and mic bias
669 * widgets.
670 */
671 SND_SOC_DAPM_OUTPUT("Detection"),
672 };
673
674 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
675 /* Mono Output */
676 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
677
678 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
679 &aic3x_mono_mixer_controls[0],
680 ARRAY_SIZE(aic3x_mono_mixer_controls)),
681
682 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
683 };
684
685 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
686 /* Class-D outputs */
687 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
688 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
689
690 SND_SOC_DAPM_OUTPUT("SPOP"),
691 SND_SOC_DAPM_OUTPUT("SPOM"),
692 };
693
694 static const struct snd_soc_dapm_route intercon[] = {
695 /* Left Input */
696 {"Left Line1L Mux", "single-ended", "LINE1L"},
697 {"Left Line1L Mux", "differential", "LINE1L"},
698 {"Left Line1R Mux", "single-ended", "LINE1R"},
699 {"Left Line1R Mux", "differential", "LINE1R"},
700
701 {"Left Line2L Mux", "single-ended", "LINE2L"},
702 {"Left Line2L Mux", "differential", "LINE2L"},
703
704 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
705 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
706 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
707 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
708 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
709
710 {"Left ADC", NULL, "Left PGA Mixer"},
711 {"Left ADC", NULL, "GPIO1 dmic modclk"},
712
713 /* Right Input */
714 {"Right Line1R Mux", "single-ended", "LINE1R"},
715 {"Right Line1R Mux", "differential", "LINE1R"},
716 {"Right Line1L Mux", "single-ended", "LINE1L"},
717 {"Right Line1L Mux", "differential", "LINE1L"},
718
719 {"Right Line2R Mux", "single-ended", "LINE2R"},
720 {"Right Line2R Mux", "differential", "LINE2R"},
721
722 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
723 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
724 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
725 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
726 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
727
728 {"Right ADC", NULL, "Right PGA Mixer"},
729 {"Right ADC", NULL, "GPIO1 dmic modclk"},
730
731 /*
732 * Logical path between digital mic enable and GPIO1 modulator clock
733 * output function
734 */
735 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
736 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
737 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
738
739 /* Left DAC Output */
740 {"Left DAC Mux", "DAC_L1", "Left DAC"},
741 {"Left DAC Mux", "DAC_L2", "Left DAC"},
742 {"Left DAC Mux", "DAC_L3", "Left DAC"},
743
744 /* Right DAC Output */
745 {"Right DAC Mux", "DAC_R1", "Right DAC"},
746 {"Right DAC Mux", "DAC_R2", "Right DAC"},
747 {"Right DAC Mux", "DAC_R3", "Right DAC"},
748
749 /* Left Line Output */
750 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
751 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
752 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
753 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
754 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
755 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
756
757 {"Left Line Out", NULL, "Left Line Mixer"},
758 {"Left Line Out", NULL, "Left DAC Mux"},
759 {"LLOUT", NULL, "Left Line Out"},
760
761 /* Right Line Output */
762 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
763 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
764 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
765 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
766 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
767 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
768
769 {"Right Line Out", NULL, "Right Line Mixer"},
770 {"Right Line Out", NULL, "Right DAC Mux"},
771 {"RLOUT", NULL, "Right Line Out"},
772
773 /* Left HP Output */
774 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
775 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
776 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
777 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
778 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
779 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
780
781 {"Left HP Out", NULL, "Left HP Mixer"},
782 {"Left HP Out", NULL, "Left DAC Mux"},
783 {"HPLOUT", NULL, "Left HP Out"},
784
785 /* Right HP Output */
786 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
787 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
788 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
789 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
790 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
791 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
792
793 {"Right HP Out", NULL, "Right HP Mixer"},
794 {"Right HP Out", NULL, "Right DAC Mux"},
795 {"HPROUT", NULL, "Right HP Out"},
796
797 /* Left HPCOM Output */
798 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
799 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
800 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
801 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
802 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
803 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
804
805 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
806 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
807 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
808 {"Left HP Com", NULL, "Left HPCOM Mux"},
809 {"HPLCOM", NULL, "Left HP Com"},
810
811 /* Right HPCOM Output */
812 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
813 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
814 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
815 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
816 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
817 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
818
819 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
820 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
821 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
822 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
823 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
824 {"Right HP Com", NULL, "Right HPCOM Mux"},
825 {"HPRCOM", NULL, "Right HP Com"},
826 };
827
828 static const struct snd_soc_dapm_route intercon_mono[] = {
829 /* Mono Output */
830 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
831 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
832 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
833 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
834 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
835 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
836 {"Mono Out", NULL, "Mono Mixer"},
837 {"MONO_LOUT", NULL, "Mono Out"},
838 };
839
840 static const struct snd_soc_dapm_route intercon_3007[] = {
841 /* Class-D outputs */
842 {"Left Class-D Out", NULL, "Left Line Out"},
843 {"Right Class-D Out", NULL, "Left Line Out"},
844 {"SPOP", NULL, "Left Class-D Out"},
845 {"SPOM", NULL, "Right Class-D Out"},
846 };
847
848 static int aic3x_add_widgets(struct snd_soc_codec *codec)
849 {
850 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
851 struct snd_soc_dapm_context *dapm = &codec->dapm;
852
853 switch (aic3x->model) {
854 case AIC3X_MODEL_3X:
855 case AIC3X_MODEL_33:
856 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
857 ARRAY_SIZE(aic3x_dapm_mono_widgets));
858 snd_soc_dapm_add_routes(dapm, intercon_mono,
859 ARRAY_SIZE(intercon_mono));
860 break;
861 case AIC3X_MODEL_3007:
862 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
863 ARRAY_SIZE(aic3007_dapm_widgets));
864 snd_soc_dapm_add_routes(dapm, intercon_3007,
865 ARRAY_SIZE(intercon_3007));
866 break;
867 }
868
869 return 0;
870 }
871
872 static int aic3x_hw_params(struct snd_pcm_substream *substream,
873 struct snd_pcm_hw_params *params,
874 struct snd_soc_dai *dai)
875 {
876 struct snd_soc_codec *codec = dai->codec;
877 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
878 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
879 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
880 u16 d, pll_d = 1;
881 int clk;
882
883 /* select data word length */
884 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
885 switch (params_width(params)) {
886 case 16:
887 break;
888 case 20:
889 data |= (0x01 << 4);
890 break;
891 case 24:
892 data |= (0x02 << 4);
893 break;
894 case 32:
895 data |= (0x03 << 4);
896 break;
897 }
898 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
899
900 /* Fsref can be 44100 or 48000 */
901 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
902
903 /* Try to find a value for Q which allows us to bypass the PLL and
904 * generate CODEC_CLK directly. */
905 for (pll_q = 2; pll_q < 18; pll_q++)
906 if (aic3x->sysclk / (128 * pll_q) == fsref) {
907 bypass_pll = 1;
908 break;
909 }
910
911 if (bypass_pll) {
912 pll_q &= 0xf;
913 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
914 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
915 /* disable PLL if it is bypassed */
916 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
917
918 } else {
919 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
920 /* enable PLL when it is used */
921 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
922 PLL_ENABLE, PLL_ENABLE);
923 }
924
925 /* Route Left DAC to left channel input and
926 * right DAC to right channel input */
927 data = (LDAC2LCH | RDAC2RCH);
928 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
929 if (params_rate(params) >= 64000)
930 data |= DUAL_RATE_MODE;
931 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
932
933 /* codec sample rate select */
934 data = (fsref * 20) / params_rate(params);
935 if (params_rate(params) < 64000)
936 data /= 2;
937 data /= 5;
938 data -= 2;
939 data |= (data << 4);
940 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
941
942 if (bypass_pll)
943 return 0;
944
945 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
946 * one wins the game. Try with d==0 first, next with d!=0.
947 * Constraints for j are according to the datasheet.
948 * The sysclk is divided by 1000 to prevent integer overflows.
949 */
950
951 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
952
953 for (r = 1; r <= 16; r++)
954 for (p = 1; p <= 8; p++) {
955 for (j = 4; j <= 55; j++) {
956 /* This is actually 1000*((j+(d/10000))*r)/p
957 * The term had to be converted to get
958 * rid of the division by 10000; d = 0 here
959 */
960 int tmp_clk = (1000 * j * r) / p;
961
962 /* Check whether this values get closer than
963 * the best ones we had before
964 */
965 if (abs(codec_clk - tmp_clk) <
966 abs(codec_clk - last_clk)) {
967 pll_j = j; pll_d = 0;
968 pll_r = r; pll_p = p;
969 last_clk = tmp_clk;
970 }
971
972 /* Early exit for exact matches */
973 if (tmp_clk == codec_clk)
974 goto found;
975 }
976 }
977
978 /* try with d != 0 */
979 for (p = 1; p <= 8; p++) {
980 j = codec_clk * p / 1000;
981
982 if (j < 4 || j > 11)
983 continue;
984
985 /* do not use codec_clk here since we'd loose precision */
986 d = ((2048 * p * fsref) - j * aic3x->sysclk)
987 * 100 / (aic3x->sysclk/100);
988
989 clk = (10000 * j + d) / (10 * p);
990
991 /* check whether this values get closer than the best
992 * ones we had before */
993 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
994 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
995 last_clk = clk;
996 }
997
998 /* Early exit for exact matches */
999 if (clk == codec_clk)
1000 goto found;
1001 }
1002
1003 if (last_clk == 0) {
1004 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1005 return -EINVAL;
1006 }
1007
1008 found:
1009 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1010 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1011 pll_r << PLLR_SHIFT);
1012 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1013 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1014 (pll_d >> 6) << PLLD_MSB_SHIFT);
1015 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1016 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1017
1018 return 0;
1019 }
1020
1021 static int aic3x_prepare(struct snd_pcm_substream *substream,
1022 struct snd_soc_dai *dai)
1023 {
1024 struct snd_soc_codec *codec = dai->codec;
1025 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1026 int delay = 0;
1027
1028 /* TDM slot selection only valid in DSP_A/_B mode */
1029 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1030 delay += (aic3x->tdm_delay + 1);
1031 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1032 delay += aic3x->tdm_delay;
1033
1034 /* Configure data delay */
1035 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, aic3x->tdm_delay);
1036
1037 return 0;
1038 }
1039
1040 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1041 {
1042 struct snd_soc_codec *codec = dai->codec;
1043 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1044 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1045
1046 if (mute) {
1047 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1048 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1049 } else {
1050 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1051 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1052 }
1053
1054 return 0;
1055 }
1056
1057 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1058 int clk_id, unsigned int freq, int dir)
1059 {
1060 struct snd_soc_codec *codec = codec_dai->codec;
1061 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1062
1063 /* set clock on MCLK or GPIO2 or BCLK */
1064 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1065 clk_id << PLLCLK_IN_SHIFT);
1066 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1067 clk_id << CLKDIV_IN_SHIFT);
1068
1069 aic3x->sysclk = freq;
1070 return 0;
1071 }
1072
1073 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1074 unsigned int fmt)
1075 {
1076 struct snd_soc_codec *codec = codec_dai->codec;
1077 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1078 u8 iface_areg, iface_breg;
1079
1080 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1081 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1082
1083 /* set master/slave audio interface */
1084 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1085 case SND_SOC_DAIFMT_CBM_CFM:
1086 aic3x->master = 1;
1087 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1088 break;
1089 case SND_SOC_DAIFMT_CBS_CFS:
1090 aic3x->master = 0;
1091 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1092 break;
1093 default:
1094 return -EINVAL;
1095 }
1096
1097 /*
1098 * match both interface format and signal polarities since they
1099 * are fixed
1100 */
1101 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1102 SND_SOC_DAIFMT_INV_MASK)) {
1103 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1104 break;
1105 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1106 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1107 iface_breg |= (0x01 << 6);
1108 break;
1109 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1110 iface_breg |= (0x02 << 6);
1111 break;
1112 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1113 iface_breg |= (0x03 << 6);
1114 break;
1115 default:
1116 return -EINVAL;
1117 }
1118
1119 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1120
1121 /* set iface */
1122 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1123 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1124
1125 return 0;
1126 }
1127
1128 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1129 unsigned int tx_mask, unsigned int rx_mask,
1130 int slots, int slot_width)
1131 {
1132 struct snd_soc_codec *codec = codec_dai->codec;
1133 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1134 unsigned int lsb;
1135
1136 if (tx_mask != rx_mask) {
1137 dev_err(codec->dev, "tx and rx masks must be symmetric\n");
1138 return -EINVAL;
1139 }
1140
1141 if (unlikely(!tx_mask)) {
1142 dev_err(codec->dev, "tx and rx masks need to be non 0\n");
1143 return -EINVAL;
1144 }
1145
1146 /* TDM based on DSP mode requires slots to be adjacent */
1147 lsb = __ffs(tx_mask);
1148 if ((lsb + 1) != __fls(tx_mask)) {
1149 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n");
1150 return -EINVAL;
1151 }
1152
1153 aic3x->tdm_delay = lsb * slot_width;
1154
1155 /* DOUT in high-impedance on inactive bit clocks */
1156 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
1157 DOUT_TRISTATE, DOUT_TRISTATE);
1158
1159 return 0;
1160 }
1161
1162 static int aic3x_regulator_event(struct notifier_block *nb,
1163 unsigned long event, void *data)
1164 {
1165 struct aic3x_disable_nb *disable_nb =
1166 container_of(nb, struct aic3x_disable_nb, nb);
1167 struct aic3x_priv *aic3x = disable_nb->aic3x;
1168
1169 if (event & REGULATOR_EVENT_DISABLE) {
1170 /*
1171 * Put codec to reset and require cache sync as at least one
1172 * of the supplies was disabled
1173 */
1174 if (gpio_is_valid(aic3x->gpio_reset))
1175 gpio_set_value(aic3x->gpio_reset, 0);
1176 regcache_mark_dirty(aic3x->regmap);
1177 }
1178
1179 return 0;
1180 }
1181
1182 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1183 {
1184 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1185 unsigned int pll_c, pll_d;
1186 int ret;
1187
1188 if (power) {
1189 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1190 aic3x->supplies);
1191 if (ret)
1192 goto out;
1193 aic3x->power = 1;
1194
1195 if (gpio_is_valid(aic3x->gpio_reset)) {
1196 udelay(1);
1197 gpio_set_value(aic3x->gpio_reset, 1);
1198 }
1199
1200 /* Sync reg_cache with the hardware */
1201 regcache_cache_only(aic3x->regmap, false);
1202 regcache_sync(aic3x->regmap);
1203
1204 /* Rewrite paired PLL D registers in case cached sync skipped
1205 * writing one of them and thus caused other one also not
1206 * being written
1207 */
1208 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1209 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1210 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1211 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1212 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1213 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1214 }
1215 } else {
1216 /*
1217 * Do soft reset to this codec instance in order to clear
1218 * possible VDD leakage currents in case the supply regulators
1219 * remain on
1220 */
1221 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1222 regcache_mark_dirty(aic3x->regmap);
1223 aic3x->power = 0;
1224 /* HW writes are needless when bias is off */
1225 regcache_cache_only(aic3x->regmap, true);
1226 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1227 aic3x->supplies);
1228 }
1229 out:
1230 return ret;
1231 }
1232
1233 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1234 enum snd_soc_bias_level level)
1235 {
1236 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1237
1238 switch (level) {
1239 case SND_SOC_BIAS_ON:
1240 break;
1241 case SND_SOC_BIAS_PREPARE:
1242 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1243 aic3x->master) {
1244 /* enable pll */
1245 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1246 PLL_ENABLE, PLL_ENABLE);
1247 }
1248 break;
1249 case SND_SOC_BIAS_STANDBY:
1250 if (!aic3x->power)
1251 aic3x_set_power(codec, 1);
1252 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1253 aic3x->master) {
1254 /* disable pll */
1255 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1256 PLL_ENABLE, 0);
1257 }
1258 break;
1259 case SND_SOC_BIAS_OFF:
1260 if (aic3x->power)
1261 aic3x_set_power(codec, 0);
1262 break;
1263 }
1264 codec->dapm.bias_level = level;
1265
1266 return 0;
1267 }
1268
1269 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1270 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1271 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1272 SNDRV_PCM_FMTBIT_S32_LE)
1273
1274 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1275 .hw_params = aic3x_hw_params,
1276 .prepare = aic3x_prepare,
1277 .digital_mute = aic3x_mute,
1278 .set_sysclk = aic3x_set_dai_sysclk,
1279 .set_fmt = aic3x_set_dai_fmt,
1280 .set_tdm_slot = aic3x_set_dai_tdm_slot,
1281 };
1282
1283 static struct snd_soc_dai_driver aic3x_dai = {
1284 .name = "tlv320aic3x-hifi",
1285 .playback = {
1286 .stream_name = "Playback",
1287 .channels_min = 2,
1288 .channels_max = 2,
1289 .rates = AIC3X_RATES,
1290 .formats = AIC3X_FORMATS,},
1291 .capture = {
1292 .stream_name = "Capture",
1293 .channels_min = 2,
1294 .channels_max = 2,
1295 .rates = AIC3X_RATES,
1296 .formats = AIC3X_FORMATS,},
1297 .ops = &aic3x_dai_ops,
1298 .symmetric_rates = 1,
1299 };
1300
1301 static void aic3x_mono_init(struct snd_soc_codec *codec)
1302 {
1303 /* DAC to Mono Line Out default volume and route to Output mixer */
1304 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1305 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1306
1307 /* unmute all outputs */
1308 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1309
1310 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1311 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1312 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1313
1314 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1315 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1316 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1317 }
1318
1319 /*
1320 * initialise the AIC3X driver
1321 * register the mixer and dsp interfaces with the kernel
1322 */
1323 static int aic3x_init(struct snd_soc_codec *codec)
1324 {
1325 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1326
1327 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1328 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1329
1330 /* DAC default volume and mute */
1331 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1332 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1333
1334 /* DAC to HP default volume and route to Output mixer */
1335 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1336 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1337 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1338 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1339 /* DAC to Line Out default volume and route to Output mixer */
1340 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1341 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1342
1343 /* unmute all outputs */
1344 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1345 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1346 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1347 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1348 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1349 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1350
1351 /* ADC default volume and unmute */
1352 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1353 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1354 /* By default route Line1 to ADC PGA mixer */
1355 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1356 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1357
1358 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1359 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1360 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1361 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1362 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1363 /* PGA to Line Out default volume, disconnect from Output Mixer */
1364 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1365 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1366
1367 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1368 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1369 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1370 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1371 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1372 /* Line2 Line Out default volume, disconnect from Output Mixer */
1373 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1374 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1375
1376 switch (aic3x->model) {
1377 case AIC3X_MODEL_3X:
1378 case AIC3X_MODEL_33:
1379 aic3x_mono_init(codec);
1380 break;
1381 case AIC3X_MODEL_3007:
1382 snd_soc_write(codec, CLASSD_CTRL, 0);
1383 break;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1390 {
1391 struct aic3x_priv *a;
1392
1393 list_for_each_entry(a, &reset_list, list) {
1394 if (gpio_is_valid(aic3x->gpio_reset) &&
1395 aic3x->gpio_reset == a->gpio_reset)
1396 return true;
1397 }
1398
1399 return false;
1400 }
1401
1402 static int aic3x_probe(struct snd_soc_codec *codec)
1403 {
1404 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1405 int ret, i;
1406
1407 INIT_LIST_HEAD(&aic3x->list);
1408 aic3x->codec = codec;
1409
1410 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1411 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1412 aic3x->disable_nb[i].aic3x = aic3x;
1413 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1414 &aic3x->disable_nb[i].nb);
1415 if (ret) {
1416 dev_err(codec->dev,
1417 "Failed to request regulator notifier: %d\n",
1418 ret);
1419 goto err_notif;
1420 }
1421 }
1422
1423 regcache_mark_dirty(aic3x->regmap);
1424 aic3x_init(codec);
1425
1426 if (aic3x->setup) {
1427 /* setup GPIO functions */
1428 snd_soc_write(codec, AIC3X_GPIO1_REG,
1429 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1430 snd_soc_write(codec, AIC3X_GPIO2_REG,
1431 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1432 }
1433
1434 switch (aic3x->model) {
1435 case AIC3X_MODEL_3X:
1436 case AIC3X_MODEL_33:
1437 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1438 ARRAY_SIZE(aic3x_mono_controls));
1439 break;
1440 case AIC3X_MODEL_3007:
1441 snd_soc_add_codec_controls(codec,
1442 &aic3x_classd_amp_gain_ctrl, 1);
1443 break;
1444 }
1445
1446 /* set mic bias voltage */
1447 switch (aic3x->micbias_vg) {
1448 case AIC3X_MICBIAS_2_0V:
1449 case AIC3X_MICBIAS_2_5V:
1450 case AIC3X_MICBIAS_AVDDV:
1451 snd_soc_update_bits(codec, MICBIAS_CTRL,
1452 MICBIAS_LEVEL_MASK,
1453 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1454 break;
1455 case AIC3X_MICBIAS_OFF:
1456 /*
1457 * noting to do. target won't enter here. This is just to avoid
1458 * compile time warning "warning: enumeration value
1459 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1460 */
1461 break;
1462 }
1463
1464 aic3x_add_widgets(codec);
1465
1466 return 0;
1467
1468 err_notif:
1469 while (i--)
1470 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1471 &aic3x->disable_nb[i].nb);
1472 return ret;
1473 }
1474
1475 static int aic3x_remove(struct snd_soc_codec *codec)
1476 {
1477 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1478 int i;
1479
1480 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1481 list_del(&aic3x->list);
1482 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1483 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1484 &aic3x->disable_nb[i].nb);
1485
1486 return 0;
1487 }
1488
1489 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1490 .set_bias_level = aic3x_set_bias_level,
1491 .idle_bias_off = true,
1492 .probe = aic3x_probe,
1493 .remove = aic3x_remove,
1494 .controls = aic3x_snd_controls,
1495 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1496 .dapm_widgets = aic3x_dapm_widgets,
1497 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1498 .dapm_routes = intercon,
1499 .num_dapm_routes = ARRAY_SIZE(intercon),
1500 };
1501
1502 /*
1503 * AIC3X 2 wire address can be up to 4 devices with device addresses
1504 * 0x18, 0x19, 0x1A, 0x1B
1505 */
1506
1507 static const struct i2c_device_id aic3x_i2c_id[] = {
1508 { "tlv320aic3x", AIC3X_MODEL_3X },
1509 { "tlv320aic33", AIC3X_MODEL_33 },
1510 { "tlv320aic3007", AIC3X_MODEL_3007 },
1511 { "tlv320aic3106", AIC3X_MODEL_3X },
1512 { }
1513 };
1514 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1515
1516 static const struct reg_default aic3007_class_d[] = {
1517 /* Class-D speaker driver init; datasheet p. 46 */
1518 { AIC3X_PAGE_SELECT, 0x0D },
1519 { 0xD, 0x0D },
1520 { 0x8, 0x5C },
1521 { 0x8, 0x5D },
1522 { 0x8, 0x5C },
1523 { AIC3X_PAGE_SELECT, 0x00 },
1524 };
1525
1526 /*
1527 * If the i2c layer weren't so broken, we could pass this kind of data
1528 * around
1529 */
1530 static int aic3x_i2c_probe(struct i2c_client *i2c,
1531 const struct i2c_device_id *id)
1532 {
1533 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1534 struct aic3x_priv *aic3x;
1535 struct aic3x_setup_data *ai3x_setup;
1536 struct device_node *np = i2c->dev.of_node;
1537 int ret, i;
1538 u32 value;
1539
1540 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1541 if (!aic3x)
1542 return -ENOMEM;
1543
1544 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1545 if (IS_ERR(aic3x->regmap)) {
1546 ret = PTR_ERR(aic3x->regmap);
1547 return ret;
1548 }
1549
1550 regcache_cache_only(aic3x->regmap, true);
1551
1552 i2c_set_clientdata(i2c, aic3x);
1553 if (pdata) {
1554 aic3x->gpio_reset = pdata->gpio_reset;
1555 aic3x->setup = pdata->setup;
1556 aic3x->micbias_vg = pdata->micbias_vg;
1557 } else if (np) {
1558 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1559 GFP_KERNEL);
1560 if (!ai3x_setup)
1561 return -ENOMEM;
1562
1563 ret = of_get_named_gpio(np, "gpio-reset", 0);
1564 if (ret >= 0)
1565 aic3x->gpio_reset = ret;
1566 else
1567 aic3x->gpio_reset = -1;
1568
1569 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1570 ai3x_setup->gpio_func, 2) >= 0) {
1571 aic3x->setup = ai3x_setup;
1572 }
1573
1574 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1575 switch (value) {
1576 case 1 :
1577 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1578 break;
1579 case 2 :
1580 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1581 break;
1582 case 3 :
1583 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1584 break;
1585 default :
1586 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1587 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1588 "found in DT\n");
1589 }
1590 } else {
1591 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1592 }
1593
1594 } else {
1595 aic3x->gpio_reset = -1;
1596 }
1597
1598 aic3x->model = id->driver_data;
1599
1600 if (gpio_is_valid(aic3x->gpio_reset) &&
1601 !aic3x_is_shared_reset(aic3x)) {
1602 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1603 if (ret != 0)
1604 goto err;
1605 gpio_direction_output(aic3x->gpio_reset, 0);
1606 }
1607
1608 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1609 aic3x->supplies[i].supply = aic3x_supply_names[i];
1610
1611 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1612 aic3x->supplies);
1613 if (ret != 0) {
1614 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1615 goto err_gpio;
1616 }
1617
1618 if (aic3x->model == AIC3X_MODEL_3007) {
1619 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1620 ARRAY_SIZE(aic3007_class_d));
1621 if (ret != 0)
1622 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1623 ret);
1624 }
1625
1626 ret = snd_soc_register_codec(&i2c->dev,
1627 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1628
1629 if (ret != 0)
1630 goto err_gpio;
1631
1632 list_add(&aic3x->list, &reset_list);
1633
1634 return 0;
1635
1636 err_gpio:
1637 if (gpio_is_valid(aic3x->gpio_reset) &&
1638 !aic3x_is_shared_reset(aic3x))
1639 gpio_free(aic3x->gpio_reset);
1640 err:
1641 return ret;
1642 }
1643
1644 static int aic3x_i2c_remove(struct i2c_client *client)
1645 {
1646 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1647
1648 snd_soc_unregister_codec(&client->dev);
1649 if (gpio_is_valid(aic3x->gpio_reset) &&
1650 !aic3x_is_shared_reset(aic3x)) {
1651 gpio_set_value(aic3x->gpio_reset, 0);
1652 gpio_free(aic3x->gpio_reset);
1653 }
1654 return 0;
1655 }
1656
1657 #if defined(CONFIG_OF)
1658 static const struct of_device_id tlv320aic3x_of_match[] = {
1659 { .compatible = "ti,tlv320aic3x", },
1660 { .compatible = "ti,tlv320aic33" },
1661 { .compatible = "ti,tlv320aic3007" },
1662 { .compatible = "ti,tlv320aic3106" },
1663 {},
1664 };
1665 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1666 #endif
1667
1668 /* machine i2c codec control layer */
1669 static struct i2c_driver aic3x_i2c_driver = {
1670 .driver = {
1671 .name = "tlv320aic3x-codec",
1672 .owner = THIS_MODULE,
1673 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1674 },
1675 .probe = aic3x_i2c_probe,
1676 .remove = aic3x_i2c_remove,
1677 .id_table = aic3x_i2c_id,
1678 };
1679
1680 module_i2c_driver(aic3x_i2c_driver);
1681
1682 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1683 MODULE_AUTHOR("Vladimir Barinov");
1684 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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