2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
54 #include "tlv320aic3x.h"
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names
[AIC3X_NUM_SUPPLIES
] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
64 static LIST_HEAD(reset_list
);
68 struct aic3x_disable_nb
{
69 struct notifier_block nb
;
70 struct aic3x_priv
*aic3x
;
73 /* codec private data */
75 struct snd_soc_codec
*codec
;
76 struct regmap
*regmap
;
77 struct regulator_bulk_data supplies
[AIC3X_NUM_SUPPLIES
];
78 struct aic3x_disable_nb disable_nb
[AIC3X_NUM_SUPPLIES
];
79 struct aic3x_setup_data
*setup
;
82 unsigned int tdm_delay
;
83 struct list_head list
;
87 #define AIC3X_MODEL_3X 0
88 #define AIC3X_MODEL_33 1
89 #define AIC3X_MODEL_3007 2
90 #define AIC3X_MODEL_3104 3
93 /* Selects the micbias voltage */
94 enum aic3x_micbias_voltage micbias_vg
;
97 static const struct reg_default aic3x_reg
[] = {
98 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
99 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
100 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
101 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
102 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
103 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
104 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
105 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
106 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
107 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
108 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
109 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
110 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
111 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
112 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
113 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
114 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
115 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
116 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
117 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
118 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
119 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
120 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
121 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
122 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
123 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
124 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
125 { 108, 0x00 }, { 109, 0x00 },
128 static const struct regmap_config aic3x_regmap
= {
132 .max_register
= DAC_ICC_ADJ
,
133 .reg_defaults
= aic3x_reg
,
134 .num_reg_defaults
= ARRAY_SIZE(aic3x_reg
),
135 .cache_type
= REGCACHE_RBTREE
,
138 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
139 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
140 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
143 * All input lines are connected when !0xf and disconnected with 0xf bit field,
144 * so we have to use specific dapm_put call for input mixer
146 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
147 struct snd_ctl_elem_value
*ucontrol
)
149 struct snd_soc_codec
*codec
= snd_soc_dapm_kcontrol_codec(kcontrol
);
150 struct soc_mixer_control
*mc
=
151 (struct soc_mixer_control
*)kcontrol
->private_value
;
152 unsigned int reg
= mc
->reg
;
153 unsigned int shift
= mc
->shift
;
155 unsigned int mask
= (1 << fls(max
)) - 1;
156 unsigned int invert
= mc
->invert
;
158 struct snd_soc_dapm_update update
;
161 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
175 change
= snd_soc_test_bits(codec
, reg
, mask
, val
);
177 update
.kcontrol
= kcontrol
;
182 snd_soc_dapm_mixer_update_power(&codec
->dapm
, kcontrol
, connect
,
190 * mic bias power on/off share the same register bits with
191 * output voltage of mic bias. when power on mic bias, we
192 * need reclaim it to voltage value.
194 * 0x1 = MICBIAS output is powered to 2.0V,
195 * 0x2 = MICBIAS output is powered to 2.5V
196 * 0x3 = MICBIAS output is connected to AVDD
198 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
199 struct snd_kcontrol
*kcontrol
, int event
)
201 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
202 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
205 case SND_SOC_DAPM_POST_PMU
:
206 /* change mic bias voltage to user defined */
207 snd_soc_update_bits(codec
, MICBIAS_CTRL
,
209 aic3x
->micbias_vg
<< MICBIAS_LEVEL_SHIFT
);
212 case SND_SOC_DAPM_PRE_PMD
:
213 snd_soc_update_bits(codec
, MICBIAS_CTRL
,
214 MICBIAS_LEVEL_MASK
, 0);
220 static const char * const aic3x_left_dac_mux
[] = {
221 "DAC_L1", "DAC_L3", "DAC_L2" };
222 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum
, DAC_LINE_MUX
, 6,
225 static const char * const aic3x_right_dac_mux
[] = {
226 "DAC_R1", "DAC_R3", "DAC_R2" };
227 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum
, DAC_LINE_MUX
, 4,
228 aic3x_right_dac_mux
);
230 static const char * const aic3x_left_hpcom_mux
[] = {
231 "differential of HPLOUT", "constant VCM", "single-ended" };
232 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum
, HPLCOM_CFG
, 4,
233 aic3x_left_hpcom_mux
);
235 static const char * const aic3x_right_hpcom_mux
[] = {
236 "differential of HPROUT", "constant VCM", "single-ended",
237 "differential of HPLCOM", "external feedback" };
238 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum
, HPRCOM_CFG
, 3,
239 aic3x_right_hpcom_mux
);
241 static const char * const aic3x_linein_mode_mux
[] = {
242 "single-ended", "differential" };
243 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum
, LINE1L_2_LADC_CTRL
, 7,
244 aic3x_linein_mode_mux
);
245 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum
, LINE1L_2_RADC_CTRL
, 7,
246 aic3x_linein_mode_mux
);
247 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum
, LINE1R_2_LADC_CTRL
, 7,
248 aic3x_linein_mode_mux
);
249 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum
, LINE1R_2_RADC_CTRL
, 7,
250 aic3x_linein_mode_mux
);
251 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum
, LINE2L_2_LADC_CTRL
, 7,
252 aic3x_linein_mode_mux
);
253 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum
, LINE2R_2_RADC_CTRL
, 7,
254 aic3x_linein_mode_mux
);
256 static const char * const aic3x_adc_hpf
[] = {
257 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
258 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum
, AIC3X_CODEC_DFILT_CTRL
, 6, 4,
261 static const char * const aic3x_agc_level
[] = {
262 "-5.5dB", "-8dB", "-10dB", "-12dB",
263 "-14dB", "-17dB", "-20dB", "-24dB" };
264 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum
, LAGC_CTRL_A
, 4,
266 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum
, RAGC_CTRL_A
, 4,
269 static const char * const aic3x_agc_attack
[] = {
270 "8ms", "11ms", "16ms", "20ms" };
271 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum
, LAGC_CTRL_A
, 2,
273 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum
, RAGC_CTRL_A
, 2,
276 static const char * const aic3x_agc_decay
[] = {
277 "100ms", "200ms", "400ms", "500ms" };
278 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum
, LAGC_CTRL_A
, 0,
280 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum
, RAGC_CTRL_A
, 0,
283 static const char * const aic3x_poweron_time
[] = {
284 "0us", "10us", "100us", "1ms", "10ms", "50ms",
285 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
286 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum
, HPOUT_POP_REDUCTION
, 4,
289 static const char * const aic3x_rampup_step
[] = { "0ms", "1ms", "2ms", "4ms" };
290 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum
, HPOUT_POP_REDUCTION
, 2,
294 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
296 static DECLARE_TLV_DB_SCALE(dac_tlv
, -6350, 50, 0);
297 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
298 static DECLARE_TLV_DB_SCALE(adc_tlv
, 0, 50, 0);
300 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
301 * Step size is approximately 0.5 dB over most of the scale but increasing
302 * near the very low levels.
303 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
304 * but having increasing dB difference below that (and where it doesn't count
305 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
306 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
308 static DECLARE_TLV_DB_SCALE(output_stage_tlv
, -5900, 50, 1);
310 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
312 SOC_DOUBLE_R_TLV("PCM Playback Volume",
313 LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1, dac_tlv
),
316 * Output controls that map to output mixer switches. Note these are
317 * only for swapped L-to-R and R-to-L routes. See below stereo controls
318 * for direct L-to-L and R-to-R routes.
320 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
321 PGAR_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
322 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
323 DACR1_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
325 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
326 PGAL_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
327 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
328 DACL1_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
330 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
331 PGAR_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
332 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
333 DACR1_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
335 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
336 PGAL_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
337 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
338 DACL1_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
340 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
341 PGAR_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
342 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
343 DACR1_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
345 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
346 PGAL_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
347 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
348 DACL1_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
350 /* Stereo output controls for direct L-to-L and R-to-R routes */
351 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
352 PGAL_2_LLOPM_VOL
, PGAR_2_RLOPM_VOL
,
353 0, 118, 1, output_stage_tlv
),
354 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
355 DACL1_2_LLOPM_VOL
, DACR1_2_RLOPM_VOL
,
356 0, 118, 1, output_stage_tlv
),
358 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
359 PGAL_2_HPLOUT_VOL
, PGAR_2_HPROUT_VOL
,
360 0, 118, 1, output_stage_tlv
),
361 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
362 DACL1_2_HPLOUT_VOL
, DACR1_2_HPROUT_VOL
,
363 0, 118, 1, output_stage_tlv
),
365 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
366 PGAL_2_HPLCOM_VOL
, PGAR_2_HPRCOM_VOL
,
367 0, 118, 1, output_stage_tlv
),
368 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
369 DACL1_2_HPLCOM_VOL
, DACR1_2_HPRCOM_VOL
,
370 0, 118, 1, output_stage_tlv
),
372 /* Output pin mute controls */
373 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL
, RLOPM_CTRL
, 3,
375 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
377 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
381 * Note: enable Automatic input Gain Controller with care. It can
382 * adjust PGA to max value when ADC is on and will never go back.
384 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
385 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum
),
386 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum
),
387 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum
),
388 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum
),
389 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum
),
390 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum
),
393 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL
, 2, 0, 0x01, 0),
396 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL
, RADC_VOL
,
398 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
400 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum
),
403 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum
),
404 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum
),
407 /* For other than tlv320aic3104 */
408 static const struct snd_kcontrol_new aic3x_extra_snd_controls
[] = {
410 * Output controls that map to output mixer switches. Note these are
411 * only for swapped L-to-R and R-to-L routes. See below stereo controls
412 * for direct L-to-L and R-to-R routes.
414 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
415 LINE2R_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
417 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
418 LINE2L_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
420 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
421 LINE2R_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
423 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
424 LINE2L_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
426 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
427 LINE2R_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
429 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
430 LINE2L_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
432 /* Stereo output controls for direct L-to-L and R-to-R routes */
433 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
434 LINE2L_2_LLOPM_VOL
, LINE2R_2_RLOPM_VOL
,
435 0, 118, 1, output_stage_tlv
),
437 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
438 LINE2L_2_HPLOUT_VOL
, LINE2R_2_HPROUT_VOL
,
439 0, 118, 1, output_stage_tlv
),
441 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
442 LINE2L_2_HPLCOM_VOL
, LINE2R_2_HPRCOM_VOL
,
443 0, 118, 1, output_stage_tlv
),
446 static const struct snd_kcontrol_new aic3x_mono_controls
[] = {
447 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
448 LINE2L_2_MONOLOPM_VOL
, LINE2R_2_MONOLOPM_VOL
,
449 0, 118, 1, output_stage_tlv
),
450 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
451 PGAL_2_MONOLOPM_VOL
, PGAR_2_MONOLOPM_VOL
,
452 0, 118, 1, output_stage_tlv
),
453 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
454 DACL1_2_MONOLOPM_VOL
, DACR1_2_MONOLOPM_VOL
,
455 0, 118, 1, output_stage_tlv
),
457 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
461 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
463 static DECLARE_TLV_DB_SCALE(classd_amp_tlv
, 0, 600, 0);
465 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl
=
466 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL
, 6, 4, 3, 0, classd_amp_tlv
);
469 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
470 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum
);
473 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
474 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum
);
477 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
478 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum
);
480 /* Right HPCOM Mux */
481 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
482 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum
);
484 /* Left Line Mixer */
485 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls
[] = {
486 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
487 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
488 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL
, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL
, 7, 1, 0),
490 /* Not on tlv320aic3104 */
491 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
492 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL
, 7, 1, 0),
495 /* Right Line Mixer */
496 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls
[] = {
497 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL
, 7, 1, 0),
498 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL
, 7, 1, 0),
499 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
500 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
501 /* Not on tlv320aic3104 */
502 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL
, 7, 1, 0),
503 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
507 static const struct snd_kcontrol_new aic3x_mono_mixer_controls
[] = {
508 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
509 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
510 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
511 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
512 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
513 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
517 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls
[] = {
518 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
519 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
520 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL
, 7, 1, 0),
521 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL
, 7, 1, 0),
522 /* Not on tlv320aic3104 */
523 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
524 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL
, 7, 1, 0),
528 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls
[] = {
529 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL
, 7, 1, 0),
530 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL
, 7, 1, 0),
531 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
532 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
533 /* Not on tlv320aic3104 */
534 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL
, 7, 1, 0),
535 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
538 /* Left HPCOM Mixer */
539 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls
[] = {
540 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
541 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
542 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL
, 7, 1, 0),
543 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL
, 7, 1, 0),
544 /* Not on tlv320aic3104 */
545 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
546 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL
, 7, 1, 0),
549 /* Right HPCOM Mixer */
550 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls
[] = {
551 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL
, 7, 1, 0),
552 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL
, 7, 1, 0),
553 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
554 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
555 /* Not on tlv320aic3104 */
556 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL
, 7, 1, 0),
557 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
561 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
562 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
563 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
564 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
565 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
566 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
569 /* Right PGA Mixer */
570 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
571 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
572 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
573 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
574 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
575 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
578 /* Left PGA Mixer for tlv320aic3104 */
579 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls
[] = {
580 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
581 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
582 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
583 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
586 /* Right PGA Mixer for tlv320aic3104 */
587 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls
[] = {
588 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
589 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
590 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
591 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
595 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls
=
596 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum
);
597 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls
=
598 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum
);
600 /* Right Line1 Mux */
601 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls
=
602 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum
);
603 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls
=
604 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum
);
607 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
608 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum
);
610 /* Right Line2 Mux */
611 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
612 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum
);
614 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
615 /* Left DAC to Left Outputs */
616 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
617 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
618 &aic3x_left_dac_mux_controls
),
619 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
620 &aic3x_left_hpcom_mux_controls
),
621 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
622 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
623 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
625 /* Right DAC to Right Outputs */
626 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
627 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
628 &aic3x_right_dac_mux_controls
),
629 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
630 &aic3x_right_hpcom_mux_controls
),
631 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
632 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
633 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
635 /* Inputs to Left ADC */
636 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
637 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
638 &aic3x_left_line1l_mux_controls
),
639 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM
, 0, 0,
640 &aic3x_left_line1r_mux_controls
),
642 /* Inputs to Right ADC */
643 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
644 LINE1R_2_RADC_CTRL
, 2, 0),
645 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM
, 0, 0,
646 &aic3x_right_line1l_mux_controls
),
647 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
648 &aic3x_right_line1r_mux_controls
),
651 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL
, 6, 0,
653 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
655 SND_SOC_DAPM_OUTPUT("LLOUT"),
656 SND_SOC_DAPM_OUTPUT("RLOUT"),
657 SND_SOC_DAPM_OUTPUT("HPLOUT"),
658 SND_SOC_DAPM_OUTPUT("HPROUT"),
659 SND_SOC_DAPM_OUTPUT("HPLCOM"),
660 SND_SOC_DAPM_OUTPUT("HPRCOM"),
662 SND_SOC_DAPM_INPUT("LINE1L"),
663 SND_SOC_DAPM_INPUT("LINE1R"),
666 * Virtual output pin to detection block inside codec. This can be
667 * used to keep codec bias on if gpio or detection features are needed.
668 * Force pin on or construct a path with an input jack and mic bias
671 SND_SOC_DAPM_OUTPUT("Detection"),
674 /* For other than tlv320aic3104 */
675 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets
[] = {
676 /* Inputs to Left ADC */
677 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
678 &aic3x_left_pga_mixer_controls
[0],
679 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
680 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
681 &aic3x_left_line2_mux_controls
),
683 /* Inputs to Right ADC */
684 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
685 &aic3x_right_pga_mixer_controls
[0],
686 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
687 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
688 &aic3x_right_line2_mux_controls
),
691 * Not a real mic bias widget but similar function. This is for dynamic
692 * control of GPIO1 digital mic modulator clock output function when
695 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
696 AIC3X_GPIO1_REG
, 4, 0xf,
697 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
698 AIC3X_GPIO1_FUNC_DISABLED
),
701 * Also similar function like mic bias. Selects digital mic with
702 * configurable oversampling rate instead of ADC converter.
704 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
705 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
706 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
707 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
708 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
709 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
712 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM
, 0, 0,
713 &aic3x_left_line_mixer_controls
[0],
714 ARRAY_SIZE(aic3x_left_line_mixer_controls
)),
715 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM
, 0, 0,
716 &aic3x_right_line_mixer_controls
[0],
717 ARRAY_SIZE(aic3x_right_line_mixer_controls
)),
718 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM
, 0, 0,
719 &aic3x_left_hp_mixer_controls
[0],
720 ARRAY_SIZE(aic3x_left_hp_mixer_controls
)),
721 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM
, 0, 0,
722 &aic3x_right_hp_mixer_controls
[0],
723 ARRAY_SIZE(aic3x_right_hp_mixer_controls
)),
724 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
725 &aic3x_left_hpcom_mixer_controls
[0],
726 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls
)),
727 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
728 &aic3x_right_hpcom_mixer_controls
[0],
729 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls
)),
731 SND_SOC_DAPM_INPUT("MIC3L"),
732 SND_SOC_DAPM_INPUT("MIC3R"),
733 SND_SOC_DAPM_INPUT("LINE2L"),
734 SND_SOC_DAPM_INPUT("LINE2R"),
737 /* For tlv320aic3104 */
738 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets
[] = {
739 /* Inputs to Left ADC */
740 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
741 &aic3104_left_pga_mixer_controls
[0],
742 ARRAY_SIZE(aic3104_left_pga_mixer_controls
)),
744 /* Inputs to Right ADC */
745 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
746 &aic3104_right_pga_mixer_controls
[0],
747 ARRAY_SIZE(aic3104_right_pga_mixer_controls
)),
750 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM
, 0, 0,
751 &aic3x_left_line_mixer_controls
[0],
752 ARRAY_SIZE(aic3x_left_line_mixer_controls
) - 2),
753 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM
, 0, 0,
754 &aic3x_right_line_mixer_controls
[0],
755 ARRAY_SIZE(aic3x_right_line_mixer_controls
) - 2),
756 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM
, 0, 0,
757 &aic3x_left_hp_mixer_controls
[0],
758 ARRAY_SIZE(aic3x_left_hp_mixer_controls
) - 2),
759 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM
, 0, 0,
760 &aic3x_right_hp_mixer_controls
[0],
761 ARRAY_SIZE(aic3x_right_hp_mixer_controls
) - 2),
762 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
763 &aic3x_left_hpcom_mixer_controls
[0],
764 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls
) - 2),
765 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
766 &aic3x_right_hpcom_mixer_controls
[0],
767 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls
) - 2),
769 SND_SOC_DAPM_INPUT("MIC2L"),
770 SND_SOC_DAPM_INPUT("MIC2R"),
773 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets
[] = {
775 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
777 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM
, 0, 0,
778 &aic3x_mono_mixer_controls
[0],
779 ARRAY_SIZE(aic3x_mono_mixer_controls
)),
781 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
784 static const struct snd_soc_dapm_widget aic3007_dapm_widgets
[] = {
785 /* Class-D outputs */
786 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL
, 3, 0, NULL
, 0),
787 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL
, 2, 0, NULL
, 0),
789 SND_SOC_DAPM_OUTPUT("SPOP"),
790 SND_SOC_DAPM_OUTPUT("SPOM"),
793 static const struct snd_soc_dapm_route intercon
[] = {
795 {"Left Line1L Mux", "single-ended", "LINE1L"},
796 {"Left Line1L Mux", "differential", "LINE1L"},
797 {"Left Line1R Mux", "single-ended", "LINE1R"},
798 {"Left Line1R Mux", "differential", "LINE1R"},
800 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
801 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
803 {"Left ADC", NULL
, "Left PGA Mixer"},
806 {"Right Line1R Mux", "single-ended", "LINE1R"},
807 {"Right Line1R Mux", "differential", "LINE1R"},
808 {"Right Line1L Mux", "single-ended", "LINE1L"},
809 {"Right Line1L Mux", "differential", "LINE1L"},
811 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
812 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
814 {"Right ADC", NULL
, "Right PGA Mixer"},
816 /* Left DAC Output */
817 {"Left DAC Mux", "DAC_L1", "Left DAC"},
818 {"Left DAC Mux", "DAC_L2", "Left DAC"},
819 {"Left DAC Mux", "DAC_L3", "Left DAC"},
821 /* Right DAC Output */
822 {"Right DAC Mux", "DAC_R1", "Right DAC"},
823 {"Right DAC Mux", "DAC_R2", "Right DAC"},
824 {"Right DAC Mux", "DAC_R3", "Right DAC"},
826 /* Left Line Output */
827 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
828 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
829 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
830 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
832 {"Left Line Out", NULL
, "Left Line Mixer"},
833 {"Left Line Out", NULL
, "Left DAC Mux"},
834 {"LLOUT", NULL
, "Left Line Out"},
836 /* Right Line Output */
837 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
838 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
839 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
840 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
842 {"Right Line Out", NULL
, "Right Line Mixer"},
843 {"Right Line Out", NULL
, "Right DAC Mux"},
844 {"RLOUT", NULL
, "Right Line Out"},
847 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
848 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
849 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
850 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
852 {"Left HP Out", NULL
, "Left HP Mixer"},
853 {"Left HP Out", NULL
, "Left DAC Mux"},
854 {"HPLOUT", NULL
, "Left HP Out"},
856 /* Right HP Output */
857 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
858 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
859 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
860 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
862 {"Right HP Out", NULL
, "Right HP Mixer"},
863 {"Right HP Out", NULL
, "Right DAC Mux"},
864 {"HPROUT", NULL
, "Right HP Out"},
866 /* Left HPCOM Output */
867 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
868 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
869 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
870 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
872 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
873 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
874 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
875 {"Left HP Com", NULL
, "Left HPCOM Mux"},
876 {"HPLCOM", NULL
, "Left HP Com"},
878 /* Right HPCOM Output */
879 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
880 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
881 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
882 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
884 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
885 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
886 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
887 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
888 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
889 {"Right HP Com", NULL
, "Right HPCOM Mux"},
890 {"HPRCOM", NULL
, "Right HP Com"},
893 /* For other than tlv320aic3104 */
894 static const struct snd_soc_dapm_route intercon_extra
[] = {
896 {"Left Line2L Mux", "single-ended", "LINE2L"},
897 {"Left Line2L Mux", "differential", "LINE2L"},
899 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
900 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
901 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
903 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
906 {"Right Line2R Mux", "single-ended", "LINE2R"},
907 {"Right Line2R Mux", "differential", "LINE2R"},
909 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
910 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
911 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
913 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
916 * Logical path between digital mic enable and GPIO1 modulator clock
919 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
920 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
921 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
923 /* Left Line Output */
924 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
925 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
927 /* Right Line Output */
928 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
929 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
932 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
933 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
935 /* Right HP Output */
936 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
937 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
939 /* Left HPCOM Output */
940 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
941 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
943 /* Right HPCOM Output */
944 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
945 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
948 /* For tlv320aic3104 */
949 static const struct snd_soc_dapm_route intercon_extra_3104
[] = {
951 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
952 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
955 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
956 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
959 static const struct snd_soc_dapm_route intercon_mono
[] = {
961 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
962 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
963 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
964 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
965 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
966 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
967 {"Mono Out", NULL
, "Mono Mixer"},
968 {"MONO_LOUT", NULL
, "Mono Out"},
971 static const struct snd_soc_dapm_route intercon_3007
[] = {
972 /* Class-D outputs */
973 {"Left Class-D Out", NULL
, "Left Line Out"},
974 {"Right Class-D Out", NULL
, "Left Line Out"},
975 {"SPOP", NULL
, "Left Class-D Out"},
976 {"SPOM", NULL
, "Right Class-D Out"},
979 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
981 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
982 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
984 switch (aic3x
->model
) {
987 snd_soc_dapm_new_controls(dapm
, aic3x_extra_dapm_widgets
,
988 ARRAY_SIZE(aic3x_extra_dapm_widgets
));
989 snd_soc_dapm_add_routes(dapm
, intercon_extra
,
990 ARRAY_SIZE(intercon_extra
));
991 snd_soc_dapm_new_controls(dapm
, aic3x_dapm_mono_widgets
,
992 ARRAY_SIZE(aic3x_dapm_mono_widgets
));
993 snd_soc_dapm_add_routes(dapm
, intercon_mono
,
994 ARRAY_SIZE(intercon_mono
));
996 case AIC3X_MODEL_3007
:
997 snd_soc_dapm_new_controls(dapm
, aic3x_extra_dapm_widgets
,
998 ARRAY_SIZE(aic3x_extra_dapm_widgets
));
999 snd_soc_dapm_add_routes(dapm
, intercon_extra
,
1000 ARRAY_SIZE(intercon_extra
));
1001 snd_soc_dapm_new_controls(dapm
, aic3007_dapm_widgets
,
1002 ARRAY_SIZE(aic3007_dapm_widgets
));
1003 snd_soc_dapm_add_routes(dapm
, intercon_3007
,
1004 ARRAY_SIZE(intercon_3007
));
1006 case AIC3X_MODEL_3104
:
1007 snd_soc_dapm_new_controls(dapm
, aic3104_extra_dapm_widgets
,
1008 ARRAY_SIZE(aic3104_extra_dapm_widgets
));
1009 snd_soc_dapm_add_routes(dapm
, intercon_extra_3104
,
1010 ARRAY_SIZE(intercon_extra_3104
));
1017 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
1018 struct snd_pcm_hw_params
*params
,
1019 struct snd_soc_dai
*dai
)
1021 struct snd_soc_codec
*codec
= dai
->codec
;
1022 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1023 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
1024 u8 data
, j
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
1028 /* select data word length */
1029 data
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
1030 switch (params_width(params
)) {
1034 data
|= (0x01 << 4);
1037 data
|= (0x02 << 4);
1040 data
|= (0x03 << 4);
1043 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
1045 /* Fsref can be 44100 or 48000 */
1046 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
1048 /* Try to find a value for Q which allows us to bypass the PLL and
1049 * generate CODEC_CLK directly. */
1050 for (pll_q
= 2; pll_q
< 18; pll_q
++)
1051 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
1058 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
1059 snd_soc_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
1060 /* disable PLL if it is bypassed */
1061 snd_soc_update_bits(codec
, AIC3X_PLL_PROGA_REG
, PLL_ENABLE
, 0);
1064 snd_soc_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
1065 /* enable PLL when it is used */
1066 snd_soc_update_bits(codec
, AIC3X_PLL_PROGA_REG
,
1067 PLL_ENABLE
, PLL_ENABLE
);
1070 /* Route Left DAC to left channel input and
1071 * right DAC to right channel input */
1072 data
= (LDAC2LCH
| RDAC2RCH
);
1073 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
1074 if (params_rate(params
) >= 64000)
1075 data
|= DUAL_RATE_MODE
;
1076 snd_soc_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
1078 /* codec sample rate select */
1079 data
= (fsref
* 20) / params_rate(params
);
1080 if (params_rate(params
) < 64000)
1084 data
|= (data
<< 4);
1085 snd_soc_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
1090 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1091 * one wins the game. Try with d==0 first, next with d!=0.
1092 * Constraints for j are according to the datasheet.
1093 * The sysclk is divided by 1000 to prevent integer overflows.
1096 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
1098 for (r
= 1; r
<= 16; r
++)
1099 for (p
= 1; p
<= 8; p
++) {
1100 for (j
= 4; j
<= 55; j
++) {
1101 /* This is actually 1000*((j+(d/10000))*r)/p
1102 * The term had to be converted to get
1103 * rid of the division by 10000; d = 0 here
1105 int tmp_clk
= (1000 * j
* r
) / p
;
1107 /* Check whether this values get closer than
1108 * the best ones we had before
1110 if (abs(codec_clk
- tmp_clk
) <
1111 abs(codec_clk
- last_clk
)) {
1112 pll_j
= j
; pll_d
= 0;
1113 pll_r
= r
; pll_p
= p
;
1117 /* Early exit for exact matches */
1118 if (tmp_clk
== codec_clk
)
1123 /* try with d != 0 */
1124 for (p
= 1; p
<= 8; p
++) {
1125 j
= codec_clk
* p
/ 1000;
1127 if (j
< 4 || j
> 11)
1130 /* do not use codec_clk here since we'd loose precision */
1131 d
= ((2048 * p
* fsref
) - j
* aic3x
->sysclk
)
1132 * 100 / (aic3x
->sysclk
/100);
1134 clk
= (10000 * j
+ d
) / (10 * p
);
1136 /* check whether this values get closer than the best
1137 * ones we had before */
1138 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
1139 pll_j
= j
; pll_d
= d
; pll_r
= 1; pll_p
= p
;
1143 /* Early exit for exact matches */
1144 if (clk
== codec_clk
)
1148 if (last_clk
== 0) {
1149 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
1154 snd_soc_update_bits(codec
, AIC3X_PLL_PROGA_REG
, PLLP_MASK
, pll_p
);
1155 snd_soc_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
,
1156 pll_r
<< PLLR_SHIFT
);
1157 snd_soc_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
1158 snd_soc_write(codec
, AIC3X_PLL_PROGC_REG
,
1159 (pll_d
>> 6) << PLLD_MSB_SHIFT
);
1160 snd_soc_write(codec
, AIC3X_PLL_PROGD_REG
,
1161 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
1166 static int aic3x_prepare(struct snd_pcm_substream
*substream
,
1167 struct snd_soc_dai
*dai
)
1169 struct snd_soc_codec
*codec
= dai
->codec
;
1170 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1173 /* TDM slot selection only valid in DSP_A/_B mode */
1174 if (aic3x
->dai_fmt
== SND_SOC_DAIFMT_DSP_A
)
1175 delay
+= (aic3x
->tdm_delay
+ 1);
1176 else if (aic3x
->dai_fmt
== SND_SOC_DAIFMT_DSP_B
)
1177 delay
+= aic3x
->tdm_delay
;
1179 /* Configure data delay */
1180 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLC
, delay
);
1185 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
1187 struct snd_soc_codec
*codec
= dai
->codec
;
1188 u8 ldac_reg
= snd_soc_read(codec
, LDAC_VOL
) & ~MUTE_ON
;
1189 u8 rdac_reg
= snd_soc_read(codec
, RDAC_VOL
) & ~MUTE_ON
;
1192 snd_soc_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
1193 snd_soc_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
1195 snd_soc_write(codec
, LDAC_VOL
, ldac_reg
);
1196 snd_soc_write(codec
, RDAC_VOL
, rdac_reg
);
1202 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1203 int clk_id
, unsigned int freq
, int dir
)
1205 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1206 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1208 /* set clock on MCLK or GPIO2 or BCLK */
1209 snd_soc_update_bits(codec
, AIC3X_CLKGEN_CTRL_REG
, PLLCLK_IN_MASK
,
1210 clk_id
<< PLLCLK_IN_SHIFT
);
1211 snd_soc_update_bits(codec
, AIC3X_CLKGEN_CTRL_REG
, CLKDIV_IN_MASK
,
1212 clk_id
<< CLKDIV_IN_SHIFT
);
1214 aic3x
->sysclk
= freq
;
1218 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1221 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1222 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1223 u8 iface_areg
, iface_breg
;
1225 iface_areg
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
1226 iface_breg
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
1228 /* set master/slave audio interface */
1229 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1230 case SND_SOC_DAIFMT_CBM_CFM
:
1232 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
1234 case SND_SOC_DAIFMT_CBS_CFS
:
1236 iface_areg
&= ~(BIT_CLK_MASTER
| WORD_CLK_MASTER
);
1243 * match both interface format and signal polarities since they
1246 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
1247 SND_SOC_DAIFMT_INV_MASK
)) {
1248 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
1250 case (SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
):
1251 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
1252 iface_breg
|= (0x01 << 6);
1254 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
1255 iface_breg
|= (0x02 << 6);
1257 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
1258 iface_breg
|= (0x03 << 6);
1264 aic3x
->dai_fmt
= fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
1267 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
1268 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
1273 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai
*codec_dai
,
1274 unsigned int tx_mask
, unsigned int rx_mask
,
1275 int slots
, int slot_width
)
1277 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1278 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1281 if (tx_mask
!= rx_mask
) {
1282 dev_err(codec
->dev
, "tx and rx masks must be symmetric\n");
1286 if (unlikely(!tx_mask
)) {
1287 dev_err(codec
->dev
, "tx and rx masks need to be non 0\n");
1291 /* TDM based on DSP mode requires slots to be adjacent */
1292 lsb
= __ffs(tx_mask
);
1293 if ((lsb
+ 1) != __fls(tx_mask
)) {
1294 dev_err(codec
->dev
, "Invalid mask, slots must be adjacent\n");
1298 aic3x
->tdm_delay
= lsb
* slot_width
;
1300 /* DOUT in high-impedance on inactive bit clocks */
1301 snd_soc_update_bits(codec
, AIC3X_ASD_INTF_CTRLA
,
1302 DOUT_TRISTATE
, DOUT_TRISTATE
);
1307 static int aic3x_regulator_event(struct notifier_block
*nb
,
1308 unsigned long event
, void *data
)
1310 struct aic3x_disable_nb
*disable_nb
=
1311 container_of(nb
, struct aic3x_disable_nb
, nb
);
1312 struct aic3x_priv
*aic3x
= disable_nb
->aic3x
;
1314 if (event
& REGULATOR_EVENT_DISABLE
) {
1316 * Put codec to reset and require cache sync as at least one
1317 * of the supplies was disabled
1319 if (gpio_is_valid(aic3x
->gpio_reset
))
1320 gpio_set_value(aic3x
->gpio_reset
, 0);
1321 regcache_mark_dirty(aic3x
->regmap
);
1327 static int aic3x_set_power(struct snd_soc_codec
*codec
, int power
)
1329 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1330 unsigned int pll_c
, pll_d
;
1334 ret
= regulator_bulk_enable(ARRAY_SIZE(aic3x
->supplies
),
1340 if (gpio_is_valid(aic3x
->gpio_reset
)) {
1342 gpio_set_value(aic3x
->gpio_reset
, 1);
1345 /* Sync reg_cache with the hardware */
1346 regcache_cache_only(aic3x
->regmap
, false);
1347 regcache_sync(aic3x
->regmap
);
1349 /* Rewrite paired PLL D registers in case cached sync skipped
1350 * writing one of them and thus caused other one also not
1353 pll_c
= snd_soc_read(codec
, AIC3X_PLL_PROGC_REG
);
1354 pll_d
= snd_soc_read(codec
, AIC3X_PLL_PROGD_REG
);
1355 if (pll_c
== aic3x_reg
[AIC3X_PLL_PROGC_REG
].def
||
1356 pll_d
== aic3x_reg
[AIC3X_PLL_PROGD_REG
].def
) {
1357 snd_soc_write(codec
, AIC3X_PLL_PROGC_REG
, pll_c
);
1358 snd_soc_write(codec
, AIC3X_PLL_PROGD_REG
, pll_d
);
1362 * Do soft reset to this codec instance in order to clear
1363 * possible VDD leakage currents in case the supply regulators
1366 snd_soc_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1367 regcache_mark_dirty(aic3x
->regmap
);
1369 /* HW writes are needless when bias is off */
1370 regcache_cache_only(aic3x
->regmap
, true);
1371 ret
= regulator_bulk_disable(ARRAY_SIZE(aic3x
->supplies
),
1378 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
1379 enum snd_soc_bias_level level
)
1381 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1384 case SND_SOC_BIAS_ON
:
1386 case SND_SOC_BIAS_PREPARE
:
1387 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
&&
1390 snd_soc_update_bits(codec
, AIC3X_PLL_PROGA_REG
,
1391 PLL_ENABLE
, PLL_ENABLE
);
1394 case SND_SOC_BIAS_STANDBY
:
1396 aic3x_set_power(codec
, 1);
1397 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
&&
1400 snd_soc_update_bits(codec
, AIC3X_PLL_PROGA_REG
,
1404 case SND_SOC_BIAS_OFF
:
1406 aic3x_set_power(codec
, 0);
1413 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1414 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1415 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1416 SNDRV_PCM_FMTBIT_S32_LE)
1418 static const struct snd_soc_dai_ops aic3x_dai_ops
= {
1419 .hw_params
= aic3x_hw_params
,
1420 .prepare
= aic3x_prepare
,
1421 .digital_mute
= aic3x_mute
,
1422 .set_sysclk
= aic3x_set_dai_sysclk
,
1423 .set_fmt
= aic3x_set_dai_fmt
,
1424 .set_tdm_slot
= aic3x_set_dai_tdm_slot
,
1427 static struct snd_soc_dai_driver aic3x_dai
= {
1428 .name
= "tlv320aic3x-hifi",
1430 .stream_name
= "Playback",
1433 .rates
= AIC3X_RATES
,
1434 .formats
= AIC3X_FORMATS
,},
1436 .stream_name
= "Capture",
1439 .rates
= AIC3X_RATES
,
1440 .formats
= AIC3X_FORMATS
,},
1441 .ops
= &aic3x_dai_ops
,
1442 .symmetric_rates
= 1,
1445 static void aic3x_mono_init(struct snd_soc_codec
*codec
)
1447 /* DAC to Mono Line Out default volume and route to Output mixer */
1448 snd_soc_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1449 snd_soc_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1451 /* unmute all outputs */
1452 snd_soc_update_bits(codec
, MONOLOPM_CTRL
, UNMUTE
, UNMUTE
);
1454 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1455 snd_soc_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1456 snd_soc_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1458 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1459 snd_soc_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1460 snd_soc_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1464 * initialise the AIC3X driver
1465 * register the mixer and dsp interfaces with the kernel
1467 static int aic3x_init(struct snd_soc_codec
*codec
)
1469 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1471 snd_soc_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1472 snd_soc_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1474 /* DAC default volume and mute */
1475 snd_soc_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1476 snd_soc_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1478 /* DAC to HP default volume and route to Output mixer */
1479 snd_soc_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1480 snd_soc_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1481 snd_soc_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1482 snd_soc_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1483 /* DAC to Line Out default volume and route to Output mixer */
1484 snd_soc_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1485 snd_soc_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1487 /* unmute all outputs */
1488 snd_soc_update_bits(codec
, LLOPM_CTRL
, UNMUTE
, UNMUTE
);
1489 snd_soc_update_bits(codec
, RLOPM_CTRL
, UNMUTE
, UNMUTE
);
1490 snd_soc_update_bits(codec
, HPLOUT_CTRL
, UNMUTE
, UNMUTE
);
1491 snd_soc_update_bits(codec
, HPROUT_CTRL
, UNMUTE
, UNMUTE
);
1492 snd_soc_update_bits(codec
, HPLCOM_CTRL
, UNMUTE
, UNMUTE
);
1493 snd_soc_update_bits(codec
, HPRCOM_CTRL
, UNMUTE
, UNMUTE
);
1495 /* ADC default volume and unmute */
1496 snd_soc_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1497 snd_soc_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1498 /* By default route Line1 to ADC PGA mixer */
1499 snd_soc_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1500 snd_soc_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1502 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1503 snd_soc_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1504 snd_soc_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1505 snd_soc_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1506 snd_soc_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1507 /* PGA to Line Out default volume, disconnect from Output Mixer */
1508 snd_soc_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1509 snd_soc_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1511 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1512 snd_soc_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1513 snd_soc_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1514 snd_soc_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1515 snd_soc_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1516 /* Line2 Line Out default volume, disconnect from Output Mixer */
1517 snd_soc_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1518 snd_soc_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1520 switch (aic3x
->model
) {
1521 case AIC3X_MODEL_3X
:
1522 case AIC3X_MODEL_33
:
1523 aic3x_mono_init(codec
);
1525 case AIC3X_MODEL_3007
:
1526 snd_soc_write(codec
, CLASSD_CTRL
, 0);
1533 static bool aic3x_is_shared_reset(struct aic3x_priv
*aic3x
)
1535 struct aic3x_priv
*a
;
1537 list_for_each_entry(a
, &reset_list
, list
) {
1538 if (gpio_is_valid(aic3x
->gpio_reset
) &&
1539 aic3x
->gpio_reset
== a
->gpio_reset
)
1546 static int aic3x_probe(struct snd_soc_codec
*codec
)
1548 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1551 INIT_LIST_HEAD(&aic3x
->list
);
1552 aic3x
->codec
= codec
;
1554 for (i
= 0; i
< ARRAY_SIZE(aic3x
->supplies
); i
++) {
1555 aic3x
->disable_nb
[i
].nb
.notifier_call
= aic3x_regulator_event
;
1556 aic3x
->disable_nb
[i
].aic3x
= aic3x
;
1557 ret
= regulator_register_notifier(aic3x
->supplies
[i
].consumer
,
1558 &aic3x
->disable_nb
[i
].nb
);
1561 "Failed to request regulator notifier: %d\n",
1567 regcache_mark_dirty(aic3x
->regmap
);
1571 if (aic3x
->model
!= AIC3X_MODEL_3104
) {
1572 /* setup GPIO functions */
1573 snd_soc_write(codec
, AIC3X_GPIO1_REG
,
1574 (aic3x
->setup
->gpio_func
[0] & 0xf) << 4);
1575 snd_soc_write(codec
, AIC3X_GPIO2_REG
,
1576 (aic3x
->setup
->gpio_func
[1] & 0xf) << 4);
1578 dev_warn(codec
->dev
, "GPIO functionality is not supported on tlv320aic3104\n");
1582 switch (aic3x
->model
) {
1583 case AIC3X_MODEL_3X
:
1584 case AIC3X_MODEL_33
:
1585 snd_soc_add_codec_controls(codec
, aic3x_extra_snd_controls
,
1586 ARRAY_SIZE(aic3x_extra_snd_controls
));
1587 snd_soc_add_codec_controls(codec
, aic3x_mono_controls
,
1588 ARRAY_SIZE(aic3x_mono_controls
));
1590 case AIC3X_MODEL_3007
:
1591 snd_soc_add_codec_controls(codec
, aic3x_extra_snd_controls
,
1592 ARRAY_SIZE(aic3x_extra_snd_controls
));
1593 snd_soc_add_codec_controls(codec
,
1594 &aic3x_classd_amp_gain_ctrl
, 1);
1596 case AIC3X_MODEL_3104
:
1600 /* set mic bias voltage */
1601 switch (aic3x
->micbias_vg
) {
1602 case AIC3X_MICBIAS_2_0V
:
1603 case AIC3X_MICBIAS_2_5V
:
1604 case AIC3X_MICBIAS_AVDDV
:
1605 snd_soc_update_bits(codec
, MICBIAS_CTRL
,
1607 (aic3x
->micbias_vg
) << MICBIAS_LEVEL_SHIFT
);
1609 case AIC3X_MICBIAS_OFF
:
1611 * noting to do. target won't enter here. This is just to avoid
1612 * compile time warning "warning: enumeration value
1613 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1618 aic3x_add_widgets(codec
);
1624 regulator_unregister_notifier(aic3x
->supplies
[i
].consumer
,
1625 &aic3x
->disable_nb
[i
].nb
);
1629 static int aic3x_remove(struct snd_soc_codec
*codec
)
1631 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1634 list_del(&aic3x
->list
);
1635 for (i
= 0; i
< ARRAY_SIZE(aic3x
->supplies
); i
++)
1636 regulator_unregister_notifier(aic3x
->supplies
[i
].consumer
,
1637 &aic3x
->disable_nb
[i
].nb
);
1642 static struct snd_soc_codec_driver soc_codec_dev_aic3x
= {
1643 .set_bias_level
= aic3x_set_bias_level
,
1644 .idle_bias_off
= true,
1645 .probe
= aic3x_probe
,
1646 .remove
= aic3x_remove
,
1647 .controls
= aic3x_snd_controls
,
1648 .num_controls
= ARRAY_SIZE(aic3x_snd_controls
),
1649 .dapm_widgets
= aic3x_dapm_widgets
,
1650 .num_dapm_widgets
= ARRAY_SIZE(aic3x_dapm_widgets
),
1651 .dapm_routes
= intercon
,
1652 .num_dapm_routes
= ARRAY_SIZE(intercon
),
1656 * AIC3X 2 wire address can be up to 4 devices with device addresses
1657 * 0x18, 0x19, 0x1A, 0x1B
1660 static const struct i2c_device_id aic3x_i2c_id
[] = {
1661 { "tlv320aic3x", AIC3X_MODEL_3X
},
1662 { "tlv320aic33", AIC3X_MODEL_33
},
1663 { "tlv320aic3007", AIC3X_MODEL_3007
},
1664 { "tlv320aic3106", AIC3X_MODEL_3X
},
1665 { "tlv320aic3104", AIC3X_MODEL_3104
},
1668 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1670 static const struct reg_default aic3007_class_d
[] = {
1671 /* Class-D speaker driver init; datasheet p. 46 */
1672 { AIC3X_PAGE_SELECT
, 0x0D },
1677 { AIC3X_PAGE_SELECT
, 0x00 },
1681 * If the i2c layer weren't so broken, we could pass this kind of data
1684 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1685 const struct i2c_device_id
*id
)
1687 struct aic3x_pdata
*pdata
= i2c
->dev
.platform_data
;
1688 struct aic3x_priv
*aic3x
;
1689 struct aic3x_setup_data
*ai3x_setup
;
1690 struct device_node
*np
= i2c
->dev
.of_node
;
1694 aic3x
= devm_kzalloc(&i2c
->dev
, sizeof(struct aic3x_priv
), GFP_KERNEL
);
1698 aic3x
->regmap
= devm_regmap_init_i2c(i2c
, &aic3x_regmap
);
1699 if (IS_ERR(aic3x
->regmap
)) {
1700 ret
= PTR_ERR(aic3x
->regmap
);
1704 regcache_cache_only(aic3x
->regmap
, true);
1706 i2c_set_clientdata(i2c
, aic3x
);
1708 aic3x
->gpio_reset
= pdata
->gpio_reset
;
1709 aic3x
->setup
= pdata
->setup
;
1710 aic3x
->micbias_vg
= pdata
->micbias_vg
;
1712 ai3x_setup
= devm_kzalloc(&i2c
->dev
, sizeof(*ai3x_setup
),
1717 ret
= of_get_named_gpio(np
, "gpio-reset", 0);
1719 aic3x
->gpio_reset
= ret
;
1721 aic3x
->gpio_reset
= -1;
1723 if (of_property_read_u32_array(np
, "ai3x-gpio-func",
1724 ai3x_setup
->gpio_func
, 2) >= 0) {
1725 aic3x
->setup
= ai3x_setup
;
1728 if (!of_property_read_u32(np
, "ai3x-micbias-vg", &value
)) {
1731 aic3x
->micbias_vg
= AIC3X_MICBIAS_2_0V
;
1734 aic3x
->micbias_vg
= AIC3X_MICBIAS_2_5V
;
1737 aic3x
->micbias_vg
= AIC3X_MICBIAS_AVDDV
;
1740 aic3x
->micbias_vg
= AIC3X_MICBIAS_OFF
;
1741 dev_err(&i2c
->dev
, "Unsuitable MicBias voltage "
1745 aic3x
->micbias_vg
= AIC3X_MICBIAS_OFF
;
1749 aic3x
->gpio_reset
= -1;
1752 aic3x
->model
= id
->driver_data
;
1754 if (gpio_is_valid(aic3x
->gpio_reset
) &&
1755 !aic3x_is_shared_reset(aic3x
)) {
1756 ret
= gpio_request(aic3x
->gpio_reset
, "tlv320aic3x reset");
1759 gpio_direction_output(aic3x
->gpio_reset
, 0);
1762 for (i
= 0; i
< ARRAY_SIZE(aic3x
->supplies
); i
++)
1763 aic3x
->supplies
[i
].supply
= aic3x_supply_names
[i
];
1765 ret
= devm_regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(aic3x
->supplies
),
1768 dev_err(&i2c
->dev
, "Failed to request supplies: %d\n", ret
);
1772 if (aic3x
->model
== AIC3X_MODEL_3007
) {
1773 ret
= regmap_register_patch(aic3x
->regmap
, aic3007_class_d
,
1774 ARRAY_SIZE(aic3007_class_d
));
1776 dev_err(&i2c
->dev
, "Failed to init class D: %d\n",
1780 ret
= snd_soc_register_codec(&i2c
->dev
,
1781 &soc_codec_dev_aic3x
, &aic3x_dai
, 1);
1786 list_add(&aic3x
->list
, &reset_list
);
1791 if (gpio_is_valid(aic3x
->gpio_reset
) &&
1792 !aic3x_is_shared_reset(aic3x
))
1793 gpio_free(aic3x
->gpio_reset
);
1798 static int aic3x_i2c_remove(struct i2c_client
*client
)
1800 struct aic3x_priv
*aic3x
= i2c_get_clientdata(client
);
1802 snd_soc_unregister_codec(&client
->dev
);
1803 if (gpio_is_valid(aic3x
->gpio_reset
) &&
1804 !aic3x_is_shared_reset(aic3x
)) {
1805 gpio_set_value(aic3x
->gpio_reset
, 0);
1806 gpio_free(aic3x
->gpio_reset
);
1811 #if defined(CONFIG_OF)
1812 static const struct of_device_id tlv320aic3x_of_match
[] = {
1813 { .compatible
= "ti,tlv320aic3x", },
1814 { .compatible
= "ti,tlv320aic33" },
1815 { .compatible
= "ti,tlv320aic3007" },
1816 { .compatible
= "ti,tlv320aic3106" },
1817 { .compatible
= "ti,tlv320aic3104" },
1820 MODULE_DEVICE_TABLE(of
, tlv320aic3x_of_match
);
1823 /* machine i2c codec control layer */
1824 static struct i2c_driver aic3x_i2c_driver
= {
1826 .name
= "tlv320aic3x-codec",
1827 .owner
= THIS_MODULE
,
1828 .of_match_table
= of_match_ptr(tlv320aic3x_of_match
),
1830 .probe
= aic3x_i2c_probe
,
1831 .remove
= aic3x_i2c_remove
,
1832 .id_table
= aic3x_i2c_id
,
1835 module_i2c_driver(aic3x_i2c_driver
);
1837 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1838 MODULE_AUTHOR("Vladimir Barinov");
1839 MODULE_LICENSE("GPL");