sound/soc/codecs/tlv320aic3x.h

   1 /*
   2  * ALSA SoC TLV320AIC3X codec driver
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef _AIC3X_H
  13 #define _AIC3X_H
  14
  15 /* AIC3X register space */
  16 #define AIC3X_CACHEREGNUM               103
  17
  18 /* Page select register */
  19 #define AIC3X_PAGE_SELECT               0
  20 /* Software reset register */
  21 #define AIC3X_RESET                     1
  22 /* Codec Sample rate select register */
  23 #define AIC3X_SAMPLE_RATE_SEL_REG       2
  24 /* PLL progrramming register A */
  25 #define AIC3X_PLL_PROGA_REG             3
  26 /* PLL progrramming register B */
  27 #define AIC3X_PLL_PROGB_REG             4
  28 /* PLL progrramming register C */
  29 #define AIC3X_PLL_PROGC_REG             5
  30 /* PLL progrramming register D */
  31 #define AIC3X_PLL_PROGD_REG             6
  32 /* Codec datapath setup register */
  33 #define AIC3X_CODEC_DATAPATH_REG        7
  34 /* Audio serial data interface control register A */
  35 #define AIC3X_ASD_INTF_CTRLA            8
  36 /* Audio serial data interface control register B */
  37 #define AIC3X_ASD_INTF_CTRLB            9
  38 /* Audio overflow status and PLL R value programming register */
  39 #define AIC3X_OVRF_STATUS_AND_PLLR_REG  11
  40 /* Audio codec digital filter control register */
  41 #define AIC3X_CODEC_DFILT_CTRL          12
  42
  43 /* ADC PGA Gain control registers */
  44 #define LADC_VOL                        15
  45 #define RADC_VOL                        16
  46 /* MIC3 control registers */
  47 #define MIC3LR_2_LADC_CTRL              17
  48 #define MIC3LR_2_RADC_CTRL              18
  49 /* Line1 Input control registers */
  50 #define LINE1L_2_LADC_CTRL              19
  51 #define LINE1R_2_RADC_CTRL              22
  52 /* Line2 Input control registers */
  53 #define LINE2L_2_LADC_CTRL              20
  54 #define LINE2R_2_RADC_CTRL              23
  55 /* MICBIAS Control Register */
  56 #define MICBIAS_CTRL                    25
  57
  58 /* AGC Control Registers A, B, C */
  59 #define LAGC_CTRL_A                     26
  60 #define LAGC_CTRL_B                     27
  61 #define LAGC_CTRL_C                     28
  62 #define RAGC_CTRL_A                     29
  63 #define RAGC_CTRL_B                     30
  64 #define RAGC_CTRL_C                     31
  65
  66 /* DAC Power and Left High Power Output control registers */
  67 #define DAC_PWR                         37
  68 #define HPLCOM_CFG                      37
  69 /* Right High Power Output control registers */
  70 #define HPRCOM_CFG                      38
  71 /* DAC Output Switching control registers */
  72 #define DAC_LINE_MUX                    41
  73 /* High Power Output Driver Pop Reduction registers */
  74 #define HPOUT_POP_REDUCTION             42
  75 /* DAC Digital control registers */
  76 #define LDAC_VOL                        43
  77 #define RDAC_VOL                        44
  78 /* High Power Output control registers */
  79 #define LINE2L_2_HPLOUT_VOL             45
  80 #define LINE2R_2_HPROUT_VOL             62
  81 #define PGAL_2_HPLOUT_VOL               46
  82 #define PGAR_2_HPROUT_VOL               63
  83 #define DACL1_2_HPLOUT_VOL              47
  84 #define DACR1_2_HPROUT_VOL              64
  85 #define HPLOUT_CTRL                     51
  86 #define HPROUT_CTRL                     65
  87 /* High Power COM control registers */
  88 #define LINE2L_2_HPLCOM_VOL             52
  89 #define LINE2R_2_HPRCOM_VOL             69
  90 #define PGAL_2_HPLCOM_VOL               53
  91 #define PGAR_2_HPRCOM_VOL               70
  92 #define DACL1_2_HPLCOM_VOL              54
  93 #define DACR1_2_HPRCOM_VOL              71
  94 #define HPLCOM_CTRL                     58
  95 #define HPRCOM_CTRL                     72
  96 /* Mono Line Output Plus/Minus control registers */
  97 #define LINE2L_2_MONOLOPM_VOL           73
  98 #define LINE2R_2_MONOLOPM_VOL           76
  99 #define PGAL_2_MONOLOPM_VOL             74
 100 #define PGAR_2_MONOLOPM_VOL             77
 101 #define DACL1_2_MONOLOPM_VOL            75
 102 #define DACR1_2_MONOLOPM_VOL            78
 103 #define MONOLOPM_CTRL                   79
 104 /* Line Output Plus/Minus control registers */
 105 #define LINE2L_2_LLOPM_VOL              80
 106 #define LINE2R_2_RLOPM_VOL              90
 107 #define PGAL_2_LLOPM_VOL                81
 108 #define PGAR_2_RLOPM_VOL                91
 109 #define DACL1_2_LLOPM_VOL               82
 110 #define DACR1_2_RLOPM_VOL               92
 111 #define LLOPM_CTRL                      86
 112 #define RLOPM_CTRL                      93
 113 /* GPIO/IRQ registers */
 114 #define AIC3X_STICKY_IRQ_FLAGS_REG      96
 115 #define AIC3X_RT_IRQ_FLAGS_REG          97
 116 #define AIC3X_GPIO1_REG                 98
 117 #define AIC3X_GPIO2_REG                 99
 118 #define AIC3X_GPIOA_REG                 100
 119 #define AIC3X_GPIOB_REG                 101
 120 /* Clock generation control register */
 121 #define AIC3X_CLKGEN_CTRL_REG           102
 122
 123 /* Page select register bits */
 124 #define PAGE0_SELECT            0
 125 #define PAGE1_SELECT            1
 126
 127 /* Audio serial data interface control register A bits */
 128 #define BIT_CLK_MASTER          0x80
 129 #define WORD_CLK_MASTER         0x40
 130
 131 /* Codec Datapath setup register 7 */
 132 #define FSREF_44100             (1 << 7)
 133 #define FSREF_48000             (0 << 7)
 134 #define DUAL_RATE_MODE          ((1 << 5) | (1 << 6))
 135 #define LDAC2LCH                (0x1 << 3)
 136 #define RDAC2RCH                (0x1 << 1)
 137
 138 /* PLL registers bitfields */
 139 #define PLLP_SHIFT              0
 140 #define PLLQ_SHIFT              3
 141 #define PLLR_SHIFT              0
 142 #define PLLJ_SHIFT              2
 143 #define PLLD_MSB_SHIFT          0
 144 #define PLLD_LSB_SHIFT          2
 145
 146 /* Clock generation register bits */
 147 #define CODEC_CLKIN_PLLDIV      0
 148 #define CODEC_CLKIN_CLKDIV      1
 149 #define PLL_CLKIN_SHIFT         4
 150 #define MCLK_SOURCE             0x0
 151 #define PLL_CLKDIV_SHIFT        0
 152
 153 /* Software reset register bits */
 154 #define SOFT_RESET              0x80
 155
 156 /* PLL progrramming register A bits */
 157 #define PLL_ENABLE              0x80
 158
 159 /* Route bits */
 160 #define ROUTE_ON                0x80
 161
 162 /* Mute bits */
 163 #define UNMUTE                  0x08
 164 #define MUTE_ON                 0x80
 165
 166 /* Power bits */
 167 #define LADC_PWR_ON             0x04
 168 #define RADC_PWR_ON             0x04
 169 #define LDAC_PWR_ON             0x80
 170 #define RDAC_PWR_ON             0x40
 171 #define HPLOUT_PWR_ON           0x01
 172 #define HPROUT_PWR_ON           0x01
 173 #define HPLCOM_PWR_ON           0x01
 174 #define HPRCOM_PWR_ON           0x01
 175 #define MONOLOPM_PWR_ON         0x01
 176 #define LLOPM_PWR_ON            0x01
 177 #define RLOPM_PWR_ON    0x01
 178
 179 #define INVERT_VOL(val)   (0x7f - val)
 180
 181 /* Default output volume (inverted) */
 182 #define DEFAULT_VOL     INVERT_VOL(0x50)
 183 /* Default input volume */
 184 #define DEFAULT_GAIN    0x20
 185
 186 /* GPIO API */
 187 enum {
 188         AIC3X_GPIO1_FUNC_DISABLED               = 0,
 189         AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC      = 1,
 190         AIC3X_GPIO1_FUNC_CLOCK_MUX              = 2,
 191         AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2         = 3,
 192         AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4         = 4,
 193         AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8         = 5,
 194         AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ      = 6,
 195         AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ          = 7,
 196         AIC3X_GPIO1_FUNC_INPUT                  = 8,
 197         AIC3X_GPIO1_FUNC_OUTPUT                 = 9,
 198         AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK     = 10,
 199         AIC3X_GPIO1_FUNC_AUDIO_WORDCLK          = 11,
 200         AIC3X_GPIO1_FUNC_BUTTON_IRQ             = 12,
 201         AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ     = 13,
 202         AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ   = 14,
 203         AIC3X_GPIO1_FUNC_ALL_IRQ                = 16
 204 };
 205
 206 enum {
 207         AIC3X_GPIO2_FUNC_DISABLED               = 0,
 208         AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ     = 2,
 209         AIC3X_GPIO2_FUNC_INPUT                  = 3,
 210         AIC3X_GPIO2_FUNC_OUTPUT                 = 4,
 211         AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT      = 5,
 212         AIC3X_GPIO2_FUNC_AUDIO_BITCLK           = 8,
 213         AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
 214         AIC3X_GPIO2_FUNC_ALL_IRQ                = 10,
 215         AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
 216         AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
 217         AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ      = 13,
 218         AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ          = 14,
 219         AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ       = 15
 220 };
 221
 222 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
 223 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
 224 int aic3x_headset_detected(struct snd_soc_codec *codec);
 225
 226 struct aic3x_setup_data {
 227         int i2c_bus;
 228         unsigned short i2c_address;
 229         unsigned int gpio_func[2];
 230 };
 231
 232 extern struct snd_soc_dai aic3x_dai;
 233 extern struct snd_soc_codec_device soc_codec_dev_aic3x;
 234
 235 #endif /* _AIC3X_H */