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ASoC: tlv320dac33: Avoid powering off while in BIAS_OFF
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
1 /*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
44
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49 #define NSAMPLE_MAX 5700
50
51 #define LATENCY_TIME_MS 20
52
53 #define MODE7_LTHR 10
54 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
56 #define BURST_BASEFREQ_HZ 49152000
57
58 #define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61 #define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64 static void dac33_calculate_times(struct snd_pcm_substream *substream);
65 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
66
67 static struct snd_soc_codec *tlv320dac33_codec;
68
69 enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74 };
75
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
79 DAC33_FIFO_MODE7,
80 DAC33_FIFO_LAST_MODE,
81 };
82
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88 };
89
90 struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
104 * this */
105 unsigned int nsample_max; /* nsample should not be higher than
106 * this */
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
108 unsigned int nsample; /* burst read amount from host */
109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
110 unsigned int burst_rate; /* Interface speed in Burst modes */
111
112 int keep_bclk; /* Keep the BCLK continuously running
113 * in FIFO modes */
114 spinlock_t lock;
115 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
116 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
117
118 unsigned int mode1_us_burst; /* Time to burst read n number of
119 * samples */
120 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
121
122 enum dac33_state state;
123 };
124
125 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
126 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
127 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
128 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
129 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
130 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
131 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
132 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
133 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
134 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
135 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
136 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
137 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
138 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
139 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
140 0x00, 0x00, /* 0x38 - 0x39 */
141 /* Registers 0x3a - 0x3f are reserved */
142 0x00, 0x00, /* 0x3a - 0x3b */
143 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
144
145 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
146 0x00, 0x80, /* 0x44 - 0x45 */
147 /* Registers 0x46 - 0x47 are reserved */
148 0x80, 0x80, /* 0x46 - 0x47 */
149
150 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
151 /* Registers 0x4b - 0x7c are reserved */
152 0x00, /* 0x4b */
153 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
154 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
155 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
156 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
157 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
158 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
159 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
160 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
161 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
162 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
163 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
164 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
165 0x00, /* 0x7c */
166
167 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
168 };
169
170 /* Register read and write */
171 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
172 unsigned reg)
173 {
174 u8 *cache = codec->reg_cache;
175 if (reg >= DAC33_CACHEREGNUM)
176 return 0;
177
178 return cache[reg];
179 }
180
181 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
182 u8 reg, u8 value)
183 {
184 u8 *cache = codec->reg_cache;
185 if (reg >= DAC33_CACHEREGNUM)
186 return;
187
188 cache[reg] = value;
189 }
190
191 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
192 u8 *value)
193 {
194 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
195 int val;
196
197 *value = reg & 0xff;
198
199 /* If powered off, return the cached value */
200 if (dac33->chip_power) {
201 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
202 if (val < 0) {
203 dev_err(codec->dev, "Read failed (%d)\n", val);
204 value[0] = dac33_read_reg_cache(codec, reg);
205 } else {
206 value[0] = val;
207 dac33_write_reg_cache(codec, reg, val);
208 }
209 } else {
210 value[0] = dac33_read_reg_cache(codec, reg);
211 }
212
213 return 0;
214 }
215
216 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
217 unsigned int value)
218 {
219 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
220 u8 data[2];
221 int ret = 0;
222
223 /*
224 * data is
225 * D15..D8 dac33 register offset
226 * D7...D0 register data
227 */
228 data[0] = reg & 0xff;
229 data[1] = value & 0xff;
230
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 if (dac33->chip_power) {
233 ret = codec->hw_write(codec->control_data, data, 2);
234 if (ret != 2)
235 dev_err(codec->dev, "Write failed (%d)\n", ret);
236 else
237 ret = 0;
238 }
239
240 return ret;
241 }
242
243 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
244 unsigned int value)
245 {
246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
247 int ret;
248
249 mutex_lock(&dac33->mutex);
250 ret = dac33_write(codec, reg, value);
251 mutex_unlock(&dac33->mutex);
252
253 return ret;
254 }
255
256 #define DAC33_I2C_ADDR_AUTOINC 0x80
257 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
258 unsigned int value)
259 {
260 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
261 u8 data[3];
262 int ret = 0;
263
264 /*
265 * data is
266 * D23..D16 dac33 register offset
267 * D15..D8 register data MSB
268 * D7...D0 register data LSB
269 */
270 data[0] = reg & 0xff;
271 data[1] = (value >> 8) & 0xff;
272 data[2] = value & 0xff;
273
274 dac33_write_reg_cache(codec, data[0], data[1]);
275 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
276
277 if (dac33->chip_power) {
278 /* We need to set autoincrement mode for 16 bit writes */
279 data[0] |= DAC33_I2C_ADDR_AUTOINC;
280 ret = codec->hw_write(codec->control_data, data, 3);
281 if (ret != 3)
282 dev_err(codec->dev, "Write failed (%d)\n", ret);
283 else
284 ret = 0;
285 }
286
287 return ret;
288 }
289
290 static void dac33_init_chip(struct snd_soc_codec *codec)
291 {
292 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
293
294 if (unlikely(!dac33->chip_power))
295 return;
296
297 /* 44-46: DAC Control Registers */
298 /* A : DAC sample rate Fsref/1.5 */
299 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
300 /* B : DAC src=normal, not muted */
301 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
302 DAC33_DACSRCL_LEFT);
303 /* C : (defaults) */
304 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
305
306 /* 73 : volume soft stepping control,
307 clock source = internal osc (?) */
308 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
309
310 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
311
312 /* Restore only selected registers (gains mostly) */
313 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
314 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
315 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
316 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
317
318 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
319 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
320 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
321 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
322 }
323
324 static inline void dac33_read_id(struct snd_soc_codec *codec)
325 {
326 u8 reg;
327
328 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
329 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
330 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
331 }
332
333 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
334 {
335 u8 reg;
336
337 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
338 if (power)
339 reg |= DAC33_PDNALLB;
340 else
341 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
342 DAC33_DACRPDNB | DAC33_DACLPDNB);
343 dac33_write(codec, DAC33_PWR_CTRL, reg);
344 }
345
346 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
347 {
348 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
349 int ret = 0;
350
351 mutex_lock(&dac33->mutex);
352
353 /* Safety check */
354 if (unlikely(power == dac33->chip_power)) {
355 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
356 power ? "ON" : "OFF");
357 goto exit;
358 }
359
360 if (power) {
361 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
362 dac33->supplies);
363 if (ret != 0) {
364 dev_err(codec->dev,
365 "Failed to enable supplies: %d\n", ret);
366 goto exit;
367 }
368
369 if (dac33->power_gpio >= 0)
370 gpio_set_value(dac33->power_gpio, 1);
371
372 dac33->chip_power = 1;
373 } else {
374 dac33_soft_power(codec, 0);
375 if (dac33->power_gpio >= 0)
376 gpio_set_value(dac33->power_gpio, 0);
377
378 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
379 dac33->supplies);
380 if (ret != 0) {
381 dev_err(codec->dev,
382 "Failed to disable supplies: %d\n", ret);
383 goto exit;
384 }
385
386 dac33->chip_power = 0;
387 }
388
389 exit:
390 mutex_unlock(&dac33->mutex);
391 return ret;
392 }
393
394 static int playback_event(struct snd_soc_dapm_widget *w,
395 struct snd_kcontrol *kcontrol, int event)
396 {
397 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
398
399 switch (event) {
400 case SND_SOC_DAPM_PRE_PMU:
401 if (likely(dac33->substream)) {
402 dac33_calculate_times(dac33->substream);
403 dac33_prepare_chip(dac33->substream);
404 }
405 break;
406 }
407 return 0;
408 }
409
410 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
411 struct snd_ctl_elem_value *ucontrol)
412 {
413 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
414 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
415
416 ucontrol->value.integer.value[0] = dac33->nsample;
417
418 return 0;
419 }
420
421 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423 {
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
426 int ret = 0;
427
428 if (dac33->nsample == ucontrol->value.integer.value[0])
429 return 0;
430
431 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
432 ucontrol->value.integer.value[0] > dac33->nsample_max) {
433 ret = -EINVAL;
434 } else {
435 dac33->nsample = ucontrol->value.integer.value[0];
436 /* Re calculate the burst time */
437 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
438 dac33->nsample);
439 }
440
441 return ret;
442 }
443
444 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
445 struct snd_ctl_elem_value *ucontrol)
446 {
447 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
448 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
449
450 ucontrol->value.integer.value[0] = dac33->fifo_mode;
451
452 return 0;
453 }
454
455 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
457 {
458 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
459 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
460 int ret = 0;
461
462 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
463 return 0;
464 /* Do not allow changes while stream is running*/
465 if (codec->active)
466 return -EPERM;
467
468 if (ucontrol->value.integer.value[0] < 0 ||
469 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
470 ret = -EINVAL;
471 else
472 dac33->fifo_mode = ucontrol->value.integer.value[0];
473
474 return ret;
475 }
476
477 /* Codec operation modes */
478 static const char *dac33_fifo_mode_texts[] = {
479 "Bypass", "Mode 1", "Mode 7"
480 };
481
482 static const struct soc_enum dac33_fifo_mode_enum =
483 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
484 dac33_fifo_mode_texts);
485
486 /*
487 * DACL/R digital volume control:
488 * from 0 dB to -63.5 in 0.5 dB steps
489 * Need to be inverted later on:
490 * 0x00 == 0 dB
491 * 0x7f == -63.5 dB
492 */
493 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
494
495 static const struct snd_kcontrol_new dac33_snd_controls[] = {
496 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
497 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
498 0, 0x7f, 1, dac_digivol_tlv),
499 SOC_DOUBLE_R("DAC Digital Playback Switch",
500 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
501 SOC_DOUBLE_R("Line to Line Out Volume",
502 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
503 };
504
505 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
506 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
507 dac33_get_nsample, dac33_set_nsample),
508 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
509 dac33_get_fifo_mode, dac33_set_fifo_mode),
510 };
511
512 /* Analog bypass */
513 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
514 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
515
516 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
517 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
518
519 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
520 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
521 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
522
523 SND_SOC_DAPM_INPUT("LINEL"),
524 SND_SOC_DAPM_INPUT("LINER"),
525
526 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
527 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
528
529 /* Analog bypass */
530 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
531 &dac33_dapm_abypassl_control),
532 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
533 &dac33_dapm_abypassr_control),
534
535 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
536 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
537 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
538 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
539
540 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
541 };
542
543 static const struct snd_soc_dapm_route audio_map[] = {
544 /* Analog bypass */
545 {"Analog Left Bypass", "Switch", "LINEL"},
546 {"Analog Right Bypass", "Switch", "LINER"},
547
548 {"Output Left Amp Power", NULL, "DACL"},
549 {"Output Right Amp Power", NULL, "DACR"},
550
551 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
552 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
553
554 /* output */
555 {"LEFT_LO", NULL, "Output Left Amp Power"},
556 {"RIGHT_LO", NULL, "Output Right Amp Power"},
557 };
558
559 static int dac33_add_widgets(struct snd_soc_codec *codec)
560 {
561 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
562 ARRAY_SIZE(dac33_dapm_widgets));
563
564 /* set up audio path interconnects */
565 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
566
567 return 0;
568 }
569
570 static int dac33_set_bias_level(struct snd_soc_codec *codec,
571 enum snd_soc_bias_level level)
572 {
573 int ret;
574
575 switch (level) {
576 case SND_SOC_BIAS_ON:
577 dac33_soft_power(codec, 1);
578 break;
579 case SND_SOC_BIAS_PREPARE:
580 break;
581 case SND_SOC_BIAS_STANDBY:
582 if (codec->bias_level == SND_SOC_BIAS_OFF) {
583 /* Coming from OFF, switch on the codec */
584 ret = dac33_hard_power(codec, 1);
585 if (ret != 0)
586 return ret;
587
588 dac33_init_chip(codec);
589 }
590 break;
591 case SND_SOC_BIAS_OFF:
592 /* Do not power off, when the codec is already off */
593 if (codec->bias_level == SND_SOC_BIAS_OFF)
594 return 0;
595 ret = dac33_hard_power(codec, 0);
596 if (ret != 0)
597 return ret;
598 break;
599 }
600 codec->bias_level = level;
601
602 return 0;
603 }
604
605 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
606 {
607 struct snd_soc_codec *codec;
608
609 codec = &dac33->codec;
610
611 switch (dac33->fifo_mode) {
612 case DAC33_FIFO_MODE1:
613 dac33_write16(codec, DAC33_NSAMPLE_MSB,
614 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
615
616 /* Take the timestamps */
617 spin_lock_irq(&dac33->lock);
618 dac33->t_stamp2 = ktime_to_us(ktime_get());
619 dac33->t_stamp1 = dac33->t_stamp2;
620 spin_unlock_irq(&dac33->lock);
621
622 dac33_write16(codec, DAC33_PREFILL_MSB,
623 DAC33_THRREG(dac33->alarm_threshold));
624 /* Enable Alarm Threshold IRQ with a delay */
625 udelay(SAMPLES_TO_US(dac33->burst_rate,
626 dac33->alarm_threshold));
627 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
628 break;
629 case DAC33_FIFO_MODE7:
630 /* Take the timestamp */
631 spin_lock_irq(&dac33->lock);
632 dac33->t_stamp1 = ktime_to_us(ktime_get());
633 /* Move back the timestamp with drain time */
634 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
635 spin_unlock_irq(&dac33->lock);
636
637 dac33_write16(codec, DAC33_PREFILL_MSB,
638 DAC33_THRREG(MODE7_LTHR));
639
640 /* Enable Upper Threshold IRQ */
641 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
642 break;
643 default:
644 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
645 dac33->fifo_mode);
646 break;
647 }
648 }
649
650 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
651 {
652 struct snd_soc_codec *codec;
653
654 codec = &dac33->codec;
655
656 switch (dac33->fifo_mode) {
657 case DAC33_FIFO_MODE1:
658 /* Take the timestamp */
659 spin_lock_irq(&dac33->lock);
660 dac33->t_stamp2 = ktime_to_us(ktime_get());
661 spin_unlock_irq(&dac33->lock);
662
663 dac33_write16(codec, DAC33_NSAMPLE_MSB,
664 DAC33_THRREG(dac33->nsample));
665 break;
666 case DAC33_FIFO_MODE7:
667 /* At the moment we are not using interrupts in mode7 */
668 break;
669 default:
670 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
671 dac33->fifo_mode);
672 break;
673 }
674 }
675
676 static void dac33_work(struct work_struct *work)
677 {
678 struct snd_soc_codec *codec;
679 struct tlv320dac33_priv *dac33;
680 u8 reg;
681
682 dac33 = container_of(work, struct tlv320dac33_priv, work);
683 codec = &dac33->codec;
684
685 mutex_lock(&dac33->mutex);
686 switch (dac33->state) {
687 case DAC33_PREFILL:
688 dac33->state = DAC33_PLAYBACK;
689 dac33_prefill_handler(dac33);
690 break;
691 case DAC33_PLAYBACK:
692 dac33_playback_handler(dac33);
693 break;
694 case DAC33_IDLE:
695 break;
696 case DAC33_FLUSH:
697 dac33->state = DAC33_IDLE;
698 /* Mask all interrupts from dac33 */
699 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
700
701 /* flush fifo */
702 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
703 reg |= DAC33_FIFOFLUSH;
704 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
705 break;
706 }
707 mutex_unlock(&dac33->mutex);
708 }
709
710 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
711 {
712 struct snd_soc_codec *codec = dev;
713 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
714
715 spin_lock(&dac33->lock);
716 dac33->t_stamp1 = ktime_to_us(ktime_get());
717 spin_unlock(&dac33->lock);
718
719 /* Do not schedule the workqueue in Mode7 */
720 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
721 queue_work(dac33->dac33_wq, &dac33->work);
722
723 return IRQ_HANDLED;
724 }
725
726 static void dac33_oscwait(struct snd_soc_codec *codec)
727 {
728 int timeout = 20;
729 u8 reg;
730
731 do {
732 msleep(1);
733 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
734 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
735 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
736 dev_err(codec->dev,
737 "internal oscillator calibration failed\n");
738 }
739
740 static int dac33_startup(struct snd_pcm_substream *substream,
741 struct snd_soc_dai *dai)
742 {
743 struct snd_soc_pcm_runtime *rtd = substream->private_data;
744 struct snd_soc_device *socdev = rtd->socdev;
745 struct snd_soc_codec *codec = socdev->card->codec;
746 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
747
748 /* Stream started, save the substream pointer */
749 dac33->substream = substream;
750
751 return 0;
752 }
753
754 static void dac33_shutdown(struct snd_pcm_substream *substream,
755 struct snd_soc_dai *dai)
756 {
757 struct snd_soc_pcm_runtime *rtd = substream->private_data;
758 struct snd_soc_device *socdev = rtd->socdev;
759 struct snd_soc_codec *codec = socdev->card->codec;
760 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
761
762 dac33->substream = NULL;
763 }
764
765 static int dac33_hw_params(struct snd_pcm_substream *substream,
766 struct snd_pcm_hw_params *params,
767 struct snd_soc_dai *dai)
768 {
769 struct snd_soc_pcm_runtime *rtd = substream->private_data;
770 struct snd_soc_device *socdev = rtd->socdev;
771 struct snd_soc_codec *codec = socdev->card->codec;
772
773 /* Check parameters for validity */
774 switch (params_rate(params)) {
775 case 44100:
776 case 48000:
777 break;
778 default:
779 dev_err(codec->dev, "unsupported rate %d\n",
780 params_rate(params));
781 return -EINVAL;
782 }
783
784 switch (params_format(params)) {
785 case SNDRV_PCM_FORMAT_S16_LE:
786 break;
787 default:
788 dev_err(codec->dev, "unsupported format %d\n",
789 params_format(params));
790 return -EINVAL;
791 }
792
793 return 0;
794 }
795
796 #define CALC_OSCSET(rate, refclk) ( \
797 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
798 #define CALC_RATIOSET(rate, refclk) ( \
799 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
800
801 /*
802 * tlv320dac33 is strict on the sequence of the register writes, if the register
803 * writes happens in different order, than dac33 might end up in unknown state.
804 * Use the known, working sequence of register writes to initialize the dac33.
805 */
806 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
807 {
808 struct snd_soc_pcm_runtime *rtd = substream->private_data;
809 struct snd_soc_device *socdev = rtd->socdev;
810 struct snd_soc_codec *codec = socdev->card->codec;
811 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
812 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
813 u8 aictrl_a, aictrl_b, fifoctrl_a;
814
815 switch (substream->runtime->rate) {
816 case 44100:
817 case 48000:
818 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
819 ratioset = CALC_RATIOSET(substream->runtime->rate,
820 dac33->refclk);
821 break;
822 default:
823 dev_err(codec->dev, "unsupported rate %d\n",
824 substream->runtime->rate);
825 return -EINVAL;
826 }
827
828
829 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
830 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
831 /* Read FIFO control A, and clear FIFO flush bit */
832 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
833 fifoctrl_a &= ~DAC33_FIFOFLUSH;
834
835 fifoctrl_a &= ~DAC33_WIDTH;
836 switch (substream->runtime->format) {
837 case SNDRV_PCM_FORMAT_S16_LE:
838 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
839 fifoctrl_a |= DAC33_WIDTH;
840 break;
841 default:
842 dev_err(codec->dev, "unsupported format %d\n",
843 substream->runtime->format);
844 return -EINVAL;
845 }
846
847 mutex_lock(&dac33->mutex);
848
849 if (!dac33->chip_power) {
850 /*
851 * Chip is not powered yet.
852 * Do the init in the dac33_set_bias_level later.
853 */
854 mutex_unlock(&dac33->mutex);
855 return 0;
856 }
857
858 dac33_soft_power(codec, 0);
859 dac33_soft_power(codec, 1);
860
861 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
862 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
863
864 /* Write registers 0x08 and 0x09 (MSB, LSB) */
865 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
866
867 /* calib time: 128 is a nice number ;) */
868 dac33_write(codec, DAC33_CALIB_TIME, 128);
869
870 /* adjustment treshold & step */
871 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
872 DAC33_ADJSTEP(1));
873
874 /* div=4 / gain=1 / div */
875 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
876
877 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
878 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
879 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
880
881 dac33_oscwait(codec);
882
883 if (dac33->fifo_mode) {
884 /* Generic for all FIFO modes */
885 /* 50-51 : ASRC Control registers */
886 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
887 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
888
889 /* Write registers 0x34 and 0x35 (MSB, LSB) */
890 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
891
892 /* Set interrupts to high active */
893 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
894 } else {
895 /* FIFO bypass mode */
896 /* 50-51 : ASRC Control registers */
897 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
898 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
899 }
900
901 /* Interrupt behaviour configuration */
902 switch (dac33->fifo_mode) {
903 case DAC33_FIFO_MODE1:
904 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
905 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
906 break;
907 case DAC33_FIFO_MODE7:
908 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
909 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
910 break;
911 default:
912 /* in FIFO bypass mode, the interrupts are not used */
913 break;
914 }
915
916 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
917
918 switch (dac33->fifo_mode) {
919 case DAC33_FIFO_MODE1:
920 /*
921 * For mode1:
922 * Disable the FIFO bypass (Enable the use of FIFO)
923 * Select nSample mode
924 * BCLK is only running when data is needed by DAC33
925 */
926 fifoctrl_a &= ~DAC33_FBYPAS;
927 fifoctrl_a &= ~DAC33_FAUTO;
928 if (dac33->keep_bclk)
929 aictrl_b |= DAC33_BCLKON;
930 else
931 aictrl_b &= ~DAC33_BCLKON;
932 break;
933 case DAC33_FIFO_MODE7:
934 /*
935 * For mode1:
936 * Disable the FIFO bypass (Enable the use of FIFO)
937 * Select Threshold mode
938 * BCLK is only running when data is needed by DAC33
939 */
940 fifoctrl_a &= ~DAC33_FBYPAS;
941 fifoctrl_a |= DAC33_FAUTO;
942 if (dac33->keep_bclk)
943 aictrl_b |= DAC33_BCLKON;
944 else
945 aictrl_b &= ~DAC33_BCLKON;
946 break;
947 default:
948 /*
949 * For FIFO bypass mode:
950 * Enable the FIFO bypass (Disable the FIFO use)
951 * Set the BCLK as continous
952 */
953 fifoctrl_a |= DAC33_FBYPAS;
954 aictrl_b |= DAC33_BCLKON;
955 break;
956 }
957
958 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
959 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
960 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
961
962 /*
963 * BCLK divide ratio
964 * 0: 1.5
965 * 1: 1
966 * 2: 2
967 * ...
968 * 254: 254
969 * 255: 255
970 */
971 if (dac33->fifo_mode)
972 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
973 dac33->burst_bclkdiv);
974 else
975 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
976
977 switch (dac33->fifo_mode) {
978 case DAC33_FIFO_MODE1:
979 dac33_write16(codec, DAC33_ATHR_MSB,
980 DAC33_THRREG(dac33->alarm_threshold));
981 break;
982 case DAC33_FIFO_MODE7:
983 /*
984 * Configure the threshold levels, and leave 10 sample space
985 * at the bottom, and also at the top of the FIFO
986 */
987 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
988 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
989 break;
990 default:
991 break;
992 }
993
994 mutex_unlock(&dac33->mutex);
995
996 return 0;
997 }
998
999 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1000 {
1001 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1002 struct snd_soc_device *socdev = rtd->socdev;
1003 struct snd_soc_codec *codec = socdev->card->codec;
1004 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1005 unsigned int nsample_limit;
1006
1007 /* In bypass mode we don't need to calculate */
1008 if (!dac33->fifo_mode)
1009 return;
1010
1011 /* Number of samples (16bit, stereo) in one period */
1012 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1013
1014 /* Number of samples (16bit, stereo) in ALSA buffer */
1015 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1016 /* Subtract one period from the total */
1017 dac33->nsample_max -= dac33->nsample_min;
1018
1019 /* Number of samples for LATENCY_TIME_MS / 2 */
1020 dac33->alarm_threshold = substream->runtime->rate /
1021 (1000 / (LATENCY_TIME_MS / 2));
1022
1023 /* Find and fix up the lowest nsmaple limit */
1024 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1025
1026 if (dac33->nsample_min < nsample_limit)
1027 dac33->nsample_min = nsample_limit;
1028
1029 if (dac33->nsample < dac33->nsample_min)
1030 dac33->nsample = dac33->nsample_min;
1031
1032 /*
1033 * Find and fix up the highest nsmaple limit
1034 * In order to not overflow the DAC33 buffer substract the
1035 * alarm_threshold value from the size of the DAC33 buffer
1036 */
1037 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1038
1039 if (dac33->nsample_max > nsample_limit)
1040 dac33->nsample_max = nsample_limit;
1041
1042 if (dac33->nsample > dac33->nsample_max)
1043 dac33->nsample = dac33->nsample_max;
1044
1045 switch (dac33->fifo_mode) {
1046 case DAC33_FIFO_MODE1:
1047 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1048 dac33->nsample);
1049 dac33->t_stamp1 = 0;
1050 dac33->t_stamp2 = 0;
1051 break;
1052 case DAC33_FIFO_MODE7:
1053 dac33->mode7_us_to_lthr =
1054 SAMPLES_TO_US(substream->runtime->rate,
1055 MODE7_UTHR - MODE7_LTHR + 1);
1056 dac33->t_stamp1 = 0;
1057 break;
1058 default:
1059 break;
1060 }
1061
1062 }
1063
1064 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1065 struct snd_soc_dai *dai)
1066 {
1067 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1068 struct snd_soc_device *socdev = rtd->socdev;
1069 struct snd_soc_codec *codec = socdev->card->codec;
1070 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1071 int ret = 0;
1072
1073 switch (cmd) {
1074 case SNDRV_PCM_TRIGGER_START:
1075 case SNDRV_PCM_TRIGGER_RESUME:
1076 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1077 if (dac33->fifo_mode) {
1078 dac33->state = DAC33_PREFILL;
1079 queue_work(dac33->dac33_wq, &dac33->work);
1080 }
1081 break;
1082 case SNDRV_PCM_TRIGGER_STOP:
1083 case SNDRV_PCM_TRIGGER_SUSPEND:
1084 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1085 if (dac33->fifo_mode) {
1086 dac33->state = DAC33_FLUSH;
1087 queue_work(dac33->dac33_wq, &dac33->work);
1088 }
1089 break;
1090 default:
1091 ret = -EINVAL;
1092 }
1093
1094 return ret;
1095 }
1096
1097 static snd_pcm_sframes_t dac33_dai_delay(
1098 struct snd_pcm_substream *substream,
1099 struct snd_soc_dai *dai)
1100 {
1101 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1102 struct snd_soc_device *socdev = rtd->socdev;
1103 struct snd_soc_codec *codec = socdev->card->codec;
1104 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1105 unsigned long long t0, t1, t_now;
1106 unsigned int time_delta;
1107 int samples_out, samples_in, samples;
1108 snd_pcm_sframes_t delay = 0;
1109
1110 switch (dac33->fifo_mode) {
1111 case DAC33_FIFO_BYPASS:
1112 break;
1113 case DAC33_FIFO_MODE1:
1114 spin_lock(&dac33->lock);
1115 t0 = dac33->t_stamp1;
1116 t1 = dac33->t_stamp2;
1117 spin_unlock(&dac33->lock);
1118 t_now = ktime_to_us(ktime_get());
1119
1120 /* We have not started to fill the FIFO yet, delay is 0 */
1121 if (!t1)
1122 goto out;
1123
1124 if (t0 > t1) {
1125 /*
1126 * Phase 1:
1127 * After Alarm threshold, and before nSample write
1128 */
1129 time_delta = t_now - t0;
1130 samples_out = time_delta ? US_TO_SAMPLES(
1131 substream->runtime->rate,
1132 time_delta) : 0;
1133
1134 if (likely(dac33->alarm_threshold > samples_out))
1135 delay = dac33->alarm_threshold - samples_out;
1136 else
1137 delay = 0;
1138 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1139 /*
1140 * Phase 2:
1141 * After nSample write (during burst operation)
1142 */
1143 time_delta = t_now - t0;
1144 samples_out = time_delta ? US_TO_SAMPLES(
1145 substream->runtime->rate,
1146 time_delta) : 0;
1147
1148 time_delta = t_now - t1;
1149 samples_in = time_delta ? US_TO_SAMPLES(
1150 dac33->burst_rate,
1151 time_delta) : 0;
1152
1153 samples = dac33->alarm_threshold;
1154 samples += (samples_in - samples_out);
1155
1156 if (likely(samples > 0))
1157 delay = samples;
1158 else
1159 delay = 0;
1160 } else {
1161 /*
1162 * Phase 3:
1163 * After burst operation, before next alarm threshold
1164 */
1165 time_delta = t_now - t0;
1166 samples_out = time_delta ? US_TO_SAMPLES(
1167 substream->runtime->rate,
1168 time_delta) : 0;
1169
1170 samples_in = dac33->nsample;
1171 samples = dac33->alarm_threshold;
1172 samples += (samples_in - samples_out);
1173
1174 if (likely(samples > 0))
1175 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1176 DAC33_BUFFER_SIZE_SAMPLES : samples;
1177 else
1178 delay = 0;
1179 }
1180 break;
1181 case DAC33_FIFO_MODE7:
1182 spin_lock(&dac33->lock);
1183 t0 = dac33->t_stamp1;
1184 spin_unlock(&dac33->lock);
1185 t_now = ktime_to_us(ktime_get());
1186
1187 /* We have not started to fill the FIFO yet, delay is 0 */
1188 if (!t0)
1189 goto out;
1190
1191 if (t_now <= t0) {
1192 /*
1193 * Either the timestamps are messed or equal. Report
1194 * maximum delay
1195 */
1196 delay = MODE7_UTHR;
1197 goto out;
1198 }
1199
1200 time_delta = t_now - t0;
1201 if (time_delta <= dac33->mode7_us_to_lthr) {
1202 /*
1203 * Phase 1:
1204 * After burst (draining phase)
1205 */
1206 samples_out = US_TO_SAMPLES(
1207 substream->runtime->rate,
1208 time_delta);
1209
1210 if (likely(MODE7_UTHR > samples_out))
1211 delay = MODE7_UTHR - samples_out;
1212 else
1213 delay = 0;
1214 } else {
1215 /*
1216 * Phase 2:
1217 * During burst operation
1218 */
1219 time_delta = time_delta - dac33->mode7_us_to_lthr;
1220
1221 samples_out = US_TO_SAMPLES(
1222 substream->runtime->rate,
1223 time_delta);
1224 samples_in = US_TO_SAMPLES(
1225 dac33->burst_rate,
1226 time_delta);
1227 delay = MODE7_LTHR + samples_in - samples_out;
1228
1229 if (unlikely(delay > MODE7_UTHR))
1230 delay = MODE7_UTHR;
1231 }
1232 break;
1233 default:
1234 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1235 dac33->fifo_mode);
1236 break;
1237 }
1238 out:
1239 return delay;
1240 }
1241
1242 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1243 int clk_id, unsigned int freq, int dir)
1244 {
1245 struct snd_soc_codec *codec = codec_dai->codec;
1246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1247 u8 ioc_reg, asrcb_reg;
1248
1249 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1250 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1251 switch (clk_id) {
1252 case TLV320DAC33_MCLK:
1253 ioc_reg |= DAC33_REFSEL;
1254 asrcb_reg |= DAC33_SRCREFSEL;
1255 break;
1256 case TLV320DAC33_SLEEPCLK:
1257 ioc_reg &= ~DAC33_REFSEL;
1258 asrcb_reg &= ~DAC33_SRCREFSEL;
1259 break;
1260 default:
1261 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1262 break;
1263 }
1264 dac33->refclk = freq;
1265
1266 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1267 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1268
1269 return 0;
1270 }
1271
1272 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1273 unsigned int fmt)
1274 {
1275 struct snd_soc_codec *codec = codec_dai->codec;
1276 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1277 u8 aictrl_a, aictrl_b;
1278
1279 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1280 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1281 /* set master/slave audio interface */
1282 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1283 case SND_SOC_DAIFMT_CBM_CFM:
1284 /* Codec Master */
1285 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1286 break;
1287 case SND_SOC_DAIFMT_CBS_CFS:
1288 /* Codec Slave */
1289 if (dac33->fifo_mode) {
1290 dev_err(codec->dev, "FIFO mode requires master mode\n");
1291 return -EINVAL;
1292 } else
1293 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1294 break;
1295 default:
1296 return -EINVAL;
1297 }
1298
1299 aictrl_a &= ~DAC33_AFMT_MASK;
1300 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1301 case SND_SOC_DAIFMT_I2S:
1302 aictrl_a |= DAC33_AFMT_I2S;
1303 break;
1304 case SND_SOC_DAIFMT_DSP_A:
1305 aictrl_a |= DAC33_AFMT_DSP;
1306 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1307 aictrl_b |= DAC33_DATA_DELAY(0);
1308 break;
1309 case SND_SOC_DAIFMT_RIGHT_J:
1310 aictrl_a |= DAC33_AFMT_RIGHT_J;
1311 break;
1312 case SND_SOC_DAIFMT_LEFT_J:
1313 aictrl_a |= DAC33_AFMT_LEFT_J;
1314 break;
1315 default:
1316 dev_err(codec->dev, "Unsupported format (%u)\n",
1317 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1318 return -EINVAL;
1319 }
1320
1321 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1322 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1323
1324 return 0;
1325 }
1326
1327 static int dac33_soc_probe(struct platform_device *pdev)
1328 {
1329 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1330 struct snd_soc_codec *codec;
1331 struct tlv320dac33_priv *dac33;
1332 int ret = 0;
1333
1334 BUG_ON(!tlv320dac33_codec);
1335
1336 codec = tlv320dac33_codec;
1337 socdev->card->codec = codec;
1338 dac33 = snd_soc_codec_get_drvdata(codec);
1339
1340 /* register pcms */
1341 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1342 if (ret < 0) {
1343 dev_err(codec->dev, "failed to create pcms\n");
1344 goto pcm_err;
1345 }
1346
1347 snd_soc_add_controls(codec, dac33_snd_controls,
1348 ARRAY_SIZE(dac33_snd_controls));
1349 /* Only add the nSample controls, if we have valid IRQ number */
1350 if (dac33->irq >= 0)
1351 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1352 ARRAY_SIZE(dac33_nsample_snd_controls));
1353
1354 dac33_add_widgets(codec);
1355
1356 return 0;
1357
1358 pcm_err:
1359 dac33_hard_power(codec, 0);
1360 return ret;
1361 }
1362
1363 static int dac33_soc_remove(struct platform_device *pdev)
1364 {
1365 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1366 struct snd_soc_codec *codec = socdev->card->codec;
1367
1368 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1369
1370 snd_soc_free_pcms(socdev);
1371 snd_soc_dapm_free(socdev);
1372
1373 return 0;
1374 }
1375
1376 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1377 {
1378 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1379 struct snd_soc_codec *codec = socdev->card->codec;
1380
1381 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1382
1383 return 0;
1384 }
1385
1386 static int dac33_soc_resume(struct platform_device *pdev)
1387 {
1388 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1389 struct snd_soc_codec *codec = socdev->card->codec;
1390
1391 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1392
1393 return 0;
1394 }
1395
1396 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1397 .probe = dac33_soc_probe,
1398 .remove = dac33_soc_remove,
1399 .suspend = dac33_soc_suspend,
1400 .resume = dac33_soc_resume,
1401 };
1402 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1403
1404 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1405 SNDRV_PCM_RATE_48000)
1406 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1407
1408 static struct snd_soc_dai_ops dac33_dai_ops = {
1409 .startup = dac33_startup,
1410 .shutdown = dac33_shutdown,
1411 .hw_params = dac33_hw_params,
1412 .trigger = dac33_pcm_trigger,
1413 .delay = dac33_dai_delay,
1414 .set_sysclk = dac33_set_dai_sysclk,
1415 .set_fmt = dac33_set_dai_fmt,
1416 };
1417
1418 struct snd_soc_dai dac33_dai = {
1419 .name = "tlv320dac33",
1420 .playback = {
1421 .stream_name = "Playback",
1422 .channels_min = 2,
1423 .channels_max = 2,
1424 .rates = DAC33_RATES,
1425 .formats = DAC33_FORMATS,},
1426 .ops = &dac33_dai_ops,
1427 };
1428 EXPORT_SYMBOL_GPL(dac33_dai);
1429
1430 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1431 const struct i2c_device_id *id)
1432 {
1433 struct tlv320dac33_platform_data *pdata;
1434 struct tlv320dac33_priv *dac33;
1435 struct snd_soc_codec *codec;
1436 int ret, i;
1437
1438 if (client->dev.platform_data == NULL) {
1439 dev_err(&client->dev, "Platform data not set\n");
1440 return -ENODEV;
1441 }
1442 pdata = client->dev.platform_data;
1443
1444 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1445 if (dac33 == NULL)
1446 return -ENOMEM;
1447
1448 codec = &dac33->codec;
1449 snd_soc_codec_set_drvdata(codec, dac33);
1450 codec->control_data = client;
1451
1452 mutex_init(&codec->mutex);
1453 mutex_init(&dac33->mutex);
1454 spin_lock_init(&dac33->lock);
1455 INIT_LIST_HEAD(&codec->dapm_widgets);
1456 INIT_LIST_HEAD(&codec->dapm_paths);
1457
1458 codec->name = "tlv320dac33";
1459 codec->owner = THIS_MODULE;
1460 codec->read = dac33_read_reg_cache;
1461 codec->write = dac33_write_locked;
1462 codec->hw_write = (hw_write_t) i2c_master_send;
1463 codec->bias_level = SND_SOC_BIAS_OFF;
1464 codec->set_bias_level = dac33_set_bias_level;
1465 codec->idle_bias_off = 1;
1466 codec->dai = &dac33_dai;
1467 codec->num_dai = 1;
1468 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1469 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1470 GFP_KERNEL);
1471 if (codec->reg_cache == NULL) {
1472 ret = -ENOMEM;
1473 goto error_reg;
1474 }
1475
1476 i2c_set_clientdata(client, dac33);
1477
1478 dac33->power_gpio = pdata->power_gpio;
1479 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1480 /* Pre calculate the burst rate */
1481 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1482 dac33->keep_bclk = pdata->keep_bclk;
1483 dac33->irq = client->irq;
1484 dac33->nsample = NSAMPLE_MAX;
1485 dac33->nsample_max = NSAMPLE_MAX;
1486 /* Disable FIFO use by default */
1487 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1488
1489 tlv320dac33_codec = codec;
1490
1491 codec->dev = &client->dev;
1492 dac33_dai.dev = codec->dev;
1493
1494 /* Check if the reset GPIO number is valid and request it */
1495 if (dac33->power_gpio >= 0) {
1496 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1497 if (ret < 0) {
1498 dev_err(codec->dev,
1499 "Failed to request reset GPIO (%d)\n",
1500 dac33->power_gpio);
1501 snd_soc_unregister_dai(&dac33_dai);
1502 snd_soc_unregister_codec(codec);
1503 goto error_gpio;
1504 }
1505 gpio_direction_output(dac33->power_gpio, 0);
1506 }
1507
1508 /* Check if the IRQ number is valid and request it */
1509 if (dac33->irq >= 0) {
1510 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1511 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1512 codec->name, codec);
1513 if (ret < 0) {
1514 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1515 dac33->irq, ret);
1516 dac33->irq = -1;
1517 }
1518 if (dac33->irq != -1) {
1519 /* Setup work queue */
1520 dac33->dac33_wq =
1521 create_singlethread_workqueue("tlv320dac33");
1522 if (dac33->dac33_wq == NULL) {
1523 free_irq(dac33->irq, &dac33->codec);
1524 ret = -ENOMEM;
1525 goto error_wq;
1526 }
1527
1528 INIT_WORK(&dac33->work, dac33_work);
1529 }
1530 }
1531
1532 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1533 dac33->supplies[i].supply = dac33_supply_names[i];
1534
1535 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1536 dac33->supplies);
1537
1538 if (ret != 0) {
1539 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1540 goto err_get;
1541 }
1542
1543 /* Read the tlv320dac33 ID registers */
1544 ret = dac33_hard_power(codec, 1);
1545 if (ret != 0) {
1546 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1547 goto error_codec;
1548 }
1549 dac33_read_id(codec);
1550 dac33_hard_power(codec, 0);
1551
1552 ret = snd_soc_register_codec(codec);
1553 if (ret != 0) {
1554 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1555 goto error_codec;
1556 }
1557
1558 ret = snd_soc_register_dai(&dac33_dai);
1559 if (ret != 0) {
1560 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1561 snd_soc_unregister_codec(codec);
1562 goto error_codec;
1563 }
1564
1565 return ret;
1566
1567 error_codec:
1568 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1569 err_get:
1570 if (dac33->irq >= 0) {
1571 free_irq(dac33->irq, &dac33->codec);
1572 destroy_workqueue(dac33->dac33_wq);
1573 }
1574 error_wq:
1575 if (dac33->power_gpio >= 0)
1576 gpio_free(dac33->power_gpio);
1577 error_gpio:
1578 kfree(codec->reg_cache);
1579 error_reg:
1580 tlv320dac33_codec = NULL;
1581 kfree(dac33);
1582
1583 return ret;
1584 }
1585
1586 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1587 {
1588 struct tlv320dac33_priv *dac33;
1589
1590 dac33 = i2c_get_clientdata(client);
1591
1592 if (unlikely(dac33->chip_power))
1593 dac33_hard_power(&dac33->codec, 0);
1594
1595 if (dac33->power_gpio >= 0)
1596 gpio_free(dac33->power_gpio);
1597 if (dac33->irq >= 0)
1598 free_irq(dac33->irq, &dac33->codec);
1599
1600 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1601
1602 destroy_workqueue(dac33->dac33_wq);
1603 snd_soc_unregister_dai(&dac33_dai);
1604 snd_soc_unregister_codec(&dac33->codec);
1605 kfree(dac33->codec.reg_cache);
1606 kfree(dac33);
1607 tlv320dac33_codec = NULL;
1608
1609 return 0;
1610 }
1611
1612 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1613 {
1614 .name = "tlv320dac33",
1615 .driver_data = 0,
1616 },
1617 { },
1618 };
1619
1620 static struct i2c_driver tlv320dac33_i2c_driver = {
1621 .driver = {
1622 .name = "tlv320dac33",
1623 .owner = THIS_MODULE,
1624 },
1625 .probe = dac33_i2c_probe,
1626 .remove = __devexit_p(dac33_i2c_remove),
1627 .id_table = tlv320dac33_i2c_id,
1628 };
1629
1630 static int __init dac33_module_init(void)
1631 {
1632 int r;
1633 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1634 if (r < 0) {
1635 printk(KERN_ERR "DAC33: driver registration failed\n");
1636 return r;
1637 }
1638 return 0;
1639 }
1640 module_init(dac33_module_init);
1641
1642 static void __exit dac33_module_exit(void)
1643 {
1644 i2c_del_driver(&tlv320dac33_i2c_driver);
1645 }
1646 module_exit(dac33_module_exit);
1647
1648
1649 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1650 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1651 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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