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Merge branch 'for-2.6.33' into for-2.6.34
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
1 /*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
44
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49 #define NSAMPLE_MAX 5700
50
51 #define LATENCY_TIME_MS 20
52
53 static struct snd_soc_codec *tlv320dac33_codec;
54
55 enum dac33_state {
56 DAC33_IDLE = 0,
57 DAC33_PREFILL,
58 DAC33_PLAYBACK,
59 DAC33_FLUSH,
60 };
61
62 enum dac33_fifo_modes {
63 DAC33_FIFO_BYPASS = 0,
64 DAC33_FIFO_MODE1,
65 DAC33_FIFO_MODE7,
66 DAC33_FIFO_LAST_MODE,
67 };
68
69 #define DAC33_NUM_SUPPLIES 3
70 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
71 "AVDD",
72 "DVDD",
73 "IOVDD",
74 };
75
76 struct tlv320dac33_priv {
77 struct mutex mutex;
78 struct workqueue_struct *dac33_wq;
79 struct work_struct work;
80 struct snd_soc_codec codec;
81 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
82 int power_gpio;
83 int chip_power;
84 int irq;
85 unsigned int refclk;
86
87 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
88 unsigned int nsample_min; /* nsample should not be lower than
89 * this */
90 unsigned int nsample_max; /* nsample should not be higher than
91 * this */
92 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
93 unsigned int nsample; /* burst read amount from host */
94 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
95
96 enum dac33_state state;
97 };
98
99 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
100 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
101 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
102 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
103 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
104 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
105 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
106 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
107 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
108 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
109 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
110 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
111 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
112 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
113 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
114 0x00, 0x00, /* 0x38 - 0x39 */
115 /* Registers 0x3a - 0x3f are reserved */
116 0x00, 0x00, /* 0x3a - 0x3b */
117 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
118
119 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
120 0x00, 0x80, /* 0x44 - 0x45 */
121 /* Registers 0x46 - 0x47 are reserved */
122 0x80, 0x80, /* 0x46 - 0x47 */
123
124 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
125 /* Registers 0x4b - 0x7c are reserved */
126 0x00, /* 0x4b */
127 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
128 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
129 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
130 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
131 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
132 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
133 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
134 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
135 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
136 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
137 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
138 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
139 0x00, /* 0x7c */
140
141 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
142 };
143
144 /* Register read and write */
145 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned reg)
147 {
148 u8 *cache = codec->reg_cache;
149 if (reg >= DAC33_CACHEREGNUM)
150 return 0;
151
152 return cache[reg];
153 }
154
155 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
156 u8 reg, u8 value)
157 {
158 u8 *cache = codec->reg_cache;
159 if (reg >= DAC33_CACHEREGNUM)
160 return;
161
162 cache[reg] = value;
163 }
164
165 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
166 u8 *value)
167 {
168 struct tlv320dac33_priv *dac33 = codec->private_data;
169 int val;
170
171 *value = reg & 0xff;
172
173 /* If powered off, return the cached value */
174 if (dac33->chip_power) {
175 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
176 if (val < 0) {
177 dev_err(codec->dev, "Read failed (%d)\n", val);
178 value[0] = dac33_read_reg_cache(codec, reg);
179 } else {
180 value[0] = val;
181 dac33_write_reg_cache(codec, reg, val);
182 }
183 } else {
184 value[0] = dac33_read_reg_cache(codec, reg);
185 }
186
187 return 0;
188 }
189
190 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
191 unsigned int value)
192 {
193 struct tlv320dac33_priv *dac33 = codec->private_data;
194 u8 data[2];
195 int ret = 0;
196
197 /*
198 * data is
199 * D15..D8 dac33 register offset
200 * D7...D0 register data
201 */
202 data[0] = reg & 0xff;
203 data[1] = value & 0xff;
204
205 dac33_write_reg_cache(codec, data[0], data[1]);
206 if (dac33->chip_power) {
207 ret = codec->hw_write(codec->control_data, data, 2);
208 if (ret != 2)
209 dev_err(codec->dev, "Write failed (%d)\n", ret);
210 else
211 ret = 0;
212 }
213
214 return ret;
215 }
216
217 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
218 unsigned int value)
219 {
220 struct tlv320dac33_priv *dac33 = codec->private_data;
221 int ret;
222
223 mutex_lock(&dac33->mutex);
224 ret = dac33_write(codec, reg, value);
225 mutex_unlock(&dac33->mutex);
226
227 return ret;
228 }
229
230 #define DAC33_I2C_ADDR_AUTOINC 0x80
231 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
232 unsigned int value)
233 {
234 struct tlv320dac33_priv *dac33 = codec->private_data;
235 u8 data[3];
236 int ret = 0;
237
238 /*
239 * data is
240 * D23..D16 dac33 register offset
241 * D15..D8 register data MSB
242 * D7...D0 register data LSB
243 */
244 data[0] = reg & 0xff;
245 data[1] = (value >> 8) & 0xff;
246 data[2] = value & 0xff;
247
248 dac33_write_reg_cache(codec, data[0], data[1]);
249 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
250
251 if (dac33->chip_power) {
252 /* We need to set autoincrement mode for 16 bit writes */
253 data[0] |= DAC33_I2C_ADDR_AUTOINC;
254 ret = codec->hw_write(codec->control_data, data, 3);
255 if (ret != 3)
256 dev_err(codec->dev, "Write failed (%d)\n", ret);
257 else
258 ret = 0;
259 }
260
261 return ret;
262 }
263
264 static void dac33_restore_regs(struct snd_soc_codec *codec)
265 {
266 struct tlv320dac33_priv *dac33 = codec->private_data;
267 u8 *cache = codec->reg_cache;
268 u8 data[2];
269 int i, ret;
270
271 if (!dac33->chip_power)
272 return;
273
274 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
275 data[0] = i;
276 data[1] = cache[i];
277 /* Skip the read only registers */
278 if ((i >= DAC33_INT_OSC_STATUS &&
279 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
280 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
281 i == DAC33_DAC_STATUS_FLAGS ||
282 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
283 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
284 continue;
285 ret = codec->hw_write(codec->control_data, data, 2);
286 if (ret != 2)
287 dev_err(codec->dev, "Write failed (%d)\n", ret);
288 }
289 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
290 data[0] = i;
291 data[1] = cache[i];
292 ret = codec->hw_write(codec->control_data, data, 2);
293 if (ret != 2)
294 dev_err(codec->dev, "Write failed (%d)\n", ret);
295 }
296 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
297 data[0] = i;
298 data[1] = cache[i];
299 ret = codec->hw_write(codec->control_data, data, 2);
300 if (ret != 2)
301 dev_err(codec->dev, "Write failed (%d)\n", ret);
302 }
303 }
304
305 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
306 {
307 u8 reg;
308
309 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
310 if (power)
311 reg |= DAC33_PDNALLB;
312 else
313 reg &= ~DAC33_PDNALLB;
314 dac33_write(codec, DAC33_PWR_CTRL, reg);
315 }
316
317 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
318 {
319 struct tlv320dac33_priv *dac33 = codec->private_data;
320 int ret;
321
322 mutex_lock(&dac33->mutex);
323 if (power) {
324 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
325 dac33->supplies);
326 if (ret != 0) {
327 dev_err(codec->dev,
328 "Failed to enable supplies: %d\n", ret);
329 goto exit;
330 }
331
332 if (dac33->power_gpio >= 0)
333 gpio_set_value(dac33->power_gpio, 1);
334
335 dac33->chip_power = 1;
336
337 /* Restore registers */
338 dac33_restore_regs(codec);
339
340 dac33_soft_power(codec, 1);
341 } else {
342 dac33_soft_power(codec, 0);
343 if (dac33->power_gpio >= 0)
344 gpio_set_value(dac33->power_gpio, 0);
345
346 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
347 dac33->supplies);
348 if (ret != 0) {
349 dev_err(codec->dev,
350 "Failed to disable supplies: %d\n", ret);
351 goto exit;
352 }
353
354 dac33->chip_power = 0;
355 }
356
357 exit:
358 mutex_unlock(&dac33->mutex);
359 return ret;
360 }
361
362 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364 {
365 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
366 struct tlv320dac33_priv *dac33 = codec->private_data;
367
368 ucontrol->value.integer.value[0] = dac33->nsample;
369
370 return 0;
371 }
372
373 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
374 struct snd_ctl_elem_value *ucontrol)
375 {
376 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
377 struct tlv320dac33_priv *dac33 = codec->private_data;
378 int ret = 0;
379
380 if (dac33->nsample == ucontrol->value.integer.value[0])
381 return 0;
382
383 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
384 ucontrol->value.integer.value[0] > dac33->nsample_max)
385 ret = -EINVAL;
386 else
387 dac33->nsample = ucontrol->value.integer.value[0];
388
389 return ret;
390 }
391
392 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
393 struct snd_ctl_elem_value *ucontrol)
394 {
395 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
396 struct tlv320dac33_priv *dac33 = codec->private_data;
397
398 ucontrol->value.integer.value[0] = dac33->fifo_mode;
399
400 return 0;
401 }
402
403 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
404 struct snd_ctl_elem_value *ucontrol)
405 {
406 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
407 struct tlv320dac33_priv *dac33 = codec->private_data;
408 int ret = 0;
409
410 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
411 return 0;
412 /* Do not allow changes while stream is running*/
413 if (codec->active)
414 return -EPERM;
415
416 if (ucontrol->value.integer.value[0] < 0 ||
417 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
418 ret = -EINVAL;
419 else
420 dac33->fifo_mode = ucontrol->value.integer.value[0];
421
422 return ret;
423 }
424
425 /* Codec operation modes */
426 static const char *dac33_fifo_mode_texts[] = {
427 "Bypass", "Mode 1", "Mode 7"
428 };
429
430 static const struct soc_enum dac33_fifo_mode_enum =
431 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
432 dac33_fifo_mode_texts);
433
434 /*
435 * DACL/R digital volume control:
436 * from 0 dB to -63.5 in 0.5 dB steps
437 * Need to be inverted later on:
438 * 0x00 == 0 dB
439 * 0x7f == -63.5 dB
440 */
441 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
442
443 static const struct snd_kcontrol_new dac33_snd_controls[] = {
444 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
445 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
446 0, 0x7f, 1, dac_digivol_tlv),
447 SOC_DOUBLE_R("DAC Digital Playback Switch",
448 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
449 SOC_DOUBLE_R("Line to Line Out Volume",
450 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
451 };
452
453 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
454 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
455 dac33_get_nsample, dac33_set_nsample),
456 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
457 dac33_get_fifo_mode, dac33_set_fifo_mode),
458 };
459
460 /* Analog bypass */
461 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
462 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
463
464 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
465 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
466
467 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
468 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
469 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
470
471 SND_SOC_DAPM_INPUT("LINEL"),
472 SND_SOC_DAPM_INPUT("LINER"),
473
474 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
475 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
476
477 /* Analog bypass */
478 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
479 &dac33_dapm_abypassl_control),
480 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
481 &dac33_dapm_abypassr_control),
482
483 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
484 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
485 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
486 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
487 };
488
489 static const struct snd_soc_dapm_route audio_map[] = {
490 /* Analog bypass */
491 {"Analog Left Bypass", "Switch", "LINEL"},
492 {"Analog Right Bypass", "Switch", "LINER"},
493
494 {"Output Left Amp Power", NULL, "DACL"},
495 {"Output Right Amp Power", NULL, "DACR"},
496
497 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
498 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
499
500 /* output */
501 {"LEFT_LO", NULL, "Output Left Amp Power"},
502 {"RIGHT_LO", NULL, "Output Right Amp Power"},
503 };
504
505 static int dac33_add_widgets(struct snd_soc_codec *codec)
506 {
507 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
508 ARRAY_SIZE(dac33_dapm_widgets));
509
510 /* set up audio path interconnects */
511 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
512
513 return 0;
514 }
515
516 static int dac33_set_bias_level(struct snd_soc_codec *codec,
517 enum snd_soc_bias_level level)
518 {
519 int ret;
520
521 switch (level) {
522 case SND_SOC_BIAS_ON:
523 dac33_soft_power(codec, 1);
524 break;
525 case SND_SOC_BIAS_PREPARE:
526 break;
527 case SND_SOC_BIAS_STANDBY:
528 if (codec->bias_level == SND_SOC_BIAS_OFF) {
529 ret = dac33_hard_power(codec, 1);
530 if (ret != 0)
531 return ret;
532 }
533
534 dac33_soft_power(codec, 0);
535 break;
536 case SND_SOC_BIAS_OFF:
537 ret = dac33_hard_power(codec, 0);
538 if (ret != 0)
539 return ret;
540
541 break;
542 }
543 codec->bias_level = level;
544
545 return 0;
546 }
547
548 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
549 {
550 struct snd_soc_codec *codec;
551
552 codec = &dac33->codec;
553
554 switch (dac33->fifo_mode) {
555 case DAC33_FIFO_MODE1:
556 dac33_write16(codec, DAC33_NSAMPLE_MSB,
557 DAC33_THRREG(dac33->nsample));
558 dac33_write16(codec, DAC33_PREFILL_MSB,
559 DAC33_THRREG(dac33->alarm_threshold));
560 break;
561 case DAC33_FIFO_MODE7:
562 dac33_write16(codec, DAC33_PREFILL_MSB,
563 DAC33_THRREG(10));
564 break;
565 default:
566 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
567 dac33->fifo_mode);
568 break;
569 }
570 }
571
572 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
573 {
574 struct snd_soc_codec *codec;
575
576 codec = &dac33->codec;
577
578 switch (dac33->fifo_mode) {
579 case DAC33_FIFO_MODE1:
580 dac33_write16(codec, DAC33_NSAMPLE_MSB,
581 DAC33_THRREG(dac33->nsample));
582 break;
583 case DAC33_FIFO_MODE7:
584 /* At the moment we are not using interrupts in mode7 */
585 break;
586 default:
587 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
588 dac33->fifo_mode);
589 break;
590 }
591 }
592
593 static void dac33_work(struct work_struct *work)
594 {
595 struct snd_soc_codec *codec;
596 struct tlv320dac33_priv *dac33;
597 u8 reg;
598
599 dac33 = container_of(work, struct tlv320dac33_priv, work);
600 codec = &dac33->codec;
601
602 mutex_lock(&dac33->mutex);
603 switch (dac33->state) {
604 case DAC33_PREFILL:
605 dac33->state = DAC33_PLAYBACK;
606 dac33_prefill_handler(dac33);
607 break;
608 case DAC33_PLAYBACK:
609 dac33_playback_handler(dac33);
610 break;
611 case DAC33_IDLE:
612 break;
613 case DAC33_FLUSH:
614 dac33->state = DAC33_IDLE;
615 /* Mask all interrupts from dac33 */
616 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
617
618 /* flush fifo */
619 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
620 reg |= DAC33_FIFOFLUSH;
621 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
622 break;
623 }
624 mutex_unlock(&dac33->mutex);
625 }
626
627 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
628 {
629 struct snd_soc_codec *codec = dev;
630 struct tlv320dac33_priv *dac33 = codec->private_data;
631
632 queue_work(dac33->dac33_wq, &dac33->work);
633
634 return IRQ_HANDLED;
635 }
636
637 static void dac33_shutdown(struct snd_pcm_substream *substream,
638 struct snd_soc_dai *dai)
639 {
640 struct snd_soc_pcm_runtime *rtd = substream->private_data;
641 struct snd_soc_device *socdev = rtd->socdev;
642 struct snd_soc_codec *codec = socdev->card->codec;
643 struct tlv320dac33_priv *dac33 = codec->private_data;
644 unsigned int pwr_ctrl;
645
646 /* Stop pending workqueue */
647 if (dac33->fifo_mode)
648 cancel_work_sync(&dac33->work);
649
650 mutex_lock(&dac33->mutex);
651 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
652 pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
653 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
654 mutex_unlock(&dac33->mutex);
655 }
656
657 static void dac33_oscwait(struct snd_soc_codec *codec)
658 {
659 int timeout = 20;
660 u8 reg;
661
662 do {
663 msleep(1);
664 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
665 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
666 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
667 dev_err(codec->dev,
668 "internal oscillator calibration failed\n");
669 }
670
671 static int dac33_hw_params(struct snd_pcm_substream *substream,
672 struct snd_pcm_hw_params *params,
673 struct snd_soc_dai *dai)
674 {
675 struct snd_soc_pcm_runtime *rtd = substream->private_data;
676 struct snd_soc_device *socdev = rtd->socdev;
677 struct snd_soc_codec *codec = socdev->card->codec;
678
679 /* Check parameters for validity */
680 switch (params_rate(params)) {
681 case 44100:
682 case 48000:
683 break;
684 default:
685 dev_err(codec->dev, "unsupported rate %d\n",
686 params_rate(params));
687 return -EINVAL;
688 }
689
690 switch (params_format(params)) {
691 case SNDRV_PCM_FORMAT_S16_LE:
692 break;
693 default:
694 dev_err(codec->dev, "unsupported format %d\n",
695 params_format(params));
696 return -EINVAL;
697 }
698
699 return 0;
700 }
701
702 #define CALC_OSCSET(rate, refclk) ( \
703 ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
704 #define CALC_RATIOSET(rate, refclk) ( \
705 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
706
707 /*
708 * tlv320dac33 is strict on the sequence of the register writes, if the register
709 * writes happens in different order, than dac33 might end up in unknown state.
710 * Use the known, working sequence of register writes to initialize the dac33.
711 */
712 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
713 {
714 struct snd_soc_pcm_runtime *rtd = substream->private_data;
715 struct snd_soc_device *socdev = rtd->socdev;
716 struct snd_soc_codec *codec = socdev->card->codec;
717 struct tlv320dac33_priv *dac33 = codec->private_data;
718 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
719 u8 aictrl_a, aictrl_b, fifoctrl_a;
720
721 switch (substream->runtime->rate) {
722 case 44100:
723 case 48000:
724 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
725 ratioset = CALC_RATIOSET(substream->runtime->rate,
726 dac33->refclk);
727 break;
728 default:
729 dev_err(codec->dev, "unsupported rate %d\n",
730 substream->runtime->rate);
731 return -EINVAL;
732 }
733
734
735 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
736 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
737 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
738 fifoctrl_a &= ~DAC33_WIDTH;
739 switch (substream->runtime->format) {
740 case SNDRV_PCM_FORMAT_S16_LE:
741 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
742 fifoctrl_a |= DAC33_WIDTH;
743 break;
744 default:
745 dev_err(codec->dev, "unsupported format %d\n",
746 substream->runtime->format);
747 return -EINVAL;
748 }
749
750 mutex_lock(&dac33->mutex);
751 dac33_soft_power(codec, 1);
752
753 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
754 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
755
756 /* Write registers 0x08 and 0x09 (MSB, LSB) */
757 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
758
759 /* calib time: 128 is a nice number ;) */
760 dac33_write(codec, DAC33_CALIB_TIME, 128);
761
762 /* adjustment treshold & step */
763 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
764 DAC33_ADJSTEP(1));
765
766 /* div=4 / gain=1 / div */
767 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
768
769 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
770 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
771 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
772
773 dac33_oscwait(codec);
774
775 if (dac33->fifo_mode) {
776 /* Generic for all FIFO modes */
777 /* 50-51 : ASRC Control registers */
778 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
779 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
780
781 /* Write registers 0x34 and 0x35 (MSB, LSB) */
782 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
783
784 /* Set interrupts to high active */
785 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
786 } else {
787 /* FIFO bypass mode */
788 /* 50-51 : ASRC Control registers */
789 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
790 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
791 }
792
793 /* Interrupt behaviour configuration */
794 switch (dac33->fifo_mode) {
795 case DAC33_FIFO_MODE1:
796 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
797 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
798 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
799 break;
800 case DAC33_FIFO_MODE7:
801 /* Disable all interrupts */
802 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
803 break;
804 default:
805 /* in FIFO bypass mode, the interrupts are not used */
806 break;
807 }
808
809 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
810
811 switch (dac33->fifo_mode) {
812 case DAC33_FIFO_MODE1:
813 /*
814 * For mode1:
815 * Disable the FIFO bypass (Enable the use of FIFO)
816 * Select nSample mode
817 * BCLK is only running when data is needed by DAC33
818 */
819 fifoctrl_a &= ~DAC33_FBYPAS;
820 fifoctrl_a &= ~DAC33_FAUTO;
821 aictrl_b &= ~DAC33_BCLKON;
822 break;
823 case DAC33_FIFO_MODE7:
824 /*
825 * For mode1:
826 * Disable the FIFO bypass (Enable the use of FIFO)
827 * Select Threshold mode
828 * BCLK is only running when data is needed by DAC33
829 */
830 fifoctrl_a &= ~DAC33_FBYPAS;
831 fifoctrl_a |= DAC33_FAUTO;
832 aictrl_b &= ~DAC33_BCLKON;
833 break;
834 default:
835 /*
836 * For FIFO bypass mode:
837 * Enable the FIFO bypass (Disable the FIFO use)
838 * Set the BCLK as continous
839 */
840 fifoctrl_a |= DAC33_FBYPAS;
841 aictrl_b |= DAC33_BCLKON;
842 break;
843 }
844
845 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
846 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
847 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
848
849 /*
850 * BCLK divide ratio
851 * 0: 1.5
852 * 1: 1
853 * 2: 2
854 * ...
855 * 254: 254
856 * 255: 255
857 */
858 if (dac33->fifo_mode)
859 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
860 dac33->burst_bclkdiv);
861 else
862 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
863
864 switch (dac33->fifo_mode) {
865 case DAC33_FIFO_MODE1:
866 dac33_write16(codec, DAC33_ATHR_MSB,
867 DAC33_THRREG(dac33->alarm_threshold));
868 break;
869 case DAC33_FIFO_MODE7:
870 /*
871 * Configure the threshold levels, and leave 10 sample space
872 * at the bottom, and also at the top of the FIFO
873 */
874 dac33_write16(codec, DAC33_UTHR_MSB,
875 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10));
876 dac33_write16(codec, DAC33_LTHR_MSB,
877 DAC33_THRREG(10));
878 break;
879 default:
880 break;
881 }
882
883 mutex_unlock(&dac33->mutex);
884
885 return 0;
886 }
887
888 static void dac33_calculate_times(struct snd_pcm_substream *substream)
889 {
890 struct snd_soc_pcm_runtime *rtd = substream->private_data;
891 struct snd_soc_device *socdev = rtd->socdev;
892 struct snd_soc_codec *codec = socdev->card->codec;
893 struct tlv320dac33_priv *dac33 = codec->private_data;
894 unsigned int nsample_limit;
895
896 /* Number of samples (16bit, stereo) in one period */
897 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
898
899 /* Number of samples (16bit, stereo) in ALSA buffer */
900 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
901 /* Subtract one period from the total */
902 dac33->nsample_max -= dac33->nsample_min;
903
904 /* Number of samples for LATENCY_TIME_MS / 2 */
905 dac33->alarm_threshold = substream->runtime->rate /
906 (1000 / (LATENCY_TIME_MS / 2));
907
908 /* Find and fix up the lowest nsmaple limit */
909 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
910
911 if (dac33->nsample_min < nsample_limit)
912 dac33->nsample_min = nsample_limit;
913
914 if (dac33->nsample < dac33->nsample_min)
915 dac33->nsample = dac33->nsample_min;
916
917 /*
918 * Find and fix up the highest nsmaple limit
919 * In order to not overflow the DAC33 buffer substract the
920 * alarm_threshold value from the size of the DAC33 buffer
921 */
922 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
923
924 if (dac33->nsample_max > nsample_limit)
925 dac33->nsample_max = nsample_limit;
926
927 if (dac33->nsample > dac33->nsample_max)
928 dac33->nsample = dac33->nsample_max;
929 }
930
931 static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
932 struct snd_soc_dai *dai)
933 {
934 dac33_calculate_times(substream);
935 dac33_prepare_chip(substream);
936
937 return 0;
938 }
939
940 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
941 struct snd_soc_dai *dai)
942 {
943 struct snd_soc_pcm_runtime *rtd = substream->private_data;
944 struct snd_soc_device *socdev = rtd->socdev;
945 struct snd_soc_codec *codec = socdev->card->codec;
946 struct tlv320dac33_priv *dac33 = codec->private_data;
947 int ret = 0;
948
949 switch (cmd) {
950 case SNDRV_PCM_TRIGGER_START:
951 case SNDRV_PCM_TRIGGER_RESUME:
952 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
953 if (dac33->fifo_mode) {
954 dac33->state = DAC33_PREFILL;
955 queue_work(dac33->dac33_wq, &dac33->work);
956 }
957 break;
958 case SNDRV_PCM_TRIGGER_STOP:
959 case SNDRV_PCM_TRIGGER_SUSPEND:
960 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
961 if (dac33->fifo_mode) {
962 dac33->state = DAC33_FLUSH;
963 queue_work(dac33->dac33_wq, &dac33->work);
964 }
965 break;
966 default:
967 ret = -EINVAL;
968 }
969
970 return ret;
971 }
972
973 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
974 int clk_id, unsigned int freq, int dir)
975 {
976 struct snd_soc_codec *codec = codec_dai->codec;
977 struct tlv320dac33_priv *dac33 = codec->private_data;
978 u8 ioc_reg, asrcb_reg;
979
980 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
981 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
982 switch (clk_id) {
983 case TLV320DAC33_MCLK:
984 ioc_reg |= DAC33_REFSEL;
985 asrcb_reg |= DAC33_SRCREFSEL;
986 break;
987 case TLV320DAC33_SLEEPCLK:
988 ioc_reg &= ~DAC33_REFSEL;
989 asrcb_reg &= ~DAC33_SRCREFSEL;
990 break;
991 default:
992 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
993 break;
994 }
995 dac33->refclk = freq;
996
997 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
998 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
999
1000 return 0;
1001 }
1002
1003 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1004 unsigned int fmt)
1005 {
1006 struct snd_soc_codec *codec = codec_dai->codec;
1007 struct tlv320dac33_priv *dac33 = codec->private_data;
1008 u8 aictrl_a, aictrl_b;
1009
1010 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1011 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1012 /* set master/slave audio interface */
1013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1014 case SND_SOC_DAIFMT_CBM_CFM:
1015 /* Codec Master */
1016 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1017 break;
1018 case SND_SOC_DAIFMT_CBS_CFS:
1019 /* Codec Slave */
1020 if (dac33->fifo_mode) {
1021 dev_err(codec->dev, "FIFO mode requires master mode\n");
1022 return -EINVAL;
1023 } else
1024 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 aictrl_a &= ~DAC33_AFMT_MASK;
1031 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1032 case SND_SOC_DAIFMT_I2S:
1033 aictrl_a |= DAC33_AFMT_I2S;
1034 break;
1035 case SND_SOC_DAIFMT_DSP_A:
1036 aictrl_a |= DAC33_AFMT_DSP;
1037 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1038 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
1039 break;
1040 case SND_SOC_DAIFMT_DSP_B:
1041 aictrl_a |= DAC33_AFMT_DSP;
1042 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
1043 break;
1044 case SND_SOC_DAIFMT_RIGHT_J:
1045 aictrl_a |= DAC33_AFMT_RIGHT_J;
1046 break;
1047 case SND_SOC_DAIFMT_LEFT_J:
1048 aictrl_a |= DAC33_AFMT_LEFT_J;
1049 break;
1050 default:
1051 dev_err(codec->dev, "Unsupported format (%u)\n",
1052 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1053 return -EINVAL;
1054 }
1055
1056 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1057 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1058
1059 return 0;
1060 }
1061
1062 static void dac33_init_chip(struct snd_soc_codec *codec)
1063 {
1064 /* 44-46: DAC Control Registers */
1065 /* A : DAC sample rate Fsref/1.5 */
1066 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
1067 /* B : DAC src=normal, not muted */
1068 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1069 DAC33_DACSRCL_LEFT);
1070 /* C : (defaults) */
1071 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1072
1073 /* 64-65 : L&R DAC power control
1074 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1075 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1076 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1077
1078 /* 73 : volume soft stepping control,
1079 clock source = internal osc (?) */
1080 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1081
1082 /* 66 : LOP/LOM Modes */
1083 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1084
1085 /* 68 : LOM inverted from LOP */
1086 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1087
1088 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1089 }
1090
1091 static int dac33_soc_probe(struct platform_device *pdev)
1092 {
1093 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1094 struct snd_soc_codec *codec;
1095 struct tlv320dac33_priv *dac33;
1096 int ret = 0;
1097
1098 BUG_ON(!tlv320dac33_codec);
1099
1100 codec = tlv320dac33_codec;
1101 socdev->card->codec = codec;
1102 dac33 = codec->private_data;
1103
1104 /* Power up the codec */
1105 dac33_hard_power(codec, 1);
1106 /* Set default configuration */
1107 dac33_init_chip(codec);
1108
1109 /* register pcms */
1110 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1111 if (ret < 0) {
1112 dev_err(codec->dev, "failed to create pcms\n");
1113 goto pcm_err;
1114 }
1115
1116 snd_soc_add_controls(codec, dac33_snd_controls,
1117 ARRAY_SIZE(dac33_snd_controls));
1118 /* Only add the nSample controls, if we have valid IRQ number */
1119 if (dac33->irq >= 0)
1120 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1121 ARRAY_SIZE(dac33_nsample_snd_controls));
1122
1123 dac33_add_widgets(codec);
1124
1125 /* power on device */
1126 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1127
1128 /* Bias level configuration has enabled regulator an extra time */
1129 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1130
1131 return 0;
1132
1133 pcm_err:
1134 dac33_hard_power(codec, 0);
1135 return ret;
1136 }
1137
1138 static int dac33_soc_remove(struct platform_device *pdev)
1139 {
1140 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1141 struct snd_soc_codec *codec = socdev->card->codec;
1142
1143 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1144
1145 snd_soc_free_pcms(socdev);
1146 snd_soc_dapm_free(socdev);
1147
1148 return 0;
1149 }
1150
1151 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1152 {
1153 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1154 struct snd_soc_codec *codec = socdev->card->codec;
1155
1156 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1157
1158 return 0;
1159 }
1160
1161 static int dac33_soc_resume(struct platform_device *pdev)
1162 {
1163 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1164 struct snd_soc_codec *codec = socdev->card->codec;
1165
1166 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1167 dac33_set_bias_level(codec, codec->suspend_bias_level);
1168
1169 return 0;
1170 }
1171
1172 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1173 .probe = dac33_soc_probe,
1174 .remove = dac33_soc_remove,
1175 .suspend = dac33_soc_suspend,
1176 .resume = dac33_soc_resume,
1177 };
1178 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1179
1180 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1181 SNDRV_PCM_RATE_48000)
1182 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1183
1184 static struct snd_soc_dai_ops dac33_dai_ops = {
1185 .shutdown = dac33_shutdown,
1186 .hw_params = dac33_hw_params,
1187 .prepare = dac33_pcm_prepare,
1188 .trigger = dac33_pcm_trigger,
1189 .set_sysclk = dac33_set_dai_sysclk,
1190 .set_fmt = dac33_set_dai_fmt,
1191 };
1192
1193 struct snd_soc_dai dac33_dai = {
1194 .name = "tlv320dac33",
1195 .playback = {
1196 .stream_name = "Playback",
1197 .channels_min = 2,
1198 .channels_max = 2,
1199 .rates = DAC33_RATES,
1200 .formats = DAC33_FORMATS,},
1201 .ops = &dac33_dai_ops,
1202 };
1203 EXPORT_SYMBOL_GPL(dac33_dai);
1204
1205 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1206 const struct i2c_device_id *id)
1207 {
1208 struct tlv320dac33_platform_data *pdata;
1209 struct tlv320dac33_priv *dac33;
1210 struct snd_soc_codec *codec;
1211 int ret, i;
1212
1213 if (client->dev.platform_data == NULL) {
1214 dev_err(&client->dev, "Platform data not set\n");
1215 return -ENODEV;
1216 }
1217 pdata = client->dev.platform_data;
1218
1219 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1220 if (dac33 == NULL)
1221 return -ENOMEM;
1222
1223 codec = &dac33->codec;
1224 codec->private_data = dac33;
1225 codec->control_data = client;
1226
1227 mutex_init(&codec->mutex);
1228 mutex_init(&dac33->mutex);
1229 INIT_LIST_HEAD(&codec->dapm_widgets);
1230 INIT_LIST_HEAD(&codec->dapm_paths);
1231
1232 codec->name = "tlv320dac33";
1233 codec->owner = THIS_MODULE;
1234 codec->read = dac33_read_reg_cache;
1235 codec->write = dac33_write_locked;
1236 codec->hw_write = (hw_write_t) i2c_master_send;
1237 codec->bias_level = SND_SOC_BIAS_OFF;
1238 codec->set_bias_level = dac33_set_bias_level;
1239 codec->dai = &dac33_dai;
1240 codec->num_dai = 1;
1241 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1242 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1243 GFP_KERNEL);
1244 if (codec->reg_cache == NULL) {
1245 ret = -ENOMEM;
1246 goto error_reg;
1247 }
1248
1249 i2c_set_clientdata(client, dac33);
1250
1251 dac33->power_gpio = pdata->power_gpio;
1252 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1253 dac33->irq = client->irq;
1254 dac33->nsample = NSAMPLE_MAX;
1255 /* Disable FIFO use by default */
1256 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1257
1258 tlv320dac33_codec = codec;
1259
1260 codec->dev = &client->dev;
1261 dac33_dai.dev = codec->dev;
1262
1263 /* Check if the reset GPIO number is valid and request it */
1264 if (dac33->power_gpio >= 0) {
1265 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1266 if (ret < 0) {
1267 dev_err(codec->dev,
1268 "Failed to request reset GPIO (%d)\n",
1269 dac33->power_gpio);
1270 snd_soc_unregister_dai(&dac33_dai);
1271 snd_soc_unregister_codec(codec);
1272 goto error_gpio;
1273 }
1274 gpio_direction_output(dac33->power_gpio, 0);
1275 } else {
1276 dac33->chip_power = 1;
1277 }
1278
1279 /* Check if the IRQ number is valid and request it */
1280 if (dac33->irq >= 0) {
1281 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1282 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1283 codec->name, codec);
1284 if (ret < 0) {
1285 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1286 dac33->irq, ret);
1287 dac33->irq = -1;
1288 }
1289 if (dac33->irq != -1) {
1290 /* Setup work queue */
1291 dac33->dac33_wq =
1292 create_singlethread_workqueue("tlv320dac33");
1293 if (dac33->dac33_wq == NULL) {
1294 free_irq(dac33->irq, &dac33->codec);
1295 ret = -ENOMEM;
1296 goto error_wq;
1297 }
1298
1299 INIT_WORK(&dac33->work, dac33_work);
1300 }
1301 }
1302
1303 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1304 dac33->supplies[i].supply = dac33_supply_names[i];
1305
1306 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1307 dac33->supplies);
1308
1309 if (ret != 0) {
1310 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1311 goto err_get;
1312 }
1313
1314 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1315 dac33->supplies);
1316 if (ret != 0) {
1317 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1318 goto err_enable;
1319 }
1320
1321 ret = snd_soc_register_codec(codec);
1322 if (ret != 0) {
1323 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1324 goto error_codec;
1325 }
1326
1327 ret = snd_soc_register_dai(&dac33_dai);
1328 if (ret != 0) {
1329 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1330 snd_soc_unregister_codec(codec);
1331 goto error_codec;
1332 }
1333
1334 /* Shut down the codec for now */
1335 dac33_hard_power(codec, 0);
1336
1337 return ret;
1338
1339 error_codec:
1340 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1341 err_enable:
1342 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1343 err_get:
1344 if (dac33->irq >= 0) {
1345 free_irq(dac33->irq, &dac33->codec);
1346 destroy_workqueue(dac33->dac33_wq);
1347 }
1348 error_wq:
1349 if (dac33->power_gpio >= 0)
1350 gpio_free(dac33->power_gpio);
1351 error_gpio:
1352 kfree(codec->reg_cache);
1353 error_reg:
1354 tlv320dac33_codec = NULL;
1355 kfree(dac33);
1356
1357 return ret;
1358 }
1359
1360 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1361 {
1362 struct tlv320dac33_priv *dac33;
1363
1364 dac33 = i2c_get_clientdata(client);
1365 dac33_hard_power(&dac33->codec, 0);
1366
1367 if (dac33->power_gpio >= 0)
1368 gpio_free(dac33->power_gpio);
1369 if (dac33->irq >= 0)
1370 free_irq(dac33->irq, &dac33->codec);
1371
1372 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1373
1374 destroy_workqueue(dac33->dac33_wq);
1375 snd_soc_unregister_dai(&dac33_dai);
1376 snd_soc_unregister_codec(&dac33->codec);
1377 kfree(dac33->codec.reg_cache);
1378 kfree(dac33);
1379 tlv320dac33_codec = NULL;
1380
1381 return 0;
1382 }
1383
1384 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1385 {
1386 .name = "tlv320dac33",
1387 .driver_data = 0,
1388 },
1389 { },
1390 };
1391
1392 static struct i2c_driver tlv320dac33_i2c_driver = {
1393 .driver = {
1394 .name = "tlv320dac33",
1395 .owner = THIS_MODULE,
1396 },
1397 .probe = dac33_i2c_probe,
1398 .remove = __devexit_p(dac33_i2c_remove),
1399 .id_table = tlv320dac33_i2c_id,
1400 };
1401
1402 static int __init dac33_module_init(void)
1403 {
1404 int r;
1405 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1406 if (r < 0) {
1407 printk(KERN_ERR "DAC33: driver registration failed\n");
1408 return r;
1409 }
1410 return 0;
1411 }
1412 module_init(dac33_module_init);
1413
1414 static void __exit dac33_module_exit(void)
1415 {
1416 i2c_del_driver(&tlv320dac33_i2c_driver);
1417 }
1418 module_exit(dac33_module_exit);
1419
1420
1421 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1422 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1423 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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