2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
49 #define NSAMPLE_MAX 5700
51 #define LATENCY_TIME_MS 20
53 static struct snd_soc_codec
*tlv320dac33_codec
;
62 enum dac33_fifo_modes
{
63 DAC33_FIFO_BYPASS
= 0,
69 #define DAC33_NUM_SUPPLIES 3
70 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
76 struct tlv320dac33_priv
{
78 struct workqueue_struct
*dac33_wq
;
79 struct work_struct work
;
80 struct snd_soc_codec codec
;
81 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
87 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
88 unsigned int nsample_min
; /* nsample should not be lower than
90 unsigned int nsample_max
; /* nsample should not be higher than
92 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
93 unsigned int nsample
; /* burst read amount from host */
94 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
96 enum dac33_state state
;
99 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
100 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
101 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
102 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
103 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
104 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
105 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
106 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
107 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
108 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
109 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
110 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
111 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
112 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
113 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
114 0x00, 0x00, /* 0x38 - 0x39 */
115 /* Registers 0x3a - 0x3f are reserved */
116 0x00, 0x00, /* 0x3a - 0x3b */
117 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
119 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
120 0x00, 0x80, /* 0x44 - 0x45 */
121 /* Registers 0x46 - 0x47 are reserved */
122 0x80, 0x80, /* 0x46 - 0x47 */
124 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
125 /* Registers 0x4b - 0x7c are reserved */
127 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
128 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
129 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
130 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
131 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
132 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
133 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
134 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
135 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
136 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
137 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
138 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
141 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
144 /* Register read and write */
145 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
148 u8
*cache
= codec
->reg_cache
;
149 if (reg
>= DAC33_CACHEREGNUM
)
155 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
158 u8
*cache
= codec
->reg_cache
;
159 if (reg
>= DAC33_CACHEREGNUM
)
165 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
168 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
173 /* If powered off, return the cached value */
174 if (dac33
->chip_power
) {
175 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
177 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
178 value
[0] = dac33_read_reg_cache(codec
, reg
);
181 dac33_write_reg_cache(codec
, reg
, val
);
184 value
[0] = dac33_read_reg_cache(codec
, reg
);
190 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
193 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
199 * D15..D8 dac33 register offset
200 * D7...D0 register data
202 data
[0] = reg
& 0xff;
203 data
[1] = value
& 0xff;
205 dac33_write_reg_cache(codec
, data
[0], data
[1]);
206 if (dac33
->chip_power
) {
207 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
209 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
217 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
220 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
223 mutex_lock(&dac33
->mutex
);
224 ret
= dac33_write(codec
, reg
, value
);
225 mutex_unlock(&dac33
->mutex
);
230 #define DAC33_I2C_ADDR_AUTOINC 0x80
231 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
234 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
240 * D23..D16 dac33 register offset
241 * D15..D8 register data MSB
242 * D7...D0 register data LSB
244 data
[0] = reg
& 0xff;
245 data
[1] = (value
>> 8) & 0xff;
246 data
[2] = value
& 0xff;
248 dac33_write_reg_cache(codec
, data
[0], data
[1]);
249 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
251 if (dac33
->chip_power
) {
252 /* We need to set autoincrement mode for 16 bit writes */
253 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
254 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
256 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
264 static void dac33_restore_regs(struct snd_soc_codec
*codec
)
266 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
267 u8
*cache
= codec
->reg_cache
;
271 if (!dac33
->chip_power
)
274 for (i
= DAC33_PWR_CTRL
; i
<= DAC33_INTP_CTRL_B
; i
++) {
277 /* Skip the read only registers */
278 if ((i
>= DAC33_INT_OSC_STATUS
&&
279 i
<= DAC33_INT_OSC_FREQ_RAT_READ_B
) ||
280 (i
>= DAC33_FIFO_WPTR_MSB
&& i
<= DAC33_FIFO_IRQ_FLAG
) ||
281 i
== DAC33_DAC_STATUS_FLAGS
||
282 i
== DAC33_SRC_EST_REF_CLK_RATIO_A
||
283 i
== DAC33_SRC_EST_REF_CLK_RATIO_B
)
285 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
287 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
289 for (i
= DAC33_LDAC_PWR_CTRL
; i
<= DAC33_LINEL_TO_LLO_VOL
; i
++) {
292 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
294 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
296 for (i
= DAC33_LINER_TO_RLO_VOL
; i
<= DAC33_OSC_TRIM
; i
++) {
299 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
301 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
305 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
309 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
311 reg
|= DAC33_PDNALLB
;
313 reg
&= ~DAC33_PDNALLB
;
314 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
317 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
319 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
322 mutex_lock(&dac33
->mutex
);
324 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
328 "Failed to enable supplies: %d\n", ret
);
332 if (dac33
->power_gpio
>= 0)
333 gpio_set_value(dac33
->power_gpio
, 1);
335 dac33
->chip_power
= 1;
337 /* Restore registers */
338 dac33_restore_regs(codec
);
340 dac33_soft_power(codec
, 1);
342 dac33_soft_power(codec
, 0);
343 if (dac33
->power_gpio
>= 0)
344 gpio_set_value(dac33
->power_gpio
, 0);
346 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
350 "Failed to disable supplies: %d\n", ret
);
354 dac33
->chip_power
= 0;
358 mutex_unlock(&dac33
->mutex
);
362 static int dac33_get_nsample(struct snd_kcontrol
*kcontrol
,
363 struct snd_ctl_elem_value
*ucontrol
)
365 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
366 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
368 ucontrol
->value
.integer
.value
[0] = dac33
->nsample
;
373 static int dac33_set_nsample(struct snd_kcontrol
*kcontrol
,
374 struct snd_ctl_elem_value
*ucontrol
)
376 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
377 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
380 if (dac33
->nsample
== ucontrol
->value
.integer
.value
[0])
383 if (ucontrol
->value
.integer
.value
[0] < dac33
->nsample_min
||
384 ucontrol
->value
.integer
.value
[0] > dac33
->nsample_max
)
387 dac33
->nsample
= ucontrol
->value
.integer
.value
[0];
392 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
393 struct snd_ctl_elem_value
*ucontrol
)
395 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
396 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
398 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
403 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
404 struct snd_ctl_elem_value
*ucontrol
)
406 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
407 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
410 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
412 /* Do not allow changes while stream is running*/
416 if (ucontrol
->value
.integer
.value
[0] < 0 ||
417 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
420 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
425 /* Codec operation modes */
426 static const char *dac33_fifo_mode_texts
[] = {
427 "Bypass", "Mode 1", "Mode 7"
430 static const struct soc_enum dac33_fifo_mode_enum
=
431 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
432 dac33_fifo_mode_texts
);
435 * DACL/R digital volume control:
436 * from 0 dB to -63.5 in 0.5 dB steps
437 * Need to be inverted later on:
441 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
443 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
444 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
445 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
446 0, 0x7f, 1, dac_digivol_tlv
),
447 SOC_DOUBLE_R("DAC Digital Playback Switch",
448 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
449 SOC_DOUBLE_R("Line to Line Out Volume",
450 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
453 static const struct snd_kcontrol_new dac33_nsample_snd_controls
[] = {
454 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
455 dac33_get_nsample
, dac33_set_nsample
),
456 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
457 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
461 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
462 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
464 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
465 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
467 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
468 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
469 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
471 SND_SOC_DAPM_INPUT("LINEL"),
472 SND_SOC_DAPM_INPUT("LINER"),
474 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL
, 2, 0),
475 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL
, 2, 0),
478 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
479 &dac33_dapm_abypassl_control
),
480 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
481 &dac33_dapm_abypassr_control
),
483 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amp Power",
484 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
485 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amp Power",
486 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
489 static const struct snd_soc_dapm_route audio_map
[] = {
491 {"Analog Left Bypass", "Switch", "LINEL"},
492 {"Analog Right Bypass", "Switch", "LINER"},
494 {"Output Left Amp Power", NULL
, "DACL"},
495 {"Output Right Amp Power", NULL
, "DACR"},
497 {"Output Left Amp Power", NULL
, "Analog Left Bypass"},
498 {"Output Right Amp Power", NULL
, "Analog Right Bypass"},
501 {"LEFT_LO", NULL
, "Output Left Amp Power"},
502 {"RIGHT_LO", NULL
, "Output Right Amp Power"},
505 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
507 snd_soc_dapm_new_controls(codec
, dac33_dapm_widgets
,
508 ARRAY_SIZE(dac33_dapm_widgets
));
510 /* set up audio path interconnects */
511 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
516 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
517 enum snd_soc_bias_level level
)
522 case SND_SOC_BIAS_ON
:
523 dac33_soft_power(codec
, 1);
525 case SND_SOC_BIAS_PREPARE
:
527 case SND_SOC_BIAS_STANDBY
:
528 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
529 ret
= dac33_hard_power(codec
, 1);
534 dac33_soft_power(codec
, 0);
536 case SND_SOC_BIAS_OFF
:
537 ret
= dac33_hard_power(codec
, 0);
543 codec
->bias_level
= level
;
548 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
550 struct snd_soc_codec
*codec
;
552 codec
= &dac33
->codec
;
554 switch (dac33
->fifo_mode
) {
555 case DAC33_FIFO_MODE1
:
556 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
557 DAC33_THRREG(dac33
->nsample
));
558 dac33_write16(codec
, DAC33_PREFILL_MSB
,
559 DAC33_THRREG(dac33
->alarm_threshold
));
561 case DAC33_FIFO_MODE7
:
562 dac33_write16(codec
, DAC33_PREFILL_MSB
,
566 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
572 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
574 struct snd_soc_codec
*codec
;
576 codec
= &dac33
->codec
;
578 switch (dac33
->fifo_mode
) {
579 case DAC33_FIFO_MODE1
:
580 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
581 DAC33_THRREG(dac33
->nsample
));
583 case DAC33_FIFO_MODE7
:
584 /* At the moment we are not using interrupts in mode7 */
587 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
593 static void dac33_work(struct work_struct
*work
)
595 struct snd_soc_codec
*codec
;
596 struct tlv320dac33_priv
*dac33
;
599 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
600 codec
= &dac33
->codec
;
602 mutex_lock(&dac33
->mutex
);
603 switch (dac33
->state
) {
605 dac33
->state
= DAC33_PLAYBACK
;
606 dac33_prefill_handler(dac33
);
609 dac33_playback_handler(dac33
);
614 dac33
->state
= DAC33_IDLE
;
615 /* Mask all interrupts from dac33 */
616 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
619 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
620 reg
|= DAC33_FIFOFLUSH
;
621 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
624 mutex_unlock(&dac33
->mutex
);
627 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
629 struct snd_soc_codec
*codec
= dev
;
630 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
632 queue_work(dac33
->dac33_wq
, &dac33
->work
);
637 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
638 struct snd_soc_dai
*dai
)
640 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
641 struct snd_soc_device
*socdev
= rtd
->socdev
;
642 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
643 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
644 unsigned int pwr_ctrl
;
646 /* Stop pending workqueue */
647 if (dac33
->fifo_mode
)
648 cancel_work_sync(&dac33
->work
);
650 mutex_lock(&dac33
->mutex
);
651 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
652 pwr_ctrl
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
653 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
654 mutex_unlock(&dac33
->mutex
);
657 static void dac33_oscwait(struct snd_soc_codec
*codec
)
664 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
665 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
666 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
668 "internal oscillator calibration failed\n");
671 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
672 struct snd_pcm_hw_params
*params
,
673 struct snd_soc_dai
*dai
)
675 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
676 struct snd_soc_device
*socdev
= rtd
->socdev
;
677 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
679 /* Check parameters for validity */
680 switch (params_rate(params
)) {
685 dev_err(codec
->dev
, "unsupported rate %d\n",
686 params_rate(params
));
690 switch (params_format(params
)) {
691 case SNDRV_PCM_FORMAT_S16_LE
:
694 dev_err(codec
->dev
, "unsupported format %d\n",
695 params_format(params
));
702 #define CALC_OSCSET(rate, refclk) ( \
703 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
704 #define CALC_RATIOSET(rate, refclk) ( \
705 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
708 * tlv320dac33 is strict on the sequence of the register writes, if the register
709 * writes happens in different order, than dac33 might end up in unknown state.
710 * Use the known, working sequence of register writes to initialize the dac33.
712 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
714 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
715 struct snd_soc_device
*socdev
= rtd
->socdev
;
716 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
717 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
718 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
719 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
721 switch (substream
->runtime
->rate
) {
724 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
725 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
729 dev_err(codec
->dev
, "unsupported rate %d\n",
730 substream
->runtime
->rate
);
735 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
736 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
737 /* Read FIFO control A, and clear FIFO flush bit */
738 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
739 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
741 fifoctrl_a
&= ~DAC33_WIDTH
;
742 switch (substream
->runtime
->format
) {
743 case SNDRV_PCM_FORMAT_S16_LE
:
744 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
745 fifoctrl_a
|= DAC33_WIDTH
;
748 dev_err(codec
->dev
, "unsupported format %d\n",
749 substream
->runtime
->format
);
753 mutex_lock(&dac33
->mutex
);
754 dac33_soft_power(codec
, 1);
756 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
757 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
759 /* Write registers 0x08 and 0x09 (MSB, LSB) */
760 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
762 /* calib time: 128 is a nice number ;) */
763 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
765 /* adjustment treshold & step */
766 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
769 /* div=4 / gain=1 / div */
770 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
772 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
773 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
774 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
776 dac33_oscwait(codec
);
778 if (dac33
->fifo_mode
) {
779 /* Generic for all FIFO modes */
780 /* 50-51 : ASRC Control registers */
781 dac33_write(codec
, DAC33_ASRC_CTRL_A
, (1 << 4)); /* div=2 */
782 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
784 /* Write registers 0x34 and 0x35 (MSB, LSB) */
785 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
787 /* Set interrupts to high active */
788 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
790 /* FIFO bypass mode */
791 /* 50-51 : ASRC Control registers */
792 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
793 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
796 /* Interrupt behaviour configuration */
797 switch (dac33
->fifo_mode
) {
798 case DAC33_FIFO_MODE1
:
799 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
800 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
801 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
803 case DAC33_FIFO_MODE7
:
804 /* Disable all interrupts */
805 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
808 /* in FIFO bypass mode, the interrupts are not used */
812 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
814 switch (dac33
->fifo_mode
) {
815 case DAC33_FIFO_MODE1
:
818 * Disable the FIFO bypass (Enable the use of FIFO)
819 * Select nSample mode
820 * BCLK is only running when data is needed by DAC33
822 fifoctrl_a
&= ~DAC33_FBYPAS
;
823 fifoctrl_a
&= ~DAC33_FAUTO
;
824 aictrl_b
&= ~DAC33_BCLKON
;
826 case DAC33_FIFO_MODE7
:
829 * Disable the FIFO bypass (Enable the use of FIFO)
830 * Select Threshold mode
831 * BCLK is only running when data is needed by DAC33
833 fifoctrl_a
&= ~DAC33_FBYPAS
;
834 fifoctrl_a
|= DAC33_FAUTO
;
835 aictrl_b
&= ~DAC33_BCLKON
;
839 * For FIFO bypass mode:
840 * Enable the FIFO bypass (Disable the FIFO use)
841 * Set the BCLK as continous
843 fifoctrl_a
|= DAC33_FBYPAS
;
844 aictrl_b
|= DAC33_BCLKON
;
848 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
849 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
850 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
861 if (dac33
->fifo_mode
)
862 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
863 dac33
->burst_bclkdiv
);
865 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
867 switch (dac33
->fifo_mode
) {
868 case DAC33_FIFO_MODE1
:
869 dac33_write16(codec
, DAC33_ATHR_MSB
,
870 DAC33_THRREG(dac33
->alarm_threshold
));
872 case DAC33_FIFO_MODE7
:
874 * Configure the threshold levels, and leave 10 sample space
875 * at the bottom, and also at the top of the FIFO
877 dac33_write16(codec
, DAC33_UTHR_MSB
,
878 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES
- 10));
879 dac33_write16(codec
, DAC33_LTHR_MSB
,
886 mutex_unlock(&dac33
->mutex
);
891 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
893 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
894 struct snd_soc_device
*socdev
= rtd
->socdev
;
895 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
896 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
897 unsigned int nsample_limit
;
899 /* Number of samples (16bit, stereo) in one period */
900 dac33
->nsample_min
= snd_pcm_lib_period_bytes(substream
) / 4;
902 /* Number of samples (16bit, stereo) in ALSA buffer */
903 dac33
->nsample_max
= snd_pcm_lib_buffer_bytes(substream
) / 4;
904 /* Subtract one period from the total */
905 dac33
->nsample_max
-= dac33
->nsample_min
;
907 /* Number of samples for LATENCY_TIME_MS / 2 */
908 dac33
->alarm_threshold
= substream
->runtime
->rate
/
909 (1000 / (LATENCY_TIME_MS
/ 2));
911 /* Find and fix up the lowest nsmaple limit */
912 nsample_limit
= substream
->runtime
->rate
/ (1000 / LATENCY_TIME_MS
);
914 if (dac33
->nsample_min
< nsample_limit
)
915 dac33
->nsample_min
= nsample_limit
;
917 if (dac33
->nsample
< dac33
->nsample_min
)
918 dac33
->nsample
= dac33
->nsample_min
;
921 * Find and fix up the highest nsmaple limit
922 * In order to not overflow the DAC33 buffer substract the
923 * alarm_threshold value from the size of the DAC33 buffer
925 nsample_limit
= DAC33_BUFFER_SIZE_SAMPLES
- dac33
->alarm_threshold
;
927 if (dac33
->nsample_max
> nsample_limit
)
928 dac33
->nsample_max
= nsample_limit
;
930 if (dac33
->nsample
> dac33
->nsample_max
)
931 dac33
->nsample
= dac33
->nsample_max
;
934 static int dac33_pcm_prepare(struct snd_pcm_substream
*substream
,
935 struct snd_soc_dai
*dai
)
937 dac33_calculate_times(substream
);
938 dac33_prepare_chip(substream
);
943 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
944 struct snd_soc_dai
*dai
)
946 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
947 struct snd_soc_device
*socdev
= rtd
->socdev
;
948 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
949 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
953 case SNDRV_PCM_TRIGGER_START
:
954 case SNDRV_PCM_TRIGGER_RESUME
:
955 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
956 if (dac33
->fifo_mode
) {
957 dac33
->state
= DAC33_PREFILL
;
958 queue_work(dac33
->dac33_wq
, &dac33
->work
);
961 case SNDRV_PCM_TRIGGER_STOP
:
962 case SNDRV_PCM_TRIGGER_SUSPEND
:
963 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
964 if (dac33
->fifo_mode
) {
965 dac33
->state
= DAC33_FLUSH
;
966 queue_work(dac33
->dac33_wq
, &dac33
->work
);
976 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
977 int clk_id
, unsigned int freq
, int dir
)
979 struct snd_soc_codec
*codec
= codec_dai
->codec
;
980 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
981 u8 ioc_reg
, asrcb_reg
;
983 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
984 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
986 case TLV320DAC33_MCLK
:
987 ioc_reg
|= DAC33_REFSEL
;
988 asrcb_reg
|= DAC33_SRCREFSEL
;
990 case TLV320DAC33_SLEEPCLK
:
991 ioc_reg
&= ~DAC33_REFSEL
;
992 asrcb_reg
&= ~DAC33_SRCREFSEL
;
995 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
998 dac33
->refclk
= freq
;
1000 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1001 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1006 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1009 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1010 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
1011 u8 aictrl_a
, aictrl_b
;
1013 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1014 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1015 /* set master/slave audio interface */
1016 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1017 case SND_SOC_DAIFMT_CBM_CFM
:
1019 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1021 case SND_SOC_DAIFMT_CBS_CFS
:
1023 if (dac33
->fifo_mode
) {
1024 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1027 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1033 aictrl_a
&= ~DAC33_AFMT_MASK
;
1034 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1035 case SND_SOC_DAIFMT_I2S
:
1036 aictrl_a
|= DAC33_AFMT_I2S
;
1038 case SND_SOC_DAIFMT_DSP_A
:
1039 aictrl_a
|= DAC33_AFMT_DSP
;
1040 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1041 aictrl_b
|= DAC33_DATA_DELAY(1); /* 1 bit delay */
1043 case SND_SOC_DAIFMT_DSP_B
:
1044 aictrl_a
|= DAC33_AFMT_DSP
;
1045 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
; /* No delay */
1047 case SND_SOC_DAIFMT_RIGHT_J
:
1048 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1050 case SND_SOC_DAIFMT_LEFT_J
:
1051 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1054 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1055 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1059 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1060 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1065 static void dac33_init_chip(struct snd_soc_codec
*codec
)
1067 /* 44-46: DAC Control Registers */
1068 /* A : DAC sample rate Fsref/1.5 */
1069 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(1));
1070 /* B : DAC src=normal, not muted */
1071 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
1072 DAC33_DACSRCL_LEFT
);
1073 /* C : (defaults) */
1074 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
1076 /* 64-65 : L&R DAC power control
1077 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1078 dac33_write(codec
, DAC33_LDAC_PWR_CTRL
, DAC33_LROUT_GAIN(2));
1079 dac33_write(codec
, DAC33_RDAC_PWR_CTRL
, DAC33_LROUT_GAIN(2));
1081 /* 73 : volume soft stepping control,
1082 clock source = internal osc (?) */
1083 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
1085 /* 66 : LOP/LOM Modes */
1086 dac33_write(codec
, DAC33_OUT_AMP_CM_CTRL
, 0xff);
1088 /* 68 : LOM inverted from LOP */
1089 dac33_write(codec
, DAC33_OUT_AMP_CTRL
, (3<<2));
1091 dac33_write(codec
, DAC33_PWR_CTRL
, DAC33_PDNALLB
);
1094 static int dac33_soc_probe(struct platform_device
*pdev
)
1096 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1097 struct snd_soc_codec
*codec
;
1098 struct tlv320dac33_priv
*dac33
;
1101 BUG_ON(!tlv320dac33_codec
);
1103 codec
= tlv320dac33_codec
;
1104 socdev
->card
->codec
= codec
;
1105 dac33
= codec
->private_data
;
1107 /* Power up the codec */
1108 dac33_hard_power(codec
, 1);
1109 /* Set default configuration */
1110 dac33_init_chip(codec
);
1113 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1115 dev_err(codec
->dev
, "failed to create pcms\n");
1119 snd_soc_add_controls(codec
, dac33_snd_controls
,
1120 ARRAY_SIZE(dac33_snd_controls
));
1121 /* Only add the nSample controls, if we have valid IRQ number */
1122 if (dac33
->irq
>= 0)
1123 snd_soc_add_controls(codec
, dac33_nsample_snd_controls
,
1124 ARRAY_SIZE(dac33_nsample_snd_controls
));
1126 dac33_add_widgets(codec
);
1128 /* power on device */
1129 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1131 /* Bias level configuration has enabled regulator an extra time */
1132 regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1137 dac33_hard_power(codec
, 0);
1141 static int dac33_soc_remove(struct platform_device
*pdev
)
1143 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1144 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1146 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1148 snd_soc_free_pcms(socdev
);
1149 snd_soc_dapm_free(socdev
);
1154 static int dac33_soc_suspend(struct platform_device
*pdev
, pm_message_t state
)
1156 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1157 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1159 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1164 static int dac33_soc_resume(struct platform_device
*pdev
)
1166 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1167 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1169 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1170 dac33_set_bias_level(codec
, codec
->suspend_bias_level
);
1175 struct snd_soc_codec_device soc_codec_dev_tlv320dac33
= {
1176 .probe
= dac33_soc_probe
,
1177 .remove
= dac33_soc_remove
,
1178 .suspend
= dac33_soc_suspend
,
1179 .resume
= dac33_soc_resume
,
1181 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33
);
1183 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1184 SNDRV_PCM_RATE_48000)
1185 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1187 static struct snd_soc_dai_ops dac33_dai_ops
= {
1188 .shutdown
= dac33_shutdown
,
1189 .hw_params
= dac33_hw_params
,
1190 .prepare
= dac33_pcm_prepare
,
1191 .trigger
= dac33_pcm_trigger
,
1192 .set_sysclk
= dac33_set_dai_sysclk
,
1193 .set_fmt
= dac33_set_dai_fmt
,
1196 struct snd_soc_dai dac33_dai
= {
1197 .name
= "tlv320dac33",
1199 .stream_name
= "Playback",
1202 .rates
= DAC33_RATES
,
1203 .formats
= DAC33_FORMATS
,},
1204 .ops
= &dac33_dai_ops
,
1206 EXPORT_SYMBOL_GPL(dac33_dai
);
1208 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1209 const struct i2c_device_id
*id
)
1211 struct tlv320dac33_platform_data
*pdata
;
1212 struct tlv320dac33_priv
*dac33
;
1213 struct snd_soc_codec
*codec
;
1216 if (client
->dev
.platform_data
== NULL
) {
1217 dev_err(&client
->dev
, "Platform data not set\n");
1220 pdata
= client
->dev
.platform_data
;
1222 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1226 codec
= &dac33
->codec
;
1227 codec
->private_data
= dac33
;
1228 codec
->control_data
= client
;
1230 mutex_init(&codec
->mutex
);
1231 mutex_init(&dac33
->mutex
);
1232 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1233 INIT_LIST_HEAD(&codec
->dapm_paths
);
1235 codec
->name
= "tlv320dac33";
1236 codec
->owner
= THIS_MODULE
;
1237 codec
->read
= dac33_read_reg_cache
;
1238 codec
->write
= dac33_write_locked
;
1239 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1240 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1241 codec
->set_bias_level
= dac33_set_bias_level
;
1242 codec
->dai
= &dac33_dai
;
1244 codec
->reg_cache_size
= ARRAY_SIZE(dac33_reg
);
1245 codec
->reg_cache
= kmemdup(dac33_reg
, ARRAY_SIZE(dac33_reg
),
1247 if (codec
->reg_cache
== NULL
) {
1252 i2c_set_clientdata(client
, dac33
);
1254 dac33
->power_gpio
= pdata
->power_gpio
;
1255 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1256 dac33
->irq
= client
->irq
;
1257 dac33
->nsample
= NSAMPLE_MAX
;
1258 /* Disable FIFO use by default */
1259 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1261 tlv320dac33_codec
= codec
;
1263 codec
->dev
= &client
->dev
;
1264 dac33_dai
.dev
= codec
->dev
;
1266 /* Check if the reset GPIO number is valid and request it */
1267 if (dac33
->power_gpio
>= 0) {
1268 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1271 "Failed to request reset GPIO (%d)\n",
1273 snd_soc_unregister_dai(&dac33_dai
);
1274 snd_soc_unregister_codec(codec
);
1277 gpio_direction_output(dac33
->power_gpio
, 0);
1279 dac33
->chip_power
= 1;
1282 /* Check if the IRQ number is valid and request it */
1283 if (dac33
->irq
>= 0) {
1284 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1285 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1286 codec
->name
, codec
);
1288 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1292 if (dac33
->irq
!= -1) {
1293 /* Setup work queue */
1295 create_singlethread_workqueue("tlv320dac33");
1296 if (dac33
->dac33_wq
== NULL
) {
1297 free_irq(dac33
->irq
, &dac33
->codec
);
1302 INIT_WORK(&dac33
->work
, dac33_work
);
1306 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1307 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1309 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(dac33
->supplies
),
1313 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
1317 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
1320 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
1324 ret
= snd_soc_register_codec(codec
);
1326 dev_err(codec
->dev
, "Failed to register codec: %d\n", ret
);
1330 ret
= snd_soc_register_dai(&dac33_dai
);
1332 dev_err(codec
->dev
, "Failed to register DAI: %d\n", ret
);
1333 snd_soc_unregister_codec(codec
);
1337 /* Shut down the codec for now */
1338 dac33_hard_power(codec
, 0);
1343 regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1345 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1347 if (dac33
->irq
>= 0) {
1348 free_irq(dac33
->irq
, &dac33
->codec
);
1349 destroy_workqueue(dac33
->dac33_wq
);
1352 if (dac33
->power_gpio
>= 0)
1353 gpio_free(dac33
->power_gpio
);
1355 kfree(codec
->reg_cache
);
1357 tlv320dac33_codec
= NULL
;
1363 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1365 struct tlv320dac33_priv
*dac33
;
1367 dac33
= i2c_get_clientdata(client
);
1368 dac33_hard_power(&dac33
->codec
, 0);
1370 if (dac33
->power_gpio
>= 0)
1371 gpio_free(dac33
->power_gpio
);
1372 if (dac33
->irq
>= 0)
1373 free_irq(dac33
->irq
, &dac33
->codec
);
1375 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1377 destroy_workqueue(dac33
->dac33_wq
);
1378 snd_soc_unregister_dai(&dac33_dai
);
1379 snd_soc_unregister_codec(&dac33
->codec
);
1380 kfree(dac33
->codec
.reg_cache
);
1382 tlv320dac33_codec
= NULL
;
1387 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1389 .name
= "tlv320dac33",
1395 static struct i2c_driver tlv320dac33_i2c_driver
= {
1397 .name
= "tlv320dac33",
1398 .owner
= THIS_MODULE
,
1400 .probe
= dac33_i2c_probe
,
1401 .remove
= __devexit_p(dac33_i2c_remove
),
1402 .id_table
= tlv320dac33_i2c_id
,
1405 static int __init
dac33_module_init(void)
1408 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1410 printk(KERN_ERR
"DAC33: driver registration failed\n");
1415 module_init(dac33_module_init
);
1417 static void __exit
dac33_module_exit(void)
1419 i2c_del_driver(&tlv320dac33_i2c_driver
);
1421 module_exit(dac33_module_exit
);
1424 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1425 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1426 MODULE_LICENSE("GPL");