2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
51 #define DAC33_FIFO_SIZE_16BIT 6144
52 #define DAC33_FIFO_SIZE_24BIT 4096
53 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
55 #define BURST_BASEFREQ_HZ 49152000
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
66 static void dac33_calculate_times(struct snd_pcm_substream
*substream
);
67 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
);
76 enum dac33_fifo_modes
{
77 DAC33_FIFO_BYPASS
= 0,
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
90 struct tlv320dac33_priv
{
92 struct workqueue_struct
*dac33_wq
;
93 struct work_struct work
;
94 struct snd_soc_codec
*codec
;
95 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
96 struct snd_pcm_substream
*substream
;
102 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
103 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
104 unsigned int fifo_size
; /* Size of the FIFO in samples */
105 unsigned int nsample
; /* burst read amount from host */
106 int mode1_latency
; /* latency caused by the i2c writes in
108 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
109 unsigned int burst_rate
; /* Interface speed in Burst modes */
111 int keep_bclk
; /* Keep the BCLK continuously running
114 unsigned long long t_stamp1
; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2
; /* calculate the FIFO caused delay */
117 unsigned int mode1_us_burst
; /* Time to burst read n number of
119 unsigned int mode7_us_to_lthr
; /* Time to reach lthr from uthr */
123 enum dac33_state state
;
124 enum snd_soc_control_type control_type
;
128 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
143 0x00, 0x00, /* 0x38 - 0x39 */
144 /* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
149 0x00, 0x80, /* 0x44 - 0x45 */
150 /* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
153 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
154 /* Registers 0x4b - 0x7c are reserved */
156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
173 /* Register read and write */
174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
177 u8
*cache
= codec
->reg_cache
;
178 if (reg
>= DAC33_CACHEREGNUM
)
184 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
187 u8
*cache
= codec
->reg_cache
;
188 if (reg
>= DAC33_CACHEREGNUM
)
194 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
197 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
202 /* If powered off, return the cached value */
203 if (dac33
->chip_power
) {
204 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
206 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
207 value
[0] = dac33_read_reg_cache(codec
, reg
);
211 dac33_write_reg_cache(codec
, reg
, val
);
214 value
[0] = dac33_read_reg_cache(codec
, reg
);
220 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
223 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
232 data
[0] = reg
& 0xff;
233 data
[1] = value
& 0xff;
235 dac33_write_reg_cache(codec
, data
[0], data
[1]);
236 if (dac33
->chip_power
) {
237 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
239 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
247 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
250 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
253 mutex_lock(&dac33
->mutex
);
254 ret
= dac33_write(codec
, reg
, value
);
255 mutex_unlock(&dac33
->mutex
);
260 #define DAC33_I2C_ADDR_AUTOINC 0x80
261 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
264 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
274 data
[0] = reg
& 0xff;
275 data
[1] = (value
>> 8) & 0xff;
276 data
[2] = value
& 0xff;
278 dac33_write_reg_cache(codec
, data
[0], data
[1]);
279 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
281 if (dac33
->chip_power
) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
284 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
286 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
294 static void dac33_init_chip(struct snd_soc_codec
*codec
)
296 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
298 if (unlikely(!dac33
->chip_power
))
301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
307 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
313 /* Restore only selected registers (gains mostly) */
314 dac33_write(codec
, DAC33_LDAC_DIG_VOL_CTRL
,
315 dac33_read_reg_cache(codec
, DAC33_LDAC_DIG_VOL_CTRL
));
316 dac33_write(codec
, DAC33_RDAC_DIG_VOL_CTRL
,
317 dac33_read_reg_cache(codec
, DAC33_RDAC_DIG_VOL_CTRL
));
319 dac33_write(codec
, DAC33_LINEL_TO_LLO_VOL
,
320 dac33_read_reg_cache(codec
, DAC33_LINEL_TO_LLO_VOL
));
321 dac33_write(codec
, DAC33_LINER_TO_RLO_VOL
,
322 dac33_read_reg_cache(codec
, DAC33_LINER_TO_RLO_VOL
));
324 dac33_write(codec
, DAC33_OUT_AMP_CTRL
,
325 dac33_read_reg_cache(codec
, DAC33_OUT_AMP_CTRL
));
329 static inline int dac33_read_id(struct snd_soc_codec
*codec
)
334 for (i
= 0; i
< 3; i
++) {
335 ret
= dac33_read(codec
, DAC33_DEVICE_ID_MSB
+ i
, ®
);
343 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
347 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
349 reg
|= DAC33_PDNALLB
;
351 reg
&= ~(DAC33_PDNALLB
| DAC33_OSCPDNB
|
352 DAC33_DACRPDNB
| DAC33_DACLPDNB
);
353 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
356 static inline void dac33_disable_digital(struct snd_soc_codec
*codec
)
360 /* Stop the DAI clock */
361 reg
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
362 reg
&= ~DAC33_BCLKON
;
363 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, reg
);
365 /* Power down the Oscillator, and DACs */
366 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
367 reg
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
368 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
371 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
373 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
376 mutex_lock(&dac33
->mutex
);
379 if (unlikely(power
== dac33
->chip_power
)) {
380 dev_dbg(codec
->dev
, "Trying to set the same power state: %s\n",
381 power
? "ON" : "OFF");
386 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
390 "Failed to enable supplies: %d\n", ret
);
394 if (dac33
->power_gpio
>= 0)
395 gpio_set_value(dac33
->power_gpio
, 1);
397 dac33
->chip_power
= 1;
399 dac33_soft_power(codec
, 0);
400 if (dac33
->power_gpio
>= 0)
401 gpio_set_value(dac33
->power_gpio
, 0);
403 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
407 "Failed to disable supplies: %d\n", ret
);
411 dac33
->chip_power
= 0;
415 mutex_unlock(&dac33
->mutex
);
419 static int dac33_playback_event(struct snd_soc_dapm_widget
*w
,
420 struct snd_kcontrol
*kcontrol
, int event
)
422 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(w
->codec
);
425 case SND_SOC_DAPM_PRE_PMU
:
426 if (likely(dac33
->substream
)) {
427 dac33_calculate_times(dac33
->substream
);
428 dac33_prepare_chip(dac33
->substream
);
431 case SND_SOC_DAPM_POST_PMD
:
432 dac33_disable_digital(w
->codec
);
438 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
439 struct snd_ctl_elem_value
*ucontrol
)
441 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
442 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
444 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
449 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
450 struct snd_ctl_elem_value
*ucontrol
)
452 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
453 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
456 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
458 /* Do not allow changes while stream is running*/
462 if (ucontrol
->value
.integer
.value
[0] < 0 ||
463 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
466 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
471 /* Codec operation modes */
472 static const char *dac33_fifo_mode_texts
[] = {
473 "Bypass", "Mode 1", "Mode 7"
476 static const struct soc_enum dac33_fifo_mode_enum
=
477 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
478 dac33_fifo_mode_texts
);
480 /* L/R Line Output Gain */
481 static const char *lr_lineout_gain_texts
[] = {
482 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
483 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
486 static const struct soc_enum l_lineout_gain_enum
=
487 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL
, 0,
488 ARRAY_SIZE(lr_lineout_gain_texts
),
489 lr_lineout_gain_texts
);
491 static const struct soc_enum r_lineout_gain_enum
=
492 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL
, 0,
493 ARRAY_SIZE(lr_lineout_gain_texts
),
494 lr_lineout_gain_texts
);
497 * DACL/R digital volume control:
498 * from 0 dB to -63.5 in 0.5 dB steps
499 * Need to be inverted later on:
503 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
505 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
506 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
507 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
508 0, 0x7f, 1, dac_digivol_tlv
),
509 SOC_DOUBLE_R("DAC Digital Playback Switch",
510 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
511 SOC_DOUBLE_R("Line to Line Out Volume",
512 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
513 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum
),
514 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum
),
517 static const struct snd_kcontrol_new dac33_mode_snd_controls
[] = {
518 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
519 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
523 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
524 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
526 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
527 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
529 /* LOP L/R invert selection */
530 static const char *dac33_lr_lom_texts
[] = {"DAC", "LOP"};
532 static const struct soc_enum dac33_left_lom_enum
=
533 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL
, 3,
534 ARRAY_SIZE(dac33_lr_lom_texts
),
537 static const struct snd_kcontrol_new dac33_dapm_left_lom_control
=
538 SOC_DAPM_ENUM("Route", dac33_left_lom_enum
);
540 static const struct soc_enum dac33_right_lom_enum
=
541 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL
, 2,
542 ARRAY_SIZE(dac33_lr_lom_texts
),
545 static const struct snd_kcontrol_new dac33_dapm_right_lom_control
=
546 SOC_DAPM_ENUM("Route", dac33_right_lom_enum
);
548 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
549 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
550 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
552 SND_SOC_DAPM_INPUT("LINEL"),
553 SND_SOC_DAPM_INPUT("LINER"),
555 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM
, 0, 0),
556 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM
, 0, 0),
559 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
560 &dac33_dapm_abypassl_control
),
561 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
562 &dac33_dapm_abypassr_control
),
564 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM
, 0, 0,
565 &dac33_dapm_left_lom_control
),
566 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM
, 0, 0,
567 &dac33_dapm_right_lom_control
),
569 * For DAPM path, when only the anlog bypass path is enabled, and the
570 * LOP inverted from the corresponding DAC side.
571 * This is needed, so we can attach the DAC power supply in this case.
573 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
574 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
576 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amplifier",
577 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
578 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amplifier",
579 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
581 SND_SOC_DAPM_SUPPLY("Left DAC Power",
582 DAC33_LDAC_PWR_CTRL
, 2, 0, NULL
, 0),
583 SND_SOC_DAPM_SUPPLY("Right DAC Power",
584 DAC33_RDAC_PWR_CTRL
, 2, 0, NULL
, 0),
586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event
),
587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event
),
590 static const struct snd_soc_dapm_route audio_map
[] = {
592 {"Analog Left Bypass", "Switch", "LINEL"},
593 {"Analog Right Bypass", "Switch", "LINER"},
595 {"Output Left Amplifier", NULL
, "DACL"},
596 {"Output Right Amplifier", NULL
, "DACR"},
598 {"Left Bypass PGA", NULL
, "Analog Left Bypass"},
599 {"Right Bypass PGA", NULL
, "Analog Right Bypass"},
601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
606 {"Output Left Amplifier", NULL
, "Left LOM Inverted From"},
607 {"Output Right Amplifier", NULL
, "Right LOM Inverted From"},
609 {"DACL", NULL
, "Left DAC Power"},
610 {"DACR", NULL
, "Right DAC Power"},
612 {"Left Bypass PGA", NULL
, "Left DAC Power"},
613 {"Right Bypass PGA", NULL
, "Right DAC Power"},
616 {"LEFT_LO", NULL
, "Output Left Amplifier"},
617 {"RIGHT_LO", NULL
, "Output Right Amplifier"},
620 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
622 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
624 snd_soc_dapm_new_controls(dapm
, dac33_dapm_widgets
,
625 ARRAY_SIZE(dac33_dapm_widgets
));
626 /* set up audio path interconnects */
627 snd_soc_dapm_add_routes(dapm
, audio_map
, ARRAY_SIZE(audio_map
));
632 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
633 enum snd_soc_bias_level level
)
635 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
639 case SND_SOC_BIAS_ON
:
640 if (!dac33
->substream
)
641 dac33_soft_power(codec
, 1);
643 case SND_SOC_BIAS_PREPARE
:
645 case SND_SOC_BIAS_STANDBY
:
646 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
647 /* Coming from OFF, switch on the codec */
648 ret
= dac33_hard_power(codec
, 1);
652 dac33_init_chip(codec
);
655 case SND_SOC_BIAS_OFF
:
656 /* Do not power off, when the codec is already off */
657 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
)
659 ret
= dac33_hard_power(codec
, 0);
664 codec
->dapm
.bias_level
= level
;
669 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
671 struct snd_soc_codec
*codec
= dac33
->codec
;
675 switch (dac33
->fifo_mode
) {
676 case DAC33_FIFO_MODE1
:
677 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
678 DAC33_THRREG(dac33
->nsample
));
680 /* Take the timestamps */
681 spin_lock_irqsave(&dac33
->lock
, flags
);
682 dac33
->t_stamp2
= ktime_to_us(ktime_get());
683 dac33
->t_stamp1
= dac33
->t_stamp2
;
684 spin_unlock_irqrestore(&dac33
->lock
, flags
);
686 dac33_write16(codec
, DAC33_PREFILL_MSB
,
687 DAC33_THRREG(dac33
->alarm_threshold
));
688 /* Enable Alarm Threshold IRQ with a delay */
689 delay
= SAMPLES_TO_US(dac33
->burst_rate
,
690 dac33
->alarm_threshold
) + 1000;
691 usleep_range(delay
, delay
+ 500);
692 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
694 case DAC33_FIFO_MODE7
:
695 /* Take the timestamp */
696 spin_lock_irqsave(&dac33
->lock
, flags
);
697 dac33
->t_stamp1
= ktime_to_us(ktime_get());
698 /* Move back the timestamp with drain time */
699 dac33
->t_stamp1
-= dac33
->mode7_us_to_lthr
;
700 spin_unlock_irqrestore(&dac33
->lock
, flags
);
702 dac33_write16(codec
, DAC33_PREFILL_MSB
,
703 DAC33_THRREG(DAC33_MODE7_MARGIN
));
705 /* Enable Upper Threshold IRQ */
706 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MUT
);
709 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
715 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
717 struct snd_soc_codec
*codec
= dac33
->codec
;
720 switch (dac33
->fifo_mode
) {
721 case DAC33_FIFO_MODE1
:
722 /* Take the timestamp */
723 spin_lock_irqsave(&dac33
->lock
, flags
);
724 dac33
->t_stamp2
= ktime_to_us(ktime_get());
725 spin_unlock_irqrestore(&dac33
->lock
, flags
);
727 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
728 DAC33_THRREG(dac33
->nsample
));
730 case DAC33_FIFO_MODE7
:
731 /* At the moment we are not using interrupts in mode7 */
734 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
740 static void dac33_work(struct work_struct
*work
)
742 struct snd_soc_codec
*codec
;
743 struct tlv320dac33_priv
*dac33
;
746 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
747 codec
= dac33
->codec
;
749 mutex_lock(&dac33
->mutex
);
750 switch (dac33
->state
) {
752 dac33
->state
= DAC33_PLAYBACK
;
753 dac33_prefill_handler(dac33
);
756 dac33_playback_handler(dac33
);
761 dac33
->state
= DAC33_IDLE
;
762 /* Mask all interrupts from dac33 */
763 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
766 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
767 reg
|= DAC33_FIFOFLUSH
;
768 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
771 mutex_unlock(&dac33
->mutex
);
774 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
776 struct snd_soc_codec
*codec
= dev
;
777 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
780 spin_lock_irqsave(&dac33
->lock
, flags
);
781 dac33
->t_stamp1
= ktime_to_us(ktime_get());
782 spin_unlock_irqrestore(&dac33
->lock
, flags
);
784 /* Do not schedule the workqueue in Mode7 */
785 if (dac33
->fifo_mode
!= DAC33_FIFO_MODE7
)
786 queue_work(dac33
->dac33_wq
, &dac33
->work
);
791 static void dac33_oscwait(struct snd_soc_codec
*codec
)
797 usleep_range(1000, 2000);
798 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
799 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
800 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
802 "internal oscillator calibration failed\n");
805 static int dac33_startup(struct snd_pcm_substream
*substream
,
806 struct snd_soc_dai
*dai
)
808 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
809 struct snd_soc_codec
*codec
= rtd
->codec
;
810 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
812 /* Stream started, save the substream pointer */
813 dac33
->substream
= substream
;
815 snd_pcm_hw_constraint_msbits(substream
->runtime
, 0, 32, 24);
820 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
821 struct snd_soc_dai
*dai
)
823 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
824 struct snd_soc_codec
*codec
= rtd
->codec
;
825 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
827 dac33
->substream
= NULL
;
830 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
831 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
832 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
833 struct snd_pcm_hw_params
*params
,
834 struct snd_soc_dai
*dai
)
836 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
837 struct snd_soc_codec
*codec
= rtd
->codec
;
838 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
840 /* Check parameters for validity */
841 switch (params_rate(params
)) {
846 dev_err(codec
->dev
, "unsupported rate %d\n",
847 params_rate(params
));
851 switch (params_format(params
)) {
852 case SNDRV_PCM_FORMAT_S16_LE
:
853 dac33
->fifo_size
= DAC33_FIFO_SIZE_16BIT
;
854 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 32);
856 case SNDRV_PCM_FORMAT_S32_LE
:
857 dac33
->fifo_size
= DAC33_FIFO_SIZE_24BIT
;
858 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 64);
861 dev_err(codec
->dev
, "unsupported format %d\n",
862 params_format(params
));
869 #define CALC_OSCSET(rate, refclk) ( \
870 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
871 #define CALC_RATIOSET(rate, refclk) ( \
872 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
875 * tlv320dac33 is strict on the sequence of the register writes, if the register
876 * writes happens in different order, than dac33 might end up in unknown state.
877 * Use the known, working sequence of register writes to initialize the dac33.
879 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
881 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
882 struct snd_soc_codec
*codec
= rtd
->codec
;
883 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
884 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
885 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
887 switch (substream
->runtime
->rate
) {
890 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
891 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
895 dev_err(codec
->dev
, "unsupported rate %d\n",
896 substream
->runtime
->rate
);
901 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
902 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
903 /* Read FIFO control A, and clear FIFO flush bit */
904 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
905 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
907 fifoctrl_a
&= ~DAC33_WIDTH
;
908 switch (substream
->runtime
->format
) {
909 case SNDRV_PCM_FORMAT_S16_LE
:
910 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
911 fifoctrl_a
|= DAC33_WIDTH
;
913 case SNDRV_PCM_FORMAT_S32_LE
:
914 aictrl_a
|= (DAC33_NCYCL_32
| DAC33_WLEN_24
);
917 dev_err(codec
->dev
, "unsupported format %d\n",
918 substream
->runtime
->format
);
922 mutex_lock(&dac33
->mutex
);
924 if (!dac33
->chip_power
) {
926 * Chip is not powered yet.
927 * Do the init in the dac33_set_bias_level later.
929 mutex_unlock(&dac33
->mutex
);
933 dac33_soft_power(codec
, 0);
934 dac33_soft_power(codec
, 1);
936 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
937 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
939 /* Write registers 0x08 and 0x09 (MSB, LSB) */
940 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
942 /* calib time: 128 is a nice number ;) */
943 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
945 /* adjustment treshold & step */
946 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
949 /* div=4 / gain=1 / div */
950 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
952 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
953 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
954 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
956 dac33_oscwait(codec
);
958 if (dac33
->fifo_mode
) {
959 /* Generic for all FIFO modes */
960 /* 50-51 : ASRC Control registers */
961 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
962 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
964 /* Write registers 0x34 and 0x35 (MSB, LSB) */
965 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
967 /* Set interrupts to high active */
968 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
970 /* FIFO bypass mode */
971 /* 50-51 : ASRC Control registers */
972 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
973 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
976 /* Interrupt behaviour configuration */
977 switch (dac33
->fifo_mode
) {
978 case DAC33_FIFO_MODE1
:
979 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
980 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
982 case DAC33_FIFO_MODE7
:
983 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_A
,
984 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL
));
987 /* in FIFO bypass mode, the interrupts are not used */
991 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
993 switch (dac33
->fifo_mode
) {
994 case DAC33_FIFO_MODE1
:
997 * Disable the FIFO bypass (Enable the use of FIFO)
998 * Select nSample mode
999 * BCLK is only running when data is needed by DAC33
1001 fifoctrl_a
&= ~DAC33_FBYPAS
;
1002 fifoctrl_a
&= ~DAC33_FAUTO
;
1003 if (dac33
->keep_bclk
)
1004 aictrl_b
|= DAC33_BCLKON
;
1006 aictrl_b
&= ~DAC33_BCLKON
;
1008 case DAC33_FIFO_MODE7
:
1011 * Disable the FIFO bypass (Enable the use of FIFO)
1012 * Select Threshold mode
1013 * BCLK is only running when data is needed by DAC33
1015 fifoctrl_a
&= ~DAC33_FBYPAS
;
1016 fifoctrl_a
|= DAC33_FAUTO
;
1017 if (dac33
->keep_bclk
)
1018 aictrl_b
|= DAC33_BCLKON
;
1020 aictrl_b
&= ~DAC33_BCLKON
;
1024 * For FIFO bypass mode:
1025 * Enable the FIFO bypass (Disable the FIFO use)
1026 * Set the BCLK as continous
1028 fifoctrl_a
|= DAC33_FBYPAS
;
1029 aictrl_b
|= DAC33_BCLKON
;
1033 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
1034 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1035 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1046 if (dac33
->fifo_mode
)
1047 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
1048 dac33
->burst_bclkdiv
);
1050 if (substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
)
1051 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
1053 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 16);
1055 switch (dac33
->fifo_mode
) {
1056 case DAC33_FIFO_MODE1
:
1057 dac33_write16(codec
, DAC33_ATHR_MSB
,
1058 DAC33_THRREG(dac33
->alarm_threshold
));
1060 case DAC33_FIFO_MODE7
:
1062 * Configure the threshold levels, and leave 10 sample space
1063 * at the bottom, and also at the top of the FIFO
1065 dac33_write16(codec
, DAC33_UTHR_MSB
, DAC33_THRREG(dac33
->uthr
));
1066 dac33_write16(codec
, DAC33_LTHR_MSB
,
1067 DAC33_THRREG(DAC33_MODE7_MARGIN
));
1073 mutex_unlock(&dac33
->mutex
);
1078 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
1080 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1081 struct snd_soc_codec
*codec
= rtd
->codec
;
1082 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1083 unsigned int period_size
= substream
->runtime
->period_size
;
1084 unsigned int rate
= substream
->runtime
->rate
;
1085 unsigned int nsample_limit
;
1087 /* In bypass mode we don't need to calculate */
1088 if (!dac33
->fifo_mode
)
1091 switch (dac33
->fifo_mode
) {
1092 case DAC33_FIFO_MODE1
:
1093 /* Number of samples under i2c latency */
1094 dac33
->alarm_threshold
= US_TO_SAMPLES(rate
,
1095 dac33
->mode1_latency
);
1096 nsample_limit
= dac33
->fifo_size
- dac33
->alarm_threshold
;
1098 if (period_size
<= dac33
->alarm_threshold
)
1100 * Configure nSamaple to number of periods,
1101 * which covers the latency requironment.
1103 dac33
->nsample
= period_size
*
1104 ((dac33
->alarm_threshold
/ period_size
) +
1105 (dac33
->alarm_threshold
% period_size
?
1107 else if (period_size
> nsample_limit
)
1108 dac33
->nsample
= nsample_limit
;
1110 dac33
->nsample
= period_size
;
1112 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
1114 dac33
->t_stamp1
= 0;
1115 dac33
->t_stamp2
= 0;
1117 case DAC33_FIFO_MODE7
:
1118 dac33
->uthr
= UTHR_FROM_PERIOD_SIZE(period_size
, rate
,
1119 dac33
->burst_rate
) + 9;
1120 if (dac33
->uthr
> (dac33
->fifo_size
- DAC33_MODE7_MARGIN
))
1121 dac33
->uthr
= dac33
->fifo_size
- DAC33_MODE7_MARGIN
;
1122 if (dac33
->uthr
< (DAC33_MODE7_MARGIN
+ 10))
1123 dac33
->uthr
= (DAC33_MODE7_MARGIN
+ 10);
1125 dac33
->mode7_us_to_lthr
=
1126 SAMPLES_TO_US(substream
->runtime
->rate
,
1127 dac33
->uthr
- DAC33_MODE7_MARGIN
+ 1);
1128 dac33
->t_stamp1
= 0;
1136 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1137 struct snd_soc_dai
*dai
)
1139 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1140 struct snd_soc_codec
*codec
= rtd
->codec
;
1141 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1145 case SNDRV_PCM_TRIGGER_START
:
1146 case SNDRV_PCM_TRIGGER_RESUME
:
1147 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1148 if (dac33
->fifo_mode
) {
1149 dac33
->state
= DAC33_PREFILL
;
1150 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1153 case SNDRV_PCM_TRIGGER_STOP
:
1154 case SNDRV_PCM_TRIGGER_SUSPEND
:
1155 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1156 if (dac33
->fifo_mode
) {
1157 dac33
->state
= DAC33_FLUSH
;
1158 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1168 static snd_pcm_sframes_t
dac33_dai_delay(
1169 struct snd_pcm_substream
*substream
,
1170 struct snd_soc_dai
*dai
)
1172 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1173 struct snd_soc_codec
*codec
= rtd
->codec
;
1174 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1175 unsigned long long t0
, t1
, t_now
;
1176 unsigned int time_delta
, uthr
;
1177 int samples_out
, samples_in
, samples
;
1178 snd_pcm_sframes_t delay
= 0;
1179 unsigned long flags
;
1181 switch (dac33
->fifo_mode
) {
1182 case DAC33_FIFO_BYPASS
:
1184 case DAC33_FIFO_MODE1
:
1185 spin_lock_irqsave(&dac33
->lock
, flags
);
1186 t0
= dac33
->t_stamp1
;
1187 t1
= dac33
->t_stamp2
;
1188 spin_unlock_irqrestore(&dac33
->lock
, flags
);
1189 t_now
= ktime_to_us(ktime_get());
1191 /* We have not started to fill the FIFO yet, delay is 0 */
1198 * After Alarm threshold, and before nSample write
1200 time_delta
= t_now
- t0
;
1201 samples_out
= time_delta
? US_TO_SAMPLES(
1202 substream
->runtime
->rate
,
1205 if (likely(dac33
->alarm_threshold
> samples_out
))
1206 delay
= dac33
->alarm_threshold
- samples_out
;
1209 } else if ((t_now
- t1
) <= dac33
->mode1_us_burst
) {
1212 * After nSample write (during burst operation)
1214 time_delta
= t_now
- t0
;
1215 samples_out
= time_delta
? US_TO_SAMPLES(
1216 substream
->runtime
->rate
,
1219 time_delta
= t_now
- t1
;
1220 samples_in
= time_delta
? US_TO_SAMPLES(
1224 samples
= dac33
->alarm_threshold
;
1225 samples
+= (samples_in
- samples_out
);
1227 if (likely(samples
> 0))
1234 * After burst operation, before next alarm threshold
1236 time_delta
= t_now
- t0
;
1237 samples_out
= time_delta
? US_TO_SAMPLES(
1238 substream
->runtime
->rate
,
1241 samples_in
= dac33
->nsample
;
1242 samples
= dac33
->alarm_threshold
;
1243 samples
+= (samples_in
- samples_out
);
1245 if (likely(samples
> 0))
1246 delay
= samples
> dac33
->fifo_size
?
1247 dac33
->fifo_size
: samples
;
1252 case DAC33_FIFO_MODE7
:
1253 spin_lock_irqsave(&dac33
->lock
, flags
);
1254 t0
= dac33
->t_stamp1
;
1256 spin_unlock_irqrestore(&dac33
->lock
, flags
);
1257 t_now
= ktime_to_us(ktime_get());
1259 /* We have not started to fill the FIFO yet, delay is 0 */
1265 * Either the timestamps are messed or equal. Report
1272 time_delta
= t_now
- t0
;
1273 if (time_delta
<= dac33
->mode7_us_to_lthr
) {
1276 * After burst (draining phase)
1278 samples_out
= US_TO_SAMPLES(
1279 substream
->runtime
->rate
,
1282 if (likely(uthr
> samples_out
))
1283 delay
= uthr
- samples_out
;
1289 * During burst operation
1291 time_delta
= time_delta
- dac33
->mode7_us_to_lthr
;
1293 samples_out
= US_TO_SAMPLES(
1294 substream
->runtime
->rate
,
1296 samples_in
= US_TO_SAMPLES(
1299 delay
= DAC33_MODE7_MARGIN
+ samples_in
- samples_out
;
1301 if (unlikely(delay
> uthr
))
1306 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
1314 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1315 int clk_id
, unsigned int freq
, int dir
)
1317 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1318 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1319 u8 ioc_reg
, asrcb_reg
;
1321 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
1322 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
1324 case TLV320DAC33_MCLK
:
1325 ioc_reg
|= DAC33_REFSEL
;
1326 asrcb_reg
|= DAC33_SRCREFSEL
;
1328 case TLV320DAC33_SLEEPCLK
:
1329 ioc_reg
&= ~DAC33_REFSEL
;
1330 asrcb_reg
&= ~DAC33_SRCREFSEL
;
1333 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
1336 dac33
->refclk
= freq
;
1338 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1339 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1344 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1347 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1348 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1349 u8 aictrl_a
, aictrl_b
;
1351 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1352 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1353 /* set master/slave audio interface */
1354 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1355 case SND_SOC_DAIFMT_CBM_CFM
:
1357 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1359 case SND_SOC_DAIFMT_CBS_CFS
:
1361 if (dac33
->fifo_mode
) {
1362 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1365 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1371 aictrl_a
&= ~DAC33_AFMT_MASK
;
1372 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1373 case SND_SOC_DAIFMT_I2S
:
1374 aictrl_a
|= DAC33_AFMT_I2S
;
1376 case SND_SOC_DAIFMT_DSP_A
:
1377 aictrl_a
|= DAC33_AFMT_DSP
;
1378 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1379 aictrl_b
|= DAC33_DATA_DELAY(0);
1381 case SND_SOC_DAIFMT_RIGHT_J
:
1382 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1384 case SND_SOC_DAIFMT_LEFT_J
:
1385 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1388 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1389 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1393 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1394 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1399 static int dac33_soc_probe(struct snd_soc_codec
*codec
)
1401 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1404 codec
->control_data
= dac33
->control_data
;
1405 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1406 codec
->dapm
.idle_bias_off
= 1;
1407 dac33
->codec
= codec
;
1409 /* Read the tlv320dac33 ID registers */
1410 ret
= dac33_hard_power(codec
, 1);
1412 dev_err(codec
->dev
, "Failed to power up codec: %d\n", ret
);
1415 ret
= dac33_read_id(codec
);
1416 dac33_hard_power(codec
, 0);
1419 dev_err(codec
->dev
, "Failed to read chip ID: %d\n", ret
);
1424 /* Check if the IRQ number is valid and request it */
1425 if (dac33
->irq
>= 0) {
1426 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1427 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1428 codec
->name
, codec
);
1430 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1434 if (dac33
->irq
!= -1) {
1435 /* Setup work queue */
1437 create_singlethread_workqueue("tlv320dac33");
1438 if (dac33
->dac33_wq
== NULL
) {
1439 free_irq(dac33
->irq
, codec
);
1443 INIT_WORK(&dac33
->work
, dac33_work
);
1447 snd_soc_add_controls(codec
, dac33_snd_controls
,
1448 ARRAY_SIZE(dac33_snd_controls
));
1449 /* Only add the FIFO controls, if we have valid IRQ number */
1450 if (dac33
->irq
>= 0)
1451 snd_soc_add_controls(codec
, dac33_mode_snd_controls
,
1452 ARRAY_SIZE(dac33_mode_snd_controls
));
1454 dac33_add_widgets(codec
);
1460 static int dac33_soc_remove(struct snd_soc_codec
*codec
)
1462 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1464 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1466 if (dac33
->irq
>= 0) {
1467 free_irq(dac33
->irq
, dac33
->codec
);
1468 destroy_workqueue(dac33
->dac33_wq
);
1473 static int dac33_soc_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1475 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1480 static int dac33_soc_resume(struct snd_soc_codec
*codec
)
1482 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1487 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33
= {
1488 .read
= dac33_read_reg_cache
,
1489 .write
= dac33_write_locked
,
1490 .set_bias_level
= dac33_set_bias_level
,
1491 .reg_cache_size
= ARRAY_SIZE(dac33_reg
),
1492 .reg_word_size
= sizeof(u8
),
1493 .reg_cache_default
= dac33_reg
,
1494 .probe
= dac33_soc_probe
,
1495 .remove
= dac33_soc_remove
,
1496 .suspend
= dac33_soc_suspend
,
1497 .resume
= dac33_soc_resume
,
1500 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1501 SNDRV_PCM_RATE_48000)
1502 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1504 static struct snd_soc_dai_ops dac33_dai_ops
= {
1505 .startup
= dac33_startup
,
1506 .shutdown
= dac33_shutdown
,
1507 .hw_params
= dac33_hw_params
,
1508 .trigger
= dac33_pcm_trigger
,
1509 .delay
= dac33_dai_delay
,
1510 .set_sysclk
= dac33_set_dai_sysclk
,
1511 .set_fmt
= dac33_set_dai_fmt
,
1514 static struct snd_soc_dai_driver dac33_dai
= {
1515 .name
= "tlv320dac33-hifi",
1517 .stream_name
= "Playback",
1520 .rates
= DAC33_RATES
,
1521 .formats
= DAC33_FORMATS
,},
1522 .ops
= &dac33_dai_ops
,
1525 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1526 const struct i2c_device_id
*id
)
1528 struct tlv320dac33_platform_data
*pdata
;
1529 struct tlv320dac33_priv
*dac33
;
1532 if (client
->dev
.platform_data
== NULL
) {
1533 dev_err(&client
->dev
, "Platform data not set\n");
1536 pdata
= client
->dev
.platform_data
;
1538 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1542 dac33
->control_data
= client
;
1543 mutex_init(&dac33
->mutex
);
1544 spin_lock_init(&dac33
->lock
);
1546 i2c_set_clientdata(client
, dac33
);
1548 dac33
->power_gpio
= pdata
->power_gpio
;
1549 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1550 dac33
->keep_bclk
= pdata
->keep_bclk
;
1551 dac33
->mode1_latency
= pdata
->mode1_latency
;
1552 if (!dac33
->mode1_latency
)
1553 dac33
->mode1_latency
= 10000; /* 10ms */
1554 dac33
->irq
= client
->irq
;
1555 /* Disable FIFO use by default */
1556 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1558 /* Check if the reset GPIO number is valid and request it */
1559 if (dac33
->power_gpio
>= 0) {
1560 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1562 dev_err(&client
->dev
,
1563 "Failed to request reset GPIO (%d)\n",
1567 gpio_direction_output(dac33
->power_gpio
, 0);
1570 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1571 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1573 ret
= regulator_bulk_get(&client
->dev
, ARRAY_SIZE(dac33
->supplies
),
1577 dev_err(&client
->dev
, "Failed to request supplies: %d\n", ret
);
1581 ret
= snd_soc_register_codec(&client
->dev
,
1582 &soc_codec_dev_tlv320dac33
, &dac33_dai
, 1);
1588 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1590 if (dac33
->power_gpio
>= 0)
1591 gpio_free(dac33
->power_gpio
);
1597 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1599 struct tlv320dac33_priv
*dac33
= i2c_get_clientdata(client
);
1601 if (unlikely(dac33
->chip_power
))
1602 dac33_hard_power(dac33
->codec
, 0);
1604 if (dac33
->power_gpio
>= 0)
1605 gpio_free(dac33
->power_gpio
);
1607 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1609 snd_soc_unregister_codec(&client
->dev
);
1615 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1617 .name
= "tlv320dac33",
1623 static struct i2c_driver tlv320dac33_i2c_driver
= {
1625 .name
= "tlv320dac33-codec",
1626 .owner
= THIS_MODULE
,
1628 .probe
= dac33_i2c_probe
,
1629 .remove
= __devexit_p(dac33_i2c_remove
),
1630 .id_table
= tlv320dac33_i2c_id
,
1633 static int __init
dac33_module_init(void)
1636 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1638 printk(KERN_ERR
"DAC33: driver registration failed\n");
1643 module_init(dac33_module_init
);
1645 static void __exit
dac33_module_exit(void)
1647 i2c_del_driver(&tlv320dac33_i2c_driver
);
1649 module_exit(dac33_module_exit
);
1652 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1653 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1654 MODULE_LICENSE("GPL");