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ASoC: tlv320dac33: Support for turning off the codec
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
1 /*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/soc-dapm.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
44
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49 #define NSAMPLE_MAX 5700
50
51 #define LATENCY_TIME_MS 20
52
53 #define MODE7_LTHR 10
54 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
56 #define BURST_BASEFREQ_HZ 49152000
57
58 #define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61 #define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64 static void dac33_calculate_times(struct snd_pcm_substream *substream);
65 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
66
67 static struct snd_soc_codec *tlv320dac33_codec;
68
69 enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74 };
75
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
79 DAC33_FIFO_MODE7,
80 DAC33_FIFO_LAST_MODE,
81 };
82
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88 };
89
90 struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
104 * this */
105 unsigned int nsample_max; /* nsample should not be higher than
106 * this */
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
108 unsigned int nsample; /* burst read amount from host */
109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
110 unsigned int burst_rate; /* Interface speed in Burst modes */
111
112 int keep_bclk; /* Keep the BCLK continuously running
113 * in FIFO modes */
114 spinlock_t lock;
115 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
116 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
117
118 unsigned int mode1_us_burst; /* Time to burst read n number of
119 * samples */
120 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
121
122 enum dac33_state state;
123 };
124
125 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
126 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
127 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
128 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
129 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
130 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
131 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
132 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
133 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
134 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
135 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
136 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
137 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
138 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
139 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
140 0x00, 0x00, /* 0x38 - 0x39 */
141 /* Registers 0x3a - 0x3f are reserved */
142 0x00, 0x00, /* 0x3a - 0x3b */
143 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
144
145 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
146 0x00, 0x80, /* 0x44 - 0x45 */
147 /* Registers 0x46 - 0x47 are reserved */
148 0x80, 0x80, /* 0x46 - 0x47 */
149
150 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
151 /* Registers 0x4b - 0x7c are reserved */
152 0x00, /* 0x4b */
153 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
154 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
155 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
156 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
157 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
158 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
159 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
160 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
161 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
162 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
163 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
164 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
165 0x00, /* 0x7c */
166
167 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
168 };
169
170 /* Register read and write */
171 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
172 unsigned reg)
173 {
174 u8 *cache = codec->reg_cache;
175 if (reg >= DAC33_CACHEREGNUM)
176 return 0;
177
178 return cache[reg];
179 }
180
181 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
182 u8 reg, u8 value)
183 {
184 u8 *cache = codec->reg_cache;
185 if (reg >= DAC33_CACHEREGNUM)
186 return;
187
188 cache[reg] = value;
189 }
190
191 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
192 u8 *value)
193 {
194 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
195 int val;
196
197 *value = reg & 0xff;
198
199 /* If powered off, return the cached value */
200 if (dac33->chip_power) {
201 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
202 if (val < 0) {
203 dev_err(codec->dev, "Read failed (%d)\n", val);
204 value[0] = dac33_read_reg_cache(codec, reg);
205 } else {
206 value[0] = val;
207 dac33_write_reg_cache(codec, reg, val);
208 }
209 } else {
210 value[0] = dac33_read_reg_cache(codec, reg);
211 }
212
213 return 0;
214 }
215
216 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
217 unsigned int value)
218 {
219 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
220 u8 data[2];
221 int ret = 0;
222
223 /*
224 * data is
225 * D15..D8 dac33 register offset
226 * D7...D0 register data
227 */
228 data[0] = reg & 0xff;
229 data[1] = value & 0xff;
230
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 if (dac33->chip_power) {
233 ret = codec->hw_write(codec->control_data, data, 2);
234 if (ret != 2)
235 dev_err(codec->dev, "Write failed (%d)\n", ret);
236 else
237 ret = 0;
238 }
239
240 return ret;
241 }
242
243 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
244 unsigned int value)
245 {
246 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
247 int ret;
248
249 mutex_lock(&dac33->mutex);
250 ret = dac33_write(codec, reg, value);
251 mutex_unlock(&dac33->mutex);
252
253 return ret;
254 }
255
256 #define DAC33_I2C_ADDR_AUTOINC 0x80
257 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
258 unsigned int value)
259 {
260 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
261 u8 data[3];
262 int ret = 0;
263
264 /*
265 * data is
266 * D23..D16 dac33 register offset
267 * D15..D8 register data MSB
268 * D7...D0 register data LSB
269 */
270 data[0] = reg & 0xff;
271 data[1] = (value >> 8) & 0xff;
272 data[2] = value & 0xff;
273
274 dac33_write_reg_cache(codec, data[0], data[1]);
275 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
276
277 if (dac33->chip_power) {
278 /* We need to set autoincrement mode for 16 bit writes */
279 data[0] |= DAC33_I2C_ADDR_AUTOINC;
280 ret = codec->hw_write(codec->control_data, data, 3);
281 if (ret != 3)
282 dev_err(codec->dev, "Write failed (%d)\n", ret);
283 else
284 ret = 0;
285 }
286
287 return ret;
288 }
289
290 static void dac33_init_chip(struct snd_soc_codec *codec)
291 {
292 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
293
294 if (unlikely(!dac33->chip_power))
295 return;
296
297 /* 44-46: DAC Control Registers */
298 /* A : DAC sample rate Fsref/1.5 */
299 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
300 /* B : DAC src=normal, not muted */
301 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
302 DAC33_DACSRCL_LEFT);
303 /* C : (defaults) */
304 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
305
306 /* 64-65 : L&R DAC power control
307 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
308 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
309 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
310
311 /* 73 : volume soft stepping control,
312 clock source = internal osc (?) */
313 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
314
315 /* 66 : LOP/LOM Modes */
316 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
317
318 /* 68 : LOM inverted from LOP */
319 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
320
321 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
322
323 /* Restore only selected registers (gains mostly) */
324 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
325 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
326 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
327 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
328
329 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
330 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
331 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
332 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
333 }
334
335 static inline void dac33_read_id(struct snd_soc_codec *codec)
336 {
337 u8 reg;
338
339 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
340 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
341 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
342 }
343
344 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
345 {
346 u8 reg;
347
348 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
349 if (power)
350 reg |= DAC33_PDNALLB;
351 else
352 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
353 DAC33_DACRPDNB | DAC33_DACLPDNB);
354 dac33_write(codec, DAC33_PWR_CTRL, reg);
355 }
356
357 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
358 {
359 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
360 int ret = 0;
361
362 mutex_lock(&dac33->mutex);
363
364 /* Safety check */
365 if (unlikely(power == dac33->chip_power)) {
366 dev_warn(codec->dev, "Trying to set the same power state: %s\n",
367 power ? "ON" : "OFF");
368 goto exit;
369 }
370
371 if (power) {
372 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
373 dac33->supplies);
374 if (ret != 0) {
375 dev_err(codec->dev,
376 "Failed to enable supplies: %d\n", ret);
377 goto exit;
378 }
379
380 if (dac33->power_gpio >= 0)
381 gpio_set_value(dac33->power_gpio, 1);
382
383 dac33->chip_power = 1;
384 } else {
385 dac33_soft_power(codec, 0);
386 if (dac33->power_gpio >= 0)
387 gpio_set_value(dac33->power_gpio, 0);
388
389 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
390 dac33->supplies);
391 if (ret != 0) {
392 dev_err(codec->dev,
393 "Failed to disable supplies: %d\n", ret);
394 goto exit;
395 }
396
397 dac33->chip_power = 0;
398 }
399
400 exit:
401 mutex_unlock(&dac33->mutex);
402 return ret;
403 }
404
405 static int playback_event(struct snd_soc_dapm_widget *w,
406 struct snd_kcontrol *kcontrol, int event)
407 {
408 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
409
410 switch (event) {
411 case SND_SOC_DAPM_PRE_PMU:
412 if (likely(dac33->substream)) {
413 dac33_calculate_times(dac33->substream);
414 dac33_prepare_chip(dac33->substream);
415 }
416 break;
417 }
418 return 0;
419 }
420
421 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423 {
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
426
427 ucontrol->value.integer.value[0] = dac33->nsample;
428
429 return 0;
430 }
431
432 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
433 struct snd_ctl_elem_value *ucontrol)
434 {
435 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
436 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
437 int ret = 0;
438
439 if (dac33->nsample == ucontrol->value.integer.value[0])
440 return 0;
441
442 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
443 ucontrol->value.integer.value[0] > dac33->nsample_max) {
444 ret = -EINVAL;
445 } else {
446 dac33->nsample = ucontrol->value.integer.value[0];
447 /* Re calculate the burst time */
448 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
449 dac33->nsample);
450 }
451
452 return ret;
453 }
454
455 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
457 {
458 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
459 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
460
461 ucontrol->value.integer.value[0] = dac33->fifo_mode;
462
463 return 0;
464 }
465
466 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_value *ucontrol)
468 {
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
470 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
471 int ret = 0;
472
473 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
474 return 0;
475 /* Do not allow changes while stream is running*/
476 if (codec->active)
477 return -EPERM;
478
479 if (ucontrol->value.integer.value[0] < 0 ||
480 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
481 ret = -EINVAL;
482 else
483 dac33->fifo_mode = ucontrol->value.integer.value[0];
484
485 return ret;
486 }
487
488 /* Codec operation modes */
489 static const char *dac33_fifo_mode_texts[] = {
490 "Bypass", "Mode 1", "Mode 7"
491 };
492
493 static const struct soc_enum dac33_fifo_mode_enum =
494 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
495 dac33_fifo_mode_texts);
496
497 /*
498 * DACL/R digital volume control:
499 * from 0 dB to -63.5 in 0.5 dB steps
500 * Need to be inverted later on:
501 * 0x00 == 0 dB
502 * 0x7f == -63.5 dB
503 */
504 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
505
506 static const struct snd_kcontrol_new dac33_snd_controls[] = {
507 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
508 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
509 0, 0x7f, 1, dac_digivol_tlv),
510 SOC_DOUBLE_R("DAC Digital Playback Switch",
511 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
512 SOC_DOUBLE_R("Line to Line Out Volume",
513 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
514 };
515
516 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
517 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
518 dac33_get_nsample, dac33_set_nsample),
519 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
520 dac33_get_fifo_mode, dac33_set_fifo_mode),
521 };
522
523 /* Analog bypass */
524 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
525 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
526
527 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
528 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
529
530 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
531 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
532 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
533
534 SND_SOC_DAPM_INPUT("LINEL"),
535 SND_SOC_DAPM_INPUT("LINER"),
536
537 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
538 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
539
540 /* Analog bypass */
541 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
542 &dac33_dapm_abypassl_control),
543 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
544 &dac33_dapm_abypassr_control),
545
546 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
547 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
548 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
549 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
550
551 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
552 };
553
554 static const struct snd_soc_dapm_route audio_map[] = {
555 /* Analog bypass */
556 {"Analog Left Bypass", "Switch", "LINEL"},
557 {"Analog Right Bypass", "Switch", "LINER"},
558
559 {"Output Left Amp Power", NULL, "DACL"},
560 {"Output Right Amp Power", NULL, "DACR"},
561
562 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
563 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
564
565 /* output */
566 {"LEFT_LO", NULL, "Output Left Amp Power"},
567 {"RIGHT_LO", NULL, "Output Right Amp Power"},
568 };
569
570 static int dac33_add_widgets(struct snd_soc_codec *codec)
571 {
572 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
573 ARRAY_SIZE(dac33_dapm_widgets));
574
575 /* set up audio path interconnects */
576 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
577
578 return 0;
579 }
580
581 static int dac33_set_bias_level(struct snd_soc_codec *codec,
582 enum snd_soc_bias_level level)
583 {
584 int ret;
585
586 switch (level) {
587 case SND_SOC_BIAS_ON:
588 dac33_soft_power(codec, 1);
589 break;
590 case SND_SOC_BIAS_PREPARE:
591 break;
592 case SND_SOC_BIAS_STANDBY:
593 if (codec->bias_level == SND_SOC_BIAS_OFF) {
594 /* Coming from OFF, switch on the codec */
595 ret = dac33_hard_power(codec, 1);
596 if (ret != 0)
597 return ret;
598
599 dac33_init_chip(codec);
600 }
601 break;
602 case SND_SOC_BIAS_OFF:
603 ret = dac33_hard_power(codec, 0);
604 if (ret != 0)
605 return ret;
606 break;
607 }
608 codec->bias_level = level;
609
610 return 0;
611 }
612
613 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
614 {
615 struct snd_soc_codec *codec;
616
617 codec = &dac33->codec;
618
619 switch (dac33->fifo_mode) {
620 case DAC33_FIFO_MODE1:
621 dac33_write16(codec, DAC33_NSAMPLE_MSB,
622 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
623
624 /* Take the timestamps */
625 spin_lock_irq(&dac33->lock);
626 dac33->t_stamp2 = ktime_to_us(ktime_get());
627 dac33->t_stamp1 = dac33->t_stamp2;
628 spin_unlock_irq(&dac33->lock);
629
630 dac33_write16(codec, DAC33_PREFILL_MSB,
631 DAC33_THRREG(dac33->alarm_threshold));
632 /* Enable Alarm Threshold IRQ with a delay */
633 udelay(SAMPLES_TO_US(dac33->burst_rate,
634 dac33->alarm_threshold));
635 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
636 break;
637 case DAC33_FIFO_MODE7:
638 /* Take the timestamp */
639 spin_lock_irq(&dac33->lock);
640 dac33->t_stamp1 = ktime_to_us(ktime_get());
641 /* Move back the timestamp with drain time */
642 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
643 spin_unlock_irq(&dac33->lock);
644
645 dac33_write16(codec, DAC33_PREFILL_MSB,
646 DAC33_THRREG(MODE7_LTHR));
647
648 /* Enable Upper Threshold IRQ */
649 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
650 break;
651 default:
652 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
653 dac33->fifo_mode);
654 break;
655 }
656 }
657
658 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
659 {
660 struct snd_soc_codec *codec;
661
662 codec = &dac33->codec;
663
664 switch (dac33->fifo_mode) {
665 case DAC33_FIFO_MODE1:
666 /* Take the timestamp */
667 spin_lock_irq(&dac33->lock);
668 dac33->t_stamp2 = ktime_to_us(ktime_get());
669 spin_unlock_irq(&dac33->lock);
670
671 dac33_write16(codec, DAC33_NSAMPLE_MSB,
672 DAC33_THRREG(dac33->nsample));
673 break;
674 case DAC33_FIFO_MODE7:
675 /* At the moment we are not using interrupts in mode7 */
676 break;
677 default:
678 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
679 dac33->fifo_mode);
680 break;
681 }
682 }
683
684 static void dac33_work(struct work_struct *work)
685 {
686 struct snd_soc_codec *codec;
687 struct tlv320dac33_priv *dac33;
688 u8 reg;
689
690 dac33 = container_of(work, struct tlv320dac33_priv, work);
691 codec = &dac33->codec;
692
693 mutex_lock(&dac33->mutex);
694 switch (dac33->state) {
695 case DAC33_PREFILL:
696 dac33->state = DAC33_PLAYBACK;
697 dac33_prefill_handler(dac33);
698 break;
699 case DAC33_PLAYBACK:
700 dac33_playback_handler(dac33);
701 break;
702 case DAC33_IDLE:
703 break;
704 case DAC33_FLUSH:
705 dac33->state = DAC33_IDLE;
706 /* Mask all interrupts from dac33 */
707 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
708
709 /* flush fifo */
710 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
711 reg |= DAC33_FIFOFLUSH;
712 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
713 break;
714 }
715 mutex_unlock(&dac33->mutex);
716 }
717
718 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
719 {
720 struct snd_soc_codec *codec = dev;
721 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
722
723 spin_lock(&dac33->lock);
724 dac33->t_stamp1 = ktime_to_us(ktime_get());
725 spin_unlock(&dac33->lock);
726
727 /* Do not schedule the workqueue in Mode7 */
728 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
729 queue_work(dac33->dac33_wq, &dac33->work);
730
731 return IRQ_HANDLED;
732 }
733
734 static void dac33_oscwait(struct snd_soc_codec *codec)
735 {
736 int timeout = 20;
737 u8 reg;
738
739 do {
740 msleep(1);
741 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
742 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
743 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
744 dev_err(codec->dev,
745 "internal oscillator calibration failed\n");
746 }
747
748 static int dac33_startup(struct snd_pcm_substream *substream,
749 struct snd_soc_dai *dai)
750 {
751 struct snd_soc_pcm_runtime *rtd = substream->private_data;
752 struct snd_soc_device *socdev = rtd->socdev;
753 struct snd_soc_codec *codec = socdev->card->codec;
754 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
755
756 /* Stream started, save the substream pointer */
757 dac33->substream = substream;
758
759 return 0;
760 }
761
762 static void dac33_shutdown(struct snd_pcm_substream *substream,
763 struct snd_soc_dai *dai)
764 {
765 struct snd_soc_pcm_runtime *rtd = substream->private_data;
766 struct snd_soc_device *socdev = rtd->socdev;
767 struct snd_soc_codec *codec = socdev->card->codec;
768 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
769
770 dac33->substream = NULL;
771 }
772
773 static int dac33_hw_params(struct snd_pcm_substream *substream,
774 struct snd_pcm_hw_params *params,
775 struct snd_soc_dai *dai)
776 {
777 struct snd_soc_pcm_runtime *rtd = substream->private_data;
778 struct snd_soc_device *socdev = rtd->socdev;
779 struct snd_soc_codec *codec = socdev->card->codec;
780
781 /* Check parameters for validity */
782 switch (params_rate(params)) {
783 case 44100:
784 case 48000:
785 break;
786 default:
787 dev_err(codec->dev, "unsupported rate %d\n",
788 params_rate(params));
789 return -EINVAL;
790 }
791
792 switch (params_format(params)) {
793 case SNDRV_PCM_FORMAT_S16_LE:
794 break;
795 default:
796 dev_err(codec->dev, "unsupported format %d\n",
797 params_format(params));
798 return -EINVAL;
799 }
800
801 return 0;
802 }
803
804 #define CALC_OSCSET(rate, refclk) ( \
805 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
806 #define CALC_RATIOSET(rate, refclk) ( \
807 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
808
809 /*
810 * tlv320dac33 is strict on the sequence of the register writes, if the register
811 * writes happens in different order, than dac33 might end up in unknown state.
812 * Use the known, working sequence of register writes to initialize the dac33.
813 */
814 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
815 {
816 struct snd_soc_pcm_runtime *rtd = substream->private_data;
817 struct snd_soc_device *socdev = rtd->socdev;
818 struct snd_soc_codec *codec = socdev->card->codec;
819 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
820 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
821 u8 aictrl_a, aictrl_b, fifoctrl_a;
822
823 switch (substream->runtime->rate) {
824 case 44100:
825 case 48000:
826 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
827 ratioset = CALC_RATIOSET(substream->runtime->rate,
828 dac33->refclk);
829 break;
830 default:
831 dev_err(codec->dev, "unsupported rate %d\n",
832 substream->runtime->rate);
833 return -EINVAL;
834 }
835
836
837 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
838 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
839 /* Read FIFO control A, and clear FIFO flush bit */
840 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
841 fifoctrl_a &= ~DAC33_FIFOFLUSH;
842
843 fifoctrl_a &= ~DAC33_WIDTH;
844 switch (substream->runtime->format) {
845 case SNDRV_PCM_FORMAT_S16_LE:
846 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
847 fifoctrl_a |= DAC33_WIDTH;
848 break;
849 default:
850 dev_err(codec->dev, "unsupported format %d\n",
851 substream->runtime->format);
852 return -EINVAL;
853 }
854
855 mutex_lock(&dac33->mutex);
856
857 if (!dac33->chip_power) {
858 /*
859 * Chip is not powered yet.
860 * Do the init in the dac33_set_bias_level later.
861 */
862 mutex_unlock(&dac33->mutex);
863 return 0;
864 }
865
866 dac33_soft_power(codec, 0);
867 dac33_soft_power(codec, 1);
868
869 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
870 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
871
872 /* Write registers 0x08 and 0x09 (MSB, LSB) */
873 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
874
875 /* calib time: 128 is a nice number ;) */
876 dac33_write(codec, DAC33_CALIB_TIME, 128);
877
878 /* adjustment treshold & step */
879 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
880 DAC33_ADJSTEP(1));
881
882 /* div=4 / gain=1 / div */
883 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
884
885 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
886 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
887 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
888
889 dac33_oscwait(codec);
890
891 if (dac33->fifo_mode) {
892 /* Generic for all FIFO modes */
893 /* 50-51 : ASRC Control registers */
894 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
895 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
896
897 /* Write registers 0x34 and 0x35 (MSB, LSB) */
898 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
899
900 /* Set interrupts to high active */
901 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
902 } else {
903 /* FIFO bypass mode */
904 /* 50-51 : ASRC Control registers */
905 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
906 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
907 }
908
909 /* Interrupt behaviour configuration */
910 switch (dac33->fifo_mode) {
911 case DAC33_FIFO_MODE1:
912 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
913 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
914 break;
915 case DAC33_FIFO_MODE7:
916 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
917 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
918 break;
919 default:
920 /* in FIFO bypass mode, the interrupts are not used */
921 break;
922 }
923
924 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
925
926 switch (dac33->fifo_mode) {
927 case DAC33_FIFO_MODE1:
928 /*
929 * For mode1:
930 * Disable the FIFO bypass (Enable the use of FIFO)
931 * Select nSample mode
932 * BCLK is only running when data is needed by DAC33
933 */
934 fifoctrl_a &= ~DAC33_FBYPAS;
935 fifoctrl_a &= ~DAC33_FAUTO;
936 if (dac33->keep_bclk)
937 aictrl_b |= DAC33_BCLKON;
938 else
939 aictrl_b &= ~DAC33_BCLKON;
940 break;
941 case DAC33_FIFO_MODE7:
942 /*
943 * For mode1:
944 * Disable the FIFO bypass (Enable the use of FIFO)
945 * Select Threshold mode
946 * BCLK is only running when data is needed by DAC33
947 */
948 fifoctrl_a &= ~DAC33_FBYPAS;
949 fifoctrl_a |= DAC33_FAUTO;
950 if (dac33->keep_bclk)
951 aictrl_b |= DAC33_BCLKON;
952 else
953 aictrl_b &= ~DAC33_BCLKON;
954 break;
955 default:
956 /*
957 * For FIFO bypass mode:
958 * Enable the FIFO bypass (Disable the FIFO use)
959 * Set the BCLK as continous
960 */
961 fifoctrl_a |= DAC33_FBYPAS;
962 aictrl_b |= DAC33_BCLKON;
963 break;
964 }
965
966 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
967 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
968 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
969
970 /*
971 * BCLK divide ratio
972 * 0: 1.5
973 * 1: 1
974 * 2: 2
975 * ...
976 * 254: 254
977 * 255: 255
978 */
979 if (dac33->fifo_mode)
980 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
981 dac33->burst_bclkdiv);
982 else
983 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
984
985 switch (dac33->fifo_mode) {
986 case DAC33_FIFO_MODE1:
987 dac33_write16(codec, DAC33_ATHR_MSB,
988 DAC33_THRREG(dac33->alarm_threshold));
989 break;
990 case DAC33_FIFO_MODE7:
991 /*
992 * Configure the threshold levels, and leave 10 sample space
993 * at the bottom, and also at the top of the FIFO
994 */
995 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
996 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
997 break;
998 default:
999 break;
1000 }
1001
1002 mutex_unlock(&dac33->mutex);
1003
1004 return 0;
1005 }
1006
1007 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1008 {
1009 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1010 struct snd_soc_device *socdev = rtd->socdev;
1011 struct snd_soc_codec *codec = socdev->card->codec;
1012 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1013 unsigned int nsample_limit;
1014
1015 /* In bypass mode we don't need to calculate */
1016 if (!dac33->fifo_mode)
1017 return;
1018
1019 /* Number of samples (16bit, stereo) in one period */
1020 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1021
1022 /* Number of samples (16bit, stereo) in ALSA buffer */
1023 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1024 /* Subtract one period from the total */
1025 dac33->nsample_max -= dac33->nsample_min;
1026
1027 /* Number of samples for LATENCY_TIME_MS / 2 */
1028 dac33->alarm_threshold = substream->runtime->rate /
1029 (1000 / (LATENCY_TIME_MS / 2));
1030
1031 /* Find and fix up the lowest nsmaple limit */
1032 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1033
1034 if (dac33->nsample_min < nsample_limit)
1035 dac33->nsample_min = nsample_limit;
1036
1037 if (dac33->nsample < dac33->nsample_min)
1038 dac33->nsample = dac33->nsample_min;
1039
1040 /*
1041 * Find and fix up the highest nsmaple limit
1042 * In order to not overflow the DAC33 buffer substract the
1043 * alarm_threshold value from the size of the DAC33 buffer
1044 */
1045 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1046
1047 if (dac33->nsample_max > nsample_limit)
1048 dac33->nsample_max = nsample_limit;
1049
1050 if (dac33->nsample > dac33->nsample_max)
1051 dac33->nsample = dac33->nsample_max;
1052
1053 switch (dac33->fifo_mode) {
1054 case DAC33_FIFO_MODE1:
1055 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1056 dac33->nsample);
1057 dac33->t_stamp1 = 0;
1058 dac33->t_stamp2 = 0;
1059 break;
1060 case DAC33_FIFO_MODE7:
1061 dac33->mode7_us_to_lthr =
1062 SAMPLES_TO_US(substream->runtime->rate,
1063 MODE7_UTHR - MODE7_LTHR + 1);
1064 dac33->t_stamp1 = 0;
1065 break;
1066 default:
1067 break;
1068 }
1069
1070 }
1071
1072 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1073 struct snd_soc_dai *dai)
1074 {
1075 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1076 struct snd_soc_device *socdev = rtd->socdev;
1077 struct snd_soc_codec *codec = socdev->card->codec;
1078 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1079 int ret = 0;
1080
1081 switch (cmd) {
1082 case SNDRV_PCM_TRIGGER_START:
1083 case SNDRV_PCM_TRIGGER_RESUME:
1084 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1085 if (dac33->fifo_mode) {
1086 dac33->state = DAC33_PREFILL;
1087 queue_work(dac33->dac33_wq, &dac33->work);
1088 }
1089 break;
1090 case SNDRV_PCM_TRIGGER_STOP:
1091 case SNDRV_PCM_TRIGGER_SUSPEND:
1092 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1093 if (dac33->fifo_mode) {
1094 dac33->state = DAC33_FLUSH;
1095 queue_work(dac33->dac33_wq, &dac33->work);
1096 }
1097 break;
1098 default:
1099 ret = -EINVAL;
1100 }
1101
1102 return ret;
1103 }
1104
1105 static snd_pcm_sframes_t dac33_dai_delay(
1106 struct snd_pcm_substream *substream,
1107 struct snd_soc_dai *dai)
1108 {
1109 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1110 struct snd_soc_device *socdev = rtd->socdev;
1111 struct snd_soc_codec *codec = socdev->card->codec;
1112 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1113 unsigned long long t0, t1, t_now;
1114 unsigned int time_delta;
1115 int samples_out, samples_in, samples;
1116 snd_pcm_sframes_t delay = 0;
1117
1118 switch (dac33->fifo_mode) {
1119 case DAC33_FIFO_BYPASS:
1120 break;
1121 case DAC33_FIFO_MODE1:
1122 spin_lock(&dac33->lock);
1123 t0 = dac33->t_stamp1;
1124 t1 = dac33->t_stamp2;
1125 spin_unlock(&dac33->lock);
1126 t_now = ktime_to_us(ktime_get());
1127
1128 /* We have not started to fill the FIFO yet, delay is 0 */
1129 if (!t1)
1130 goto out;
1131
1132 if (t0 > t1) {
1133 /*
1134 * Phase 1:
1135 * After Alarm threshold, and before nSample write
1136 */
1137 time_delta = t_now - t0;
1138 samples_out = time_delta ? US_TO_SAMPLES(
1139 substream->runtime->rate,
1140 time_delta) : 0;
1141
1142 if (likely(dac33->alarm_threshold > samples_out))
1143 delay = dac33->alarm_threshold - samples_out;
1144 else
1145 delay = 0;
1146 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1147 /*
1148 * Phase 2:
1149 * After nSample write (during burst operation)
1150 */
1151 time_delta = t_now - t0;
1152 samples_out = time_delta ? US_TO_SAMPLES(
1153 substream->runtime->rate,
1154 time_delta) : 0;
1155
1156 time_delta = t_now - t1;
1157 samples_in = time_delta ? US_TO_SAMPLES(
1158 dac33->burst_rate,
1159 time_delta) : 0;
1160
1161 samples = dac33->alarm_threshold;
1162 samples += (samples_in - samples_out);
1163
1164 if (likely(samples > 0))
1165 delay = samples;
1166 else
1167 delay = 0;
1168 } else {
1169 /*
1170 * Phase 3:
1171 * After burst operation, before next alarm threshold
1172 */
1173 time_delta = t_now - t0;
1174 samples_out = time_delta ? US_TO_SAMPLES(
1175 substream->runtime->rate,
1176 time_delta) : 0;
1177
1178 samples_in = dac33->nsample;
1179 samples = dac33->alarm_threshold;
1180 samples += (samples_in - samples_out);
1181
1182 if (likely(samples > 0))
1183 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1184 DAC33_BUFFER_SIZE_SAMPLES : samples;
1185 else
1186 delay = 0;
1187 }
1188 break;
1189 case DAC33_FIFO_MODE7:
1190 spin_lock(&dac33->lock);
1191 t0 = dac33->t_stamp1;
1192 spin_unlock(&dac33->lock);
1193 t_now = ktime_to_us(ktime_get());
1194
1195 /* We have not started to fill the FIFO yet, delay is 0 */
1196 if (!t0)
1197 goto out;
1198
1199 if (t_now <= t0) {
1200 /*
1201 * Either the timestamps are messed or equal. Report
1202 * maximum delay
1203 */
1204 delay = MODE7_UTHR;
1205 goto out;
1206 }
1207
1208 time_delta = t_now - t0;
1209 if (time_delta <= dac33->mode7_us_to_lthr) {
1210 /*
1211 * Phase 1:
1212 * After burst (draining phase)
1213 */
1214 samples_out = US_TO_SAMPLES(
1215 substream->runtime->rate,
1216 time_delta);
1217
1218 if (likely(MODE7_UTHR > samples_out))
1219 delay = MODE7_UTHR - samples_out;
1220 else
1221 delay = 0;
1222 } else {
1223 /*
1224 * Phase 2:
1225 * During burst operation
1226 */
1227 time_delta = time_delta - dac33->mode7_us_to_lthr;
1228
1229 samples_out = US_TO_SAMPLES(
1230 substream->runtime->rate,
1231 time_delta);
1232 samples_in = US_TO_SAMPLES(
1233 dac33->burst_rate,
1234 time_delta);
1235 delay = MODE7_LTHR + samples_in - samples_out;
1236
1237 if (unlikely(delay > MODE7_UTHR))
1238 delay = MODE7_UTHR;
1239 }
1240 break;
1241 default:
1242 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1243 dac33->fifo_mode);
1244 break;
1245 }
1246 out:
1247 return delay;
1248 }
1249
1250 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1251 int clk_id, unsigned int freq, int dir)
1252 {
1253 struct snd_soc_codec *codec = codec_dai->codec;
1254 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1255 u8 ioc_reg, asrcb_reg;
1256
1257 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1258 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1259 switch (clk_id) {
1260 case TLV320DAC33_MCLK:
1261 ioc_reg |= DAC33_REFSEL;
1262 asrcb_reg |= DAC33_SRCREFSEL;
1263 break;
1264 case TLV320DAC33_SLEEPCLK:
1265 ioc_reg &= ~DAC33_REFSEL;
1266 asrcb_reg &= ~DAC33_SRCREFSEL;
1267 break;
1268 default:
1269 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1270 break;
1271 }
1272 dac33->refclk = freq;
1273
1274 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1275 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1276
1277 return 0;
1278 }
1279
1280 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1281 unsigned int fmt)
1282 {
1283 struct snd_soc_codec *codec = codec_dai->codec;
1284 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1285 u8 aictrl_a, aictrl_b;
1286
1287 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1288 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1289 /* set master/slave audio interface */
1290 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1291 case SND_SOC_DAIFMT_CBM_CFM:
1292 /* Codec Master */
1293 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1294 break;
1295 case SND_SOC_DAIFMT_CBS_CFS:
1296 /* Codec Slave */
1297 if (dac33->fifo_mode) {
1298 dev_err(codec->dev, "FIFO mode requires master mode\n");
1299 return -EINVAL;
1300 } else
1301 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1302 break;
1303 default:
1304 return -EINVAL;
1305 }
1306
1307 aictrl_a &= ~DAC33_AFMT_MASK;
1308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1309 case SND_SOC_DAIFMT_I2S:
1310 aictrl_a |= DAC33_AFMT_I2S;
1311 break;
1312 case SND_SOC_DAIFMT_DSP_A:
1313 aictrl_a |= DAC33_AFMT_DSP;
1314 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1315 aictrl_b |= DAC33_DATA_DELAY(0);
1316 break;
1317 case SND_SOC_DAIFMT_RIGHT_J:
1318 aictrl_a |= DAC33_AFMT_RIGHT_J;
1319 break;
1320 case SND_SOC_DAIFMT_LEFT_J:
1321 aictrl_a |= DAC33_AFMT_LEFT_J;
1322 break;
1323 default:
1324 dev_err(codec->dev, "Unsupported format (%u)\n",
1325 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1326 return -EINVAL;
1327 }
1328
1329 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1330 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1331
1332 return 0;
1333 }
1334
1335 static int dac33_soc_probe(struct platform_device *pdev)
1336 {
1337 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1338 struct snd_soc_codec *codec;
1339 struct tlv320dac33_priv *dac33;
1340 int ret = 0;
1341
1342 BUG_ON(!tlv320dac33_codec);
1343
1344 codec = tlv320dac33_codec;
1345 socdev->card->codec = codec;
1346 dac33 = snd_soc_codec_get_drvdata(codec);
1347
1348 /* register pcms */
1349 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1350 if (ret < 0) {
1351 dev_err(codec->dev, "failed to create pcms\n");
1352 goto pcm_err;
1353 }
1354
1355 snd_soc_add_controls(codec, dac33_snd_controls,
1356 ARRAY_SIZE(dac33_snd_controls));
1357 /* Only add the nSample controls, if we have valid IRQ number */
1358 if (dac33->irq >= 0)
1359 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1360 ARRAY_SIZE(dac33_nsample_snd_controls));
1361
1362 dac33_add_widgets(codec);
1363
1364 return 0;
1365
1366 pcm_err:
1367 dac33_hard_power(codec, 0);
1368 return ret;
1369 }
1370
1371 static int dac33_soc_remove(struct platform_device *pdev)
1372 {
1373 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1374 struct snd_soc_codec *codec = socdev->card->codec;
1375
1376 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1377
1378 snd_soc_free_pcms(socdev);
1379 snd_soc_dapm_free(socdev);
1380
1381 return 0;
1382 }
1383
1384 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1385 {
1386 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1387 struct snd_soc_codec *codec = socdev->card->codec;
1388
1389 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1390
1391 return 0;
1392 }
1393
1394 static int dac33_soc_resume(struct platform_device *pdev)
1395 {
1396 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1397 struct snd_soc_codec *codec = socdev->card->codec;
1398
1399 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1400 if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
1401 dac33_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1402 dac33_set_bias_level(codec, codec->suspend_bias_level);
1403
1404 return 0;
1405 }
1406
1407 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1408 .probe = dac33_soc_probe,
1409 .remove = dac33_soc_remove,
1410 .suspend = dac33_soc_suspend,
1411 .resume = dac33_soc_resume,
1412 };
1413 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1414
1415 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1416 SNDRV_PCM_RATE_48000)
1417 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1418
1419 static struct snd_soc_dai_ops dac33_dai_ops = {
1420 .startup = dac33_startup,
1421 .shutdown = dac33_shutdown,
1422 .hw_params = dac33_hw_params,
1423 .trigger = dac33_pcm_trigger,
1424 .delay = dac33_dai_delay,
1425 .set_sysclk = dac33_set_dai_sysclk,
1426 .set_fmt = dac33_set_dai_fmt,
1427 };
1428
1429 struct snd_soc_dai dac33_dai = {
1430 .name = "tlv320dac33",
1431 .playback = {
1432 .stream_name = "Playback",
1433 .channels_min = 2,
1434 .channels_max = 2,
1435 .rates = DAC33_RATES,
1436 .formats = DAC33_FORMATS,},
1437 .ops = &dac33_dai_ops,
1438 };
1439 EXPORT_SYMBOL_GPL(dac33_dai);
1440
1441 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1442 const struct i2c_device_id *id)
1443 {
1444 struct tlv320dac33_platform_data *pdata;
1445 struct tlv320dac33_priv *dac33;
1446 struct snd_soc_codec *codec;
1447 int ret, i;
1448
1449 if (client->dev.platform_data == NULL) {
1450 dev_err(&client->dev, "Platform data not set\n");
1451 return -ENODEV;
1452 }
1453 pdata = client->dev.platform_data;
1454
1455 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1456 if (dac33 == NULL)
1457 return -ENOMEM;
1458
1459 codec = &dac33->codec;
1460 snd_soc_codec_set_drvdata(codec, dac33);
1461 codec->control_data = client;
1462
1463 mutex_init(&codec->mutex);
1464 mutex_init(&dac33->mutex);
1465 spin_lock_init(&dac33->lock);
1466 INIT_LIST_HEAD(&codec->dapm_widgets);
1467 INIT_LIST_HEAD(&codec->dapm_paths);
1468
1469 codec->name = "tlv320dac33";
1470 codec->owner = THIS_MODULE;
1471 codec->read = dac33_read_reg_cache;
1472 codec->write = dac33_write_locked;
1473 codec->hw_write = (hw_write_t) i2c_master_send;
1474 codec->bias_level = SND_SOC_BIAS_OFF;
1475 codec->set_bias_level = dac33_set_bias_level;
1476 codec->idle_bias_off = 1;
1477 codec->dai = &dac33_dai;
1478 codec->num_dai = 1;
1479 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1480 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1481 GFP_KERNEL);
1482 if (codec->reg_cache == NULL) {
1483 ret = -ENOMEM;
1484 goto error_reg;
1485 }
1486
1487 i2c_set_clientdata(client, dac33);
1488
1489 dac33->power_gpio = pdata->power_gpio;
1490 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1491 /* Pre calculate the burst rate */
1492 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1493 dac33->keep_bclk = pdata->keep_bclk;
1494 dac33->irq = client->irq;
1495 dac33->nsample = NSAMPLE_MAX;
1496 dac33->nsample_max = NSAMPLE_MAX;
1497 /* Disable FIFO use by default */
1498 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1499
1500 tlv320dac33_codec = codec;
1501
1502 codec->dev = &client->dev;
1503 dac33_dai.dev = codec->dev;
1504
1505 /* Check if the reset GPIO number is valid and request it */
1506 if (dac33->power_gpio >= 0) {
1507 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1508 if (ret < 0) {
1509 dev_err(codec->dev,
1510 "Failed to request reset GPIO (%d)\n",
1511 dac33->power_gpio);
1512 snd_soc_unregister_dai(&dac33_dai);
1513 snd_soc_unregister_codec(codec);
1514 goto error_gpio;
1515 }
1516 gpio_direction_output(dac33->power_gpio, 0);
1517 }
1518
1519 /* Check if the IRQ number is valid and request it */
1520 if (dac33->irq >= 0) {
1521 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1522 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1523 codec->name, codec);
1524 if (ret < 0) {
1525 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1526 dac33->irq, ret);
1527 dac33->irq = -1;
1528 }
1529 if (dac33->irq != -1) {
1530 /* Setup work queue */
1531 dac33->dac33_wq =
1532 create_singlethread_workqueue("tlv320dac33");
1533 if (dac33->dac33_wq == NULL) {
1534 free_irq(dac33->irq, &dac33->codec);
1535 ret = -ENOMEM;
1536 goto error_wq;
1537 }
1538
1539 INIT_WORK(&dac33->work, dac33_work);
1540 }
1541 }
1542
1543 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1544 dac33->supplies[i].supply = dac33_supply_names[i];
1545
1546 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1547 dac33->supplies);
1548
1549 if (ret != 0) {
1550 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1551 goto err_get;
1552 }
1553
1554 /* Read the tlv320dac33 ID registers */
1555 ret = dac33_hard_power(codec, 1);
1556 if (ret != 0) {
1557 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1558 goto error_codec;
1559 }
1560 dac33_read_id(codec);
1561 dac33_hard_power(codec, 0);
1562
1563 ret = snd_soc_register_codec(codec);
1564 if (ret != 0) {
1565 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1566 goto error_codec;
1567 }
1568
1569 ret = snd_soc_register_dai(&dac33_dai);
1570 if (ret != 0) {
1571 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1572 snd_soc_unregister_codec(codec);
1573 goto error_codec;
1574 }
1575
1576 return ret;
1577
1578 error_codec:
1579 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1580 err_get:
1581 if (dac33->irq >= 0) {
1582 free_irq(dac33->irq, &dac33->codec);
1583 destroy_workqueue(dac33->dac33_wq);
1584 }
1585 error_wq:
1586 if (dac33->power_gpio >= 0)
1587 gpio_free(dac33->power_gpio);
1588 error_gpio:
1589 kfree(codec->reg_cache);
1590 error_reg:
1591 tlv320dac33_codec = NULL;
1592 kfree(dac33);
1593
1594 return ret;
1595 }
1596
1597 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1598 {
1599 struct tlv320dac33_priv *dac33;
1600
1601 dac33 = i2c_get_clientdata(client);
1602
1603 if (unlikely(dac33->chip_power))
1604 dac33_hard_power(&dac33->codec, 0);
1605
1606 if (dac33->power_gpio >= 0)
1607 gpio_free(dac33->power_gpio);
1608 if (dac33->irq >= 0)
1609 free_irq(dac33->irq, &dac33->codec);
1610
1611 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1612
1613 destroy_workqueue(dac33->dac33_wq);
1614 snd_soc_unregister_dai(&dac33_dai);
1615 snd_soc_unregister_codec(&dac33->codec);
1616 kfree(dac33->codec.reg_cache);
1617 kfree(dac33);
1618 tlv320dac33_codec = NULL;
1619
1620 return 0;
1621 }
1622
1623 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1624 {
1625 .name = "tlv320dac33",
1626 .driver_data = 0,
1627 },
1628 { },
1629 };
1630
1631 static struct i2c_driver tlv320dac33_i2c_driver = {
1632 .driver = {
1633 .name = "tlv320dac33",
1634 .owner = THIS_MODULE,
1635 },
1636 .probe = dac33_i2c_probe,
1637 .remove = __devexit_p(dac33_i2c_remove),
1638 .id_table = tlv320dac33_i2c_id,
1639 };
1640
1641 static int __init dac33_module_init(void)
1642 {
1643 int r;
1644 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1645 if (r < 0) {
1646 printk(KERN_ERR "DAC33: driver registration failed\n");
1647 return r;
1648 }
1649 return 0;
1650 }
1651 module_init(dac33_module_init);
1652
1653 static void __exit dac33_module_exit(void)
1654 {
1655 i2c_del_driver(&tlv320dac33_i2c_driver);
1656 }
1657 module_exit(dac33_module_exit);
1658
1659
1660 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1661 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1662 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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