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ASoC: twl4030: Move hs_extmute GPIO handling to driver
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl.h>
30 #include <linux/slab.h>
31 #include <linux/gpio.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/soc.h>
36 #include <sound/initval.h>
37 #include <sound/tlv.h>
38
39 /* Register descriptions are here */
40 #include <linux/mfd/twl4030-audio.h>
41
42 /* Shadow register used by the audio driver */
43 #define TWL4030_REG_SW_SHADOW 0x4A
44 #define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
45
46 /* TWL4030_REG_SW_SHADOW (0x4A) Fields */
47 #define TWL4030_HFL_EN 0x01
48 #define TWL4030_HFR_EN 0x02
49
50 /*
51 * twl4030 register cache & default register settings
52 */
53 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
54 0x00, /* this register not used */
55 0x00, /* REG_CODEC_MODE (0x1) */
56 0x00, /* REG_OPTION (0x2) */
57 0x00, /* REG_UNKNOWN (0x3) */
58 0x00, /* REG_MICBIAS_CTL (0x4) */
59 0x00, /* REG_ANAMICL (0x5) */
60 0x00, /* REG_ANAMICR (0x6) */
61 0x00, /* REG_AVADC_CTL (0x7) */
62 0x00, /* REG_ADCMICSEL (0x8) */
63 0x00, /* REG_DIGMIXING (0x9) */
64 0x0f, /* REG_ATXL1PGA (0xA) */
65 0x0f, /* REG_ATXR1PGA (0xB) */
66 0x0f, /* REG_AVTXL2PGA (0xC) */
67 0x0f, /* REG_AVTXR2PGA (0xD) */
68 0x00, /* REG_AUDIO_IF (0xE) */
69 0x00, /* REG_VOICE_IF (0xF) */
70 0x3f, /* REG_ARXR1PGA (0x10) */
71 0x3f, /* REG_ARXL1PGA (0x11) */
72 0x3f, /* REG_ARXR2PGA (0x12) */
73 0x3f, /* REG_ARXL2PGA (0x13) */
74 0x25, /* REG_VRXPGA (0x14) */
75 0x00, /* REG_VSTPGA (0x15) */
76 0x00, /* REG_VRX2ARXPGA (0x16) */
77 0x00, /* REG_AVDAC_CTL (0x17) */
78 0x00, /* REG_ARX2VTXPGA (0x18) */
79 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
80 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
81 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
82 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
83 0x00, /* REG_ATX2ARXPGA (0x1D) */
84 0x00, /* REG_BT_IF (0x1E) */
85 0x55, /* REG_BTPGA (0x1F) */
86 0x00, /* REG_BTSTPGA (0x20) */
87 0x00, /* REG_EAR_CTL (0x21) */
88 0x00, /* REG_HS_SEL (0x22) */
89 0x00, /* REG_HS_GAIN_SET (0x23) */
90 0x00, /* REG_HS_POPN_SET (0x24) */
91 0x00, /* REG_PREDL_CTL (0x25) */
92 0x00, /* REG_PREDR_CTL (0x26) */
93 0x00, /* REG_PRECKL_CTL (0x27) */
94 0x00, /* REG_PRECKR_CTL (0x28) */
95 0x00, /* REG_HFL_CTL (0x29) */
96 0x00, /* REG_HFR_CTL (0x2A) */
97 0x05, /* REG_ALC_CTL (0x2B) */
98 0x00, /* REG_ALC_SET1 (0x2C) */
99 0x00, /* REG_ALC_SET2 (0x2D) */
100 0x00, /* REG_BOOST_CTL (0x2E) */
101 0x00, /* REG_SOFTVOL_CTL (0x2F) */
102 0x13, /* REG_DTMF_FREQSEL (0x30) */
103 0x00, /* REG_DTMF_TONEXT1H (0x31) */
104 0x00, /* REG_DTMF_TONEXT1L (0x32) */
105 0x00, /* REG_DTMF_TONEXT2H (0x33) */
106 0x00, /* REG_DTMF_TONEXT2L (0x34) */
107 0x79, /* REG_DTMF_TONOFF (0x35) */
108 0x11, /* REG_DTMF_WANONOFF (0x36) */
109 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
110 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
111 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
112 0x06, /* REG_APLL_CTL (0x3A) */
113 0x00, /* REG_DTMF_CTL (0x3B) */
114 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
115 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
116 0x00, /* REG_MISC_SET_1 (0x3E) */
117 0x00, /* REG_PCMBTMUX (0x3F) */
118 0x00, /* not used (0x40) */
119 0x00, /* not used (0x41) */
120 0x00, /* not used (0x42) */
121 0x00, /* REG_RX_PATH_SEL (0x43) */
122 0x32, /* REG_VDL_APGA_CTL (0x44) */
123 0x00, /* REG_VIBRA_CTL (0x45) */
124 0x00, /* REG_VIBRA_SET (0x46) */
125 0x00, /* REG_VIBRA_PWM_SET (0x47) */
126 0x00, /* REG_ANAMIC_GAIN (0x48) */
127 0x00, /* REG_MISC_SET_2 (0x49) */
128 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
129 };
130
131 /* codec private data */
132 struct twl4030_priv {
133 struct snd_soc_codec codec;
134
135 unsigned int codec_powered;
136
137 /* reference counts of AIF/APLL users */
138 unsigned int apll_enabled;
139
140 struct snd_pcm_substream *master_substream;
141 struct snd_pcm_substream *slave_substream;
142
143 unsigned int configured;
144 unsigned int rate;
145 unsigned int sample_bits;
146 unsigned int channels;
147
148 unsigned int sysclk;
149
150 /* Output (with associated amp) states */
151 u8 hsl_enabled, hsr_enabled;
152 u8 earpiece_enabled;
153 u8 predrivel_enabled, predriver_enabled;
154 u8 carkitl_enabled, carkitr_enabled;
155
156 /* Delay needed after enabling the digimic interface */
157 unsigned int digimic_delay;
158 };
159
160 /*
161 * read twl4030 register cache
162 */
163 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
164 unsigned int reg)
165 {
166 u8 *cache = codec->reg_cache;
167
168 if (reg >= TWL4030_CACHEREGNUM)
169 return -EIO;
170
171 return cache[reg];
172 }
173
174 /*
175 * write twl4030 register cache
176 */
177 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
178 u8 reg, u8 value)
179 {
180 u8 *cache = codec->reg_cache;
181
182 if (reg >= TWL4030_CACHEREGNUM)
183 return;
184 cache[reg] = value;
185 }
186
187 /*
188 * write to the twl4030 register space
189 */
190 static int twl4030_write(struct snd_soc_codec *codec,
191 unsigned int reg, unsigned int value)
192 {
193 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
194 int write_to_reg = 0;
195
196 twl4030_write_reg_cache(codec, reg, value);
197 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
198 /* Decide if the given register can be written */
199 switch (reg) {
200 case TWL4030_REG_EAR_CTL:
201 if (twl4030->earpiece_enabled)
202 write_to_reg = 1;
203 break;
204 case TWL4030_REG_PREDL_CTL:
205 if (twl4030->predrivel_enabled)
206 write_to_reg = 1;
207 break;
208 case TWL4030_REG_PREDR_CTL:
209 if (twl4030->predriver_enabled)
210 write_to_reg = 1;
211 break;
212 case TWL4030_REG_PRECKL_CTL:
213 if (twl4030->carkitl_enabled)
214 write_to_reg = 1;
215 break;
216 case TWL4030_REG_PRECKR_CTL:
217 if (twl4030->carkitr_enabled)
218 write_to_reg = 1;
219 break;
220 case TWL4030_REG_HS_GAIN_SET:
221 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
222 write_to_reg = 1;
223 break;
224 default:
225 /* All other register can be written */
226 write_to_reg = 1;
227 break;
228 }
229 if (write_to_reg)
230 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 value, reg);
232 }
233 return 0;
234 }
235
236 static inline void twl4030_wait_ms(int time)
237 {
238 if (time < 60) {
239 time *= 1000;
240 usleep_range(time, time + 500);
241 } else {
242 msleep(time);
243 }
244 }
245
246 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
247 {
248 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
249 int mode;
250
251 if (enable == twl4030->codec_powered)
252 return;
253
254 if (enable)
255 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
256 else
257 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
258
259 if (mode >= 0) {
260 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
261 twl4030->codec_powered = enable;
262 }
263
264 /* REVISIT: this delay is present in TI sample drivers */
265 /* but there seems to be no TRM requirement for it */
266 udelay(10);
267 }
268
269 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
270 {
271 int i, difference = 0;
272 u8 val;
273
274 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
275 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
276 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
277 if (val != twl4030_reg[i]) {
278 difference++;
279 dev_dbg(codec->dev,
280 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
281 i, val, twl4030_reg[i]);
282 }
283 }
284 dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
285 difference, difference ? "Not OK" : "OK");
286 }
287
288 static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
289 {
290 int i;
291
292 /* set all audio section registers to reasonable defaults */
293 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
294 if (i != TWL4030_REG_APLL_CTL)
295 twl4030_write(codec, i, twl4030_reg[i]);
296
297 }
298
299 static void twl4030_init_chip(struct snd_soc_codec *codec)
300 {
301 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
302 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
303 u8 reg, byte;
304 int i = 0;
305
306 if (pdata && pdata->hs_extmute &&
307 gpio_is_valid(pdata->hs_extmute_gpio)) {
308 int ret;
309
310 if (!pdata->hs_extmute_gpio)
311 dev_warn(codec->dev,
312 "Extmute GPIO is 0 is this correct?\n");
313
314 ret = gpio_request_one(pdata->hs_extmute_gpio,
315 GPIOF_OUT_INIT_LOW, "hs_extmute");
316 if (ret) {
317 dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
318 pdata->hs_extmute_gpio = -1;
319 }
320 }
321
322 /* Check defaults, if instructed before anything else */
323 if (pdata && pdata->check_defaults)
324 twl4030_check_defaults(codec);
325
326 /* Reset registers, if no setup data or if instructed to do so */
327 if (!pdata || (pdata && pdata->reset_registers))
328 twl4030_reset_registers(codec);
329
330 /* Refresh APLL_CTL register from HW */
331 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
332 TWL4030_REG_APLL_CTL);
333 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
334
335 /* anti-pop when changing analog gain */
336 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
337 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
338 reg | TWL4030_SMOOTH_ANAVOL_EN);
339
340 twl4030_write(codec, TWL4030_REG_OPTION,
341 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
342 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
343
344 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
345 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
346
347 /* Machine dependent setup */
348 if (!pdata)
349 return;
350
351 twl4030->digimic_delay = pdata->digimic_delay;
352
353 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
354 reg &= ~TWL4030_RAMP_DELAY;
355 reg |= (pdata->ramp_delay_value << 2);
356 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
357
358 /* initiate offset cancellation */
359 twl4030_codec_enable(codec, 1);
360
361 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
362 reg &= ~TWL4030_OFFSET_CNCL_SEL;
363 reg |= pdata->offset_cncl_path;
364 twl4030_write(codec, TWL4030_REG_ANAMICL,
365 reg | TWL4030_CNCL_OFFSET_START);
366
367 /*
368 * Wait for offset cancellation to complete.
369 * Since this takes a while, do not slam the i2c.
370 * Start polling the status after ~20ms.
371 */
372 msleep(20);
373 do {
374 usleep_range(1000, 2000);
375 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
376 TWL4030_REG_ANAMICL);
377 } while ((i++ < 100) &&
378 ((byte & TWL4030_CNCL_OFFSET_START) ==
379 TWL4030_CNCL_OFFSET_START));
380
381 /* Make sure that the reg_cache has the same value as the HW */
382 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
383
384 twl4030_codec_enable(codec, 0);
385 }
386
387 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
388 {
389 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
390 int status = -1;
391
392 if (enable) {
393 twl4030->apll_enabled++;
394 if (twl4030->apll_enabled == 1)
395 status = twl4030_audio_enable_resource(
396 TWL4030_AUDIO_RES_APLL);
397 } else {
398 twl4030->apll_enabled--;
399 if (!twl4030->apll_enabled)
400 status = twl4030_audio_disable_resource(
401 TWL4030_AUDIO_RES_APLL);
402 }
403
404 if (status >= 0)
405 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
406 }
407
408 /* Earpiece */
409 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
410 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
411 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
412 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
413 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
414 };
415
416 /* PreDrive Left */
417 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
418 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
419 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
420 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
421 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
422 };
423
424 /* PreDrive Right */
425 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
426 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
427 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
428 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
429 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
430 };
431
432 /* Headset Left */
433 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
434 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
435 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
436 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
437 };
438
439 /* Headset Right */
440 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
441 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
442 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
443 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
444 };
445
446 /* Carkit Left */
447 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
448 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
449 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
450 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
451 };
452
453 /* Carkit Right */
454 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
455 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
456 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
457 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
458 };
459
460 /* Handsfree Left */
461 static const char *twl4030_handsfreel_texts[] =
462 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
463
464 static const struct soc_enum twl4030_handsfreel_enum =
465 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
466 ARRAY_SIZE(twl4030_handsfreel_texts),
467 twl4030_handsfreel_texts);
468
469 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
470 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
471
472 /* Handsfree Left virtual mute */
473 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
474 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
475
476 /* Handsfree Right */
477 static const char *twl4030_handsfreer_texts[] =
478 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
479
480 static const struct soc_enum twl4030_handsfreer_enum =
481 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
482 ARRAY_SIZE(twl4030_handsfreer_texts),
483 twl4030_handsfreer_texts);
484
485 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
486 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
487
488 /* Handsfree Right virtual mute */
489 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
490 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
491
492 /* Vibra */
493 /* Vibra audio path selection */
494 static const char *twl4030_vibra_texts[] =
495 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
496
497 static const struct soc_enum twl4030_vibra_enum =
498 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
499 ARRAY_SIZE(twl4030_vibra_texts),
500 twl4030_vibra_texts);
501
502 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
503 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
504
505 /* Vibra path selection: local vibrator (PWM) or audio driven */
506 static const char *twl4030_vibrapath_texts[] =
507 {"Local vibrator", "Audio"};
508
509 static const struct soc_enum twl4030_vibrapath_enum =
510 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
511 ARRAY_SIZE(twl4030_vibrapath_texts),
512 twl4030_vibrapath_texts);
513
514 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
515 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
516
517 /* Left analog microphone selection */
518 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
519 SOC_DAPM_SINGLE("Main Mic Capture Switch",
520 TWL4030_REG_ANAMICL, 0, 1, 0),
521 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
522 TWL4030_REG_ANAMICL, 1, 1, 0),
523 SOC_DAPM_SINGLE("AUXL Capture Switch",
524 TWL4030_REG_ANAMICL, 2, 1, 0),
525 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
526 TWL4030_REG_ANAMICL, 3, 1, 0),
527 };
528
529 /* Right analog microphone selection */
530 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
531 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
532 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
533 };
534
535 /* TX1 L/R Analog/Digital microphone selection */
536 static const char *twl4030_micpathtx1_texts[] =
537 {"Analog", "Digimic0"};
538
539 static const struct soc_enum twl4030_micpathtx1_enum =
540 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
541 ARRAY_SIZE(twl4030_micpathtx1_texts),
542 twl4030_micpathtx1_texts);
543
544 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
545 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
546
547 /* TX2 L/R Analog/Digital microphone selection */
548 static const char *twl4030_micpathtx2_texts[] =
549 {"Analog", "Digimic1"};
550
551 static const struct soc_enum twl4030_micpathtx2_enum =
552 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
553 ARRAY_SIZE(twl4030_micpathtx2_texts),
554 twl4030_micpathtx2_texts);
555
556 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
557 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
558
559 /* Analog bypass for AudioR1 */
560 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
561 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
562
563 /* Analog bypass for AudioL1 */
564 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
565 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
566
567 /* Analog bypass for AudioR2 */
568 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
569 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
570
571 /* Analog bypass for AudioL2 */
572 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
573 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
574
575 /* Analog bypass for Voice */
576 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
577 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
578
579 /* Digital bypass gain, mute instead of -30dB */
580 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
581 TLV_DB_RANGE_HEAD(3),
582 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
583 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
584 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
585 };
586
587 /* Digital bypass left (TX1L -> RX2L) */
588 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
589 SOC_DAPM_SINGLE_TLV("Volume",
590 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
591 twl4030_dapm_dbypass_tlv);
592
593 /* Digital bypass right (TX1R -> RX2R) */
594 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
595 SOC_DAPM_SINGLE_TLV("Volume",
596 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
597 twl4030_dapm_dbypass_tlv);
598
599 /*
600 * Voice Sidetone GAIN volume control:
601 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
602 */
603 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
604
605 /* Digital bypass voice: sidetone (VUL -> VDL)*/
606 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
607 SOC_DAPM_SINGLE_TLV("Volume",
608 TWL4030_REG_VSTPGA, 0, 0x29, 0,
609 twl4030_dapm_dbypassv_tlv);
610
611 /*
612 * Output PGA builder:
613 * Handle the muting and unmuting of the given output (turning off the
614 * amplifier associated with the output pin)
615 * On mute bypass the reg_cache and write 0 to the register
616 * On unmute: restore the register content from the reg_cache
617 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
618 */
619 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
620 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
621 struct snd_kcontrol *kcontrol, int event) \
622 { \
623 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
624 \
625 switch (event) { \
626 case SND_SOC_DAPM_POST_PMU: \
627 twl4030->pin_name##_enabled = 1; \
628 twl4030_write(w->codec, reg, \
629 twl4030_read_reg_cache(w->codec, reg)); \
630 break; \
631 case SND_SOC_DAPM_POST_PMD: \
632 twl4030->pin_name##_enabled = 0; \
633 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
634 0, reg); \
635 break; \
636 } \
637 return 0; \
638 }
639
640 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
641 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
642 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
643 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
644 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
645
646 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
647 {
648 unsigned char hs_ctl;
649
650 hs_ctl = twl4030_read_reg_cache(codec, reg);
651
652 if (ramp) {
653 /* HF ramp-up */
654 hs_ctl |= TWL4030_HF_CTL_REF_EN;
655 twl4030_write(codec, reg, hs_ctl);
656 udelay(10);
657 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
658 twl4030_write(codec, reg, hs_ctl);
659 udelay(40);
660 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
661 hs_ctl |= TWL4030_HF_CTL_HB_EN;
662 twl4030_write(codec, reg, hs_ctl);
663 } else {
664 /* HF ramp-down */
665 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
666 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
667 twl4030_write(codec, reg, hs_ctl);
668 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
669 twl4030_write(codec, reg, hs_ctl);
670 udelay(40);
671 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
672 twl4030_write(codec, reg, hs_ctl);
673 }
674 }
675
676 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
677 struct snd_kcontrol *kcontrol, int event)
678 {
679 switch (event) {
680 case SND_SOC_DAPM_POST_PMU:
681 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
682 break;
683 case SND_SOC_DAPM_POST_PMD:
684 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
685 break;
686 }
687 return 0;
688 }
689
690 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
691 struct snd_kcontrol *kcontrol, int event)
692 {
693 switch (event) {
694 case SND_SOC_DAPM_POST_PMU:
695 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
696 break;
697 case SND_SOC_DAPM_POST_PMD:
698 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
699 break;
700 }
701 return 0;
702 }
703
704 static int vibramux_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706 {
707 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
708 return 0;
709 }
710
711 static int apll_event(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol, int event)
713 {
714 switch (event) {
715 case SND_SOC_DAPM_PRE_PMU:
716 twl4030_apll_enable(w->codec, 1);
717 break;
718 case SND_SOC_DAPM_POST_PMD:
719 twl4030_apll_enable(w->codec, 0);
720 break;
721 }
722 return 0;
723 }
724
725 static int aif_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727 {
728 u8 audio_if;
729
730 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
731 switch (event) {
732 case SND_SOC_DAPM_PRE_PMU:
733 /* Enable AIF */
734 /* enable the PLL before we use it to clock the DAI */
735 twl4030_apll_enable(w->codec, 1);
736
737 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
738 audio_if | TWL4030_AIF_EN);
739 break;
740 case SND_SOC_DAPM_POST_PMD:
741 /* disable the DAI before we stop it's source PLL */
742 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
743 audio_if & ~TWL4030_AIF_EN);
744 twl4030_apll_enable(w->codec, 0);
745 break;
746 }
747 return 0;
748 }
749
750 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
751 {
752 struct twl4030_codec_data *pdata = codec->dev->platform_data;
753 unsigned char hs_gain, hs_pop;
754 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
755 /* Base values for ramp delay calculation: 2^19 - 2^26 */
756 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
757 8388608, 16777216, 33554432, 67108864};
758 unsigned int delay;
759
760 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
761 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
762 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
763 twl4030->sysclk) + 1;
764
765 /* Enable external mute control, this dramatically reduces
766 * the pop-noise */
767 if (pdata && pdata->hs_extmute) {
768 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
769 gpio_set_value(pdata->hs_extmute_gpio, 1);
770 } else if (pdata->set_hs_extmute) {
771 dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
772 pdata->set_hs_extmute(1);
773 } else {
774 hs_pop |= TWL4030_EXTMUTE;
775 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
776 }
777 }
778
779 if (ramp) {
780 /* Headset ramp-up according to the TRM */
781 hs_pop |= TWL4030_VMID_EN;
782 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
783 /* Actually write to the register */
784 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
785 hs_gain,
786 TWL4030_REG_HS_GAIN_SET);
787 hs_pop |= TWL4030_RAMP_EN;
788 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
789 /* Wait ramp delay time + 1, so the VMID can settle */
790 twl4030_wait_ms(delay);
791 } else {
792 /* Headset ramp-down _not_ according to
793 * the TRM, but in a way that it is working */
794 hs_pop &= ~TWL4030_RAMP_EN;
795 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
796 /* Wait ramp delay time + 1, so the VMID can settle */
797 twl4030_wait_ms(delay);
798 /* Bypass the reg_cache to mute the headset */
799 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
800 hs_gain & (~0x0f),
801 TWL4030_REG_HS_GAIN_SET);
802
803 hs_pop &= ~TWL4030_VMID_EN;
804 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
805 }
806
807 /* Disable external mute */
808 if (pdata && pdata->hs_extmute) {
809 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
810 gpio_set_value(pdata->hs_extmute_gpio, 0);
811 } else if (pdata->set_hs_extmute) {
812 dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
813 pdata->set_hs_extmute(0);
814 } else {
815 hs_pop &= ~TWL4030_EXTMUTE;
816 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
817 }
818 }
819 }
820
821 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
822 struct snd_kcontrol *kcontrol, int event)
823 {
824 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
825
826 switch (event) {
827 case SND_SOC_DAPM_POST_PMU:
828 /* Do the ramp-up only once */
829 if (!twl4030->hsr_enabled)
830 headset_ramp(w->codec, 1);
831
832 twl4030->hsl_enabled = 1;
833 break;
834 case SND_SOC_DAPM_POST_PMD:
835 /* Do the ramp-down only if both headsetL/R is disabled */
836 if (!twl4030->hsr_enabled)
837 headset_ramp(w->codec, 0);
838
839 twl4030->hsl_enabled = 0;
840 break;
841 }
842 return 0;
843 }
844
845 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
846 struct snd_kcontrol *kcontrol, int event)
847 {
848 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
849
850 switch (event) {
851 case SND_SOC_DAPM_POST_PMU:
852 /* Do the ramp-up only once */
853 if (!twl4030->hsl_enabled)
854 headset_ramp(w->codec, 1);
855
856 twl4030->hsr_enabled = 1;
857 break;
858 case SND_SOC_DAPM_POST_PMD:
859 /* Do the ramp-down only if both headsetL/R is disabled */
860 if (!twl4030->hsl_enabled)
861 headset_ramp(w->codec, 0);
862
863 twl4030->hsr_enabled = 0;
864 break;
865 }
866 return 0;
867 }
868
869 static int digimic_event(struct snd_soc_dapm_widget *w,
870 struct snd_kcontrol *kcontrol, int event)
871 {
872 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
873
874 if (twl4030->digimic_delay)
875 twl4030_wait_ms(twl4030->digimic_delay);
876 return 0;
877 }
878
879 /*
880 * Some of the gain controls in TWL (mostly those which are associated with
881 * the outputs) are implemented in an interesting way:
882 * 0x0 : Power down (mute)
883 * 0x1 : 6dB
884 * 0x2 : 0 dB
885 * 0x3 : -6 dB
886 * Inverting not going to help with these.
887 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
888 */
889 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
890 struct snd_ctl_elem_value *ucontrol)
891 {
892 struct soc_mixer_control *mc =
893 (struct soc_mixer_control *)kcontrol->private_value;
894 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
895 unsigned int reg = mc->reg;
896 unsigned int shift = mc->shift;
897 unsigned int rshift = mc->rshift;
898 int max = mc->max;
899 int mask = (1 << fls(max)) - 1;
900
901 ucontrol->value.integer.value[0] =
902 (snd_soc_read(codec, reg) >> shift) & mask;
903 if (ucontrol->value.integer.value[0])
904 ucontrol->value.integer.value[0] =
905 max + 1 - ucontrol->value.integer.value[0];
906
907 if (shift != rshift) {
908 ucontrol->value.integer.value[1] =
909 (snd_soc_read(codec, reg) >> rshift) & mask;
910 if (ucontrol->value.integer.value[1])
911 ucontrol->value.integer.value[1] =
912 max + 1 - ucontrol->value.integer.value[1];
913 }
914
915 return 0;
916 }
917
918 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
919 struct snd_ctl_elem_value *ucontrol)
920 {
921 struct soc_mixer_control *mc =
922 (struct soc_mixer_control *)kcontrol->private_value;
923 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
924 unsigned int reg = mc->reg;
925 unsigned int shift = mc->shift;
926 unsigned int rshift = mc->rshift;
927 int max = mc->max;
928 int mask = (1 << fls(max)) - 1;
929 unsigned short val, val2, val_mask;
930
931 val = (ucontrol->value.integer.value[0] & mask);
932
933 val_mask = mask << shift;
934 if (val)
935 val = max + 1 - val;
936 val = val << shift;
937 if (shift != rshift) {
938 val2 = (ucontrol->value.integer.value[1] & mask);
939 val_mask |= mask << rshift;
940 if (val2)
941 val2 = max + 1 - val2;
942 val |= val2 << rshift;
943 }
944 return snd_soc_update_bits(codec, reg, val_mask, val);
945 }
946
947 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
948 struct snd_ctl_elem_value *ucontrol)
949 {
950 struct soc_mixer_control *mc =
951 (struct soc_mixer_control *)kcontrol->private_value;
952 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
953 unsigned int reg = mc->reg;
954 unsigned int reg2 = mc->rreg;
955 unsigned int shift = mc->shift;
956 int max = mc->max;
957 int mask = (1<<fls(max))-1;
958
959 ucontrol->value.integer.value[0] =
960 (snd_soc_read(codec, reg) >> shift) & mask;
961 ucontrol->value.integer.value[1] =
962 (snd_soc_read(codec, reg2) >> shift) & mask;
963
964 if (ucontrol->value.integer.value[0])
965 ucontrol->value.integer.value[0] =
966 max + 1 - ucontrol->value.integer.value[0];
967 if (ucontrol->value.integer.value[1])
968 ucontrol->value.integer.value[1] =
969 max + 1 - ucontrol->value.integer.value[1];
970
971 return 0;
972 }
973
974 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
975 struct snd_ctl_elem_value *ucontrol)
976 {
977 struct soc_mixer_control *mc =
978 (struct soc_mixer_control *)kcontrol->private_value;
979 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
980 unsigned int reg = mc->reg;
981 unsigned int reg2 = mc->rreg;
982 unsigned int shift = mc->shift;
983 int max = mc->max;
984 int mask = (1 << fls(max)) - 1;
985 int err;
986 unsigned short val, val2, val_mask;
987
988 val_mask = mask << shift;
989 val = (ucontrol->value.integer.value[0] & mask);
990 val2 = (ucontrol->value.integer.value[1] & mask);
991
992 if (val)
993 val = max + 1 - val;
994 if (val2)
995 val2 = max + 1 - val2;
996
997 val = val << shift;
998 val2 = val2 << shift;
999
1000 err = snd_soc_update_bits(codec, reg, val_mask, val);
1001 if (err < 0)
1002 return err;
1003
1004 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1005 return err;
1006 }
1007
1008 /* Codec operation modes */
1009 static const char *twl4030_op_modes_texts[] = {
1010 "Option 2 (voice/audio)", "Option 1 (audio)"
1011 };
1012
1013 static const struct soc_enum twl4030_op_modes_enum =
1014 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1015 ARRAY_SIZE(twl4030_op_modes_texts),
1016 twl4030_op_modes_texts);
1017
1018 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1019 struct snd_ctl_elem_value *ucontrol)
1020 {
1021 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1022 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1023 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1024 unsigned short val;
1025 unsigned short mask;
1026
1027 if (twl4030->configured) {
1028 dev_err(codec->dev,
1029 "operation mode cannot be changed on-the-fly\n");
1030 return -EBUSY;
1031 }
1032
1033 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1034 return -EINVAL;
1035
1036 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1037 mask = e->mask << e->shift_l;
1038 if (e->shift_l != e->shift_r) {
1039 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1040 return -EINVAL;
1041 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1042 mask |= e->mask << e->shift_r;
1043 }
1044
1045 return snd_soc_update_bits(codec, e->reg, mask, val);
1046 }
1047
1048 /*
1049 * FGAIN volume control:
1050 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1051 */
1052 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1053
1054 /*
1055 * CGAIN volume control:
1056 * 0 dB to 12 dB in 6 dB steps
1057 * value 2 and 3 means 12 dB
1058 */
1059 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1060
1061 /*
1062 * Voice Downlink GAIN volume control:
1063 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1064 */
1065 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1066
1067 /*
1068 * Analog playback gain
1069 * -24 dB to 12 dB in 2 dB steps
1070 */
1071 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1072
1073 /*
1074 * Gain controls tied to outputs
1075 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1076 */
1077 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1078
1079 /*
1080 * Gain control for earpiece amplifier
1081 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1082 */
1083 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1084
1085 /*
1086 * Capture gain after the ADCs
1087 * from 0 dB to 31 dB in 1 dB steps
1088 */
1089 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1090
1091 /*
1092 * Gain control for input amplifiers
1093 * 0 dB to 30 dB in 6 dB steps
1094 */
1095 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1096
1097 /* AVADC clock priority */
1098 static const char *twl4030_avadc_clk_priority_texts[] = {
1099 "Voice high priority", "HiFi high priority"
1100 };
1101
1102 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1103 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1104 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1105 twl4030_avadc_clk_priority_texts);
1106
1107 static const char *twl4030_rampdelay_texts[] = {
1108 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1109 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1110 "3495/2581/1748 ms"
1111 };
1112
1113 static const struct soc_enum twl4030_rampdelay_enum =
1114 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1115 ARRAY_SIZE(twl4030_rampdelay_texts),
1116 twl4030_rampdelay_texts);
1117
1118 /* Vibra H-bridge direction mode */
1119 static const char *twl4030_vibradirmode_texts[] = {
1120 "Vibra H-bridge direction", "Audio data MSB",
1121 };
1122
1123 static const struct soc_enum twl4030_vibradirmode_enum =
1124 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1125 ARRAY_SIZE(twl4030_vibradirmode_texts),
1126 twl4030_vibradirmode_texts);
1127
1128 /* Vibra H-bridge direction */
1129 static const char *twl4030_vibradir_texts[] = {
1130 "Positive polarity", "Negative polarity",
1131 };
1132
1133 static const struct soc_enum twl4030_vibradir_enum =
1134 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1135 ARRAY_SIZE(twl4030_vibradir_texts),
1136 twl4030_vibradir_texts);
1137
1138 /* Digimic Left and right swapping */
1139 static const char *twl4030_digimicswap_texts[] = {
1140 "Not swapped", "Swapped",
1141 };
1142
1143 static const struct soc_enum twl4030_digimicswap_enum =
1144 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1145 ARRAY_SIZE(twl4030_digimicswap_texts),
1146 twl4030_digimicswap_texts);
1147
1148 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1149 /* Codec operation mode control */
1150 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1151 snd_soc_get_enum_double,
1152 snd_soc_put_twl4030_opmode_enum_double),
1153
1154 /* Common playback gain controls */
1155 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1156 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1157 0, 0x3f, 0, digital_fine_tlv),
1158 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1159 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1160 0, 0x3f, 0, digital_fine_tlv),
1161
1162 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1163 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1164 6, 0x2, 0, digital_coarse_tlv),
1165 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1166 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1167 6, 0x2, 0, digital_coarse_tlv),
1168
1169 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1170 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1171 3, 0x12, 1, analog_tlv),
1172 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1173 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1174 3, 0x12, 1, analog_tlv),
1175 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1176 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1177 1, 1, 0),
1178 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1179 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1180 1, 1, 0),
1181
1182 /* Common voice downlink gain controls */
1183 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1184 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1185
1186 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1187 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1188
1189 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1190 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1191
1192 /* Separate output gain controls */
1193 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
1194 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1195 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1196 snd_soc_put_volsw_r2_twl4030, output_tvl),
1197
1198 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1199 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1200 snd_soc_put_volsw_twl4030, output_tvl),
1201
1202 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
1203 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1204 4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1205 snd_soc_put_volsw_r2_twl4030, output_tvl),
1206
1207 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1208 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1209 snd_soc_put_volsw_twl4030, output_ear_tvl),
1210
1211 /* Common capture gain controls */
1212 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1213 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1214 0, 0x1f, 0, digital_capture_tlv),
1215 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1216 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1217 0, 0x1f, 0, digital_capture_tlv),
1218
1219 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1220 0, 3, 5, 0, input_gain_tlv),
1221
1222 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1223
1224 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1225
1226 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1227 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1228
1229 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1230 };
1231
1232 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1233 /* Left channel inputs */
1234 SND_SOC_DAPM_INPUT("MAINMIC"),
1235 SND_SOC_DAPM_INPUT("HSMIC"),
1236 SND_SOC_DAPM_INPUT("AUXL"),
1237 SND_SOC_DAPM_INPUT("CARKITMIC"),
1238 /* Right channel inputs */
1239 SND_SOC_DAPM_INPUT("SUBMIC"),
1240 SND_SOC_DAPM_INPUT("AUXR"),
1241 /* Digital microphones (Stereo) */
1242 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1243 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1244
1245 /* Outputs */
1246 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1247 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1248 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1249 SND_SOC_DAPM_OUTPUT("HSOL"),
1250 SND_SOC_DAPM_OUTPUT("HSOR"),
1251 SND_SOC_DAPM_OUTPUT("CARKITL"),
1252 SND_SOC_DAPM_OUTPUT("CARKITR"),
1253 SND_SOC_DAPM_OUTPUT("HFL"),
1254 SND_SOC_DAPM_OUTPUT("HFR"),
1255 SND_SOC_DAPM_OUTPUT("VIBRA"),
1256
1257 /* AIF and APLL clocks for running DAIs (including loopback) */
1258 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1259 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1260 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1261
1262 /* DACs */
1263 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1264 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1265 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1266 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1267 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1268
1269 /* Analog bypasses */
1270 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_abypassr1_control),
1272 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1273 &twl4030_dapm_abypassl1_control),
1274 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1275 &twl4030_dapm_abypassr2_control),
1276 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1277 &twl4030_dapm_abypassl2_control),
1278 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_abypassv_control),
1280
1281 /* Master analog loopback switch */
1282 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1283 NULL, 0),
1284
1285 /* Digital bypasses */
1286 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1287 &twl4030_dapm_dbypassl_control),
1288 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1289 &twl4030_dapm_dbypassr_control),
1290 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1291 &twl4030_dapm_dbypassv_control),
1292
1293 /* Digital mixers, power control for the physical DACs */
1294 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1295 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1296 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1297 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1298 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1299 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1300 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1301 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1302 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1303 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1304
1305 /* Analog mixers, power control for the physical PGAs */
1306 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1307 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1308 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1309 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1310 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1311 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1312 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1313 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1314 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1315 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1316
1317 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1318 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1319
1320 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1321 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1322
1323 /* Output MIXER controls */
1324 /* Earpiece */
1325 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1326 &twl4030_dapm_earpiece_controls[0],
1327 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1328 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1329 0, 0, NULL, 0, earpiecepga_event,
1330 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1331 /* PreDrivL/R */
1332 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1333 &twl4030_dapm_predrivel_controls[0],
1334 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1335 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1336 0, 0, NULL, 0, predrivelpga_event,
1337 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1338 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1339 &twl4030_dapm_predriver_controls[0],
1340 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1341 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1342 0, 0, NULL, 0, predriverpga_event,
1343 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1344 /* HeadsetL/R */
1345 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1346 &twl4030_dapm_hsol_controls[0],
1347 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1348 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1349 0, 0, NULL, 0, headsetlpga_event,
1350 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1351 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1352 &twl4030_dapm_hsor_controls[0],
1353 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1354 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1355 0, 0, NULL, 0, headsetrpga_event,
1356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1357 /* CarkitL/R */
1358 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1359 &twl4030_dapm_carkitl_controls[0],
1360 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1361 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1362 0, 0, NULL, 0, carkitlpga_event,
1363 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1364 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1365 &twl4030_dapm_carkitr_controls[0],
1366 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1367 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1368 0, 0, NULL, 0, carkitrpga_event,
1369 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1370
1371 /* Output MUX controls */
1372 /* HandsfreeL/R */
1373 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1374 &twl4030_dapm_handsfreel_control),
1375 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1376 &twl4030_dapm_handsfreelmute_control),
1377 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1378 0, 0, NULL, 0, handsfreelpga_event,
1379 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1380 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1381 &twl4030_dapm_handsfreer_control),
1382 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1383 &twl4030_dapm_handsfreermute_control),
1384 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1385 0, 0, NULL, 0, handsfreerpga_event,
1386 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1387 /* Vibra */
1388 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1389 &twl4030_dapm_vibra_control, vibramux_event,
1390 SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1392 &twl4030_dapm_vibrapath_control),
1393
1394 /* Introducing four virtual ADC, since TWL4030 have four channel for
1395 capture */
1396 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1397 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1398 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1399 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1400
1401 /* Analog/Digital mic path selection.
1402 TX1 Left/Right: either analog Left/Right or Digimic0
1403 TX2 Left/Right: either analog Left/Right or Digimic1 */
1404 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1405 &twl4030_dapm_micpathtx1_control),
1406 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1407 &twl4030_dapm_micpathtx2_control),
1408
1409 /* Analog input mixers for the capture amplifiers */
1410 SND_SOC_DAPM_MIXER("Analog Left",
1411 TWL4030_REG_ANAMICL, 4, 0,
1412 &twl4030_dapm_analoglmic_controls[0],
1413 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1414 SND_SOC_DAPM_MIXER("Analog Right",
1415 TWL4030_REG_ANAMICR, 4, 0,
1416 &twl4030_dapm_analogrmic_controls[0],
1417 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1418
1419 SND_SOC_DAPM_PGA("ADC Physical Left",
1420 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1421 SND_SOC_DAPM_PGA("ADC Physical Right",
1422 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1423
1424 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1425 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1426 digimic_event, SND_SOC_DAPM_POST_PMU),
1427 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1428 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1429 digimic_event, SND_SOC_DAPM_POST_PMU),
1430
1431 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1432 NULL, 0),
1433 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1434 NULL, 0),
1435
1436 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1437 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1438 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1439
1440 };
1441
1442 static const struct snd_soc_dapm_route intercon[] = {
1443 /* Stream -> DAC mapping */
1444 {"DAC Right1", NULL, "HiFi Playback"},
1445 {"DAC Left1", NULL, "HiFi Playback"},
1446 {"DAC Right2", NULL, "HiFi Playback"},
1447 {"DAC Left2", NULL, "HiFi Playback"},
1448 {"DAC Voice", NULL, "Voice Playback"},
1449
1450 /* ADC -> Stream mapping */
1451 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1452 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1453 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1454 {"HiFi Capture", NULL, "ADC Virtual Right2"},
1455 {"Voice Capture", NULL, "ADC Virtual Left1"},
1456 {"Voice Capture", NULL, "ADC Virtual Right1"},
1457 {"Voice Capture", NULL, "ADC Virtual Left2"},
1458 {"Voice Capture", NULL, "ADC Virtual Right2"},
1459
1460 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1461 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1462 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1463 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1464 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1465
1466 /* Supply for the digital part (APLL) */
1467 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1468
1469 {"DAC Left1", NULL, "AIF Enable"},
1470 {"DAC Right1", NULL, "AIF Enable"},
1471 {"DAC Left2", NULL, "AIF Enable"},
1472 {"DAC Right1", NULL, "AIF Enable"},
1473
1474 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1475 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1476
1477 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1478 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1479 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1480 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1481 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1482
1483 /* Internal playback routings */
1484 /* Earpiece */
1485 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1486 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1487 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1488 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1489 {"Earpiece PGA", NULL, "Earpiece Mixer"},
1490 /* PreDrivL */
1491 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1492 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1493 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1494 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1495 {"PredriveL PGA", NULL, "PredriveL Mixer"},
1496 /* PreDrivR */
1497 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1498 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1499 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1500 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1501 {"PredriveR PGA", NULL, "PredriveR Mixer"},
1502 /* HeadsetL */
1503 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1504 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1505 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1506 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1507 /* HeadsetR */
1508 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1509 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1510 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1511 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1512 /* CarkitL */
1513 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1514 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1515 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1516 {"CarkitL PGA", NULL, "CarkitL Mixer"},
1517 /* CarkitR */
1518 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1519 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1520 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1521 {"CarkitR PGA", NULL, "CarkitR Mixer"},
1522 /* HandsfreeL */
1523 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1524 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1525 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1526 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1527 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1528 {"HandsfreeL PGA", NULL, "HandsfreeL"},
1529 /* HandsfreeR */
1530 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1531 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1532 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1533 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1534 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1535 {"HandsfreeR PGA", NULL, "HandsfreeR"},
1536 /* Vibra */
1537 {"Vibra Mux", "AudioL1", "DAC Left1"},
1538 {"Vibra Mux", "AudioR1", "DAC Right1"},
1539 {"Vibra Mux", "AudioL2", "DAC Left2"},
1540 {"Vibra Mux", "AudioR2", "DAC Right2"},
1541
1542 /* outputs */
1543 /* Must be always connected (for AIF and APLL) */
1544 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1545 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1546 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1547 {"Virtual HiFi OUT", NULL, "DAC Right2"},
1548 /* Must be always connected (for APLL) */
1549 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1550 /* Physical outputs */
1551 {"EARPIECE", NULL, "Earpiece PGA"},
1552 {"PREDRIVEL", NULL, "PredriveL PGA"},
1553 {"PREDRIVER", NULL, "PredriveR PGA"},
1554 {"HSOL", NULL, "HeadsetL PGA"},
1555 {"HSOR", NULL, "HeadsetR PGA"},
1556 {"CARKITL", NULL, "CarkitL PGA"},
1557 {"CARKITR", NULL, "CarkitR PGA"},
1558 {"HFL", NULL, "HandsfreeL PGA"},
1559 {"HFR", NULL, "HandsfreeR PGA"},
1560 {"Vibra Route", "Audio", "Vibra Mux"},
1561 {"VIBRA", NULL, "Vibra Route"},
1562
1563 /* Capture path */
1564 /* Must be always connected (for AIF and APLL) */
1565 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1566 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1567 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1568 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1569 /* Physical inputs */
1570 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1571 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1572 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1573 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1574
1575 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1576 {"Analog Right", "AUXR Capture Switch", "AUXR"},
1577
1578 {"ADC Physical Left", NULL, "Analog Left"},
1579 {"ADC Physical Right", NULL, "Analog Right"},
1580
1581 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1582 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1583
1584 {"DIGIMIC0", NULL, "micbias1 select"},
1585 {"DIGIMIC1", NULL, "micbias2 select"},
1586
1587 /* TX1 Left capture path */
1588 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1589 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1590 /* TX1 Right capture path */
1591 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1592 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1593 /* TX2 Left capture path */
1594 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1595 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1596 /* TX2 Right capture path */
1597 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1598 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1599
1600 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1601 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1602 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1603 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1604
1605 {"ADC Virtual Left1", NULL, "AIF Enable"},
1606 {"ADC Virtual Right1", NULL, "AIF Enable"},
1607 {"ADC Virtual Left2", NULL, "AIF Enable"},
1608 {"ADC Virtual Right2", NULL, "AIF Enable"},
1609
1610 /* Analog bypass routes */
1611 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1612 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1613 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1614 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1615 {"Voice Analog Loopback", "Switch", "Analog Left"},
1616
1617 /* Supply for the Analog loopbacks */
1618 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1619 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1620 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1621 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1622 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1623
1624 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1625 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1626 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1627 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1628 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1629
1630 /* Digital bypass routes */
1631 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1632 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1633 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1634
1635 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1636 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1637 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1638
1639 };
1640
1641 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1642 enum snd_soc_bias_level level)
1643 {
1644 switch (level) {
1645 case SND_SOC_BIAS_ON:
1646 break;
1647 case SND_SOC_BIAS_PREPARE:
1648 break;
1649 case SND_SOC_BIAS_STANDBY:
1650 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1651 twl4030_codec_enable(codec, 1);
1652 break;
1653 case SND_SOC_BIAS_OFF:
1654 twl4030_codec_enable(codec, 0);
1655 break;
1656 }
1657 codec->dapm.bias_level = level;
1658
1659 return 0;
1660 }
1661
1662 static void twl4030_constraints(struct twl4030_priv *twl4030,
1663 struct snd_pcm_substream *mst_substream)
1664 {
1665 struct snd_pcm_substream *slv_substream;
1666
1667 /* Pick the stream, which need to be constrained */
1668 if (mst_substream == twl4030->master_substream)
1669 slv_substream = twl4030->slave_substream;
1670 else if (mst_substream == twl4030->slave_substream)
1671 slv_substream = twl4030->master_substream;
1672 else /* This should not happen.. */
1673 return;
1674
1675 /* Set the constraints according to the already configured stream */
1676 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1677 SNDRV_PCM_HW_PARAM_RATE,
1678 twl4030->rate,
1679 twl4030->rate);
1680
1681 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1682 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1683 twl4030->sample_bits,
1684 twl4030->sample_bits);
1685
1686 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1687 SNDRV_PCM_HW_PARAM_CHANNELS,
1688 twl4030->channels,
1689 twl4030->channels);
1690 }
1691
1692 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1693 * capture has to be enabled/disabled. */
1694 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1695 int enable)
1696 {
1697 u8 reg, mask;
1698
1699 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1700
1701 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1702 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1703 else
1704 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1705
1706 if (enable)
1707 reg |= mask;
1708 else
1709 reg &= ~mask;
1710
1711 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1712 }
1713
1714 static int twl4030_startup(struct snd_pcm_substream *substream,
1715 struct snd_soc_dai *dai)
1716 {
1717 struct snd_soc_codec *codec = dai->codec;
1718 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1719
1720 if (twl4030->master_substream) {
1721 twl4030->slave_substream = substream;
1722 /* The DAI has one configuration for playback and capture, so
1723 * if the DAI has been already configured then constrain this
1724 * substream to match it. */
1725 if (twl4030->configured)
1726 twl4030_constraints(twl4030, twl4030->master_substream);
1727 } else {
1728 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1729 TWL4030_OPTION_1)) {
1730 /* In option2 4 channel is not supported, set the
1731 * constraint for the first stream for channels, the
1732 * second stream will 'inherit' this cosntraint */
1733 snd_pcm_hw_constraint_minmax(substream->runtime,
1734 SNDRV_PCM_HW_PARAM_CHANNELS,
1735 2, 2);
1736 }
1737 twl4030->master_substream = substream;
1738 }
1739
1740 return 0;
1741 }
1742
1743 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1744 struct snd_soc_dai *dai)
1745 {
1746 struct snd_soc_codec *codec = dai->codec;
1747 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1748
1749 if (twl4030->master_substream == substream)
1750 twl4030->master_substream = twl4030->slave_substream;
1751
1752 twl4030->slave_substream = NULL;
1753
1754 /* If all streams are closed, or the remaining stream has not yet
1755 * been configured than set the DAI as not configured. */
1756 if (!twl4030->master_substream)
1757 twl4030->configured = 0;
1758 else if (!twl4030->master_substream->runtime->channels)
1759 twl4030->configured = 0;
1760
1761 /* If the closing substream had 4 channel, do the necessary cleanup */
1762 if (substream->runtime->channels == 4)
1763 twl4030_tdm_enable(codec, substream->stream, 0);
1764 }
1765
1766 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1767 struct snd_pcm_hw_params *params,
1768 struct snd_soc_dai *dai)
1769 {
1770 struct snd_soc_codec *codec = dai->codec;
1771 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1772 u8 mode, old_mode, format, old_format;
1773
1774 /* If the substream has 4 channel, do the necessary setup */
1775 if (params_channels(params) == 4) {
1776 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1777 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1778
1779 /* Safety check: are we in the correct operating mode and
1780 * the interface is in TDM mode? */
1781 if ((mode & TWL4030_OPTION_1) &&
1782 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1783 twl4030_tdm_enable(codec, substream->stream, 1);
1784 else
1785 return -EINVAL;
1786 }
1787
1788 if (twl4030->configured)
1789 /* Ignoring hw_params for already configured DAI */
1790 return 0;
1791
1792 /* bit rate */
1793 old_mode = twl4030_read_reg_cache(codec,
1794 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1795 mode = old_mode & ~TWL4030_APLL_RATE;
1796
1797 switch (params_rate(params)) {
1798 case 8000:
1799 mode |= TWL4030_APLL_RATE_8000;
1800 break;
1801 case 11025:
1802 mode |= TWL4030_APLL_RATE_11025;
1803 break;
1804 case 12000:
1805 mode |= TWL4030_APLL_RATE_12000;
1806 break;
1807 case 16000:
1808 mode |= TWL4030_APLL_RATE_16000;
1809 break;
1810 case 22050:
1811 mode |= TWL4030_APLL_RATE_22050;
1812 break;
1813 case 24000:
1814 mode |= TWL4030_APLL_RATE_24000;
1815 break;
1816 case 32000:
1817 mode |= TWL4030_APLL_RATE_32000;
1818 break;
1819 case 44100:
1820 mode |= TWL4030_APLL_RATE_44100;
1821 break;
1822 case 48000:
1823 mode |= TWL4030_APLL_RATE_48000;
1824 break;
1825 case 96000:
1826 mode |= TWL4030_APLL_RATE_96000;
1827 break;
1828 default:
1829 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
1830 params_rate(params));
1831 return -EINVAL;
1832 }
1833
1834 /* sample size */
1835 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1836 format = old_format;
1837 format &= ~TWL4030_DATA_WIDTH;
1838 switch (params_format(params)) {
1839 case SNDRV_PCM_FORMAT_S16_LE:
1840 format |= TWL4030_DATA_WIDTH_16S_16W;
1841 break;
1842 case SNDRV_PCM_FORMAT_S32_LE:
1843 format |= TWL4030_DATA_WIDTH_32S_24W;
1844 break;
1845 default:
1846 dev_err(codec->dev, "%s: unknown format %d\n", __func__,
1847 params_format(params));
1848 return -EINVAL;
1849 }
1850
1851 if (format != old_format || mode != old_mode) {
1852 if (twl4030->codec_powered) {
1853 /*
1854 * If the codec is powered, than we need to toggle the
1855 * codec power.
1856 */
1857 twl4030_codec_enable(codec, 0);
1858 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1859 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1860 twl4030_codec_enable(codec, 1);
1861 } else {
1862 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1863 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1864 }
1865 }
1866
1867 /* Store the important parameters for the DAI configuration and set
1868 * the DAI as configured */
1869 twl4030->configured = 1;
1870 twl4030->rate = params_rate(params);
1871 twl4030->sample_bits = hw_param_interval(params,
1872 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1873 twl4030->channels = params_channels(params);
1874
1875 /* If both playback and capture streams are open, and one of them
1876 * is setting the hw parameters right now (since we are here), set
1877 * constraints to the other stream to match the current one. */
1878 if (twl4030->slave_substream)
1879 twl4030_constraints(twl4030, substream);
1880
1881 return 0;
1882 }
1883
1884 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1885 int clk_id, unsigned int freq, int dir)
1886 {
1887 struct snd_soc_codec *codec = codec_dai->codec;
1888 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1889
1890 switch (freq) {
1891 case 19200000:
1892 case 26000000:
1893 case 38400000:
1894 break;
1895 default:
1896 dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
1897 return -EINVAL;
1898 }
1899
1900 if ((freq / 1000) != twl4030->sysclk) {
1901 dev_err(codec->dev,
1902 "Mismatch in HFCLKIN: %u (configured: %u)\n",
1903 freq, twl4030->sysclk * 1000);
1904 return -EINVAL;
1905 }
1906
1907 return 0;
1908 }
1909
1910 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1911 unsigned int fmt)
1912 {
1913 struct snd_soc_codec *codec = codec_dai->codec;
1914 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1915 u8 old_format, format;
1916
1917 /* get format */
1918 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1919 format = old_format;
1920
1921 /* set master/slave audio interface */
1922 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1923 case SND_SOC_DAIFMT_CBM_CFM:
1924 format &= ~(TWL4030_AIF_SLAVE_EN);
1925 format &= ~(TWL4030_CLK256FS_EN);
1926 break;
1927 case SND_SOC_DAIFMT_CBS_CFS:
1928 format |= TWL4030_AIF_SLAVE_EN;
1929 format |= TWL4030_CLK256FS_EN;
1930 break;
1931 default:
1932 return -EINVAL;
1933 }
1934
1935 /* interface format */
1936 format &= ~TWL4030_AIF_FORMAT;
1937 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1938 case SND_SOC_DAIFMT_I2S:
1939 format |= TWL4030_AIF_FORMAT_CODEC;
1940 break;
1941 case SND_SOC_DAIFMT_DSP_A:
1942 format |= TWL4030_AIF_FORMAT_TDM;
1943 break;
1944 default:
1945 return -EINVAL;
1946 }
1947
1948 if (format != old_format) {
1949 if (twl4030->codec_powered) {
1950 /*
1951 * If the codec is powered, than we need to toggle the
1952 * codec power.
1953 */
1954 twl4030_codec_enable(codec, 0);
1955 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1956 twl4030_codec_enable(codec, 1);
1957 } else {
1958 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1959 }
1960 }
1961
1962 return 0;
1963 }
1964
1965 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1966 {
1967 struct snd_soc_codec *codec = dai->codec;
1968 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1969
1970 if (tristate)
1971 reg |= TWL4030_AIF_TRI_EN;
1972 else
1973 reg &= ~TWL4030_AIF_TRI_EN;
1974
1975 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1976 }
1977
1978 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1979 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1980 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1981 int enable)
1982 {
1983 u8 reg, mask;
1984
1985 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1986
1987 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1988 mask = TWL4030_ARXL1_VRX_EN;
1989 else
1990 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1991
1992 if (enable)
1993 reg |= mask;
1994 else
1995 reg &= ~mask;
1996
1997 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1998 }
1999
2000 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2001 struct snd_soc_dai *dai)
2002 {
2003 struct snd_soc_codec *codec = dai->codec;
2004 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2005 u8 mode;
2006
2007 /* If the system master clock is not 26MHz, the voice PCM interface is
2008 * not available.
2009 */
2010 if (twl4030->sysclk != 26000) {
2011 dev_err(codec->dev,
2012 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2013 __func__, twl4030->sysclk);
2014 return -EINVAL;
2015 }
2016
2017 /* If the codec mode is not option2, the voice PCM interface is not
2018 * available.
2019 */
2020 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2021 & TWL4030_OPT_MODE;
2022
2023 if (mode != TWL4030_OPTION_2) {
2024 dev_err(codec->dev, "%s: the codec mode is not option2\n",
2025 __func__);
2026 return -EINVAL;
2027 }
2028
2029 return 0;
2030 }
2031
2032 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2033 struct snd_soc_dai *dai)
2034 {
2035 struct snd_soc_codec *codec = dai->codec;
2036
2037 /* Enable voice digital filters */
2038 twl4030_voice_enable(codec, substream->stream, 0);
2039 }
2040
2041 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2042 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2043 {
2044 struct snd_soc_codec *codec = dai->codec;
2045 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2046 u8 old_mode, mode;
2047
2048 /* Enable voice digital filters */
2049 twl4030_voice_enable(codec, substream->stream, 1);
2050
2051 /* bit rate */
2052 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2053 & ~(TWL4030_CODECPDZ);
2054 mode = old_mode;
2055
2056 switch (params_rate(params)) {
2057 case 8000:
2058 mode &= ~(TWL4030_SEL_16K);
2059 break;
2060 case 16000:
2061 mode |= TWL4030_SEL_16K;
2062 break;
2063 default:
2064 dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
2065 params_rate(params));
2066 return -EINVAL;
2067 }
2068
2069 if (mode != old_mode) {
2070 if (twl4030->codec_powered) {
2071 /*
2072 * If the codec is powered, than we need to toggle the
2073 * codec power.
2074 */
2075 twl4030_codec_enable(codec, 0);
2076 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2077 twl4030_codec_enable(codec, 1);
2078 } else {
2079 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2080 }
2081 }
2082
2083 return 0;
2084 }
2085
2086 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2087 int clk_id, unsigned int freq, int dir)
2088 {
2089 struct snd_soc_codec *codec = codec_dai->codec;
2090 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2091
2092 if (freq != 26000000) {
2093 dev_err(codec->dev,
2094 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2095 __func__, freq / 1000);
2096 return -EINVAL;
2097 }
2098 if ((freq / 1000) != twl4030->sysclk) {
2099 dev_err(codec->dev,
2100 "Mismatch in HFCLKIN: %u (configured: %u)\n",
2101 freq, twl4030->sysclk * 1000);
2102 return -EINVAL;
2103 }
2104 return 0;
2105 }
2106
2107 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2108 unsigned int fmt)
2109 {
2110 struct snd_soc_codec *codec = codec_dai->codec;
2111 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2112 u8 old_format, format;
2113
2114 /* get format */
2115 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2116 format = old_format;
2117
2118 /* set master/slave audio interface */
2119 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2120 case SND_SOC_DAIFMT_CBM_CFM:
2121 format &= ~(TWL4030_VIF_SLAVE_EN);
2122 break;
2123 case SND_SOC_DAIFMT_CBS_CFS:
2124 format |= TWL4030_VIF_SLAVE_EN;
2125 break;
2126 default:
2127 return -EINVAL;
2128 }
2129
2130 /* clock inversion */
2131 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2132 case SND_SOC_DAIFMT_IB_NF:
2133 format &= ~(TWL4030_VIF_FORMAT);
2134 break;
2135 case SND_SOC_DAIFMT_NB_IF:
2136 format |= TWL4030_VIF_FORMAT;
2137 break;
2138 default:
2139 return -EINVAL;
2140 }
2141
2142 if (format != old_format) {
2143 if (twl4030->codec_powered) {
2144 /*
2145 * If the codec is powered, than we need to toggle the
2146 * codec power.
2147 */
2148 twl4030_codec_enable(codec, 0);
2149 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2150 twl4030_codec_enable(codec, 1);
2151 } else {
2152 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2153 }
2154 }
2155
2156 return 0;
2157 }
2158
2159 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2160 {
2161 struct snd_soc_codec *codec = dai->codec;
2162 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2163
2164 if (tristate)
2165 reg |= TWL4030_VIF_TRI_EN;
2166 else
2167 reg &= ~TWL4030_VIF_TRI_EN;
2168
2169 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2170 }
2171
2172 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2173 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2174
2175 static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2176 .startup = twl4030_startup,
2177 .shutdown = twl4030_shutdown,
2178 .hw_params = twl4030_hw_params,
2179 .set_sysclk = twl4030_set_dai_sysclk,
2180 .set_fmt = twl4030_set_dai_fmt,
2181 .set_tristate = twl4030_set_tristate,
2182 };
2183
2184 static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2185 .startup = twl4030_voice_startup,
2186 .shutdown = twl4030_voice_shutdown,
2187 .hw_params = twl4030_voice_hw_params,
2188 .set_sysclk = twl4030_voice_set_dai_sysclk,
2189 .set_fmt = twl4030_voice_set_dai_fmt,
2190 .set_tristate = twl4030_voice_set_tristate,
2191 };
2192
2193 static struct snd_soc_dai_driver twl4030_dai[] = {
2194 {
2195 .name = "twl4030-hifi",
2196 .playback = {
2197 .stream_name = "HiFi Playback",
2198 .channels_min = 2,
2199 .channels_max = 4,
2200 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2201 .formats = TWL4030_FORMATS,
2202 .sig_bits = 24,},
2203 .capture = {
2204 .stream_name = "HiFi Capture",
2205 .channels_min = 2,
2206 .channels_max = 4,
2207 .rates = TWL4030_RATES,
2208 .formats = TWL4030_FORMATS,
2209 .sig_bits = 24,},
2210 .ops = &twl4030_dai_hifi_ops,
2211 },
2212 {
2213 .name = "twl4030-voice",
2214 .playback = {
2215 .stream_name = "Voice Playback",
2216 .channels_min = 1,
2217 .channels_max = 1,
2218 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2219 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2220 .capture = {
2221 .stream_name = "Voice Capture",
2222 .channels_min = 1,
2223 .channels_max = 2,
2224 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2225 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2226 .ops = &twl4030_dai_voice_ops,
2227 },
2228 };
2229
2230 static int twl4030_soc_suspend(struct snd_soc_codec *codec)
2231 {
2232 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2233 return 0;
2234 }
2235
2236 static int twl4030_soc_resume(struct snd_soc_codec *codec)
2237 {
2238 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2239 return 0;
2240 }
2241
2242 static int twl4030_soc_probe(struct snd_soc_codec *codec)
2243 {
2244 struct twl4030_priv *twl4030;
2245
2246 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2247 if (twl4030 == NULL) {
2248 dev_err(codec->dev, "Can not allocate memory\n");
2249 return -ENOMEM;
2250 }
2251 snd_soc_codec_set_drvdata(codec, twl4030);
2252 /* Set the defaults, and power up the codec */
2253 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
2254
2255 twl4030_init_chip(codec);
2256
2257 return 0;
2258 }
2259
2260 static int twl4030_soc_remove(struct snd_soc_codec *codec)
2261 {
2262 struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
2263 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2264
2265 /* Reset registers to their chip default before leaving */
2266 twl4030_reset_registers(codec);
2267 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2268 kfree(twl4030);
2269
2270 if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2271 gpio_free(pdata->hs_extmute_gpio);
2272
2273 return 0;
2274 }
2275
2276 static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2277 .probe = twl4030_soc_probe,
2278 .remove = twl4030_soc_remove,
2279 .suspend = twl4030_soc_suspend,
2280 .resume = twl4030_soc_resume,
2281 .read = twl4030_read_reg_cache,
2282 .write = twl4030_write,
2283 .set_bias_level = twl4030_set_bias_level,
2284 .idle_bias_off = true,
2285 .reg_cache_size = sizeof(twl4030_reg),
2286 .reg_word_size = sizeof(u8),
2287 .reg_cache_default = twl4030_reg,
2288
2289 .controls = twl4030_snd_controls,
2290 .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2291 .dapm_widgets = twl4030_dapm_widgets,
2292 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2293 .dapm_routes = intercon,
2294 .num_dapm_routes = ARRAY_SIZE(intercon),
2295 };
2296
2297 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2298 {
2299 struct twl4030_codec_data *pdata = pdev->dev.platform_data;
2300
2301 if (!pdata) {
2302 dev_err(&pdev->dev, "platform_data is missing\n");
2303 return -EINVAL;
2304 }
2305
2306 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2307 twl4030_dai, ARRAY_SIZE(twl4030_dai));
2308 }
2309
2310 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2311 {
2312 snd_soc_unregister_codec(&pdev->dev);
2313 return 0;
2314 }
2315
2316 MODULE_ALIAS("platform:twl4030-codec");
2317
2318 static struct platform_driver twl4030_codec_driver = {
2319 .probe = twl4030_codec_probe,
2320 .remove = __devexit_p(twl4030_codec_remove),
2321 .driver = {
2322 .name = "twl4030-codec",
2323 .owner = THIS_MODULE,
2324 },
2325 };
2326
2327 module_platform_driver(twl4030_codec_driver);
2328
2329 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2330 MODULE_AUTHOR("Steve Sakoman");
2331 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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