2 * ALSA SoC TWL4030 codec driver
4 * Author: Steve Sakoman, <steve@sakoman.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
41 * twl4030 register cache & default register settings
43 static const u8 twl4030_reg
[TWL4030_CACHEREGNUM
] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
121 * read twl4030 register cache
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec
*codec
,
126 u8
*cache
= codec
->reg_cache
;
132 * write twl4030 register cache
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec
*codec
,
137 u8
*cache
= codec
->reg_cache
;
139 if (reg
>= TWL4030_CACHEREGNUM
)
145 * write to the twl4030 register space
147 static int twl4030_write(struct snd_soc_codec
*codec
,
148 unsigned int reg
, unsigned int value
)
150 twl4030_write_reg_cache(codec
, reg
, value
);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE
, value
, reg
);
154 static void twl4030_clear_codecpdz(struct snd_soc_codec
*codec
)
158 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
159 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
160 mode
& ~TWL4030_CODECPDZ
);
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
167 static void twl4030_set_codecpdz(struct snd_soc_codec
*codec
)
171 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
172 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
173 mode
| TWL4030_CODECPDZ
);
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
180 static void twl4030_init_chip(struct snd_soc_codec
*codec
)
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec
);
187 /* set all audio section registers to reasonable defaults */
188 for (i
= TWL4030_REG_OPTION
; i
<= TWL4030_REG_MISC_SET_2
; i
++)
189 twl4030_write(codec
, i
, twl4030_reg
[i
]);
194 * Some of the gain controls in TWL (mostly those which are associated with
195 * the outputs) are implemented in an interesting way:
196 * 0x0 : Power down (mute)
200 * Inverting not going to help with these.
201 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
203 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
204 xinvert, tlv_array) \
205 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
206 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
207 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
208 .tlv.p = (tlv_array), \
209 .info = snd_soc_info_volsw, \
210 .get = snd_soc_get_volsw_twl4030, \
211 .put = snd_soc_put_volsw_twl4030, \
212 .private_value = (unsigned long)&(struct soc_mixer_control) \
213 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
214 .max = xmax, .invert = xinvert} }
215 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
216 xinvert, tlv_array) \
217 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
218 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
219 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
220 .tlv.p = (tlv_array), \
221 .info = snd_soc_info_volsw_2r, \
222 .get = snd_soc_get_volsw_r2_twl4030,\
223 .put = snd_soc_put_volsw_r2_twl4030, \
224 .private_value = (unsigned long)&(struct soc_mixer_control) \
225 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
226 .max = xmax, .invert = xinvert} }
227 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
228 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
231 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
232 struct snd_ctl_elem_value
*ucontrol
)
234 struct soc_mixer_control
*mc
=
235 (struct soc_mixer_control
*)kcontrol
->private_value
;
236 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
237 unsigned int reg
= mc
->reg
;
238 unsigned int shift
= mc
->shift
;
239 unsigned int rshift
= mc
->rshift
;
241 int mask
= (1 << fls(max
)) - 1;
243 ucontrol
->value
.integer
.value
[0] =
244 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
245 if (ucontrol
->value
.integer
.value
[0])
246 ucontrol
->value
.integer
.value
[0] =
247 max
+ 1 - ucontrol
->value
.integer
.value
[0];
249 if (shift
!= rshift
) {
250 ucontrol
->value
.integer
.value
[1] =
251 (snd_soc_read(codec
, reg
) >> rshift
) & mask
;
252 if (ucontrol
->value
.integer
.value
[1])
253 ucontrol
->value
.integer
.value
[1] =
254 max
+ 1 - ucontrol
->value
.integer
.value
[1];
260 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
261 struct snd_ctl_elem_value
*ucontrol
)
263 struct soc_mixer_control
*mc
=
264 (struct soc_mixer_control
*)kcontrol
->private_value
;
265 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
266 unsigned int reg
= mc
->reg
;
267 unsigned int shift
= mc
->shift
;
268 unsigned int rshift
= mc
->rshift
;
270 int mask
= (1 << fls(max
)) - 1;
271 unsigned short val
, val2
, val_mask
;
273 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
275 val_mask
= mask
<< shift
;
279 if (shift
!= rshift
) {
280 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
281 val_mask
|= mask
<< rshift
;
283 val2
= max
+ 1 - val2
;
284 val
|= val2
<< rshift
;
286 return snd_soc_update_bits(codec
, reg
, val_mask
, val
);
289 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
290 struct snd_ctl_elem_value
*ucontrol
)
292 struct soc_mixer_control
*mc
=
293 (struct soc_mixer_control
*)kcontrol
->private_value
;
294 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
295 unsigned int reg
= mc
->reg
;
296 unsigned int reg2
= mc
->rreg
;
297 unsigned int shift
= mc
->shift
;
299 int mask
= (1<<fls(max
))-1;
301 ucontrol
->value
.integer
.value
[0] =
302 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
303 ucontrol
->value
.integer
.value
[1] =
304 (snd_soc_read(codec
, reg2
) >> shift
) & mask
;
306 if (ucontrol
->value
.integer
.value
[0])
307 ucontrol
->value
.integer
.value
[0] =
308 max
+ 1 - ucontrol
->value
.integer
.value
[0];
309 if (ucontrol
->value
.integer
.value
[1])
310 ucontrol
->value
.integer
.value
[1] =
311 max
+ 1 - ucontrol
->value
.integer
.value
[1];
316 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
317 struct snd_ctl_elem_value
*ucontrol
)
319 struct soc_mixer_control
*mc
=
320 (struct soc_mixer_control
*)kcontrol
->private_value
;
321 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
322 unsigned int reg
= mc
->reg
;
323 unsigned int reg2
= mc
->rreg
;
324 unsigned int shift
= mc
->shift
;
326 int mask
= (1 << fls(max
)) - 1;
328 unsigned short val
, val2
, val_mask
;
330 val_mask
= mask
<< shift
;
331 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
332 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
337 val2
= max
+ 1 - val2
;
340 val2
= val2
<< shift
;
342 err
= snd_soc_update_bits(codec
, reg
, val_mask
, val
);
346 err
= snd_soc_update_bits(codec
, reg2
, val_mask
, val2
);
350 static int twl4030_get_left_input(struct snd_kcontrol
*kcontrol
,
351 struct snd_ctl_elem_value
*ucontrol
)
353 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
354 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
357 /* one bit must be set a time */
358 reg
&= TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
359 | TWL4030_MAINMIC_EN
;
362 while ((reg
& 1) == 0) {
368 ucontrol
->value
.integer
.value
[0] = result
;
372 static int twl4030_put_left_input(struct snd_kcontrol
*kcontrol
,
373 struct snd_ctl_elem_value
*ucontrol
)
375 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
376 int value
= ucontrol
->value
.integer
.value
[0];
377 u8 anamicl
, micbias
, avadc_ctl
;
379 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
380 anamicl
&= ~(TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
381 | TWL4030_MAINMIC_EN
);
382 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
383 micbias
&= ~(TWL4030_HSMICBIAS_EN
| TWL4030_MICBIAS1_EN
);
384 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
388 anamicl
|= TWL4030_MAINMIC_EN
;
389 micbias
|= TWL4030_MICBIAS1_EN
;
392 anamicl
|= TWL4030_HSMIC_EN
;
393 micbias
|= TWL4030_HSMICBIAS_EN
;
396 anamicl
|= TWL4030_AUXL_EN
;
399 anamicl
|= TWL4030_CKMIC_EN
;
405 /* If some input is selected, enable amp and ADC */
407 anamicl
|= TWL4030_MICAMPL_EN
;
408 avadc_ctl
|= TWL4030_ADCL_EN
;
410 anamicl
&= ~TWL4030_MICAMPL_EN
;
411 avadc_ctl
&= ~TWL4030_ADCL_EN
;
414 twl4030_write(codec
, TWL4030_REG_ANAMICL
, anamicl
);
415 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
416 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
421 static int twl4030_get_right_input(struct snd_kcontrol
*kcontrol
,
422 struct snd_ctl_elem_value
*ucontrol
)
424 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
425 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
428 reg
&= TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
;
430 case TWL4030_SUBMIC_EN
:
433 case TWL4030_AUXR_EN
:
440 ucontrol
->value
.integer
.value
[0] = value
;
444 static int twl4030_put_right_input(struct snd_kcontrol
*kcontrol
,
445 struct snd_ctl_elem_value
*ucontrol
)
447 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
448 int value
= ucontrol
->value
.integer
.value
[0];
449 u8 anamicr
, micbias
, avadc_ctl
;
451 anamicr
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
452 anamicr
&= ~(TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
);
453 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
454 micbias
&= ~TWL4030_MICBIAS2_EN
;
455 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
459 anamicr
|= TWL4030_SUBMIC_EN
;
460 micbias
|= TWL4030_MICBIAS2_EN
;
463 anamicr
|= TWL4030_AUXR_EN
;
470 anamicr
|= TWL4030_MICAMPR_EN
;
471 avadc_ctl
|= TWL4030_ADCR_EN
;
473 anamicr
&= ~TWL4030_MICAMPR_EN
;
474 avadc_ctl
&= ~TWL4030_ADCR_EN
;
477 twl4030_write(codec
, TWL4030_REG_ANAMICR
, anamicr
);
478 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
479 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
484 static const char *twl4030_left_in_sel
[] = {
492 static const char *twl4030_right_in_sel
[] = {
498 static const struct soc_enum twl4030_left_input_mux
=
499 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel
),
500 twl4030_left_in_sel
);
502 static const struct soc_enum twl4030_right_input_mux
=
503 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel
),
504 twl4030_right_in_sel
);
507 * FGAIN volume control:
508 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
510 static DECLARE_TLV_DB_SCALE(digital_fine_tlv
, -6300, 100, 1);
513 * CGAIN volume control:
514 * 0 dB to 12 dB in 6 dB steps
515 * value 2 and 3 means 12 dB
517 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv
, 0, 600, 0);
520 * Analog playback gain
521 * -24 dB to 12 dB in 2 dB steps
523 static DECLARE_TLV_DB_SCALE(analog_tlv
, -2400, 200, 0);
526 * Gain controls tied to outputs
527 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
529 static DECLARE_TLV_DB_SCALE(output_tvl
, -1200, 600, 1);
532 * Capture gain after the ADCs
533 * from 0 dB to 31 dB in 1 dB steps
535 static DECLARE_TLV_DB_SCALE(digital_capture_tlv
, 0, 100, 0);
538 * Gain control for input amplifiers
539 * 0 dB to 30 dB in 6 dB steps
541 static DECLARE_TLV_DB_SCALE(input_gain_tlv
, 0, 600, 0);
543 static const struct snd_kcontrol_new twl4030_snd_controls
[] = {
544 /* Common playback gain controls */
545 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
546 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
547 0, 0x3f, 0, digital_fine_tlv
),
548 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
549 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
550 0, 0x3f, 0, digital_fine_tlv
),
552 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
553 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
554 6, 0x2, 0, digital_coarse_tlv
),
555 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
556 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
557 6, 0x2, 0, digital_coarse_tlv
),
559 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
560 TWL4030_REG_ARXL1_APGA_CTL
, TWL4030_REG_ARXR1_APGA_CTL
,
561 3, 0x12, 1, analog_tlv
),
562 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
563 TWL4030_REG_ARXL2_APGA_CTL
, TWL4030_REG_ARXR2_APGA_CTL
,
564 3, 0x12, 1, analog_tlv
),
566 /* Separate output gain controls */
567 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
568 TWL4030_REG_PREDL_CTL
, TWL4030_REG_PREDR_CTL
,
569 4, 3, 0, output_tvl
),
571 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
572 TWL4030_REG_HS_GAIN_SET
, 0, 2, 3, 0, output_tvl
),
574 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
575 TWL4030_REG_PRECKL_CTL
, TWL4030_REG_PRECKR_CTL
,
576 4, 3, 0, output_tvl
),
578 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
579 TWL4030_REG_EAR_CTL
, 4, 3, 0, output_tvl
),
581 /* Common capture gain controls */
582 SOC_DOUBLE_R_TLV("Capture Volume",
583 TWL4030_REG_ATXL1PGA
, TWL4030_REG_ATXR1PGA
,
584 0, 0x1f, 0, digital_capture_tlv
),
586 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN
,
587 0, 3, 5, 0, input_gain_tlv
),
589 /* Input source controls */
590 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux
,
591 twl4030_get_left_input
, twl4030_put_left_input
),
592 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux
,
593 twl4030_get_right_input
, twl4030_put_right_input
),
596 /* add non dapm controls */
597 static int twl4030_add_controls(struct snd_soc_codec
*codec
)
601 for (i
= 0; i
< ARRAY_SIZE(twl4030_snd_controls
); i
++) {
602 err
= snd_ctl_add(codec
->card
,
603 snd_soc_cnew(&twl4030_snd_controls
[i
],
612 static const struct snd_soc_dapm_widget twl4030_dapm_widgets
[] = {
613 SND_SOC_DAPM_INPUT("INL"),
614 SND_SOC_DAPM_INPUT("INR"),
616 SND_SOC_DAPM_OUTPUT("OUTL"),
617 SND_SOC_DAPM_OUTPUT("OUTR"),
619 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM
, 0, 0),
620 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM
, 0, 0),
622 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM
, 0, 0),
623 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM
, 0, 0),
626 static const struct snd_soc_dapm_route intercon
[] = {
628 {"OUTL", NULL
, "DACL"},
629 {"OUTR", NULL
, "DACR"},
632 {"ADCL", NULL
, "INL"},
633 {"ADCR", NULL
, "INR"},
636 static int twl4030_add_widgets(struct snd_soc_codec
*codec
)
638 snd_soc_dapm_new_controls(codec
, twl4030_dapm_widgets
,
639 ARRAY_SIZE(twl4030_dapm_widgets
));
641 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
643 snd_soc_dapm_new_widgets(codec
);
647 static void twl4030_power_up(struct snd_soc_codec
*codec
)
649 u8 anamicl
, regmisc1
, byte
, popn
, hsgain
;
652 /* set CODECPDZ to turn on codec */
653 twl4030_set_codecpdz(codec
);
655 /* initiate offset cancellation */
656 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
657 twl4030_write(codec
, TWL4030_REG_ANAMICL
,
658 anamicl
| TWL4030_CNCL_OFFSET_START
);
660 /* wait for offset cancellation to complete */
662 /* this takes a little while, so don't slam i2c */
664 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE
, &byte
,
665 TWL4030_REG_ANAMICL
);
666 } while ((i
++ < 100) &&
667 ((byte
& TWL4030_CNCL_OFFSET_START
) ==
668 TWL4030_CNCL_OFFSET_START
));
670 /* anti-pop when changing analog gain */
671 regmisc1
= twl4030_read_reg_cache(codec
, TWL4030_REG_MISC_SET_1
);
672 twl4030_write(codec
, TWL4030_REG_MISC_SET_1
,
673 regmisc1
| TWL4030_SMOOTH_ANAVOL_EN
);
675 /* toggle CODECPDZ as per TRM */
676 twl4030_clear_codecpdz(codec
);
677 twl4030_set_codecpdz(codec
);
679 /* program anti-pop with bias ramp delay */
680 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
681 popn
&= TWL4030_RAMP_DELAY
;
682 popn
|= TWL4030_RAMP_DELAY_645MS
;
683 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
684 popn
|= TWL4030_VMID_EN
;
685 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
687 /* enable output stage and gain setting */
688 hsgain
= TWL4030_HSR_GAIN_0DB
| TWL4030_HSL_GAIN_0DB
;
689 twl4030_write(codec
, TWL4030_REG_HS_GAIN_SET
, hsgain
);
691 /* enable anti-pop ramp */
692 popn
|= TWL4030_RAMP_EN
;
693 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
696 static void twl4030_power_down(struct snd_soc_codec
*codec
)
700 /* disable anti-pop ramp */
701 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
702 popn
&= ~TWL4030_RAMP_EN
;
703 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
705 /* disable output stage and gain setting */
706 hsgain
= TWL4030_HSR_GAIN_PWR_DOWN
| TWL4030_HSL_GAIN_PWR_DOWN
;
707 twl4030_write(codec
, TWL4030_REG_HS_GAIN_SET
, hsgain
);
709 /* disable bias out */
710 popn
&= ~TWL4030_VMID_EN
;
711 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
714 twl4030_clear_codecpdz(codec
);
717 static int twl4030_set_bias_level(struct snd_soc_codec
*codec
,
718 enum snd_soc_bias_level level
)
721 case SND_SOC_BIAS_ON
:
722 twl4030_power_up(codec
);
724 case SND_SOC_BIAS_PREPARE
:
725 /* TODO: develop a twl4030_prepare function */
727 case SND_SOC_BIAS_STANDBY
:
728 /* TODO: develop a twl4030_standby function */
729 twl4030_power_down(codec
);
731 case SND_SOC_BIAS_OFF
:
732 twl4030_power_down(codec
);
735 codec
->bias_level
= level
;
740 static int twl4030_hw_params(struct snd_pcm_substream
*substream
,
741 struct snd_pcm_hw_params
*params
,
742 struct snd_soc_dai
*dai
)
744 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
745 struct snd_soc_device
*socdev
= rtd
->socdev
;
746 struct snd_soc_codec
*codec
= socdev
->codec
;
747 u8 mode
, old_mode
, format
, old_format
;
751 old_mode
= twl4030_read_reg_cache(codec
,
752 TWL4030_REG_CODEC_MODE
) & ~TWL4030_CODECPDZ
;
753 mode
= old_mode
& ~TWL4030_APLL_RATE
;
755 switch (params_rate(params
)) {
757 mode
|= TWL4030_APLL_RATE_8000
;
760 mode
|= TWL4030_APLL_RATE_11025
;
763 mode
|= TWL4030_APLL_RATE_12000
;
766 mode
|= TWL4030_APLL_RATE_16000
;
769 mode
|= TWL4030_APLL_RATE_22050
;
772 mode
|= TWL4030_APLL_RATE_24000
;
775 mode
|= TWL4030_APLL_RATE_32000
;
778 mode
|= TWL4030_APLL_RATE_44100
;
781 mode
|= TWL4030_APLL_RATE_48000
;
784 printk(KERN_ERR
"TWL4030 hw params: unknown rate %d\n",
785 params_rate(params
));
789 if (mode
!= old_mode
) {
790 /* change rate and set CODECPDZ */
791 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
, mode
);
792 twl4030_set_codecpdz(codec
);
796 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
798 format
&= ~TWL4030_DATA_WIDTH
;
799 switch (params_format(params
)) {
800 case SNDRV_PCM_FORMAT_S16_LE
:
801 format
|= TWL4030_DATA_WIDTH_16S_16W
;
803 case SNDRV_PCM_FORMAT_S24_LE
:
804 format
|= TWL4030_DATA_WIDTH_32S_24W
;
807 printk(KERN_ERR
"TWL4030 hw params: unknown format %d\n",
808 params_format(params
));
812 if (format
!= old_format
) {
814 /* clear CODECPDZ before changing format (codec requirement) */
815 twl4030_clear_codecpdz(codec
);
818 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
820 /* set CODECPDZ afterwards */
821 twl4030_set_codecpdz(codec
);
826 static int twl4030_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
827 int clk_id
, unsigned int freq
, int dir
)
829 struct snd_soc_codec
*codec
= codec_dai
->codec
;
834 infreq
= TWL4030_APLL_INFREQ_19200KHZ
;
837 infreq
= TWL4030_APLL_INFREQ_26000KHZ
;
840 infreq
= TWL4030_APLL_INFREQ_38400KHZ
;
843 printk(KERN_ERR
"TWL4030 set sysclk: unknown rate %d\n",
848 infreq
|= TWL4030_APLL_EN
;
849 twl4030_write(codec
, TWL4030_REG_APLL_CTL
, infreq
);
854 static int twl4030_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
857 struct snd_soc_codec
*codec
= codec_dai
->codec
;
858 u8 old_format
, format
;
861 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
864 /* set master/slave audio interface */
865 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
866 case SND_SOC_DAIFMT_CBM_CFM
:
867 format
&= ~(TWL4030_AIF_SLAVE_EN
);
868 format
&= ~(TWL4030_CLK256FS_EN
);
870 case SND_SOC_DAIFMT_CBS_CFS
:
871 format
|= TWL4030_AIF_SLAVE_EN
;
872 format
|= TWL4030_CLK256FS_EN
;
878 /* interface format */
879 format
&= ~TWL4030_AIF_FORMAT
;
880 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
881 case SND_SOC_DAIFMT_I2S
:
882 format
|= TWL4030_AIF_FORMAT_CODEC
;
888 if (format
!= old_format
) {
890 /* clear CODECPDZ before changing format (codec requirement) */
891 twl4030_clear_codecpdz(codec
);
894 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
896 /* set CODECPDZ afterwards */
897 twl4030_set_codecpdz(codec
);
903 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
904 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
906 struct snd_soc_dai twl4030_dai
= {
909 .stream_name
= "Playback",
912 .rates
= TWL4030_RATES
,
913 .formats
= TWL4030_FORMATS
,},
915 .stream_name
= "Capture",
918 .rates
= TWL4030_RATES
,
919 .formats
= TWL4030_FORMATS
,},
921 .hw_params
= twl4030_hw_params
,
922 .set_sysclk
= twl4030_set_dai_sysclk
,
923 .set_fmt
= twl4030_set_dai_fmt
,
926 EXPORT_SYMBOL_GPL(twl4030_dai
);
928 static int twl4030_suspend(struct platform_device
*pdev
, pm_message_t state
)
930 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
931 struct snd_soc_codec
*codec
= socdev
->codec
;
933 twl4030_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
938 static int twl4030_resume(struct platform_device
*pdev
)
940 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
941 struct snd_soc_codec
*codec
= socdev
->codec
;
943 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
944 twl4030_set_bias_level(codec
, codec
->suspend_bias_level
);
949 * initialize the driver
950 * register the mixer and dsp interfaces with the kernel
953 static int twl4030_init(struct snd_soc_device
*socdev
)
955 struct snd_soc_codec
*codec
= socdev
->codec
;
958 printk(KERN_INFO
"TWL4030 Audio Codec init \n");
960 codec
->name
= "twl4030";
961 codec
->owner
= THIS_MODULE
;
962 codec
->read
= twl4030_read_reg_cache
;
963 codec
->write
= twl4030_write
;
964 codec
->set_bias_level
= twl4030_set_bias_level
;
965 codec
->dai
= &twl4030_dai
;
967 codec
->reg_cache_size
= sizeof(twl4030_reg
);
968 codec
->reg_cache
= kmemdup(twl4030_reg
, sizeof(twl4030_reg
),
970 if (codec
->reg_cache
== NULL
)
974 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
976 printk(KERN_ERR
"twl4030: failed to create pcms\n");
980 twl4030_init_chip(codec
);
982 /* power on device */
983 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
985 twl4030_add_controls(codec
);
986 twl4030_add_widgets(codec
);
988 ret
= snd_soc_init_card(socdev
);
990 printk(KERN_ERR
"twl4030: failed to register card\n");
997 snd_soc_free_pcms(socdev
);
998 snd_soc_dapm_free(socdev
);
1000 kfree(codec
->reg_cache
);
1004 static struct snd_soc_device
*twl4030_socdev
;
1006 static int twl4030_probe(struct platform_device
*pdev
)
1008 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1009 struct snd_soc_codec
*codec
;
1011 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1015 socdev
->codec
= codec
;
1016 mutex_init(&codec
->mutex
);
1017 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1018 INIT_LIST_HEAD(&codec
->dapm_paths
);
1020 twl4030_socdev
= socdev
;
1021 twl4030_init(socdev
);
1026 static int twl4030_remove(struct platform_device
*pdev
)
1028 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1029 struct snd_soc_codec
*codec
= socdev
->codec
;
1031 printk(KERN_INFO
"TWL4030 Audio Codec remove\n");
1037 struct snd_soc_codec_device soc_codec_dev_twl4030
= {
1038 .probe
= twl4030_probe
,
1039 .remove
= twl4030_remove
,
1040 .suspend
= twl4030_suspend
,
1041 .resume
= twl4030_resume
,
1043 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030
);
1045 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1046 MODULE_AUTHOR("Steve Sakoman");
1047 MODULE_LICENSE("GPL");