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ASoC: TWL4030: Add functionalty to reset the registers
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x00, /* REG_CODEC_MODE (0x1) */
46 0x00, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x00, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0f, /* REG_ATXL1PGA (0xA) */
55 0x0f, /* REG_ATXR1PGA (0xB) */
56 0x0f, /* REG_AVTXL2PGA (0xC) */
57 0x0f, /* REG_AVTXR2PGA (0xD) */
58 0x00, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x3f, /* REG_ARXR1PGA (0x10) */
61 0x3f, /* REG_ARXL1PGA (0x11) */
62 0x3f, /* REG_ARXR2PGA (0x12) */
63 0x3f, /* REG_ARXL2PGA (0x13) */
64 0x25, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x00, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x55, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x00, /* REG_HS_SEL (0x22) */
79 0x00, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x05, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x13, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x79, /* REG_DTMF_TONOFF (0x35) */
98 0x11, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x06, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x32, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
119 };
120
121 /* codec private data */
122 struct twl4030_priv {
123 struct snd_soc_codec codec;
124
125 unsigned int codec_powered;
126
127 /* reference counts of AIF/APLL users */
128 unsigned int apll_enabled;
129
130 struct snd_pcm_substream *master_substream;
131 struct snd_pcm_substream *slave_substream;
132
133 unsigned int configured;
134 unsigned int rate;
135 unsigned int sample_bits;
136 unsigned int channels;
137
138 unsigned int sysclk;
139
140 /* Output (with associated amp) states */
141 u8 hsl_enabled, hsr_enabled;
142 u8 earpiece_enabled;
143 u8 predrivel_enabled, predriver_enabled;
144 u8 carkitl_enabled, carkitr_enabled;
145 };
146
147 /*
148 * read twl4030 register cache
149 */
150 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned int reg)
152 {
153 u8 *cache = codec->reg_cache;
154
155 if (reg >= TWL4030_CACHEREGNUM)
156 return -EIO;
157
158 return cache[reg];
159 }
160
161 /*
162 * write twl4030 register cache
163 */
164 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
165 u8 reg, u8 value)
166 {
167 u8 *cache = codec->reg_cache;
168
169 if (reg >= TWL4030_CACHEREGNUM)
170 return;
171 cache[reg] = value;
172 }
173
174 /*
175 * write to the twl4030 register space
176 */
177 static int twl4030_write(struct snd_soc_codec *codec,
178 unsigned int reg, unsigned int value)
179 {
180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
181 int write_to_reg = 0;
182
183 twl4030_write_reg_cache(codec, reg, value);
184 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
185 /* Decide if the given register can be written */
186 switch (reg) {
187 case TWL4030_REG_EAR_CTL:
188 if (twl4030->earpiece_enabled)
189 write_to_reg = 1;
190 break;
191 case TWL4030_REG_PREDL_CTL:
192 if (twl4030->predrivel_enabled)
193 write_to_reg = 1;
194 break;
195 case TWL4030_REG_PREDR_CTL:
196 if (twl4030->predriver_enabled)
197 write_to_reg = 1;
198 break;
199 case TWL4030_REG_PRECKL_CTL:
200 if (twl4030->carkitl_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PRECKR_CTL:
204 if (twl4030->carkitr_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_HS_GAIN_SET:
208 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
209 write_to_reg = 1;
210 break;
211 default:
212 /* All other register can be written */
213 write_to_reg = 1;
214 break;
215 }
216 if (write_to_reg)
217 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
218 value, reg);
219 }
220 return 0;
221 }
222
223 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
224 {
225 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
226 int mode;
227
228 if (enable == twl4030->codec_powered)
229 return;
230
231 if (enable)
232 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
233 else
234 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
235
236 if (mode >= 0) {
237 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
238 twl4030->codec_powered = enable;
239 }
240
241 /* REVISIT: this delay is present in TI sample drivers */
242 /* but there seems to be no TRM requirement for it */
243 udelay(10);
244 }
245
246 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
247 {
248 int i, difference = 0;
249 u8 val;
250
251 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
252 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
253 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
254 if (val != twl4030_reg[i]) {
255 difference++;
256 dev_dbg(codec->dev,
257 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
258 i, val, twl4030_reg[i]);
259 }
260 }
261 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
262 difference, difference ? "Not OK" : "OK");
263 }
264
265 static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
266 {
267 int i;
268
269 /* set all audio section registers to reasonable defaults */
270 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
271 if (i != TWL4030_REG_APLL_CTL)
272 twl4030_write(codec, i, twl4030_reg[i]);
273
274 }
275
276 static void twl4030_init_chip(struct platform_device *pdev)
277 {
278 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
279 struct twl4030_setup_data *setup = socdev->codec_data;
280 struct snd_soc_codec *codec = socdev->card->codec;
281 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
282 u8 reg, byte;
283 int i = 0;
284
285 /* Check defaults, if instructed before anything else */
286 if (setup && setup->check_defaults)
287 twl4030_check_defaults(codec);
288
289 /* Reset registers, if no setup data or if instructed to do so */
290 if (!setup || (setup && setup->reset_registers))
291 twl4030_reset_registers(codec);
292
293 /* Refresh APLL_CTL register from HW */
294 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
295 TWL4030_REG_APLL_CTL);
296 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
297
298 /* anti-pop when changing analog gain */
299 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
300 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
301 reg | TWL4030_SMOOTH_ANAVOL_EN);
302
303 twl4030_write(codec, TWL4030_REG_OPTION,
304 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
305 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
306
307 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
308 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
309
310 /* Machine dependent setup */
311 if (!setup)
312 return;
313
314 /* Configuration for headset ramp delay from setup data */
315 if (setup->sysclk != twl4030->sysclk)
316 dev_warn(codec->dev,
317 "Mismatch in APLL mclk: %u (configured: %u)\n",
318 setup->sysclk, twl4030->sysclk);
319
320 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
321 reg &= ~TWL4030_RAMP_DELAY;
322 reg |= (setup->ramp_delay_value << 2);
323 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
324
325 /* initiate offset cancellation */
326 twl4030_codec_enable(codec, 1);
327
328 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
329 reg &= ~TWL4030_OFFSET_CNCL_SEL;
330 reg |= setup->offset_cncl_path;
331 twl4030_write(codec, TWL4030_REG_ANAMICL,
332 reg | TWL4030_CNCL_OFFSET_START);
333
334 /* wait for offset cancellation to complete */
335 do {
336 /* this takes a little while, so don't slam i2c */
337 udelay(2000);
338 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
339 TWL4030_REG_ANAMICL);
340 } while ((i++ < 100) &&
341 ((byte & TWL4030_CNCL_OFFSET_START) ==
342 TWL4030_CNCL_OFFSET_START));
343
344 /* Make sure that the reg_cache has the same value as the HW */
345 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
346
347 twl4030_codec_enable(codec, 0);
348 }
349
350 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
351 {
352 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
353 int status = -1;
354
355 if (enable) {
356 twl4030->apll_enabled++;
357 if (twl4030->apll_enabled == 1)
358 status = twl4030_codec_enable_resource(
359 TWL4030_CODEC_RES_APLL);
360 } else {
361 twl4030->apll_enabled--;
362 if (!twl4030->apll_enabled)
363 status = twl4030_codec_disable_resource(
364 TWL4030_CODEC_RES_APLL);
365 }
366
367 if (status >= 0)
368 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
369 }
370
371 /* Earpiece */
372 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
373 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
374 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
375 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
376 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
377 };
378
379 /* PreDrive Left */
380 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
381 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
382 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
383 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
384 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
385 };
386
387 /* PreDrive Right */
388 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
389 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
390 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
391 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
392 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
393 };
394
395 /* Headset Left */
396 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
397 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
398 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
399 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
400 };
401
402 /* Headset Right */
403 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
404 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
405 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
406 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
407 };
408
409 /* Carkit Left */
410 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
411 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
412 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
413 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
414 };
415
416 /* Carkit Right */
417 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
418 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
419 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
420 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
421 };
422
423 /* Handsfree Left */
424 static const char *twl4030_handsfreel_texts[] =
425 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
426
427 static const struct soc_enum twl4030_handsfreel_enum =
428 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
429 ARRAY_SIZE(twl4030_handsfreel_texts),
430 twl4030_handsfreel_texts);
431
432 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
433 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
434
435 /* Handsfree Left virtual mute */
436 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
437 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
438
439 /* Handsfree Right */
440 static const char *twl4030_handsfreer_texts[] =
441 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
442
443 static const struct soc_enum twl4030_handsfreer_enum =
444 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
445 ARRAY_SIZE(twl4030_handsfreer_texts),
446 twl4030_handsfreer_texts);
447
448 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
449 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
450
451 /* Handsfree Right virtual mute */
452 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
453 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
454
455 /* Vibra */
456 /* Vibra audio path selection */
457 static const char *twl4030_vibra_texts[] =
458 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
459
460 static const struct soc_enum twl4030_vibra_enum =
461 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
462 ARRAY_SIZE(twl4030_vibra_texts),
463 twl4030_vibra_texts);
464
465 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
466 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
467
468 /* Vibra path selection: local vibrator (PWM) or audio driven */
469 static const char *twl4030_vibrapath_texts[] =
470 {"Local vibrator", "Audio"};
471
472 static const struct soc_enum twl4030_vibrapath_enum =
473 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
474 ARRAY_SIZE(twl4030_vibrapath_texts),
475 twl4030_vibrapath_texts);
476
477 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
478 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
479
480 /* Left analog microphone selection */
481 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
482 SOC_DAPM_SINGLE("Main Mic Capture Switch",
483 TWL4030_REG_ANAMICL, 0, 1, 0),
484 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
485 TWL4030_REG_ANAMICL, 1, 1, 0),
486 SOC_DAPM_SINGLE("AUXL Capture Switch",
487 TWL4030_REG_ANAMICL, 2, 1, 0),
488 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
489 TWL4030_REG_ANAMICL, 3, 1, 0),
490 };
491
492 /* Right analog microphone selection */
493 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
494 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
495 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
496 };
497
498 /* TX1 L/R Analog/Digital microphone selection */
499 static const char *twl4030_micpathtx1_texts[] =
500 {"Analog", "Digimic0"};
501
502 static const struct soc_enum twl4030_micpathtx1_enum =
503 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
504 ARRAY_SIZE(twl4030_micpathtx1_texts),
505 twl4030_micpathtx1_texts);
506
507 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
508 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
509
510 /* TX2 L/R Analog/Digital microphone selection */
511 static const char *twl4030_micpathtx2_texts[] =
512 {"Analog", "Digimic1"};
513
514 static const struct soc_enum twl4030_micpathtx2_enum =
515 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
516 ARRAY_SIZE(twl4030_micpathtx2_texts),
517 twl4030_micpathtx2_texts);
518
519 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
520 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
521
522 /* Analog bypass for AudioR1 */
523 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
524 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
525
526 /* Analog bypass for AudioL1 */
527 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
528 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
529
530 /* Analog bypass for AudioR2 */
531 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
532 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
533
534 /* Analog bypass for AudioL2 */
535 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
536 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
537
538 /* Analog bypass for Voice */
539 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
540 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
541
542 /* Digital bypass gain, 0 mutes the bypass */
543 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
544 TLV_DB_RANGE_HEAD(2),
545 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
546 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
547 };
548
549 /* Digital bypass left (TX1L -> RX2L) */
550 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
551 SOC_DAPM_SINGLE_TLV("Volume",
552 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
553 twl4030_dapm_dbypass_tlv);
554
555 /* Digital bypass right (TX1R -> RX2R) */
556 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
557 SOC_DAPM_SINGLE_TLV("Volume",
558 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
559 twl4030_dapm_dbypass_tlv);
560
561 /*
562 * Voice Sidetone GAIN volume control:
563 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
564 */
565 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
566
567 /* Digital bypass voice: sidetone (VUL -> VDL)*/
568 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
569 SOC_DAPM_SINGLE_TLV("Volume",
570 TWL4030_REG_VSTPGA, 0, 0x29, 0,
571 twl4030_dapm_dbypassv_tlv);
572
573 static int micpath_event(struct snd_soc_dapm_widget *w,
574 struct snd_kcontrol *kcontrol, int event)
575 {
576 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
577 unsigned char adcmicsel, micbias_ctl;
578
579 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
580 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
581 /* Prepare the bits for the given TX path:
582 * shift_l == 0: TX1 microphone path
583 * shift_l == 2: TX2 microphone path */
584 if (e->shift_l) {
585 /* TX2 microphone path */
586 if (adcmicsel & TWL4030_TX2IN_SEL)
587 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
588 else
589 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
590 } else {
591 /* TX1 microphone path */
592 if (adcmicsel & TWL4030_TX1IN_SEL)
593 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
594 else
595 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
596 }
597
598 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
599
600 return 0;
601 }
602
603 /*
604 * Output PGA builder:
605 * Handle the muting and unmuting of the given output (turning off the
606 * amplifier associated with the output pin)
607 * On mute bypass the reg_cache and write 0 to the register
608 * On unmute: restore the register content from the reg_cache
609 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
610 */
611 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
612 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
613 struct snd_kcontrol *kcontrol, int event) \
614 { \
615 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
616 \
617 switch (event) { \
618 case SND_SOC_DAPM_POST_PMU: \
619 twl4030->pin_name##_enabled = 1; \
620 twl4030_write(w->codec, reg, \
621 twl4030_read_reg_cache(w->codec, reg)); \
622 break; \
623 case SND_SOC_DAPM_POST_PMD: \
624 twl4030->pin_name##_enabled = 0; \
625 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
626 0, reg); \
627 break; \
628 } \
629 return 0; \
630 }
631
632 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
633 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
634 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
635 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
636 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
637
638 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
639 {
640 unsigned char hs_ctl;
641
642 hs_ctl = twl4030_read_reg_cache(codec, reg);
643
644 if (ramp) {
645 /* HF ramp-up */
646 hs_ctl |= TWL4030_HF_CTL_REF_EN;
647 twl4030_write(codec, reg, hs_ctl);
648 udelay(10);
649 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
650 twl4030_write(codec, reg, hs_ctl);
651 udelay(40);
652 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
653 hs_ctl |= TWL4030_HF_CTL_HB_EN;
654 twl4030_write(codec, reg, hs_ctl);
655 } else {
656 /* HF ramp-down */
657 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
658 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
659 twl4030_write(codec, reg, hs_ctl);
660 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
661 twl4030_write(codec, reg, hs_ctl);
662 udelay(40);
663 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
664 twl4030_write(codec, reg, hs_ctl);
665 }
666 }
667
668 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
669 struct snd_kcontrol *kcontrol, int event)
670 {
671 switch (event) {
672 case SND_SOC_DAPM_POST_PMU:
673 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
674 break;
675 case SND_SOC_DAPM_POST_PMD:
676 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
677 break;
678 }
679 return 0;
680 }
681
682 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
683 struct snd_kcontrol *kcontrol, int event)
684 {
685 switch (event) {
686 case SND_SOC_DAPM_POST_PMU:
687 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
688 break;
689 case SND_SOC_DAPM_POST_PMD:
690 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
691 break;
692 }
693 return 0;
694 }
695
696 static int vibramux_event(struct snd_soc_dapm_widget *w,
697 struct snd_kcontrol *kcontrol, int event)
698 {
699 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
700 return 0;
701 }
702
703 static int apll_event(struct snd_soc_dapm_widget *w,
704 struct snd_kcontrol *kcontrol, int event)
705 {
706 switch (event) {
707 case SND_SOC_DAPM_PRE_PMU:
708 twl4030_apll_enable(w->codec, 1);
709 break;
710 case SND_SOC_DAPM_POST_PMD:
711 twl4030_apll_enable(w->codec, 0);
712 break;
713 }
714 return 0;
715 }
716
717 static int aif_event(struct snd_soc_dapm_widget *w,
718 struct snd_kcontrol *kcontrol, int event)
719 {
720 u8 audio_if;
721
722 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
723 switch (event) {
724 case SND_SOC_DAPM_PRE_PMU:
725 /* Enable AIF */
726 /* enable the PLL before we use it to clock the DAI */
727 twl4030_apll_enable(w->codec, 1);
728
729 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
730 audio_if | TWL4030_AIF_EN);
731 break;
732 case SND_SOC_DAPM_POST_PMD:
733 /* disable the DAI before we stop it's source PLL */
734 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
735 audio_if & ~TWL4030_AIF_EN);
736 twl4030_apll_enable(w->codec, 0);
737 break;
738 }
739 return 0;
740 }
741
742 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
743 {
744 struct snd_soc_device *socdev = codec->socdev;
745 struct twl4030_setup_data *setup = socdev->codec_data;
746
747 unsigned char hs_gain, hs_pop;
748 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
749 /* Base values for ramp delay calculation: 2^19 - 2^26 */
750 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
751 8388608, 16777216, 33554432, 67108864};
752
753 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
754 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
755
756 /* Enable external mute control, this dramatically reduces
757 * the pop-noise */
758 if (setup && setup->hs_extmute) {
759 if (setup->set_hs_extmute) {
760 setup->set_hs_extmute(1);
761 } else {
762 hs_pop |= TWL4030_EXTMUTE;
763 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
764 }
765 }
766
767 if (ramp) {
768 /* Headset ramp-up according to the TRM */
769 hs_pop |= TWL4030_VMID_EN;
770 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
771 /* Actually write to the register */
772 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
773 hs_gain,
774 TWL4030_REG_HS_GAIN_SET);
775 hs_pop |= TWL4030_RAMP_EN;
776 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
777 /* Wait ramp delay time + 1, so the VMID can settle */
778 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
779 twl4030->sysclk) + 1);
780 } else {
781 /* Headset ramp-down _not_ according to
782 * the TRM, but in a way that it is working */
783 hs_pop &= ~TWL4030_RAMP_EN;
784 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
785 /* Wait ramp delay time + 1, so the VMID can settle */
786 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
787 twl4030->sysclk) + 1);
788 /* Bypass the reg_cache to mute the headset */
789 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
790 hs_gain & (~0x0f),
791 TWL4030_REG_HS_GAIN_SET);
792
793 hs_pop &= ~TWL4030_VMID_EN;
794 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
795 }
796
797 /* Disable external mute */
798 if (setup && setup->hs_extmute) {
799 if (setup->set_hs_extmute) {
800 setup->set_hs_extmute(0);
801 } else {
802 hs_pop &= ~TWL4030_EXTMUTE;
803 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
804 }
805 }
806 }
807
808 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
809 struct snd_kcontrol *kcontrol, int event)
810 {
811 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
812
813 switch (event) {
814 case SND_SOC_DAPM_POST_PMU:
815 /* Do the ramp-up only once */
816 if (!twl4030->hsr_enabled)
817 headset_ramp(w->codec, 1);
818
819 twl4030->hsl_enabled = 1;
820 break;
821 case SND_SOC_DAPM_POST_PMD:
822 /* Do the ramp-down only if both headsetL/R is disabled */
823 if (!twl4030->hsr_enabled)
824 headset_ramp(w->codec, 0);
825
826 twl4030->hsl_enabled = 0;
827 break;
828 }
829 return 0;
830 }
831
832 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
833 struct snd_kcontrol *kcontrol, int event)
834 {
835 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
836
837 switch (event) {
838 case SND_SOC_DAPM_POST_PMU:
839 /* Do the ramp-up only once */
840 if (!twl4030->hsl_enabled)
841 headset_ramp(w->codec, 1);
842
843 twl4030->hsr_enabled = 1;
844 break;
845 case SND_SOC_DAPM_POST_PMD:
846 /* Do the ramp-down only if both headsetL/R is disabled */
847 if (!twl4030->hsl_enabled)
848 headset_ramp(w->codec, 0);
849
850 twl4030->hsr_enabled = 0;
851 break;
852 }
853 return 0;
854 }
855
856 /*
857 * Some of the gain controls in TWL (mostly those which are associated with
858 * the outputs) are implemented in an interesting way:
859 * 0x0 : Power down (mute)
860 * 0x1 : 6dB
861 * 0x2 : 0 dB
862 * 0x3 : -6 dB
863 * Inverting not going to help with these.
864 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
865 */
866 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
867 xinvert, tlv_array) \
868 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
869 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
870 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
871 .tlv.p = (tlv_array), \
872 .info = snd_soc_info_volsw, \
873 .get = snd_soc_get_volsw_twl4030, \
874 .put = snd_soc_put_volsw_twl4030, \
875 .private_value = (unsigned long)&(struct soc_mixer_control) \
876 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
877 .max = xmax, .invert = xinvert} }
878 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
879 xinvert, tlv_array) \
880 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
881 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
882 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
883 .tlv.p = (tlv_array), \
884 .info = snd_soc_info_volsw_2r, \
885 .get = snd_soc_get_volsw_r2_twl4030,\
886 .put = snd_soc_put_volsw_r2_twl4030, \
887 .private_value = (unsigned long)&(struct soc_mixer_control) \
888 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
889 .rshift = xshift, .max = xmax, .invert = xinvert} }
890 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
891 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
892 xinvert, tlv_array)
893
894 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
895 struct snd_ctl_elem_value *ucontrol)
896 {
897 struct soc_mixer_control *mc =
898 (struct soc_mixer_control *)kcontrol->private_value;
899 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
900 unsigned int reg = mc->reg;
901 unsigned int shift = mc->shift;
902 unsigned int rshift = mc->rshift;
903 int max = mc->max;
904 int mask = (1 << fls(max)) - 1;
905
906 ucontrol->value.integer.value[0] =
907 (snd_soc_read(codec, reg) >> shift) & mask;
908 if (ucontrol->value.integer.value[0])
909 ucontrol->value.integer.value[0] =
910 max + 1 - ucontrol->value.integer.value[0];
911
912 if (shift != rshift) {
913 ucontrol->value.integer.value[1] =
914 (snd_soc_read(codec, reg) >> rshift) & mask;
915 if (ucontrol->value.integer.value[1])
916 ucontrol->value.integer.value[1] =
917 max + 1 - ucontrol->value.integer.value[1];
918 }
919
920 return 0;
921 }
922
923 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
924 struct snd_ctl_elem_value *ucontrol)
925 {
926 struct soc_mixer_control *mc =
927 (struct soc_mixer_control *)kcontrol->private_value;
928 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
929 unsigned int reg = mc->reg;
930 unsigned int shift = mc->shift;
931 unsigned int rshift = mc->rshift;
932 int max = mc->max;
933 int mask = (1 << fls(max)) - 1;
934 unsigned short val, val2, val_mask;
935
936 val = (ucontrol->value.integer.value[0] & mask);
937
938 val_mask = mask << shift;
939 if (val)
940 val = max + 1 - val;
941 val = val << shift;
942 if (shift != rshift) {
943 val2 = (ucontrol->value.integer.value[1] & mask);
944 val_mask |= mask << rshift;
945 if (val2)
946 val2 = max + 1 - val2;
947 val |= val2 << rshift;
948 }
949 return snd_soc_update_bits(codec, reg, val_mask, val);
950 }
951
952 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
953 struct snd_ctl_elem_value *ucontrol)
954 {
955 struct soc_mixer_control *mc =
956 (struct soc_mixer_control *)kcontrol->private_value;
957 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
958 unsigned int reg = mc->reg;
959 unsigned int reg2 = mc->rreg;
960 unsigned int shift = mc->shift;
961 int max = mc->max;
962 int mask = (1<<fls(max))-1;
963
964 ucontrol->value.integer.value[0] =
965 (snd_soc_read(codec, reg) >> shift) & mask;
966 ucontrol->value.integer.value[1] =
967 (snd_soc_read(codec, reg2) >> shift) & mask;
968
969 if (ucontrol->value.integer.value[0])
970 ucontrol->value.integer.value[0] =
971 max + 1 - ucontrol->value.integer.value[0];
972 if (ucontrol->value.integer.value[1])
973 ucontrol->value.integer.value[1] =
974 max + 1 - ucontrol->value.integer.value[1];
975
976 return 0;
977 }
978
979 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
980 struct snd_ctl_elem_value *ucontrol)
981 {
982 struct soc_mixer_control *mc =
983 (struct soc_mixer_control *)kcontrol->private_value;
984 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
985 unsigned int reg = mc->reg;
986 unsigned int reg2 = mc->rreg;
987 unsigned int shift = mc->shift;
988 int max = mc->max;
989 int mask = (1 << fls(max)) - 1;
990 int err;
991 unsigned short val, val2, val_mask;
992
993 val_mask = mask << shift;
994 val = (ucontrol->value.integer.value[0] & mask);
995 val2 = (ucontrol->value.integer.value[1] & mask);
996
997 if (val)
998 val = max + 1 - val;
999 if (val2)
1000 val2 = max + 1 - val2;
1001
1002 val = val << shift;
1003 val2 = val2 << shift;
1004
1005 err = snd_soc_update_bits(codec, reg, val_mask, val);
1006 if (err < 0)
1007 return err;
1008
1009 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1010 return err;
1011 }
1012
1013 /* Codec operation modes */
1014 static const char *twl4030_op_modes_texts[] = {
1015 "Option 2 (voice/audio)", "Option 1 (audio)"
1016 };
1017
1018 static const struct soc_enum twl4030_op_modes_enum =
1019 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1020 ARRAY_SIZE(twl4030_op_modes_texts),
1021 twl4030_op_modes_texts);
1022
1023 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1024 struct snd_ctl_elem_value *ucontrol)
1025 {
1026 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1027 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1028 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1029 unsigned short val;
1030 unsigned short mask, bitmask;
1031
1032 if (twl4030->configured) {
1033 printk(KERN_ERR "twl4030 operation mode cannot be "
1034 "changed on-the-fly\n");
1035 return -EBUSY;
1036 }
1037
1038 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1039 ;
1040 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1041 return -EINVAL;
1042
1043 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1044 mask = (bitmask - 1) << e->shift_l;
1045 if (e->shift_l != e->shift_r) {
1046 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1047 return -EINVAL;
1048 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1049 mask |= (bitmask - 1) << e->shift_r;
1050 }
1051
1052 return snd_soc_update_bits(codec, e->reg, mask, val);
1053 }
1054
1055 /*
1056 * FGAIN volume control:
1057 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1058 */
1059 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1060
1061 /*
1062 * CGAIN volume control:
1063 * 0 dB to 12 dB in 6 dB steps
1064 * value 2 and 3 means 12 dB
1065 */
1066 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1067
1068 /*
1069 * Voice Downlink GAIN volume control:
1070 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1071 */
1072 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1073
1074 /*
1075 * Analog playback gain
1076 * -24 dB to 12 dB in 2 dB steps
1077 */
1078 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1079
1080 /*
1081 * Gain controls tied to outputs
1082 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1083 */
1084 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1085
1086 /*
1087 * Gain control for earpiece amplifier
1088 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1089 */
1090 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1091
1092 /*
1093 * Capture gain after the ADCs
1094 * from 0 dB to 31 dB in 1 dB steps
1095 */
1096 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1097
1098 /*
1099 * Gain control for input amplifiers
1100 * 0 dB to 30 dB in 6 dB steps
1101 */
1102 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1103
1104 /* AVADC clock priority */
1105 static const char *twl4030_avadc_clk_priority_texts[] = {
1106 "Voice high priority", "HiFi high priority"
1107 };
1108
1109 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1110 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1111 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1112 twl4030_avadc_clk_priority_texts);
1113
1114 static const char *twl4030_rampdelay_texts[] = {
1115 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1116 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1117 "3495/2581/1748 ms"
1118 };
1119
1120 static const struct soc_enum twl4030_rampdelay_enum =
1121 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1122 ARRAY_SIZE(twl4030_rampdelay_texts),
1123 twl4030_rampdelay_texts);
1124
1125 /* Vibra H-bridge direction mode */
1126 static const char *twl4030_vibradirmode_texts[] = {
1127 "Vibra H-bridge direction", "Audio data MSB",
1128 };
1129
1130 static const struct soc_enum twl4030_vibradirmode_enum =
1131 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1132 ARRAY_SIZE(twl4030_vibradirmode_texts),
1133 twl4030_vibradirmode_texts);
1134
1135 /* Vibra H-bridge direction */
1136 static const char *twl4030_vibradir_texts[] = {
1137 "Positive polarity", "Negative polarity",
1138 };
1139
1140 static const struct soc_enum twl4030_vibradir_enum =
1141 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1142 ARRAY_SIZE(twl4030_vibradir_texts),
1143 twl4030_vibradir_texts);
1144
1145 /* Digimic Left and right swapping */
1146 static const char *twl4030_digimicswap_texts[] = {
1147 "Not swapped", "Swapped",
1148 };
1149
1150 static const struct soc_enum twl4030_digimicswap_enum =
1151 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1152 ARRAY_SIZE(twl4030_digimicswap_texts),
1153 twl4030_digimicswap_texts);
1154
1155 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1156 /* Codec operation mode control */
1157 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1158 snd_soc_get_enum_double,
1159 snd_soc_put_twl4030_opmode_enum_double),
1160
1161 /* Common playback gain controls */
1162 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1163 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1164 0, 0x3f, 0, digital_fine_tlv),
1165 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1166 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1167 0, 0x3f, 0, digital_fine_tlv),
1168
1169 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1170 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1171 6, 0x2, 0, digital_coarse_tlv),
1172 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1173 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1174 6, 0x2, 0, digital_coarse_tlv),
1175
1176 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1177 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1178 3, 0x12, 1, analog_tlv),
1179 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1180 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1181 3, 0x12, 1, analog_tlv),
1182 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1183 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1184 1, 1, 0),
1185 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1186 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1187 1, 1, 0),
1188
1189 /* Common voice downlink gain controls */
1190 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1191 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1192
1193 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1194 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1195
1196 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1197 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1198
1199 /* Separate output gain controls */
1200 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1201 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1202 4, 3, 0, output_tvl),
1203
1204 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1205 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1206
1207 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1208 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1209 4, 3, 0, output_tvl),
1210
1211 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
1212 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
1213
1214 /* Common capture gain controls */
1215 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1216 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1217 0, 0x1f, 0, digital_capture_tlv),
1218 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1219 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1220 0, 0x1f, 0, digital_capture_tlv),
1221
1222 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1223 0, 3, 5, 0, input_gain_tlv),
1224
1225 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1226
1227 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1228
1229 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1230 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1231
1232 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1233 };
1234
1235 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1236 /* Left channel inputs */
1237 SND_SOC_DAPM_INPUT("MAINMIC"),
1238 SND_SOC_DAPM_INPUT("HSMIC"),
1239 SND_SOC_DAPM_INPUT("AUXL"),
1240 SND_SOC_DAPM_INPUT("CARKITMIC"),
1241 /* Right channel inputs */
1242 SND_SOC_DAPM_INPUT("SUBMIC"),
1243 SND_SOC_DAPM_INPUT("AUXR"),
1244 /* Digital microphones (Stereo) */
1245 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1246 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1247
1248 /* Outputs */
1249 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1250 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1251 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1252 SND_SOC_DAPM_OUTPUT("HSOL"),
1253 SND_SOC_DAPM_OUTPUT("HSOR"),
1254 SND_SOC_DAPM_OUTPUT("CARKITL"),
1255 SND_SOC_DAPM_OUTPUT("CARKITR"),
1256 SND_SOC_DAPM_OUTPUT("HFL"),
1257 SND_SOC_DAPM_OUTPUT("HFR"),
1258 SND_SOC_DAPM_OUTPUT("VIBRA"),
1259
1260 /* AIF and APLL clocks for running DAIs (including loopback) */
1261 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1262 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1263 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1264
1265 /* DACs */
1266 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
1267 SND_SOC_NOPM, 0, 0),
1268 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
1269 SND_SOC_NOPM, 0, 0),
1270 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
1271 SND_SOC_NOPM, 0, 0),
1272 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
1273 SND_SOC_NOPM, 0, 0),
1274 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
1275 SND_SOC_NOPM, 0, 0),
1276
1277 /* Analog bypasses */
1278 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_abypassr1_control),
1280 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_abypassl1_control),
1282 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1283 &twl4030_dapm_abypassr2_control),
1284 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_abypassl2_control),
1286 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1287 &twl4030_dapm_abypassv_control),
1288
1289 /* Master analog loopback switch */
1290 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1291 NULL, 0),
1292
1293 /* Digital bypasses */
1294 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1295 &twl4030_dapm_dbypassl_control),
1296 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1297 &twl4030_dapm_dbypassr_control),
1298 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1299 &twl4030_dapm_dbypassv_control),
1300
1301 /* Digital mixers, power control for the physical DACs */
1302 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1303 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1305 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1306 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1307 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1308 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1309 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1310 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1311 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1312
1313 /* Analog mixers, power control for the physical PGAs */
1314 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1315 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1316 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1317 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1318 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1319 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1320 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1321 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1322 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1323 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1324
1325 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1326 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1327
1328 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1329 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1330
1331 /* Output MIXER controls */
1332 /* Earpiece */
1333 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1334 &twl4030_dapm_earpiece_controls[0],
1335 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1336 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1337 0, 0, NULL, 0, earpiecepga_event,
1338 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1339 /* PreDrivL/R */
1340 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1341 &twl4030_dapm_predrivel_controls[0],
1342 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1343 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1344 0, 0, NULL, 0, predrivelpga_event,
1345 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1346 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1347 &twl4030_dapm_predriver_controls[0],
1348 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1349 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1350 0, 0, NULL, 0, predriverpga_event,
1351 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1352 /* HeadsetL/R */
1353 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1354 &twl4030_dapm_hsol_controls[0],
1355 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1356 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1357 0, 0, NULL, 0, headsetlpga_event,
1358 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1359 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1360 &twl4030_dapm_hsor_controls[0],
1361 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1362 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1363 0, 0, NULL, 0, headsetrpga_event,
1364 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1365 /* CarkitL/R */
1366 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1367 &twl4030_dapm_carkitl_controls[0],
1368 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1369 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1370 0, 0, NULL, 0, carkitlpga_event,
1371 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1372 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1373 &twl4030_dapm_carkitr_controls[0],
1374 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1375 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1376 0, 0, NULL, 0, carkitrpga_event,
1377 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1378
1379 /* Output MUX controls */
1380 /* HandsfreeL/R */
1381 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1382 &twl4030_dapm_handsfreel_control),
1383 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1384 &twl4030_dapm_handsfreelmute_control),
1385 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1386 0, 0, NULL, 0, handsfreelpga_event,
1387 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1388 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1389 &twl4030_dapm_handsfreer_control),
1390 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1391 &twl4030_dapm_handsfreermute_control),
1392 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1393 0, 0, NULL, 0, handsfreerpga_event,
1394 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1395 /* Vibra */
1396 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1397 &twl4030_dapm_vibra_control, vibramux_event,
1398 SND_SOC_DAPM_PRE_PMU),
1399 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1400 &twl4030_dapm_vibrapath_control),
1401
1402 /* Introducing four virtual ADC, since TWL4030 have four channel for
1403 capture */
1404 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1405 SND_SOC_NOPM, 0, 0),
1406 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1407 SND_SOC_NOPM, 0, 0),
1408 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1409 SND_SOC_NOPM, 0, 0),
1410 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1411 SND_SOC_NOPM, 0, 0),
1412
1413 /* Analog/Digital mic path selection.
1414 TX1 Left/Right: either analog Left/Right or Digimic0
1415 TX2 Left/Right: either analog Left/Right or Digimic1 */
1416 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1417 &twl4030_dapm_micpathtx1_control, micpath_event,
1418 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1419 SND_SOC_DAPM_POST_REG),
1420 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1421 &twl4030_dapm_micpathtx2_control, micpath_event,
1422 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1423 SND_SOC_DAPM_POST_REG),
1424
1425 /* Analog input mixers for the capture amplifiers */
1426 SND_SOC_DAPM_MIXER("Analog Left",
1427 TWL4030_REG_ANAMICL, 4, 0,
1428 &twl4030_dapm_analoglmic_controls[0],
1429 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1430 SND_SOC_DAPM_MIXER("Analog Right",
1431 TWL4030_REG_ANAMICR, 4, 0,
1432 &twl4030_dapm_analogrmic_controls[0],
1433 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1434
1435 SND_SOC_DAPM_PGA("ADC Physical Left",
1436 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1437 SND_SOC_DAPM_PGA("ADC Physical Right",
1438 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1439
1440 SND_SOC_DAPM_PGA("Digimic0 Enable",
1441 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1442 SND_SOC_DAPM_PGA("Digimic1 Enable",
1443 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1444
1445 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1446 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1447 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1448
1449 };
1450
1451 static const struct snd_soc_dapm_route intercon[] = {
1452 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1453 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1454 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1455 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1456 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1457
1458 /* Supply for the digital part (APLL) */
1459 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1460
1461 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1462 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1463 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1464 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1465
1466 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1467 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1468 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1469 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1470 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1471
1472 /* Internal playback routings */
1473 /* Earpiece */
1474 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1475 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1476 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1477 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1478 {"Earpiece PGA", NULL, "Earpiece Mixer"},
1479 /* PreDrivL */
1480 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1481 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1482 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1483 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1484 {"PredriveL PGA", NULL, "PredriveL Mixer"},
1485 /* PreDrivR */
1486 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1487 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1488 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1489 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1490 {"PredriveR PGA", NULL, "PredriveR Mixer"},
1491 /* HeadsetL */
1492 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1493 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1494 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1495 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1496 /* HeadsetR */
1497 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1498 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1499 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1500 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1501 /* CarkitL */
1502 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1503 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1504 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1505 {"CarkitL PGA", NULL, "CarkitL Mixer"},
1506 /* CarkitR */
1507 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1508 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1509 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1510 {"CarkitR PGA", NULL, "CarkitR Mixer"},
1511 /* HandsfreeL */
1512 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1513 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1514 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1515 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1516 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1517 {"HandsfreeL PGA", NULL, "HandsfreeL"},
1518 /* HandsfreeR */
1519 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1520 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1521 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1522 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1523 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1524 {"HandsfreeR PGA", NULL, "HandsfreeR"},
1525 /* Vibra */
1526 {"Vibra Mux", "AudioL1", "DAC Left1"},
1527 {"Vibra Mux", "AudioR1", "DAC Right1"},
1528 {"Vibra Mux", "AudioL2", "DAC Left2"},
1529 {"Vibra Mux", "AudioR2", "DAC Right2"},
1530
1531 /* outputs */
1532 /* Must be always connected (for AIF and APLL) */
1533 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1534 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1535 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1536 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1537 /* Must be always connected (for APLL) */
1538 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1539 /* Physical outputs */
1540 {"EARPIECE", NULL, "Earpiece PGA"},
1541 {"PREDRIVEL", NULL, "PredriveL PGA"},
1542 {"PREDRIVER", NULL, "PredriveR PGA"},
1543 {"HSOL", NULL, "HeadsetL PGA"},
1544 {"HSOR", NULL, "HeadsetR PGA"},
1545 {"CARKITL", NULL, "CarkitL PGA"},
1546 {"CARKITR", NULL, "CarkitR PGA"},
1547 {"HFL", NULL, "HandsfreeL PGA"},
1548 {"HFR", NULL, "HandsfreeR PGA"},
1549 {"Vibra Route", "Audio", "Vibra Mux"},
1550 {"VIBRA", NULL, "Vibra Route"},
1551
1552 /* Capture path */
1553 /* Must be always connected (for AIF and APLL) */
1554 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1555 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1556 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1557 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1558 /* Physical inputs */
1559 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1560 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1561 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1562 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1563
1564 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1565 {"Analog Right", "AUXR Capture Switch", "AUXR"},
1566
1567 {"ADC Physical Left", NULL, "Analog Left"},
1568 {"ADC Physical Right", NULL, "Analog Right"},
1569
1570 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1571 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1572
1573 /* TX1 Left capture path */
1574 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1575 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1576 /* TX1 Right capture path */
1577 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1578 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1579 /* TX2 Left capture path */
1580 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1581 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1582 /* TX2 Right capture path */
1583 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1584 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1585
1586 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1587 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1588 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1589 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1590
1591 {"ADC Virtual Left1", NULL, "AIF Enable"},
1592 {"ADC Virtual Right1", NULL, "AIF Enable"},
1593 {"ADC Virtual Left2", NULL, "AIF Enable"},
1594 {"ADC Virtual Right2", NULL, "AIF Enable"},
1595
1596 /* Analog bypass routes */
1597 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1598 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1599 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1600 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1601 {"Voice Analog Loopback", "Switch", "Analog Left"},
1602
1603 /* Supply for the Analog loopbacks */
1604 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1605 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1606 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1607 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1608 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1609
1610 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1611 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1612 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1613 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1614 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1615
1616 /* Digital bypass routes */
1617 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1618 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1619 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1620
1621 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1622 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1623 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1624
1625 };
1626
1627 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1628 {
1629 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1630 ARRAY_SIZE(twl4030_dapm_widgets));
1631
1632 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1633
1634 return 0;
1635 }
1636
1637 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1638 enum snd_soc_bias_level level)
1639 {
1640 switch (level) {
1641 case SND_SOC_BIAS_ON:
1642 break;
1643 case SND_SOC_BIAS_PREPARE:
1644 break;
1645 case SND_SOC_BIAS_STANDBY:
1646 if (codec->bias_level == SND_SOC_BIAS_OFF)
1647 twl4030_codec_enable(codec, 1);
1648 break;
1649 case SND_SOC_BIAS_OFF:
1650 twl4030_codec_enable(codec, 0);
1651 break;
1652 }
1653 codec->bias_level = level;
1654
1655 return 0;
1656 }
1657
1658 static void twl4030_constraints(struct twl4030_priv *twl4030,
1659 struct snd_pcm_substream *mst_substream)
1660 {
1661 struct snd_pcm_substream *slv_substream;
1662
1663 /* Pick the stream, which need to be constrained */
1664 if (mst_substream == twl4030->master_substream)
1665 slv_substream = twl4030->slave_substream;
1666 else if (mst_substream == twl4030->slave_substream)
1667 slv_substream = twl4030->master_substream;
1668 else /* This should not happen.. */
1669 return;
1670
1671 /* Set the constraints according to the already configured stream */
1672 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1673 SNDRV_PCM_HW_PARAM_RATE,
1674 twl4030->rate,
1675 twl4030->rate);
1676
1677 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1678 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1679 twl4030->sample_bits,
1680 twl4030->sample_bits);
1681
1682 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1683 SNDRV_PCM_HW_PARAM_CHANNELS,
1684 twl4030->channels,
1685 twl4030->channels);
1686 }
1687
1688 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1689 * capture has to be enabled/disabled. */
1690 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1691 int enable)
1692 {
1693 u8 reg, mask;
1694
1695 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1696
1697 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1698 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1699 else
1700 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1701
1702 if (enable)
1703 reg |= mask;
1704 else
1705 reg &= ~mask;
1706
1707 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1708 }
1709
1710 static int twl4030_startup(struct snd_pcm_substream *substream,
1711 struct snd_soc_dai *dai)
1712 {
1713 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1714 struct snd_soc_device *socdev = rtd->socdev;
1715 struct snd_soc_codec *codec = socdev->card->codec;
1716 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1717
1718 if (twl4030->master_substream) {
1719 twl4030->slave_substream = substream;
1720 /* The DAI has one configuration for playback and capture, so
1721 * if the DAI has been already configured then constrain this
1722 * substream to match it. */
1723 if (twl4030->configured)
1724 twl4030_constraints(twl4030, twl4030->master_substream);
1725 } else {
1726 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1727 TWL4030_OPTION_1)) {
1728 /* In option2 4 channel is not supported, set the
1729 * constraint for the first stream for channels, the
1730 * second stream will 'inherit' this cosntraint */
1731 snd_pcm_hw_constraint_minmax(substream->runtime,
1732 SNDRV_PCM_HW_PARAM_CHANNELS,
1733 2, 2);
1734 }
1735 twl4030->master_substream = substream;
1736 }
1737
1738 return 0;
1739 }
1740
1741 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1742 struct snd_soc_dai *dai)
1743 {
1744 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1745 struct snd_soc_device *socdev = rtd->socdev;
1746 struct snd_soc_codec *codec = socdev->card->codec;
1747 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1748
1749 if (twl4030->master_substream == substream)
1750 twl4030->master_substream = twl4030->slave_substream;
1751
1752 twl4030->slave_substream = NULL;
1753
1754 /* If all streams are closed, or the remaining stream has not yet
1755 * been configured than set the DAI as not configured. */
1756 if (!twl4030->master_substream)
1757 twl4030->configured = 0;
1758 else if (!twl4030->master_substream->runtime->channels)
1759 twl4030->configured = 0;
1760
1761 /* If the closing substream had 4 channel, do the necessary cleanup */
1762 if (substream->runtime->channels == 4)
1763 twl4030_tdm_enable(codec, substream->stream, 0);
1764 }
1765
1766 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1767 struct snd_pcm_hw_params *params,
1768 struct snd_soc_dai *dai)
1769 {
1770 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1771 struct snd_soc_device *socdev = rtd->socdev;
1772 struct snd_soc_codec *codec = socdev->card->codec;
1773 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1774 u8 mode, old_mode, format, old_format;
1775
1776 /* If the substream has 4 channel, do the necessary setup */
1777 if (params_channels(params) == 4) {
1778 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1779 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1780
1781 /* Safety check: are we in the correct operating mode and
1782 * the interface is in TDM mode? */
1783 if ((mode & TWL4030_OPTION_1) &&
1784 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1785 twl4030_tdm_enable(codec, substream->stream, 1);
1786 else
1787 return -EINVAL;
1788 }
1789
1790 if (twl4030->configured)
1791 /* Ignoring hw_params for already configured DAI */
1792 return 0;
1793
1794 /* bit rate */
1795 old_mode = twl4030_read_reg_cache(codec,
1796 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1797 mode = old_mode & ~TWL4030_APLL_RATE;
1798
1799 switch (params_rate(params)) {
1800 case 8000:
1801 mode |= TWL4030_APLL_RATE_8000;
1802 break;
1803 case 11025:
1804 mode |= TWL4030_APLL_RATE_11025;
1805 break;
1806 case 12000:
1807 mode |= TWL4030_APLL_RATE_12000;
1808 break;
1809 case 16000:
1810 mode |= TWL4030_APLL_RATE_16000;
1811 break;
1812 case 22050:
1813 mode |= TWL4030_APLL_RATE_22050;
1814 break;
1815 case 24000:
1816 mode |= TWL4030_APLL_RATE_24000;
1817 break;
1818 case 32000:
1819 mode |= TWL4030_APLL_RATE_32000;
1820 break;
1821 case 44100:
1822 mode |= TWL4030_APLL_RATE_44100;
1823 break;
1824 case 48000:
1825 mode |= TWL4030_APLL_RATE_48000;
1826 break;
1827 case 96000:
1828 mode |= TWL4030_APLL_RATE_96000;
1829 break;
1830 default:
1831 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1832 params_rate(params));
1833 return -EINVAL;
1834 }
1835
1836 /* sample size */
1837 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1838 format = old_format;
1839 format &= ~TWL4030_DATA_WIDTH;
1840 switch (params_format(params)) {
1841 case SNDRV_PCM_FORMAT_S16_LE:
1842 format |= TWL4030_DATA_WIDTH_16S_16W;
1843 break;
1844 case SNDRV_PCM_FORMAT_S24_LE:
1845 format |= TWL4030_DATA_WIDTH_32S_24W;
1846 break;
1847 default:
1848 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1849 params_format(params));
1850 return -EINVAL;
1851 }
1852
1853 if (format != old_format || mode != old_mode) {
1854 if (twl4030->codec_powered) {
1855 /*
1856 * If the codec is powered, than we need to toggle the
1857 * codec power.
1858 */
1859 twl4030_codec_enable(codec, 0);
1860 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1861 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1862 twl4030_codec_enable(codec, 1);
1863 } else {
1864 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1865 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1866 }
1867 }
1868
1869 /* Store the important parameters for the DAI configuration and set
1870 * the DAI as configured */
1871 twl4030->configured = 1;
1872 twl4030->rate = params_rate(params);
1873 twl4030->sample_bits = hw_param_interval(params,
1874 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1875 twl4030->channels = params_channels(params);
1876
1877 /* If both playback and capture streams are open, and one of them
1878 * is setting the hw parameters right now (since we are here), set
1879 * constraints to the other stream to match the current one. */
1880 if (twl4030->slave_substream)
1881 twl4030_constraints(twl4030, substream);
1882
1883 return 0;
1884 }
1885
1886 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1887 int clk_id, unsigned int freq, int dir)
1888 {
1889 struct snd_soc_codec *codec = codec_dai->codec;
1890 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1891
1892 switch (freq) {
1893 case 19200000:
1894 case 26000000:
1895 case 38400000:
1896 break;
1897 default:
1898 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
1899 return -EINVAL;
1900 }
1901
1902 if ((freq / 1000) != twl4030->sysclk) {
1903 dev_err(codec->dev,
1904 "Mismatch in APLL mclk: %u (configured: %u)\n",
1905 freq, twl4030->sysclk * 1000);
1906 return -EINVAL;
1907 }
1908
1909 return 0;
1910 }
1911
1912 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1913 unsigned int fmt)
1914 {
1915 struct snd_soc_codec *codec = codec_dai->codec;
1916 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1917 u8 old_format, format;
1918
1919 /* get format */
1920 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1921 format = old_format;
1922
1923 /* set master/slave audio interface */
1924 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1925 case SND_SOC_DAIFMT_CBM_CFM:
1926 format &= ~(TWL4030_AIF_SLAVE_EN);
1927 format &= ~(TWL4030_CLK256FS_EN);
1928 break;
1929 case SND_SOC_DAIFMT_CBS_CFS:
1930 format |= TWL4030_AIF_SLAVE_EN;
1931 format |= TWL4030_CLK256FS_EN;
1932 break;
1933 default:
1934 return -EINVAL;
1935 }
1936
1937 /* interface format */
1938 format &= ~TWL4030_AIF_FORMAT;
1939 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1940 case SND_SOC_DAIFMT_I2S:
1941 format |= TWL4030_AIF_FORMAT_CODEC;
1942 break;
1943 case SND_SOC_DAIFMT_DSP_A:
1944 format |= TWL4030_AIF_FORMAT_TDM;
1945 break;
1946 default:
1947 return -EINVAL;
1948 }
1949
1950 if (format != old_format) {
1951 if (twl4030->codec_powered) {
1952 /*
1953 * If the codec is powered, than we need to toggle the
1954 * codec power.
1955 */
1956 twl4030_codec_enable(codec, 0);
1957 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1958 twl4030_codec_enable(codec, 1);
1959 } else {
1960 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1961 }
1962 }
1963
1964 return 0;
1965 }
1966
1967 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1968 {
1969 struct snd_soc_codec *codec = dai->codec;
1970 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1971
1972 if (tristate)
1973 reg |= TWL4030_AIF_TRI_EN;
1974 else
1975 reg &= ~TWL4030_AIF_TRI_EN;
1976
1977 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1978 }
1979
1980 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1981 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1982 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1983 int enable)
1984 {
1985 u8 reg, mask;
1986
1987 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1988
1989 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1990 mask = TWL4030_ARXL1_VRX_EN;
1991 else
1992 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1993
1994 if (enable)
1995 reg |= mask;
1996 else
1997 reg &= ~mask;
1998
1999 twl4030_write(codec, TWL4030_REG_OPTION, reg);
2000 }
2001
2002 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2003 struct snd_soc_dai *dai)
2004 {
2005 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2006 struct snd_soc_device *socdev = rtd->socdev;
2007 struct snd_soc_codec *codec = socdev->card->codec;
2008 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2009 u8 mode;
2010
2011 /* If the system master clock is not 26MHz, the voice PCM interface is
2012 * not avilable.
2013 */
2014 if (twl4030->sysclk != 26000) {
2015 dev_err(codec->dev, "The board is configured for %u Hz, while"
2016 "the Voice interface needs 26MHz APLL mclk\n",
2017 twl4030->sysclk * 1000);
2018 return -EINVAL;
2019 }
2020
2021 /* If the codec mode is not option2, the voice PCM interface is not
2022 * avilable.
2023 */
2024 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2025 & TWL4030_OPT_MODE;
2026
2027 if (mode != TWL4030_OPTION_2) {
2028 printk(KERN_ERR "TWL4030 voice startup: "
2029 "the codec mode is not option2\n");
2030 return -EINVAL;
2031 }
2032
2033 return 0;
2034 }
2035
2036 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2037 struct snd_soc_dai *dai)
2038 {
2039 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2040 struct snd_soc_device *socdev = rtd->socdev;
2041 struct snd_soc_codec *codec = socdev->card->codec;
2042
2043 /* Enable voice digital filters */
2044 twl4030_voice_enable(codec, substream->stream, 0);
2045 }
2046
2047 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2048 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2049 {
2050 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2051 struct snd_soc_device *socdev = rtd->socdev;
2052 struct snd_soc_codec *codec = socdev->card->codec;
2053 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2054 u8 old_mode, mode;
2055
2056 /* Enable voice digital filters */
2057 twl4030_voice_enable(codec, substream->stream, 1);
2058
2059 /* bit rate */
2060 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2061 & ~(TWL4030_CODECPDZ);
2062 mode = old_mode;
2063
2064 switch (params_rate(params)) {
2065 case 8000:
2066 mode &= ~(TWL4030_SEL_16K);
2067 break;
2068 case 16000:
2069 mode |= TWL4030_SEL_16K;
2070 break;
2071 default:
2072 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2073 params_rate(params));
2074 return -EINVAL;
2075 }
2076
2077 if (mode != old_mode) {
2078 if (twl4030->codec_powered) {
2079 /*
2080 * If the codec is powered, than we need to toggle the
2081 * codec power.
2082 */
2083 twl4030_codec_enable(codec, 0);
2084 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2085 twl4030_codec_enable(codec, 1);
2086 } else {
2087 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2088 }
2089 }
2090
2091 return 0;
2092 }
2093
2094 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2095 int clk_id, unsigned int freq, int dir)
2096 {
2097 struct snd_soc_codec *codec = codec_dai->codec;
2098 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2099
2100 if (freq != 26000000) {
2101 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2102 "interface needs 26MHz APLL mclk\n", freq);
2103 return -EINVAL;
2104 }
2105 if ((freq / 1000) != twl4030->sysclk) {
2106 dev_err(codec->dev,
2107 "Mismatch in APLL mclk: %u (configured: %u)\n",
2108 freq, twl4030->sysclk * 1000);
2109 return -EINVAL;
2110 }
2111 return 0;
2112 }
2113
2114 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2115 unsigned int fmt)
2116 {
2117 struct snd_soc_codec *codec = codec_dai->codec;
2118 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2119 u8 old_format, format;
2120
2121 /* get format */
2122 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2123 format = old_format;
2124
2125 /* set master/slave audio interface */
2126 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2127 case SND_SOC_DAIFMT_CBM_CFM:
2128 format &= ~(TWL4030_VIF_SLAVE_EN);
2129 break;
2130 case SND_SOC_DAIFMT_CBS_CFS:
2131 format |= TWL4030_VIF_SLAVE_EN;
2132 break;
2133 default:
2134 return -EINVAL;
2135 }
2136
2137 /* clock inversion */
2138 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2139 case SND_SOC_DAIFMT_IB_NF:
2140 format &= ~(TWL4030_VIF_FORMAT);
2141 break;
2142 case SND_SOC_DAIFMT_NB_IF:
2143 format |= TWL4030_VIF_FORMAT;
2144 break;
2145 default:
2146 return -EINVAL;
2147 }
2148
2149 if (format != old_format) {
2150 if (twl4030->codec_powered) {
2151 /*
2152 * If the codec is powered, than we need to toggle the
2153 * codec power.
2154 */
2155 twl4030_codec_enable(codec, 0);
2156 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2157 twl4030_codec_enable(codec, 1);
2158 } else {
2159 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2160 }
2161 }
2162
2163 return 0;
2164 }
2165
2166 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2167 {
2168 struct snd_soc_codec *codec = dai->codec;
2169 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2170
2171 if (tristate)
2172 reg |= TWL4030_VIF_TRI_EN;
2173 else
2174 reg &= ~TWL4030_VIF_TRI_EN;
2175
2176 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2177 }
2178
2179 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2180 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2181
2182 static struct snd_soc_dai_ops twl4030_dai_ops = {
2183 .startup = twl4030_startup,
2184 .shutdown = twl4030_shutdown,
2185 .hw_params = twl4030_hw_params,
2186 .set_sysclk = twl4030_set_dai_sysclk,
2187 .set_fmt = twl4030_set_dai_fmt,
2188 .set_tristate = twl4030_set_tristate,
2189 };
2190
2191 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2192 .startup = twl4030_voice_startup,
2193 .shutdown = twl4030_voice_shutdown,
2194 .hw_params = twl4030_voice_hw_params,
2195 .set_sysclk = twl4030_voice_set_dai_sysclk,
2196 .set_fmt = twl4030_voice_set_dai_fmt,
2197 .set_tristate = twl4030_voice_set_tristate,
2198 };
2199
2200 struct snd_soc_dai twl4030_dai[] = {
2201 {
2202 .name = "twl4030",
2203 .playback = {
2204 .stream_name = "HiFi Playback",
2205 .channels_min = 2,
2206 .channels_max = 4,
2207 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2208 .formats = TWL4030_FORMATS,},
2209 .capture = {
2210 .stream_name = "Capture",
2211 .channels_min = 2,
2212 .channels_max = 4,
2213 .rates = TWL4030_RATES,
2214 .formats = TWL4030_FORMATS,},
2215 .ops = &twl4030_dai_ops,
2216 },
2217 {
2218 .name = "twl4030 Voice",
2219 .playback = {
2220 .stream_name = "Voice Playback",
2221 .channels_min = 1,
2222 .channels_max = 1,
2223 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2224 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2225 .capture = {
2226 .stream_name = "Capture",
2227 .channels_min = 1,
2228 .channels_max = 2,
2229 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2230 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2231 .ops = &twl4030_dai_voice_ops,
2232 },
2233 };
2234 EXPORT_SYMBOL_GPL(twl4030_dai);
2235
2236 static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
2237 {
2238 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2239 struct snd_soc_codec *codec = socdev->card->codec;
2240
2241 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2242
2243 return 0;
2244 }
2245
2246 static int twl4030_soc_resume(struct platform_device *pdev)
2247 {
2248 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2249 struct snd_soc_codec *codec = socdev->card->codec;
2250
2251 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2252 return 0;
2253 }
2254
2255 static struct snd_soc_codec *twl4030_codec;
2256
2257 static int twl4030_soc_probe(struct platform_device *pdev)
2258 {
2259 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2260 struct snd_soc_codec *codec;
2261 int ret;
2262
2263 BUG_ON(!twl4030_codec);
2264
2265 codec = twl4030_codec;
2266 socdev->card->codec = codec;
2267
2268 twl4030_init_chip(pdev);
2269
2270 /* register pcms */
2271 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2272 if (ret < 0) {
2273 dev_err(&pdev->dev, "failed to create pcms\n");
2274 return ret;
2275 }
2276
2277 snd_soc_add_controls(codec, twl4030_snd_controls,
2278 ARRAY_SIZE(twl4030_snd_controls));
2279 twl4030_add_widgets(codec);
2280
2281 return 0;
2282 }
2283
2284 static int twl4030_soc_remove(struct platform_device *pdev)
2285 {
2286 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2287 struct snd_soc_codec *codec = socdev->card->codec;
2288
2289 /* Reset registers to their chip default before leaving */
2290 twl4030_reset_registers(codec);
2291 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2292 snd_soc_free_pcms(socdev);
2293 snd_soc_dapm_free(socdev);
2294
2295 return 0;
2296 }
2297
2298 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2299 {
2300 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
2301 struct snd_soc_codec *codec;
2302 struct twl4030_priv *twl4030;
2303 int ret;
2304
2305 if (!pdata) {
2306 dev_err(&pdev->dev, "platform_data is missing\n");
2307 return -EINVAL;
2308 }
2309
2310 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2311 if (twl4030 == NULL) {
2312 dev_err(&pdev->dev, "Can not allocate memroy\n");
2313 return -ENOMEM;
2314 }
2315
2316 codec = &twl4030->codec;
2317 snd_soc_codec_set_drvdata(codec, twl4030);
2318 codec->dev = &pdev->dev;
2319 twl4030_dai[0].dev = &pdev->dev;
2320 twl4030_dai[1].dev = &pdev->dev;
2321
2322 mutex_init(&codec->mutex);
2323 INIT_LIST_HEAD(&codec->dapm_widgets);
2324 INIT_LIST_HEAD(&codec->dapm_paths);
2325
2326 codec->name = "twl4030";
2327 codec->owner = THIS_MODULE;
2328 codec->read = twl4030_read_reg_cache;
2329 codec->write = twl4030_write;
2330 codec->set_bias_level = twl4030_set_bias_level;
2331 codec->idle_bias_off = 1;
2332 codec->dai = twl4030_dai;
2333 codec->num_dai = ARRAY_SIZE(twl4030_dai);
2334 codec->reg_cache_size = sizeof(twl4030_reg);
2335 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2336 GFP_KERNEL);
2337 if (codec->reg_cache == NULL) {
2338 ret = -ENOMEM;
2339 goto error_cache;
2340 }
2341
2342 platform_set_drvdata(pdev, twl4030);
2343 twl4030_codec = codec;
2344
2345 /* Set the defaults, and power up the codec */
2346 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
2347 codec->bias_level = SND_SOC_BIAS_OFF;
2348
2349 ret = snd_soc_register_codec(codec);
2350 if (ret != 0) {
2351 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2352 goto error_codec;
2353 }
2354
2355 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2356 if (ret != 0) {
2357 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2358 snd_soc_unregister_codec(codec);
2359 goto error_codec;
2360 }
2361
2362 return 0;
2363
2364 error_codec:
2365 twl4030_codec_enable(codec, 0);
2366 kfree(codec->reg_cache);
2367 error_cache:
2368 kfree(twl4030);
2369 return ret;
2370 }
2371
2372 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2373 {
2374 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
2375
2376 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2377 snd_soc_unregister_codec(&twl4030->codec);
2378 kfree(twl4030->codec.reg_cache);
2379 kfree(twl4030);
2380
2381 twl4030_codec = NULL;
2382 return 0;
2383 }
2384
2385 MODULE_ALIAS("platform:twl4030_codec_audio");
2386
2387 static struct platform_driver twl4030_codec_driver = {
2388 .probe = twl4030_codec_probe,
2389 .remove = __devexit_p(twl4030_codec_remove),
2390 .driver = {
2391 .name = "twl4030_codec_audio",
2392 .owner = THIS_MODULE,
2393 },
2394 };
2395
2396 static int __init twl4030_modinit(void)
2397 {
2398 return platform_driver_register(&twl4030_codec_driver);
2399 }
2400 module_init(twl4030_modinit);
2401
2402 static void __exit twl4030_exit(void)
2403 {
2404 platform_driver_unregister(&twl4030_codec_driver);
2405 }
2406 module_exit(twl4030_exit);
2407
2408 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2409 .probe = twl4030_soc_probe,
2410 .remove = twl4030_soc_remove,
2411 .suspend = twl4030_soc_suspend,
2412 .resume = twl4030_soc_resume,
2413 };
2414 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2415
2416 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2417 MODULE_AUTHOR("Steve Sakoman");
2418 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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