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ASoC: TWL4030: Add 4 channel TDM support
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x91, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 };
119
120 /* codec private data */
121 struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
133 };
134
135 /*
136 * read twl4030 register cache
137 */
138 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140 {
141 u8 *cache = codec->reg_cache;
142
143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
146 return cache[reg];
147 }
148
149 /*
150 * write twl4030 register cache
151 */
152 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154 {
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160 }
161
162 /*
163 * write to the twl4030 register space
164 */
165 static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167 {
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170 }
171
172 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
173 {
174 struct twl4030_priv *twl4030 = codec->private_data;
175 u8 mode;
176
177 if (enable == twl4030->codec_powered)
178 return;
179
180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
185
186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
187 twl4030->codec_powered = enable;
188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192 }
193
194 static void twl4030_init_chip(struct snd_soc_codec *codec)
195 {
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
199 twl4030_codec_enable(codec, 0);
200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205 }
206
207 static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208 {
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
240 reg_val & (~TWL4030_PRECKL_GAIN),
241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272 }
273
274 static void twl4030_power_up(struct snd_soc_codec *codec)
275 {
276 struct twl4030_priv *twl4030 = codec->private_data;
277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
280 if (twl4030->codec_powered)
281 return;
282
283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312 }
313
314 /*
315 * Unconditional power down
316 */
317 static void twl4030_power_down(struct snd_soc_codec *codec)
318 {
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321 }
322
323 /* Earpiece */
324 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
326 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
327 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
328 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
329 };
330
331 /* PreDrive Left */
332 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
337 };
338
339 /* PreDrive Right */
340 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
345 };
346
347 /* Headset Left */
348 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
352 };
353
354 /* Headset Right */
355 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
357 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
358 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
359 };
360
361 /* Carkit Left */
362 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
366 };
367
368 /* Carkit Right */
369 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
370 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
371 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
372 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
373 };
374
375 /* Handsfree Left */
376 static const char *twl4030_handsfreel_texts[] =
377 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
378
379 static const struct soc_enum twl4030_handsfreel_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
381 ARRAY_SIZE(twl4030_handsfreel_texts),
382 twl4030_handsfreel_texts);
383
384 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
385 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
386
387 /* Handsfree Right */
388 static const char *twl4030_handsfreer_texts[] =
389 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
390
391 static const struct soc_enum twl4030_handsfreer_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreer_texts),
394 twl4030_handsfreer_texts);
395
396 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
397 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
398
399 /* Left analog microphone selection */
400 static const char *twl4030_analoglmic_texts[] =
401 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
402
403 static const unsigned int twl4030_analoglmic_values[] =
404 {0x0, 0x1, 0x2, 0x4, 0x8};
405
406 static const struct soc_enum twl4030_analoglmic_enum =
407 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
408 ARRAY_SIZE(twl4030_analoglmic_texts),
409 twl4030_analoglmic_texts,
410 twl4030_analoglmic_values);
411
412 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
413 SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
414
415 /* Right analog microphone selection */
416 static const char *twl4030_analogrmic_texts[] =
417 {"Off", "Sub mic", "AUXR"};
418
419 static const unsigned int twl4030_analogrmic_values[] =
420 {0x0, 0x1, 0x4};
421
422 static const struct soc_enum twl4030_analogrmic_enum =
423 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
424 ARRAY_SIZE(twl4030_analogrmic_texts),
425 twl4030_analogrmic_texts,
426 twl4030_analogrmic_values);
427
428 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
429 SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
430
431 /* TX1 L/R Analog/Digital microphone selection */
432 static const char *twl4030_micpathtx1_texts[] =
433 {"Analog", "Digimic0"};
434
435 static const struct soc_enum twl4030_micpathtx1_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
437 ARRAY_SIZE(twl4030_micpathtx1_texts),
438 twl4030_micpathtx1_texts);
439
440 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
441 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
442
443 /* TX2 L/R Analog/Digital microphone selection */
444 static const char *twl4030_micpathtx2_texts[] =
445 {"Analog", "Digimic1"};
446
447 static const struct soc_enum twl4030_micpathtx2_enum =
448 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
449 ARRAY_SIZE(twl4030_micpathtx2_texts),
450 twl4030_micpathtx2_texts);
451
452 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
453 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
454
455 /* Analog bypass for AudioR1 */
456 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
457 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
458
459 /* Analog bypass for AudioL1 */
460 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
461 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
462
463 /* Analog bypass for AudioR2 */
464 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
465 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
466
467 /* Analog bypass for AudioL2 */
468 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
469 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
470
471 /* Digital bypass gain, 0 mutes the bypass */
472 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
473 TLV_DB_RANGE_HEAD(2),
474 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
475 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
476 };
477
478 /* Digital bypass left (TX1L -> RX2L) */
479 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
480 SOC_DAPM_SINGLE_TLV("Volume",
481 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
482 twl4030_dapm_dbypass_tlv);
483
484 /* Digital bypass right (TX1R -> RX2R) */
485 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
486 SOC_DAPM_SINGLE_TLV("Volume",
487 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
488 twl4030_dapm_dbypass_tlv);
489
490 static int micpath_event(struct snd_soc_dapm_widget *w,
491 struct snd_kcontrol *kcontrol, int event)
492 {
493 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
494 unsigned char adcmicsel, micbias_ctl;
495
496 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
497 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
498 /* Prepare the bits for the given TX path:
499 * shift_l == 0: TX1 microphone path
500 * shift_l == 2: TX2 microphone path */
501 if (e->shift_l) {
502 /* TX2 microphone path */
503 if (adcmicsel & TWL4030_TX2IN_SEL)
504 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
505 else
506 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
507 } else {
508 /* TX1 microphone path */
509 if (adcmicsel & TWL4030_TX1IN_SEL)
510 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
511 else
512 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
513 }
514
515 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
516
517 return 0;
518 }
519
520 static int handsfree_event(struct snd_soc_dapm_widget *w,
521 struct snd_kcontrol *kcontrol, int event)
522 {
523 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
524 unsigned char hs_ctl;
525
526 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
527
528 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
529 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
530 twl4030_write(w->codec, e->reg, hs_ctl);
531 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
532 twl4030_write(w->codec, e->reg, hs_ctl);
533 hs_ctl |= TWL4030_HF_CTL_HB_EN;
534 twl4030_write(w->codec, e->reg, hs_ctl);
535 } else {
536 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
537 | TWL4030_HF_CTL_HB_EN);
538 twl4030_write(w->codec, e->reg, hs_ctl);
539 }
540
541 return 0;
542 }
543
544 static int headsetl_event(struct snd_soc_dapm_widget *w,
545 struct snd_kcontrol *kcontrol, int event)
546 {
547 unsigned char hs_gain, hs_pop;
548
549 /* Save the current volume */
550 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
551 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
552
553 switch (event) {
554 case SND_SOC_DAPM_POST_PMU:
555 /* Do the anti-pop/bias ramp enable according to the TRM */
556 hs_pop |= TWL4030_VMID_EN;
557 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
558 /* Is this needed? Can we just use whatever gain here? */
559 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
560 (hs_gain & (~0x0f)) | 0x0a);
561 hs_pop |= TWL4030_RAMP_EN;
562 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
563
564 /* Restore the original volume */
565 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
566 break;
567 case SND_SOC_DAPM_POST_PMD:
568 /* Do the anti-pop/bias ramp disable according to the TRM */
569 hs_pop &= ~TWL4030_RAMP_EN;
570 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
571 /* Bypass the reg_cache to mute the headset */
572 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
573 hs_gain & (~0x0f),
574 TWL4030_REG_HS_GAIN_SET);
575 hs_pop &= ~TWL4030_VMID_EN;
576 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
577 break;
578 }
579 return 0;
580 }
581
582 static int bypass_event(struct snd_soc_dapm_widget *w,
583 struct snd_kcontrol *kcontrol, int event)
584 {
585 struct soc_mixer_control *m =
586 (struct soc_mixer_control *)w->kcontrols->private_value;
587 struct twl4030_priv *twl4030 = w->codec->private_data;
588 unsigned char reg;
589
590 reg = twl4030_read_reg_cache(w->codec, m->reg);
591
592 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
593 /* Analog bypass */
594 if (reg & (1 << m->shift))
595 twl4030->bypass_state |=
596 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
597 else
598 twl4030->bypass_state &=
599 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
600 } else {
601 /* Digital bypass */
602 if (reg & (0x7 << m->shift))
603 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
604 else
605 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
606 }
607
608 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
609 if (twl4030->bypass_state)
610 twl4030_codec_mute(w->codec, 0);
611 else
612 twl4030_codec_mute(w->codec, 1);
613 }
614 return 0;
615 }
616
617 /*
618 * Some of the gain controls in TWL (mostly those which are associated with
619 * the outputs) are implemented in an interesting way:
620 * 0x0 : Power down (mute)
621 * 0x1 : 6dB
622 * 0x2 : 0 dB
623 * 0x3 : -6 dB
624 * Inverting not going to help with these.
625 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
626 */
627 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
628 xinvert, tlv_array) \
629 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
630 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
631 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
632 .tlv.p = (tlv_array), \
633 .info = snd_soc_info_volsw, \
634 .get = snd_soc_get_volsw_twl4030, \
635 .put = snd_soc_put_volsw_twl4030, \
636 .private_value = (unsigned long)&(struct soc_mixer_control) \
637 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
638 .max = xmax, .invert = xinvert} }
639 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
640 xinvert, tlv_array) \
641 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
642 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
643 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
644 .tlv.p = (tlv_array), \
645 .info = snd_soc_info_volsw_2r, \
646 .get = snd_soc_get_volsw_r2_twl4030,\
647 .put = snd_soc_put_volsw_r2_twl4030, \
648 .private_value = (unsigned long)&(struct soc_mixer_control) \
649 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
650 .rshift = xshift, .max = xmax, .invert = xinvert} }
651 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
652 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
653 xinvert, tlv_array)
654
655 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_value *ucontrol)
657 {
658 struct soc_mixer_control *mc =
659 (struct soc_mixer_control *)kcontrol->private_value;
660 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
661 unsigned int reg = mc->reg;
662 unsigned int shift = mc->shift;
663 unsigned int rshift = mc->rshift;
664 int max = mc->max;
665 int mask = (1 << fls(max)) - 1;
666
667 ucontrol->value.integer.value[0] =
668 (snd_soc_read(codec, reg) >> shift) & mask;
669 if (ucontrol->value.integer.value[0])
670 ucontrol->value.integer.value[0] =
671 max + 1 - ucontrol->value.integer.value[0];
672
673 if (shift != rshift) {
674 ucontrol->value.integer.value[1] =
675 (snd_soc_read(codec, reg) >> rshift) & mask;
676 if (ucontrol->value.integer.value[1])
677 ucontrol->value.integer.value[1] =
678 max + 1 - ucontrol->value.integer.value[1];
679 }
680
681 return 0;
682 }
683
684 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
685 struct snd_ctl_elem_value *ucontrol)
686 {
687 struct soc_mixer_control *mc =
688 (struct soc_mixer_control *)kcontrol->private_value;
689 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
690 unsigned int reg = mc->reg;
691 unsigned int shift = mc->shift;
692 unsigned int rshift = mc->rshift;
693 int max = mc->max;
694 int mask = (1 << fls(max)) - 1;
695 unsigned short val, val2, val_mask;
696
697 val = (ucontrol->value.integer.value[0] & mask);
698
699 val_mask = mask << shift;
700 if (val)
701 val = max + 1 - val;
702 val = val << shift;
703 if (shift != rshift) {
704 val2 = (ucontrol->value.integer.value[1] & mask);
705 val_mask |= mask << rshift;
706 if (val2)
707 val2 = max + 1 - val2;
708 val |= val2 << rshift;
709 }
710 return snd_soc_update_bits(codec, reg, val_mask, val);
711 }
712
713 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
714 struct snd_ctl_elem_value *ucontrol)
715 {
716 struct soc_mixer_control *mc =
717 (struct soc_mixer_control *)kcontrol->private_value;
718 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
719 unsigned int reg = mc->reg;
720 unsigned int reg2 = mc->rreg;
721 unsigned int shift = mc->shift;
722 int max = mc->max;
723 int mask = (1<<fls(max))-1;
724
725 ucontrol->value.integer.value[0] =
726 (snd_soc_read(codec, reg) >> shift) & mask;
727 ucontrol->value.integer.value[1] =
728 (snd_soc_read(codec, reg2) >> shift) & mask;
729
730 if (ucontrol->value.integer.value[0])
731 ucontrol->value.integer.value[0] =
732 max + 1 - ucontrol->value.integer.value[0];
733 if (ucontrol->value.integer.value[1])
734 ucontrol->value.integer.value[1] =
735 max + 1 - ucontrol->value.integer.value[1];
736
737 return 0;
738 }
739
740 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
741 struct snd_ctl_elem_value *ucontrol)
742 {
743 struct soc_mixer_control *mc =
744 (struct soc_mixer_control *)kcontrol->private_value;
745 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
746 unsigned int reg = mc->reg;
747 unsigned int reg2 = mc->rreg;
748 unsigned int shift = mc->shift;
749 int max = mc->max;
750 int mask = (1 << fls(max)) - 1;
751 int err;
752 unsigned short val, val2, val_mask;
753
754 val_mask = mask << shift;
755 val = (ucontrol->value.integer.value[0] & mask);
756 val2 = (ucontrol->value.integer.value[1] & mask);
757
758 if (val)
759 val = max + 1 - val;
760 if (val2)
761 val2 = max + 1 - val2;
762
763 val = val << shift;
764 val2 = val2 << shift;
765
766 err = snd_soc_update_bits(codec, reg, val_mask, val);
767 if (err < 0)
768 return err;
769
770 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
771 return err;
772 }
773
774 /*
775 * FGAIN volume control:
776 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
777 */
778 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
779
780 /*
781 * CGAIN volume control:
782 * 0 dB to 12 dB in 6 dB steps
783 * value 2 and 3 means 12 dB
784 */
785 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
786
787 /*
788 * Voice Downlink GAIN volume control:
789 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
790 */
791 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
792
793 /*
794 * Analog playback gain
795 * -24 dB to 12 dB in 2 dB steps
796 */
797 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
798
799 /*
800 * Gain controls tied to outputs
801 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
802 */
803 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
804
805 /*
806 * Capture gain after the ADCs
807 * from 0 dB to 31 dB in 1 dB steps
808 */
809 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
810
811 /*
812 * Gain control for input amplifiers
813 * 0 dB to 30 dB in 6 dB steps
814 */
815 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
816
817 static const char *twl4030_rampdelay_texts[] = {
818 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
819 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
820 "3495/2581/1748 ms"
821 };
822
823 static const struct soc_enum twl4030_rampdelay_enum =
824 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
825 ARRAY_SIZE(twl4030_rampdelay_texts),
826 twl4030_rampdelay_texts);
827
828 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
829 /* Common playback gain controls */
830 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
831 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
832 0, 0x3f, 0, digital_fine_tlv),
833 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
834 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
835 0, 0x3f, 0, digital_fine_tlv),
836
837 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
838 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
839 6, 0x2, 0, digital_coarse_tlv),
840 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
841 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
842 6, 0x2, 0, digital_coarse_tlv),
843
844 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
845 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
846 3, 0x12, 1, analog_tlv),
847 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
848 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
849 3, 0x12, 1, analog_tlv),
850 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
851 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
852 1, 1, 0),
853 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
854 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
855 1, 1, 0),
856
857 /* Common voice downlink gain controls */
858 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
859 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
860
861 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
862 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
863
864 SOC_SINGLE("DAC Voice Analog Downlink Switch",
865 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
866
867 /* Separate output gain controls */
868 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
869 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
870 4, 3, 0, output_tvl),
871
872 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
873 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
874
875 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
876 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
877 4, 3, 0, output_tvl),
878
879 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
880 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
881
882 /* Common capture gain controls */
883 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
884 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
885 0, 0x1f, 0, digital_capture_tlv),
886 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
887 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
888 0, 0x1f, 0, digital_capture_tlv),
889
890 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
891 0, 3, 5, 0, input_gain_tlv),
892
893 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
894 };
895
896 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
897 /* Left channel inputs */
898 SND_SOC_DAPM_INPUT("MAINMIC"),
899 SND_SOC_DAPM_INPUT("HSMIC"),
900 SND_SOC_DAPM_INPUT("AUXL"),
901 SND_SOC_DAPM_INPUT("CARKITMIC"),
902 /* Right channel inputs */
903 SND_SOC_DAPM_INPUT("SUBMIC"),
904 SND_SOC_DAPM_INPUT("AUXR"),
905 /* Digital microphones (Stereo) */
906 SND_SOC_DAPM_INPUT("DIGIMIC0"),
907 SND_SOC_DAPM_INPUT("DIGIMIC1"),
908
909 /* Outputs */
910 SND_SOC_DAPM_OUTPUT("OUTL"),
911 SND_SOC_DAPM_OUTPUT("OUTR"),
912 SND_SOC_DAPM_OUTPUT("EARPIECE"),
913 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
914 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
915 SND_SOC_DAPM_OUTPUT("HSOL"),
916 SND_SOC_DAPM_OUTPUT("HSOR"),
917 SND_SOC_DAPM_OUTPUT("CARKITL"),
918 SND_SOC_DAPM_OUTPUT("CARKITR"),
919 SND_SOC_DAPM_OUTPUT("HFL"),
920 SND_SOC_DAPM_OUTPUT("HFR"),
921
922 /* DACs */
923 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
924 SND_SOC_NOPM, 0, 0),
925 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
926 SND_SOC_NOPM, 0, 0),
927 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
928 SND_SOC_NOPM, 0, 0),
929 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
930 SND_SOC_NOPM, 0, 0),
931 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
932 TWL4030_REG_AVDAC_CTL, 4, 0),
933
934 /* Analog PGAs */
935 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
936 0, 0, NULL, 0),
937 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
938 0, 0, NULL, 0),
939 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
940 0, 0, NULL, 0),
941 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
942 0, 0, NULL, 0),
943 SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
944 0, 0, NULL, 0),
945
946 /* Analog bypasses */
947 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
948 &twl4030_dapm_abypassr1_control, bypass_event,
949 SND_SOC_DAPM_POST_REG),
950 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
951 &twl4030_dapm_abypassl1_control,
952 bypass_event, SND_SOC_DAPM_POST_REG),
953 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
954 &twl4030_dapm_abypassr2_control,
955 bypass_event, SND_SOC_DAPM_POST_REG),
956 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
957 &twl4030_dapm_abypassl2_control,
958 bypass_event, SND_SOC_DAPM_POST_REG),
959
960 /* Digital bypasses */
961 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
962 &twl4030_dapm_dbypassl_control, bypass_event,
963 SND_SOC_DAPM_POST_REG),
964 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
965 &twl4030_dapm_dbypassr_control, bypass_event,
966 SND_SOC_DAPM_POST_REG),
967
968 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
969 0, 0, NULL, 0),
970 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
971 1, 0, NULL, 0),
972 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
973 2, 0, NULL, 0),
974 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
975 3, 0, NULL, 0),
976
977 /* Output MIXER controls */
978 /* Earpiece */
979 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
980 &twl4030_dapm_earpiece_controls[0],
981 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
982 /* PreDrivL/R */
983 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
984 &twl4030_dapm_predrivel_controls[0],
985 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
986 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
987 &twl4030_dapm_predriver_controls[0],
988 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
989 /* HeadsetL/R */
990 SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
991 &twl4030_dapm_hsol_controls[0],
992 ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
993 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
994 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
995 &twl4030_dapm_hsor_controls[0],
996 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
997 /* CarkitL/R */
998 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
999 &twl4030_dapm_carkitl_controls[0],
1000 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1001 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1002 &twl4030_dapm_carkitr_controls[0],
1003 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1004
1005 /* Output MUX controls */
1006 /* HandsfreeL/R */
1007 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1008 &twl4030_dapm_handsfreel_control, handsfree_event,
1009 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1010 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1011 &twl4030_dapm_handsfreer_control, handsfree_event,
1012 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1013
1014 /* Introducing four virtual ADC, since TWL4030 have four channel for
1015 capture */
1016 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1017 SND_SOC_NOPM, 0, 0),
1018 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1019 SND_SOC_NOPM, 0, 0),
1020 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1021 SND_SOC_NOPM, 0, 0),
1022 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1023 SND_SOC_NOPM, 0, 0),
1024
1025 /* Analog/Digital mic path selection.
1026 TX1 Left/Right: either analog Left/Right or Digimic0
1027 TX2 Left/Right: either analog Left/Right or Digimic1 */
1028 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1029 &twl4030_dapm_micpathtx1_control, micpath_event,
1030 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1031 SND_SOC_DAPM_POST_REG),
1032 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1033 &twl4030_dapm_micpathtx2_control, micpath_event,
1034 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1035 SND_SOC_DAPM_POST_REG),
1036
1037 /* Analog input muxes with switch for the capture amplifiers */
1038 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
1039 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
1040 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
1041 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
1042
1043 SND_SOC_DAPM_PGA("ADC Physical Left",
1044 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1045 SND_SOC_DAPM_PGA("ADC Physical Right",
1046 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1047
1048 SND_SOC_DAPM_PGA("Digimic0 Enable",
1049 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1050 SND_SOC_DAPM_PGA("Digimic1 Enable",
1051 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1052
1053 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1054 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1055 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1056
1057 };
1058
1059 static const struct snd_soc_dapm_route intercon[] = {
1060 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1061 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1062 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1063 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1064
1065 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1066 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1067 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1068 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
1069
1070 {"VDL_APGA", NULL, "DAC Voice"},
1071
1072 /* Internal playback routings */
1073 /* Earpiece */
1074 {"Earpiece Mixer", "Voice", "VDL_APGA"},
1075 {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
1076 {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
1077 {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
1078 /* PreDrivL */
1079 {"PredriveL Mixer", "Voice", "VDL_APGA"},
1080 {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
1081 {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
1082 {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
1083 /* PreDrivR */
1084 {"PredriveR Mixer", "Voice", "VDL_APGA"},
1085 {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
1086 {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
1087 {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
1088 /* HeadsetL */
1089 {"HeadsetL Mixer", "Voice", "VDL_APGA"},
1090 {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
1091 {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
1092 /* HeadsetR */
1093 {"HeadsetR Mixer", "Voice", "VDL_APGA"},
1094 {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
1095 {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
1096 /* CarkitL */
1097 {"CarkitL Mixer", "Voice", "VDL_APGA"},
1098 {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
1099 {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
1100 /* CarkitR */
1101 {"CarkitR Mixer", "Voice", "VDL_APGA"},
1102 {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
1103 {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
1104 /* HandsfreeL */
1105 {"HandsfreeL Mux", "Voice", "VDL_APGA"},
1106 {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
1107 {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
1108 {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
1109 /* HandsfreeR */
1110 {"HandsfreeR Mux", "Voice", "VDL_APGA"},
1111 {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
1112 {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
1113 {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
1114
1115 /* outputs */
1116 {"OUTL", NULL, "ARXL2_APGA"},
1117 {"OUTR", NULL, "ARXR2_APGA"},
1118 {"EARPIECE", NULL, "Earpiece Mixer"},
1119 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1120 {"PREDRIVER", NULL, "PredriveR Mixer"},
1121 {"HSOL", NULL, "HeadsetL Mixer"},
1122 {"HSOR", NULL, "HeadsetR Mixer"},
1123 {"CARKITL", NULL, "CarkitL Mixer"},
1124 {"CARKITR", NULL, "CarkitR Mixer"},
1125 {"HFL", NULL, "HandsfreeL Mux"},
1126 {"HFR", NULL, "HandsfreeR Mux"},
1127
1128 /* Capture path */
1129 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1130 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1131 {"Analog Left Capture Route", "AUXL", "AUXL"},
1132 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1133
1134 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1135 {"Analog Right Capture Route", "AUXR", "AUXR"},
1136
1137 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1138 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
1139
1140 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1141 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1142
1143 /* TX1 Left capture path */
1144 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1145 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1146 /* TX1 Right capture path */
1147 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1148 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1149 /* TX2 Left capture path */
1150 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1151 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1152 /* TX2 Right capture path */
1153 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1154 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1155
1156 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1157 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1158 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1159 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1160
1161 /* Analog bypass routes */
1162 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1163 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1164 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1165 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1166
1167 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1168 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1169 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1170 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1171
1172 /* Digital bypass routes */
1173 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1174 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1175
1176 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1177 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
1178
1179 };
1180
1181 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1182 {
1183 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1184 ARRAY_SIZE(twl4030_dapm_widgets));
1185
1186 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1187
1188 snd_soc_dapm_new_widgets(codec);
1189 return 0;
1190 }
1191
1192 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1193 enum snd_soc_bias_level level)
1194 {
1195 struct twl4030_priv *twl4030 = codec->private_data;
1196
1197 switch (level) {
1198 case SND_SOC_BIAS_ON:
1199 twl4030_codec_mute(codec, 0);
1200 break;
1201 case SND_SOC_BIAS_PREPARE:
1202 twl4030_power_up(codec);
1203 if (twl4030->bypass_state)
1204 twl4030_codec_mute(codec, 0);
1205 else
1206 twl4030_codec_mute(codec, 1);
1207 break;
1208 case SND_SOC_BIAS_STANDBY:
1209 twl4030_power_up(codec);
1210 if (twl4030->bypass_state)
1211 twl4030_codec_mute(codec, 0);
1212 else
1213 twl4030_codec_mute(codec, 1);
1214 break;
1215 case SND_SOC_BIAS_OFF:
1216 twl4030_power_down(codec);
1217 break;
1218 }
1219 codec->bias_level = level;
1220
1221 return 0;
1222 }
1223
1224 static void twl4030_constraints(struct twl4030_priv *twl4030,
1225 struct snd_pcm_substream *mst_substream)
1226 {
1227 struct snd_pcm_substream *slv_substream;
1228
1229 /* Pick the stream, which need to be constrained */
1230 if (mst_substream == twl4030->master_substream)
1231 slv_substream = twl4030->slave_substream;
1232 else if (mst_substream == twl4030->slave_substream)
1233 slv_substream = twl4030->master_substream;
1234 else /* This should not happen.. */
1235 return;
1236
1237 /* Set the constraints according to the already configured stream */
1238 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1239 SNDRV_PCM_HW_PARAM_RATE,
1240 twl4030->rate,
1241 twl4030->rate);
1242
1243 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1244 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1245 twl4030->sample_bits,
1246 twl4030->sample_bits);
1247
1248 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1249 SNDRV_PCM_HW_PARAM_CHANNELS,
1250 twl4030->channels,
1251 twl4030->channels);
1252 }
1253
1254 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1255 * capture has to be enabled/disabled. */
1256 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1257 int enable)
1258 {
1259 u8 reg, mask;
1260
1261 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1262
1263 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1264 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1265 else
1266 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1267
1268 if (enable)
1269 reg |= mask;
1270 else
1271 reg &= ~mask;
1272
1273 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1274 }
1275
1276 static int twl4030_startup(struct snd_pcm_substream *substream,
1277 struct snd_soc_dai *dai)
1278 {
1279 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1280 struct snd_soc_device *socdev = rtd->socdev;
1281 struct snd_soc_codec *codec = socdev->card->codec;
1282 struct twl4030_priv *twl4030 = codec->private_data;
1283
1284 if (twl4030->master_substream) {
1285 twl4030->slave_substream = substream;
1286 /* The DAI has one configuration for playback and capture, so
1287 * if the DAI has been already configured then constrain this
1288 * substream to match it. */
1289 if (twl4030->configured)
1290 twl4030_constraints(twl4030, twl4030->master_substream);
1291 } else {
1292 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1293 TWL4030_OPTION_1)) {
1294 /* In option2 4 channel is not supported, set the
1295 * constraint for the first stream for channels, the
1296 * second stream will 'inherit' this cosntraint */
1297 snd_pcm_hw_constraint_minmax(substream->runtime,
1298 SNDRV_PCM_HW_PARAM_CHANNELS,
1299 2, 2);
1300 }
1301 twl4030->master_substream = substream;
1302 }
1303
1304 return 0;
1305 }
1306
1307 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1308 struct snd_soc_dai *dai)
1309 {
1310 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1311 struct snd_soc_device *socdev = rtd->socdev;
1312 struct snd_soc_codec *codec = socdev->card->codec;
1313 struct twl4030_priv *twl4030 = codec->private_data;
1314
1315 if (twl4030->master_substream == substream)
1316 twl4030->master_substream = twl4030->slave_substream;
1317
1318 twl4030->slave_substream = NULL;
1319
1320 /* If all streams are closed, or the remaining stream has not yet
1321 * been configured than set the DAI as not configured. */
1322 if (!twl4030->master_substream)
1323 twl4030->configured = 0;
1324 else if (!twl4030->master_substream->runtime->channels)
1325 twl4030->configured = 0;
1326
1327 /* If the closing substream had 4 channel, do the necessary cleanup */
1328 if (substream->runtime->channels == 4)
1329 twl4030_tdm_enable(codec, substream->stream, 0);
1330 }
1331
1332 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1333 struct snd_pcm_hw_params *params,
1334 struct snd_soc_dai *dai)
1335 {
1336 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1337 struct snd_soc_device *socdev = rtd->socdev;
1338 struct snd_soc_codec *codec = socdev->card->codec;
1339 struct twl4030_priv *twl4030 = codec->private_data;
1340 u8 mode, old_mode, format, old_format;
1341
1342 /* If the substream has 4 channel, do the necessary setup */
1343 if (params_channels(params) == 4) {
1344 /* Safety check: are we in the correct operating mode? */
1345 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1346 TWL4030_OPTION_1))
1347 twl4030_tdm_enable(codec, substream->stream, 1);
1348 else
1349 return -EINVAL;
1350 }
1351
1352 if (twl4030->configured)
1353 /* Ignoring hw_params for already configured DAI */
1354 return 0;
1355
1356 /* bit rate */
1357 old_mode = twl4030_read_reg_cache(codec,
1358 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1359 mode = old_mode & ~TWL4030_APLL_RATE;
1360
1361 switch (params_rate(params)) {
1362 case 8000:
1363 mode |= TWL4030_APLL_RATE_8000;
1364 break;
1365 case 11025:
1366 mode |= TWL4030_APLL_RATE_11025;
1367 break;
1368 case 12000:
1369 mode |= TWL4030_APLL_RATE_12000;
1370 break;
1371 case 16000:
1372 mode |= TWL4030_APLL_RATE_16000;
1373 break;
1374 case 22050:
1375 mode |= TWL4030_APLL_RATE_22050;
1376 break;
1377 case 24000:
1378 mode |= TWL4030_APLL_RATE_24000;
1379 break;
1380 case 32000:
1381 mode |= TWL4030_APLL_RATE_32000;
1382 break;
1383 case 44100:
1384 mode |= TWL4030_APLL_RATE_44100;
1385 break;
1386 case 48000:
1387 mode |= TWL4030_APLL_RATE_48000;
1388 break;
1389 case 96000:
1390 mode |= TWL4030_APLL_RATE_96000;
1391 break;
1392 default:
1393 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1394 params_rate(params));
1395 return -EINVAL;
1396 }
1397
1398 if (mode != old_mode) {
1399 /* change rate and set CODECPDZ */
1400 twl4030_codec_enable(codec, 0);
1401 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1402 twl4030_codec_enable(codec, 1);
1403 }
1404
1405 /* sample size */
1406 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1407 format = old_format;
1408 format &= ~TWL4030_DATA_WIDTH;
1409 switch (params_format(params)) {
1410 case SNDRV_PCM_FORMAT_S16_LE:
1411 format |= TWL4030_DATA_WIDTH_16S_16W;
1412 break;
1413 case SNDRV_PCM_FORMAT_S24_LE:
1414 format |= TWL4030_DATA_WIDTH_32S_24W;
1415 break;
1416 default:
1417 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1418 params_format(params));
1419 return -EINVAL;
1420 }
1421
1422 if (format != old_format) {
1423
1424 /* clear CODECPDZ before changing format (codec requirement) */
1425 twl4030_codec_enable(codec, 0);
1426
1427 /* change format */
1428 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1429
1430 /* set CODECPDZ afterwards */
1431 twl4030_codec_enable(codec, 1);
1432 }
1433
1434 /* Store the important parameters for the DAI configuration and set
1435 * the DAI as configured */
1436 twl4030->configured = 1;
1437 twl4030->rate = params_rate(params);
1438 twl4030->sample_bits = hw_param_interval(params,
1439 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1440 twl4030->channels = params_channels(params);
1441
1442 /* If both playback and capture streams are open, and one of them
1443 * is setting the hw parameters right now (since we are here), set
1444 * constraints to the other stream to match the current one. */
1445 if (twl4030->slave_substream)
1446 twl4030_constraints(twl4030, substream);
1447
1448 return 0;
1449 }
1450
1451 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1452 int clk_id, unsigned int freq, int dir)
1453 {
1454 struct snd_soc_codec *codec = codec_dai->codec;
1455 u8 infreq;
1456
1457 switch (freq) {
1458 case 19200000:
1459 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1460 break;
1461 case 26000000:
1462 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1463 break;
1464 case 38400000:
1465 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1466 break;
1467 default:
1468 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1469 freq);
1470 return -EINVAL;
1471 }
1472
1473 infreq |= TWL4030_APLL_EN;
1474 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1475
1476 return 0;
1477 }
1478
1479 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1480 unsigned int fmt)
1481 {
1482 struct snd_soc_codec *codec = codec_dai->codec;
1483 u8 old_format, format;
1484
1485 /* get format */
1486 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1487 format = old_format;
1488
1489 /* set master/slave audio interface */
1490 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1491 case SND_SOC_DAIFMT_CBM_CFM:
1492 format &= ~(TWL4030_AIF_SLAVE_EN);
1493 format &= ~(TWL4030_CLK256FS_EN);
1494 break;
1495 case SND_SOC_DAIFMT_CBS_CFS:
1496 format |= TWL4030_AIF_SLAVE_EN;
1497 format |= TWL4030_CLK256FS_EN;
1498 break;
1499 default:
1500 return -EINVAL;
1501 }
1502
1503 /* interface format */
1504 format &= ~TWL4030_AIF_FORMAT;
1505 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1506 case SND_SOC_DAIFMT_I2S:
1507 format |= TWL4030_AIF_FORMAT_CODEC;
1508 break;
1509 case SND_SOC_DAIFMT_DSP_A:
1510 format |= TWL4030_AIF_FORMAT_TDM;
1511 break;
1512 default:
1513 return -EINVAL;
1514 }
1515
1516 if (format != old_format) {
1517
1518 /* clear CODECPDZ before changing format (codec requirement) */
1519 twl4030_codec_enable(codec, 0);
1520
1521 /* change format */
1522 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1523
1524 /* set CODECPDZ afterwards */
1525 twl4030_codec_enable(codec, 1);
1526 }
1527
1528 return 0;
1529 }
1530
1531 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1532 struct snd_soc_dai *dai)
1533 {
1534 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1535 struct snd_soc_device *socdev = rtd->socdev;
1536 struct snd_soc_codec *codec = socdev->card->codec;
1537 u8 infreq;
1538 u8 mode;
1539
1540 /* If the system master clock is not 26MHz, the voice PCM interface is
1541 * not avilable.
1542 */
1543 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1544 & TWL4030_APLL_INFREQ;
1545
1546 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1547 printk(KERN_ERR "TWL4030 voice startup: "
1548 "MCLK is not 26MHz, call set_sysclk() on init\n");
1549 return -EINVAL;
1550 }
1551
1552 /* If the codec mode is not option2, the voice PCM interface is not
1553 * avilable.
1554 */
1555 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1556 & TWL4030_OPT_MODE;
1557
1558 if (mode != TWL4030_OPTION_2) {
1559 printk(KERN_ERR "TWL4030 voice startup: "
1560 "the codec mode is not option2\n");
1561 return -EINVAL;
1562 }
1563
1564 return 0;
1565 }
1566
1567 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1568 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1569 {
1570 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1571 struct snd_soc_device *socdev = rtd->socdev;
1572 struct snd_soc_codec *codec = socdev->card->codec;
1573 u8 old_mode, mode;
1574
1575 /* bit rate */
1576 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1577 & ~(TWL4030_CODECPDZ);
1578 mode = old_mode;
1579
1580 switch (params_rate(params)) {
1581 case 8000:
1582 mode &= ~(TWL4030_SEL_16K);
1583 break;
1584 case 16000:
1585 mode |= TWL4030_SEL_16K;
1586 break;
1587 default:
1588 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1589 params_rate(params));
1590 return -EINVAL;
1591 }
1592
1593 if (mode != old_mode) {
1594 /* change rate and set CODECPDZ */
1595 twl4030_codec_enable(codec, 0);
1596 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1597 twl4030_codec_enable(codec, 1);
1598 }
1599
1600 return 0;
1601 }
1602
1603 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1604 int clk_id, unsigned int freq, int dir)
1605 {
1606 struct snd_soc_codec *codec = codec_dai->codec;
1607 u8 infreq;
1608
1609 switch (freq) {
1610 case 26000000:
1611 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1612 break;
1613 default:
1614 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1615 freq);
1616 return -EINVAL;
1617 }
1618
1619 infreq |= TWL4030_APLL_EN;
1620 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1621
1622 return 0;
1623 }
1624
1625 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1626 unsigned int fmt)
1627 {
1628 struct snd_soc_codec *codec = codec_dai->codec;
1629 u8 old_format, format;
1630
1631 /* get format */
1632 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1633 format = old_format;
1634
1635 /* set master/slave audio interface */
1636 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1637 case SND_SOC_DAIFMT_CBS_CFM:
1638 format &= ~(TWL4030_VIF_SLAVE_EN);
1639 break;
1640 case SND_SOC_DAIFMT_CBS_CFS:
1641 format |= TWL4030_VIF_SLAVE_EN;
1642 break;
1643 default:
1644 return -EINVAL;
1645 }
1646
1647 /* clock inversion */
1648 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1649 case SND_SOC_DAIFMT_IB_NF:
1650 format &= ~(TWL4030_VIF_FORMAT);
1651 break;
1652 case SND_SOC_DAIFMT_NB_IF:
1653 format |= TWL4030_VIF_FORMAT;
1654 break;
1655 default:
1656 return -EINVAL;
1657 }
1658
1659 if (format != old_format) {
1660 /* change format and set CODECPDZ */
1661 twl4030_codec_enable(codec, 0);
1662 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1663 twl4030_codec_enable(codec, 1);
1664 }
1665
1666 return 0;
1667 }
1668
1669 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1670 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1671
1672 static struct snd_soc_dai_ops twl4030_dai_ops = {
1673 .startup = twl4030_startup,
1674 .shutdown = twl4030_shutdown,
1675 .hw_params = twl4030_hw_params,
1676 .set_sysclk = twl4030_set_dai_sysclk,
1677 .set_fmt = twl4030_set_dai_fmt,
1678 };
1679
1680 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1681 .startup = twl4030_voice_startup,
1682 .hw_params = twl4030_voice_hw_params,
1683 .set_sysclk = twl4030_voice_set_dai_sysclk,
1684 .set_fmt = twl4030_voice_set_dai_fmt,
1685 };
1686
1687 struct snd_soc_dai twl4030_dai[] = {
1688 {
1689 .name = "twl4030",
1690 .playback = {
1691 .stream_name = "Playback",
1692 .channels_min = 2,
1693 .channels_max = 4,
1694 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
1695 .formats = TWL4030_FORMATS,},
1696 .capture = {
1697 .stream_name = "Capture",
1698 .channels_min = 2,
1699 .channels_max = 4,
1700 .rates = TWL4030_RATES,
1701 .formats = TWL4030_FORMATS,},
1702 .ops = &twl4030_dai_ops,
1703 },
1704 {
1705 .name = "twl4030 Voice",
1706 .playback = {
1707 .stream_name = "Playback",
1708 .channels_min = 1,
1709 .channels_max = 1,
1710 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1711 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1712 .capture = {
1713 .stream_name = "Capture",
1714 .channels_min = 1,
1715 .channels_max = 2,
1716 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1717 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1718 .ops = &twl4030_dai_voice_ops,
1719 },
1720 };
1721 EXPORT_SYMBOL_GPL(twl4030_dai);
1722
1723 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1724 {
1725 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1726 struct snd_soc_codec *codec = socdev->card->codec;
1727
1728 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1729
1730 return 0;
1731 }
1732
1733 static int twl4030_resume(struct platform_device *pdev)
1734 {
1735 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1736 struct snd_soc_codec *codec = socdev->card->codec;
1737
1738 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1739 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1740 return 0;
1741 }
1742
1743 /*
1744 * initialize the driver
1745 * register the mixer and dsp interfaces with the kernel
1746 */
1747
1748 static int twl4030_init(struct snd_soc_device *socdev)
1749 {
1750 struct snd_soc_codec *codec = socdev->card->codec;
1751 int ret = 0;
1752
1753 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1754
1755 codec->name = "twl4030";
1756 codec->owner = THIS_MODULE;
1757 codec->read = twl4030_read_reg_cache;
1758 codec->write = twl4030_write;
1759 codec->set_bias_level = twl4030_set_bias_level;
1760 codec->dai = twl4030_dai;
1761 codec->num_dai = ARRAY_SIZE(twl4030_dai),
1762 codec->reg_cache_size = sizeof(twl4030_reg);
1763 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1764 GFP_KERNEL);
1765 if (codec->reg_cache == NULL)
1766 return -ENOMEM;
1767
1768 /* register pcms */
1769 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1770 if (ret < 0) {
1771 printk(KERN_ERR "twl4030: failed to create pcms\n");
1772 goto pcm_err;
1773 }
1774
1775 twl4030_init_chip(codec);
1776
1777 /* power on device */
1778 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1779
1780 snd_soc_add_controls(codec, twl4030_snd_controls,
1781 ARRAY_SIZE(twl4030_snd_controls));
1782 twl4030_add_widgets(codec);
1783
1784 ret = snd_soc_init_card(socdev);
1785 if (ret < 0) {
1786 printk(KERN_ERR "twl4030: failed to register card\n");
1787 goto card_err;
1788 }
1789
1790 return ret;
1791
1792 card_err:
1793 snd_soc_free_pcms(socdev);
1794 snd_soc_dapm_free(socdev);
1795 pcm_err:
1796 kfree(codec->reg_cache);
1797 return ret;
1798 }
1799
1800 static struct snd_soc_device *twl4030_socdev;
1801
1802 static int twl4030_probe(struct platform_device *pdev)
1803 {
1804 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1805 struct snd_soc_codec *codec;
1806 struct twl4030_priv *twl4030;
1807
1808 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1809 if (codec == NULL)
1810 return -ENOMEM;
1811
1812 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1813 if (twl4030 == NULL) {
1814 kfree(codec);
1815 return -ENOMEM;
1816 }
1817
1818 codec->private_data = twl4030;
1819 socdev->card->codec = codec;
1820 mutex_init(&codec->mutex);
1821 INIT_LIST_HEAD(&codec->dapm_widgets);
1822 INIT_LIST_HEAD(&codec->dapm_paths);
1823
1824 twl4030_socdev = socdev;
1825 twl4030_init(socdev);
1826
1827 return 0;
1828 }
1829
1830 static int twl4030_remove(struct platform_device *pdev)
1831 {
1832 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1833 struct snd_soc_codec *codec = socdev->card->codec;
1834
1835 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1836 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1837 snd_soc_free_pcms(socdev);
1838 snd_soc_dapm_free(socdev);
1839 kfree(codec->private_data);
1840 kfree(codec);
1841
1842 return 0;
1843 }
1844
1845 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1846 .probe = twl4030_probe,
1847 .remove = twl4030_remove,
1848 .suspend = twl4030_suspend,
1849 .resume = twl4030_resume,
1850 };
1851 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1852
1853 static int __init twl4030_modinit(void)
1854 {
1855 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
1856 }
1857 module_init(twl4030_modinit);
1858
1859 static void __exit twl4030_exit(void)
1860 {
1861 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
1862 }
1863 module_exit(twl4030_exit);
1864
1865 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1866 MODULE_AUTHOR("Steve Sakoman");
1867 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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