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ASoC: TWL4030: Change the name for the DACs
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 };
119
120 /*
121 * read twl4030 register cache
122 */
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125 {
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129 }
130
131 /*
132 * write twl4030 register cache
133 */
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136 {
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142 }
143
144 /*
145 * write to the twl4030 register space
146 */
147 static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149 {
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152 }
153
154 static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155 {
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165 }
166
167 static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168 {
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178 }
179
180 static void twl4030_init_chip(struct snd_soc_codec *codec)
181 {
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191 }
192
193 /* Earpiece */
194 static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid", "DACR1"};
196
197 static const struct soc_enum twl4030_earpiece_enum =
198 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
199 ARRAY_SIZE(twl4030_earpiece_texts),
200 twl4030_earpiece_texts);
201
202 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
203 SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
204
205 /* PreDrive Left */
206 static const char *twl4030_predrivel_texts[] =
207 {"Off", "DACL1", "DACL2", "Invalid", "DACR2"};
208
209 static const struct soc_enum twl4030_predrivel_enum =
210 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
211 ARRAY_SIZE(twl4030_predrivel_texts),
212 twl4030_predrivel_texts);
213
214 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
215 SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
216
217 /* PreDrive Right */
218 static const char *twl4030_predriver_texts[] =
219 {"Off", "DACR1", "DACR2", "Invalid", "DACL2"};
220
221 static const struct soc_enum twl4030_predriver_enum =
222 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
223 ARRAY_SIZE(twl4030_predriver_texts),
224 twl4030_predriver_texts);
225
226 static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
227 SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
228
229 /* Headset Left */
230 static const char *twl4030_hsol_texts[] =
231 {"Off", "DACL1", "DACL2"};
232
233 static const struct soc_enum twl4030_hsol_enum =
234 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
235 ARRAY_SIZE(twl4030_hsol_texts),
236 twl4030_hsol_texts);
237
238 static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
239 SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
240
241 /* Headset Right */
242 static const char *twl4030_hsor_texts[] =
243 {"Off", "DACR1", "DACR2"};
244
245 static const struct soc_enum twl4030_hsor_enum =
246 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
247 ARRAY_SIZE(twl4030_hsor_texts),
248 twl4030_hsor_texts);
249
250 static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
251 SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
252
253 /* Carkit Left */
254 static const char *twl4030_carkitl_texts[] =
255 {"Off", "DACL1", "DACL2"};
256
257 static const struct soc_enum twl4030_carkitl_enum =
258 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
259 ARRAY_SIZE(twl4030_carkitl_texts),
260 twl4030_carkitl_texts);
261
262 static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
263 SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
264
265 /* Carkit Right */
266 static const char *twl4030_carkitr_texts[] =
267 {"Off", "DACR1", "DACR2"};
268
269 static const struct soc_enum twl4030_carkitr_enum =
270 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
271 ARRAY_SIZE(twl4030_carkitr_texts),
272 twl4030_carkitr_texts);
273
274 static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
275 SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
276
277 /* Handsfree Left */
278 static const char *twl4030_handsfreel_texts[] =
279 {"Voice", "DACL1", "DACL2", "DACR2"};
280
281 static const struct soc_enum twl4030_handsfreel_enum =
282 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
283 ARRAY_SIZE(twl4030_handsfreel_texts),
284 twl4030_handsfreel_texts);
285
286 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
287 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
288
289 /* Handsfree Right */
290 static const char *twl4030_handsfreer_texts[] =
291 {"Voice", "DACR1", "DACR2", "DACL2"};
292
293 static const struct soc_enum twl4030_handsfreer_enum =
294 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
295 ARRAY_SIZE(twl4030_handsfreer_texts),
296 twl4030_handsfreer_texts);
297
298 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
299 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
300
301 static int outmixer_event(struct snd_soc_dapm_widget *w,
302 struct snd_kcontrol *kcontrol, int event)
303 {
304 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
305 int ret = 0;
306 int val;
307
308 switch (e->reg) {
309 case TWL4030_REG_PREDL_CTL:
310 case TWL4030_REG_PREDR_CTL:
311 case TWL4030_REG_EAR_CTL:
312 val = w->value >> e->shift_l;
313 if (val == 3) {
314 printk(KERN_WARNING
315 "Invalid MUX setting for register 0x%02x (%d)\n",
316 e->reg, val);
317 ret = -1;
318 }
319 break;
320 }
321
322 return ret;
323 }
324
325 /*
326 * Some of the gain controls in TWL (mostly those which are associated with
327 * the outputs) are implemented in an interesting way:
328 * 0x0 : Power down (mute)
329 * 0x1 : 6dB
330 * 0x2 : 0 dB
331 * 0x3 : -6 dB
332 * Inverting not going to help with these.
333 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
334 */
335 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
336 xinvert, tlv_array) \
337 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
338 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
339 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
340 .tlv.p = (tlv_array), \
341 .info = snd_soc_info_volsw, \
342 .get = snd_soc_get_volsw_twl4030, \
343 .put = snd_soc_put_volsw_twl4030, \
344 .private_value = (unsigned long)&(struct soc_mixer_control) \
345 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
346 .max = xmax, .invert = xinvert} }
347 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
348 xinvert, tlv_array) \
349 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
350 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
351 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
352 .tlv.p = (tlv_array), \
353 .info = snd_soc_info_volsw_2r, \
354 .get = snd_soc_get_volsw_r2_twl4030,\
355 .put = snd_soc_put_volsw_r2_twl4030, \
356 .private_value = (unsigned long)&(struct soc_mixer_control) \
357 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
358 .rshift = xshift, .max = xmax, .invert = xinvert} }
359 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
360 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
361 xinvert, tlv_array)
362
363 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365 {
366 struct soc_mixer_control *mc =
367 (struct soc_mixer_control *)kcontrol->private_value;
368 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
369 unsigned int reg = mc->reg;
370 unsigned int shift = mc->shift;
371 unsigned int rshift = mc->rshift;
372 int max = mc->max;
373 int mask = (1 << fls(max)) - 1;
374
375 ucontrol->value.integer.value[0] =
376 (snd_soc_read(codec, reg) >> shift) & mask;
377 if (ucontrol->value.integer.value[0])
378 ucontrol->value.integer.value[0] =
379 max + 1 - ucontrol->value.integer.value[0];
380
381 if (shift != rshift) {
382 ucontrol->value.integer.value[1] =
383 (snd_soc_read(codec, reg) >> rshift) & mask;
384 if (ucontrol->value.integer.value[1])
385 ucontrol->value.integer.value[1] =
386 max + 1 - ucontrol->value.integer.value[1];
387 }
388
389 return 0;
390 }
391
392 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
393 struct snd_ctl_elem_value *ucontrol)
394 {
395 struct soc_mixer_control *mc =
396 (struct soc_mixer_control *)kcontrol->private_value;
397 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
398 unsigned int reg = mc->reg;
399 unsigned int shift = mc->shift;
400 unsigned int rshift = mc->rshift;
401 int max = mc->max;
402 int mask = (1 << fls(max)) - 1;
403 unsigned short val, val2, val_mask;
404
405 val = (ucontrol->value.integer.value[0] & mask);
406
407 val_mask = mask << shift;
408 if (val)
409 val = max + 1 - val;
410 val = val << shift;
411 if (shift != rshift) {
412 val2 = (ucontrol->value.integer.value[1] & mask);
413 val_mask |= mask << rshift;
414 if (val2)
415 val2 = max + 1 - val2;
416 val |= val2 << rshift;
417 }
418 return snd_soc_update_bits(codec, reg, val_mask, val);
419 }
420
421 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423 {
424 struct soc_mixer_control *mc =
425 (struct soc_mixer_control *)kcontrol->private_value;
426 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
427 unsigned int reg = mc->reg;
428 unsigned int reg2 = mc->rreg;
429 unsigned int shift = mc->shift;
430 int max = mc->max;
431 int mask = (1<<fls(max))-1;
432
433 ucontrol->value.integer.value[0] =
434 (snd_soc_read(codec, reg) >> shift) & mask;
435 ucontrol->value.integer.value[1] =
436 (snd_soc_read(codec, reg2) >> shift) & mask;
437
438 if (ucontrol->value.integer.value[0])
439 ucontrol->value.integer.value[0] =
440 max + 1 - ucontrol->value.integer.value[0];
441 if (ucontrol->value.integer.value[1])
442 ucontrol->value.integer.value[1] =
443 max + 1 - ucontrol->value.integer.value[1];
444
445 return 0;
446 }
447
448 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
449 struct snd_ctl_elem_value *ucontrol)
450 {
451 struct soc_mixer_control *mc =
452 (struct soc_mixer_control *)kcontrol->private_value;
453 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
454 unsigned int reg = mc->reg;
455 unsigned int reg2 = mc->rreg;
456 unsigned int shift = mc->shift;
457 int max = mc->max;
458 int mask = (1 << fls(max)) - 1;
459 int err;
460 unsigned short val, val2, val_mask;
461
462 val_mask = mask << shift;
463 val = (ucontrol->value.integer.value[0] & mask);
464 val2 = (ucontrol->value.integer.value[1] & mask);
465
466 if (val)
467 val = max + 1 - val;
468 if (val2)
469 val2 = max + 1 - val2;
470
471 val = val << shift;
472 val2 = val2 << shift;
473
474 err = snd_soc_update_bits(codec, reg, val_mask, val);
475 if (err < 0)
476 return err;
477
478 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
479 return err;
480 }
481
482 static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_value *ucontrol)
484 {
485 struct snd_soc_codec *codec = kcontrol->private_data;
486 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
487 int result = 0;
488
489 /* one bit must be set a time */
490 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
491 | TWL4030_MAINMIC_EN;
492 if (reg != 0) {
493 result++;
494 while ((reg & 1) == 0) {
495 result++;
496 reg >>= 1;
497 }
498 }
499
500 ucontrol->value.integer.value[0] = result;
501 return 0;
502 }
503
504 static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506 {
507 struct snd_soc_codec *codec = kcontrol->private_data;
508 int value = ucontrol->value.integer.value[0];
509 u8 anamicl, micbias, avadc_ctl;
510
511 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
512 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
513 | TWL4030_MAINMIC_EN);
514 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
515 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
516 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
517
518 switch (value) {
519 case 1:
520 anamicl |= TWL4030_MAINMIC_EN;
521 micbias |= TWL4030_MICBIAS1_EN;
522 break;
523 case 2:
524 anamicl |= TWL4030_HSMIC_EN;
525 micbias |= TWL4030_HSMICBIAS_EN;
526 break;
527 case 3:
528 anamicl |= TWL4030_AUXL_EN;
529 break;
530 case 4:
531 anamicl |= TWL4030_CKMIC_EN;
532 break;
533 default:
534 break;
535 }
536
537 /* If some input is selected, enable amp and ADC */
538 if (value != 0) {
539 anamicl |= TWL4030_MICAMPL_EN;
540 avadc_ctl |= TWL4030_ADCL_EN;
541 } else {
542 anamicl &= ~TWL4030_MICAMPL_EN;
543 avadc_ctl &= ~TWL4030_ADCL_EN;
544 }
545
546 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
547 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
548 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
549
550 return 1;
551 }
552
553 static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
554 struct snd_ctl_elem_value *ucontrol)
555 {
556 struct snd_soc_codec *codec = kcontrol->private_data;
557 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
558 int value = 0;
559
560 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
561 switch (reg) {
562 case TWL4030_SUBMIC_EN:
563 value = 1;
564 break;
565 case TWL4030_AUXR_EN:
566 value = 2;
567 break;
568 default:
569 break;
570 }
571
572 ucontrol->value.integer.value[0] = value;
573 return 0;
574 }
575
576 static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
577 struct snd_ctl_elem_value *ucontrol)
578 {
579 struct snd_soc_codec *codec = kcontrol->private_data;
580 int value = ucontrol->value.integer.value[0];
581 u8 anamicr, micbias, avadc_ctl;
582
583 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
584 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
585 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
586 micbias &= ~TWL4030_MICBIAS2_EN;
587 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
588
589 switch (value) {
590 case 1:
591 anamicr |= TWL4030_SUBMIC_EN;
592 micbias |= TWL4030_MICBIAS2_EN;
593 break;
594 case 2:
595 anamicr |= TWL4030_AUXR_EN;
596 break;
597 default:
598 break;
599 }
600
601 if (value != 0) {
602 anamicr |= TWL4030_MICAMPR_EN;
603 avadc_ctl |= TWL4030_ADCR_EN;
604 } else {
605 anamicr &= ~TWL4030_MICAMPR_EN;
606 avadc_ctl &= ~TWL4030_ADCR_EN;
607 }
608
609 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
610 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
611 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
612
613 return 1;
614 }
615
616 static const char *twl4030_left_in_sel[] = {
617 "None",
618 "Main Mic",
619 "Headset Mic",
620 "Line In",
621 "Carkit Mic",
622 };
623
624 static const char *twl4030_right_in_sel[] = {
625 "None",
626 "Sub Mic",
627 "Line In",
628 };
629
630 static const struct soc_enum twl4030_left_input_mux =
631 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
632 twl4030_left_in_sel);
633
634 static const struct soc_enum twl4030_right_input_mux =
635 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
636 twl4030_right_in_sel);
637
638 /*
639 * FGAIN volume control:
640 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
641 */
642 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
643
644 /*
645 * CGAIN volume control:
646 * 0 dB to 12 dB in 6 dB steps
647 * value 2 and 3 means 12 dB
648 */
649 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
650
651 /*
652 * Analog playback gain
653 * -24 dB to 12 dB in 2 dB steps
654 */
655 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
656
657 /*
658 * Gain controls tied to outputs
659 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
660 */
661 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
662
663 /*
664 * Capture gain after the ADCs
665 * from 0 dB to 31 dB in 1 dB steps
666 */
667 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
668
669 /*
670 * Gain control for input amplifiers
671 * 0 dB to 30 dB in 6 dB steps
672 */
673 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
674
675 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
676 /* Common playback gain controls */
677 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
678 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
679 0, 0x3f, 0, digital_fine_tlv),
680 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
681 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
682 0, 0x3f, 0, digital_fine_tlv),
683
684 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
685 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
686 6, 0x2, 0, digital_coarse_tlv),
687 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
688 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
689 6, 0x2, 0, digital_coarse_tlv),
690
691 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
692 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
693 3, 0x12, 1, analog_tlv),
694 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
695 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
696 3, 0x12, 1, analog_tlv),
697 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
698 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
699 1, 1, 0),
700 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
701 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
702 1, 1, 0),
703
704 /* Separate output gain controls */
705 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
706 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
707 4, 3, 0, output_tvl),
708
709 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
710 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
711
712 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
713 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
714 4, 3, 0, output_tvl),
715
716 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
717 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
718
719 /* Common capture gain controls */
720 SOC_DOUBLE_R_TLV("Capture Volume",
721 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
722 0, 0x1f, 0, digital_capture_tlv),
723
724 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
725 0, 3, 5, 0, input_gain_tlv),
726
727 /* Input source controls */
728 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
729 twl4030_get_left_input, twl4030_put_left_input),
730 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
731 twl4030_get_right_input, twl4030_put_right_input),
732 };
733
734 /* add non dapm controls */
735 static int twl4030_add_controls(struct snd_soc_codec *codec)
736 {
737 int err, i;
738
739 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
740 err = snd_ctl_add(codec->card,
741 snd_soc_cnew(&twl4030_snd_controls[i],
742 codec, NULL));
743 if (err < 0)
744 return err;
745 }
746
747 return 0;
748 }
749
750 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
751 SND_SOC_DAPM_INPUT("INL"),
752 SND_SOC_DAPM_INPUT("INR"),
753
754 SND_SOC_DAPM_OUTPUT("OUTL"),
755 SND_SOC_DAPM_OUTPUT("OUTR"),
756 SND_SOC_DAPM_OUTPUT("EARPIECE"),
757 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
758 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
759 SND_SOC_DAPM_OUTPUT("HSOL"),
760 SND_SOC_DAPM_OUTPUT("HSOR"),
761 SND_SOC_DAPM_OUTPUT("CARKITL"),
762 SND_SOC_DAPM_OUTPUT("CARKITR"),
763 SND_SOC_DAPM_OUTPUT("HFL"),
764 SND_SOC_DAPM_OUTPUT("HFR"),
765
766 /* DACs */
767 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
768 TWL4030_REG_AVDAC_CTL, 0, 0),
769 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
770 TWL4030_REG_AVDAC_CTL, 1, 0),
771 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
772 TWL4030_REG_AVDAC_CTL, 2, 0),
773 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
774 TWL4030_REG_AVDAC_CTL, 3, 0),
775
776 /* Analog PGAs */
777 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
778 0, 0, NULL, 0),
779 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
780 0, 0, NULL, 0),
781 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
782 0, 0, NULL, 0),
783 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
784 0, 0, NULL, 0),
785
786 /* Output MUX controls */
787 /* Earpiece */
788 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
789 &twl4030_dapm_earpiece_control, outmixer_event,
790 SND_SOC_DAPM_PRE_REG),
791 /* PreDrivL/R */
792 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
793 &twl4030_dapm_predrivel_control, outmixer_event,
794 SND_SOC_DAPM_PRE_REG),
795 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
796 &twl4030_dapm_predriver_control, outmixer_event,
797 SND_SOC_DAPM_PRE_REG),
798 /* HeadsetL/R */
799 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
800 &twl4030_dapm_hsol_control),
801 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
802 &twl4030_dapm_hsor_control),
803 /* CarkitL/R */
804 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
805 &twl4030_dapm_carkitl_control),
806 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
807 &twl4030_dapm_carkitr_control),
808 /* HandsfreeL/R */
809 SND_SOC_DAPM_MUX("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
810 &twl4030_dapm_handsfreel_control),
811 SND_SOC_DAPM_MUX("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
812 &twl4030_dapm_handsfreer_control),
813
814 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
815 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
816 };
817
818 static const struct snd_soc_dapm_route intercon[] = {
819 {"ARXL1_APGA", NULL, "DAC Left1"},
820 {"ARXR1_APGA", NULL, "DAC Right1"},
821 {"ARXL2_APGA", NULL, "DAC Left2"},
822 {"ARXR2_APGA", NULL, "DAC Right2"},
823
824 /* Internal playback routings */
825 /* Earpiece */
826 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
827 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
828 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
829 /* PreDrivL */
830 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
831 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
832 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
833 /* PreDrivR */
834 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
835 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
836 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
837 /* HeadsetL */
838 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
839 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
840 /* HeadsetR */
841 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
842 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
843 /* CarkitL */
844 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
845 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
846 /* CarkitR */
847 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
848 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
849 /* HandsfreeL */
850 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
851 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
852 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
853 /* HandsfreeR */
854 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
855 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
856 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
857
858 /* outputs */
859 {"OUTL", NULL, "ARXL2_APGA"},
860 {"OUTR", NULL, "ARXR2_APGA"},
861 {"EARPIECE", NULL, "Earpiece Mux"},
862 {"PREDRIVEL", NULL, "PredriveL Mux"},
863 {"PREDRIVER", NULL, "PredriveR Mux"},
864 {"HSOL", NULL, "HeadsetL Mux"},
865 {"HSOR", NULL, "HeadsetR Mux"},
866 {"CARKITL", NULL, "CarkitL Mux"},
867 {"CARKITR", NULL, "CarkitR Mux"},
868 {"HFL", NULL, "HandsfreeL Mux"},
869 {"HFR", NULL, "HandsfreeR Mux"},
870
871 /* inputs */
872 {"ADCL", NULL, "INL"},
873 {"ADCR", NULL, "INR"},
874 };
875
876 static int twl4030_add_widgets(struct snd_soc_codec *codec)
877 {
878 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
879 ARRAY_SIZE(twl4030_dapm_widgets));
880
881 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
882
883 snd_soc_dapm_new_widgets(codec);
884 return 0;
885 }
886
887 static void twl4030_power_up(struct snd_soc_codec *codec)
888 {
889 u8 anamicl, regmisc1, byte, popn;
890 int i = 0;
891
892 /* set CODECPDZ to turn on codec */
893 twl4030_set_codecpdz(codec);
894
895 /* initiate offset cancellation */
896 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
897 twl4030_write(codec, TWL4030_REG_ANAMICL,
898 anamicl | TWL4030_CNCL_OFFSET_START);
899
900 /* wait for offset cancellation to complete */
901 do {
902 /* this takes a little while, so don't slam i2c */
903 udelay(2000);
904 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
905 TWL4030_REG_ANAMICL);
906 } while ((i++ < 100) &&
907 ((byte & TWL4030_CNCL_OFFSET_START) ==
908 TWL4030_CNCL_OFFSET_START));
909
910 /* anti-pop when changing analog gain */
911 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
912 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
913 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
914
915 /* toggle CODECPDZ as per TRM */
916 twl4030_clear_codecpdz(codec);
917 twl4030_set_codecpdz(codec);
918
919 /* program anti-pop with bias ramp delay */
920 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
921 popn &= TWL4030_RAMP_DELAY;
922 popn |= TWL4030_RAMP_DELAY_645MS;
923 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
924 popn |= TWL4030_VMID_EN;
925 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
926
927 /* enable anti-pop ramp */
928 popn |= TWL4030_RAMP_EN;
929 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
930 }
931
932 static void twl4030_power_down(struct snd_soc_codec *codec)
933 {
934 u8 popn;
935
936 /* disable anti-pop ramp */
937 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
938 popn &= ~TWL4030_RAMP_EN;
939 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
940
941 /* disable bias out */
942 popn &= ~TWL4030_VMID_EN;
943 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
944
945 /* power down */
946 twl4030_clear_codecpdz(codec);
947 }
948
949 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
950 enum snd_soc_bias_level level)
951 {
952 switch (level) {
953 case SND_SOC_BIAS_ON:
954 twl4030_power_up(codec);
955 break;
956 case SND_SOC_BIAS_PREPARE:
957 /* TODO: develop a twl4030_prepare function */
958 break;
959 case SND_SOC_BIAS_STANDBY:
960 /* TODO: develop a twl4030_standby function */
961 twl4030_power_down(codec);
962 break;
963 case SND_SOC_BIAS_OFF:
964 twl4030_power_down(codec);
965 break;
966 }
967 codec->bias_level = level;
968
969 return 0;
970 }
971
972 static int twl4030_hw_params(struct snd_pcm_substream *substream,
973 struct snd_pcm_hw_params *params,
974 struct snd_soc_dai *dai)
975 {
976 struct snd_soc_pcm_runtime *rtd = substream->private_data;
977 struct snd_soc_device *socdev = rtd->socdev;
978 struct snd_soc_codec *codec = socdev->codec;
979 u8 mode, old_mode, format, old_format;
980
981
982 /* bit rate */
983 old_mode = twl4030_read_reg_cache(codec,
984 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
985 mode = old_mode & ~TWL4030_APLL_RATE;
986
987 switch (params_rate(params)) {
988 case 8000:
989 mode |= TWL4030_APLL_RATE_8000;
990 break;
991 case 11025:
992 mode |= TWL4030_APLL_RATE_11025;
993 break;
994 case 12000:
995 mode |= TWL4030_APLL_RATE_12000;
996 break;
997 case 16000:
998 mode |= TWL4030_APLL_RATE_16000;
999 break;
1000 case 22050:
1001 mode |= TWL4030_APLL_RATE_22050;
1002 break;
1003 case 24000:
1004 mode |= TWL4030_APLL_RATE_24000;
1005 break;
1006 case 32000:
1007 mode |= TWL4030_APLL_RATE_32000;
1008 break;
1009 case 44100:
1010 mode |= TWL4030_APLL_RATE_44100;
1011 break;
1012 case 48000:
1013 mode |= TWL4030_APLL_RATE_48000;
1014 break;
1015 default:
1016 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1017 params_rate(params));
1018 return -EINVAL;
1019 }
1020
1021 if (mode != old_mode) {
1022 /* change rate and set CODECPDZ */
1023 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1024 twl4030_set_codecpdz(codec);
1025 }
1026
1027 /* sample size */
1028 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1029 format = old_format;
1030 format &= ~TWL4030_DATA_WIDTH;
1031 switch (params_format(params)) {
1032 case SNDRV_PCM_FORMAT_S16_LE:
1033 format |= TWL4030_DATA_WIDTH_16S_16W;
1034 break;
1035 case SNDRV_PCM_FORMAT_S24_LE:
1036 format |= TWL4030_DATA_WIDTH_32S_24W;
1037 break;
1038 default:
1039 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1040 params_format(params));
1041 return -EINVAL;
1042 }
1043
1044 if (format != old_format) {
1045
1046 /* clear CODECPDZ before changing format (codec requirement) */
1047 twl4030_clear_codecpdz(codec);
1048
1049 /* change format */
1050 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1051
1052 /* set CODECPDZ afterwards */
1053 twl4030_set_codecpdz(codec);
1054 }
1055 return 0;
1056 }
1057
1058 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1059 int clk_id, unsigned int freq, int dir)
1060 {
1061 struct snd_soc_codec *codec = codec_dai->codec;
1062 u8 infreq;
1063
1064 switch (freq) {
1065 case 19200000:
1066 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1067 break;
1068 case 26000000:
1069 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1070 break;
1071 case 38400000:
1072 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1073 break;
1074 default:
1075 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1076 freq);
1077 return -EINVAL;
1078 }
1079
1080 infreq |= TWL4030_APLL_EN;
1081 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1082
1083 return 0;
1084 }
1085
1086 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1087 unsigned int fmt)
1088 {
1089 struct snd_soc_codec *codec = codec_dai->codec;
1090 u8 old_format, format;
1091
1092 /* get format */
1093 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1094 format = old_format;
1095
1096 /* set master/slave audio interface */
1097 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1098 case SND_SOC_DAIFMT_CBM_CFM:
1099 format &= ~(TWL4030_AIF_SLAVE_EN);
1100 format &= ~(TWL4030_CLK256FS_EN);
1101 break;
1102 case SND_SOC_DAIFMT_CBS_CFS:
1103 format |= TWL4030_AIF_SLAVE_EN;
1104 format |= TWL4030_CLK256FS_EN;
1105 break;
1106 default:
1107 return -EINVAL;
1108 }
1109
1110 /* interface format */
1111 format &= ~TWL4030_AIF_FORMAT;
1112 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1113 case SND_SOC_DAIFMT_I2S:
1114 format |= TWL4030_AIF_FORMAT_CODEC;
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119
1120 if (format != old_format) {
1121
1122 /* clear CODECPDZ before changing format (codec requirement) */
1123 twl4030_clear_codecpdz(codec);
1124
1125 /* change format */
1126 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1127
1128 /* set CODECPDZ afterwards */
1129 twl4030_set_codecpdz(codec);
1130 }
1131
1132 return 0;
1133 }
1134
1135 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1136 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1137
1138 struct snd_soc_dai twl4030_dai = {
1139 .name = "twl4030",
1140 .playback = {
1141 .stream_name = "Playback",
1142 .channels_min = 2,
1143 .channels_max = 2,
1144 .rates = TWL4030_RATES,
1145 .formats = TWL4030_FORMATS,},
1146 .capture = {
1147 .stream_name = "Capture",
1148 .channels_min = 2,
1149 .channels_max = 2,
1150 .rates = TWL4030_RATES,
1151 .formats = TWL4030_FORMATS,},
1152 .ops = {
1153 .hw_params = twl4030_hw_params,
1154 .set_sysclk = twl4030_set_dai_sysclk,
1155 .set_fmt = twl4030_set_dai_fmt,
1156 }
1157 };
1158 EXPORT_SYMBOL_GPL(twl4030_dai);
1159
1160 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1161 {
1162 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1163 struct snd_soc_codec *codec = socdev->codec;
1164
1165 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1166
1167 return 0;
1168 }
1169
1170 static int twl4030_resume(struct platform_device *pdev)
1171 {
1172 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1173 struct snd_soc_codec *codec = socdev->codec;
1174
1175 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1176 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1177 return 0;
1178 }
1179
1180 /*
1181 * initialize the driver
1182 * register the mixer and dsp interfaces with the kernel
1183 */
1184
1185 static int twl4030_init(struct snd_soc_device *socdev)
1186 {
1187 struct snd_soc_codec *codec = socdev->codec;
1188 int ret = 0;
1189
1190 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1191
1192 codec->name = "twl4030";
1193 codec->owner = THIS_MODULE;
1194 codec->read = twl4030_read_reg_cache;
1195 codec->write = twl4030_write;
1196 codec->set_bias_level = twl4030_set_bias_level;
1197 codec->dai = &twl4030_dai;
1198 codec->num_dai = 1;
1199 codec->reg_cache_size = sizeof(twl4030_reg);
1200 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1201 GFP_KERNEL);
1202 if (codec->reg_cache == NULL)
1203 return -ENOMEM;
1204
1205 /* register pcms */
1206 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1207 if (ret < 0) {
1208 printk(KERN_ERR "twl4030: failed to create pcms\n");
1209 goto pcm_err;
1210 }
1211
1212 twl4030_init_chip(codec);
1213
1214 /* power on device */
1215 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1216
1217 twl4030_add_controls(codec);
1218 twl4030_add_widgets(codec);
1219
1220 ret = snd_soc_init_card(socdev);
1221 if (ret < 0) {
1222 printk(KERN_ERR "twl4030: failed to register card\n");
1223 goto card_err;
1224 }
1225
1226 return ret;
1227
1228 card_err:
1229 snd_soc_free_pcms(socdev);
1230 snd_soc_dapm_free(socdev);
1231 pcm_err:
1232 kfree(codec->reg_cache);
1233 return ret;
1234 }
1235
1236 static struct snd_soc_device *twl4030_socdev;
1237
1238 static int twl4030_probe(struct platform_device *pdev)
1239 {
1240 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1241 struct snd_soc_codec *codec;
1242
1243 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1244 if (codec == NULL)
1245 return -ENOMEM;
1246
1247 socdev->codec = codec;
1248 mutex_init(&codec->mutex);
1249 INIT_LIST_HEAD(&codec->dapm_widgets);
1250 INIT_LIST_HEAD(&codec->dapm_paths);
1251
1252 twl4030_socdev = socdev;
1253 twl4030_init(socdev);
1254
1255 return 0;
1256 }
1257
1258 static int twl4030_remove(struct platform_device *pdev)
1259 {
1260 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1261 struct snd_soc_codec *codec = socdev->codec;
1262
1263 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1264 kfree(codec);
1265
1266 return 0;
1267 }
1268
1269 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1270 .probe = twl4030_probe,
1271 .remove = twl4030_remove,
1272 .suspend = twl4030_suspend,
1273 .resume = twl4030_resume,
1274 };
1275 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1276
1277 static int __init twl4030_modinit(void)
1278 {
1279 return snd_soc_register_dai(&twl4030_dai);
1280 }
1281 module_init(twl4030_modinit);
1282
1283 static void __exit twl4030_exit(void)
1284 {
1285 snd_soc_unregister_dai(&twl4030_dai);
1286 }
1287 module_exit(twl4030_exit);
1288
1289 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1290 MODULE_AUTHOR("Steve Sakoman");
1291 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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