2 * ALSA SoC TWL4030 codec driver
4 * Author: Steve Sakoman, <steve@sakoman.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
41 * twl4030 register cache & default register settings
43 static const u8 twl4030_reg
[TWL4030_CACHEREGNUM
] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
121 * read twl4030 register cache
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec
*codec
,
126 u8
*cache
= codec
->reg_cache
;
132 * write twl4030 register cache
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec
*codec
,
137 u8
*cache
= codec
->reg_cache
;
139 if (reg
>= TWL4030_CACHEREGNUM
)
145 * write to the twl4030 register space
147 static int twl4030_write(struct snd_soc_codec
*codec
,
148 unsigned int reg
, unsigned int value
)
150 twl4030_write_reg_cache(codec
, reg
, value
);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE
, value
, reg
);
154 static void twl4030_clear_codecpdz(struct snd_soc_codec
*codec
)
158 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
159 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
160 mode
& ~TWL4030_CODECPDZ
);
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
167 static void twl4030_set_codecpdz(struct snd_soc_codec
*codec
)
171 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
172 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
173 mode
| TWL4030_CODECPDZ
);
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
180 static void twl4030_init_chip(struct snd_soc_codec
*codec
)
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec
);
187 /* set all audio section registers to reasonable defaults */
188 for (i
= TWL4030_REG_OPTION
; i
<= TWL4030_REG_MISC_SET_2
; i
++)
189 twl4030_write(codec
, i
, twl4030_reg
[i
]);
194 static const char *twl4030_earpiece_texts
[] =
195 {"Off", "DACL1", "DACL2", "Invalid", "DACR1"};
197 static const struct soc_enum twl4030_earpiece_enum
=
198 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL
, 1,
199 ARRAY_SIZE(twl4030_earpiece_texts
),
200 twl4030_earpiece_texts
);
202 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control
=
203 SOC_DAPM_ENUM("Route", twl4030_earpiece_enum
);
206 static const char *twl4030_predrivel_texts
[] =
207 {"Off", "DACL1", "DACL2", "Invalid", "DACR2"};
209 static const struct soc_enum twl4030_predrivel_enum
=
210 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL
, 1,
211 ARRAY_SIZE(twl4030_predrivel_texts
),
212 twl4030_predrivel_texts
);
214 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control
=
215 SOC_DAPM_ENUM("Route", twl4030_predrivel_enum
);
218 static const char *twl4030_predriver_texts
[] =
219 {"Off", "DACR1", "DACR2", "Invalid", "DACL2"};
221 static const struct soc_enum twl4030_predriver_enum
=
222 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL
, 1,
223 ARRAY_SIZE(twl4030_predriver_texts
),
224 twl4030_predriver_texts
);
226 static const struct snd_kcontrol_new twl4030_dapm_predriver_control
=
227 SOC_DAPM_ENUM("Route", twl4030_predriver_enum
);
230 static const char *twl4030_hsol_texts
[] =
231 {"Off", "DACL1", "DACL2"};
233 static const struct soc_enum twl4030_hsol_enum
=
234 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL
, 1,
235 ARRAY_SIZE(twl4030_hsol_texts
),
238 static const struct snd_kcontrol_new twl4030_dapm_hsol_control
=
239 SOC_DAPM_ENUM("Route", twl4030_hsol_enum
);
242 static const char *twl4030_hsor_texts
[] =
243 {"Off", "DACR1", "DACR2"};
245 static const struct soc_enum twl4030_hsor_enum
=
246 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL
, 4,
247 ARRAY_SIZE(twl4030_hsor_texts
),
250 static const struct snd_kcontrol_new twl4030_dapm_hsor_control
=
251 SOC_DAPM_ENUM("Route", twl4030_hsor_enum
);
254 static const char *twl4030_carkitl_texts
[] =
255 {"Off", "DACL1", "DACL2"};
257 static const struct soc_enum twl4030_carkitl_enum
=
258 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL
, 1,
259 ARRAY_SIZE(twl4030_carkitl_texts
),
260 twl4030_carkitl_texts
);
262 static const struct snd_kcontrol_new twl4030_dapm_carkitl_control
=
263 SOC_DAPM_ENUM("Route", twl4030_carkitl_enum
);
266 static const char *twl4030_carkitr_texts
[] =
267 {"Off", "DACR1", "DACR2"};
269 static const struct soc_enum twl4030_carkitr_enum
=
270 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL
, 1,
271 ARRAY_SIZE(twl4030_carkitr_texts
),
272 twl4030_carkitr_texts
);
274 static const struct snd_kcontrol_new twl4030_dapm_carkitr_control
=
275 SOC_DAPM_ENUM("Route", twl4030_carkitr_enum
);
278 static const char *twl4030_handsfreel_texts
[] =
279 {"Voice", "DACL1", "DACL2", "DACR2"};
281 static const struct soc_enum twl4030_handsfreel_enum
=
282 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL
, 0,
283 ARRAY_SIZE(twl4030_handsfreel_texts
),
284 twl4030_handsfreel_texts
);
286 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control
=
287 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum
);
289 /* Handsfree Right */
290 static const char *twl4030_handsfreer_texts
[] =
291 {"Voice", "DACR1", "DACR2", "DACL2"};
293 static const struct soc_enum twl4030_handsfreer_enum
=
294 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL
, 0,
295 ARRAY_SIZE(twl4030_handsfreer_texts
),
296 twl4030_handsfreer_texts
);
298 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control
=
299 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum
);
301 static int outmixer_event(struct snd_soc_dapm_widget
*w
,
302 struct snd_kcontrol
*kcontrol
, int event
)
304 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
309 case TWL4030_REG_PREDL_CTL
:
310 case TWL4030_REG_PREDR_CTL
:
311 case TWL4030_REG_EAR_CTL
:
312 val
= w
->value
>> e
->shift_l
;
315 "Invalid MUX setting for register 0x%02x (%d)\n",
325 static int handsfree_event(struct snd_soc_dapm_widget
*w
,
326 struct snd_kcontrol
*kcontrol
, int event
)
328 struct soc_enum
*e
= (struct soc_enum
*)w
->kcontrols
->private_value
;
329 unsigned char hs_ctl
;
331 hs_ctl
= twl4030_read_reg_cache(w
->codec
, e
->reg
);
333 if (hs_ctl
& TWL4030_HF_CTL_REF_EN
) {
334 hs_ctl
|= TWL4030_HF_CTL_RAMP_EN
;
335 twl4030_write(w
->codec
, e
->reg
, hs_ctl
);
336 hs_ctl
|= TWL4030_HF_CTL_LOOP_EN
;
337 twl4030_write(w
->codec
, e
->reg
, hs_ctl
);
338 hs_ctl
|= TWL4030_HF_CTL_HB_EN
;
339 twl4030_write(w
->codec
, e
->reg
, hs_ctl
);
341 hs_ctl
&= ~(TWL4030_HF_CTL_RAMP_EN
| TWL4030_HF_CTL_LOOP_EN
342 | TWL4030_HF_CTL_HB_EN
);
343 twl4030_write(w
->codec
, e
->reg
, hs_ctl
);
350 * Some of the gain controls in TWL (mostly those which are associated with
351 * the outputs) are implemented in an interesting way:
352 * 0x0 : Power down (mute)
356 * Inverting not going to help with these.
357 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
359 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
360 xinvert, tlv_array) \
361 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
362 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
363 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
364 .tlv.p = (tlv_array), \
365 .info = snd_soc_info_volsw, \
366 .get = snd_soc_get_volsw_twl4030, \
367 .put = snd_soc_put_volsw_twl4030, \
368 .private_value = (unsigned long)&(struct soc_mixer_control) \
369 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
370 .max = xmax, .invert = xinvert} }
371 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
372 xinvert, tlv_array) \
373 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
374 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
375 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
376 .tlv.p = (tlv_array), \
377 .info = snd_soc_info_volsw_2r, \
378 .get = snd_soc_get_volsw_r2_twl4030,\
379 .put = snd_soc_put_volsw_r2_twl4030, \
380 .private_value = (unsigned long)&(struct soc_mixer_control) \
381 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
382 .rshift = xshift, .max = xmax, .invert = xinvert} }
383 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
384 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
387 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
388 struct snd_ctl_elem_value
*ucontrol
)
390 struct soc_mixer_control
*mc
=
391 (struct soc_mixer_control
*)kcontrol
->private_value
;
392 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
393 unsigned int reg
= mc
->reg
;
394 unsigned int shift
= mc
->shift
;
395 unsigned int rshift
= mc
->rshift
;
397 int mask
= (1 << fls(max
)) - 1;
399 ucontrol
->value
.integer
.value
[0] =
400 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
401 if (ucontrol
->value
.integer
.value
[0])
402 ucontrol
->value
.integer
.value
[0] =
403 max
+ 1 - ucontrol
->value
.integer
.value
[0];
405 if (shift
!= rshift
) {
406 ucontrol
->value
.integer
.value
[1] =
407 (snd_soc_read(codec
, reg
) >> rshift
) & mask
;
408 if (ucontrol
->value
.integer
.value
[1])
409 ucontrol
->value
.integer
.value
[1] =
410 max
+ 1 - ucontrol
->value
.integer
.value
[1];
416 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
417 struct snd_ctl_elem_value
*ucontrol
)
419 struct soc_mixer_control
*mc
=
420 (struct soc_mixer_control
*)kcontrol
->private_value
;
421 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
422 unsigned int reg
= mc
->reg
;
423 unsigned int shift
= mc
->shift
;
424 unsigned int rshift
= mc
->rshift
;
426 int mask
= (1 << fls(max
)) - 1;
427 unsigned short val
, val2
, val_mask
;
429 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
431 val_mask
= mask
<< shift
;
435 if (shift
!= rshift
) {
436 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
437 val_mask
|= mask
<< rshift
;
439 val2
= max
+ 1 - val2
;
440 val
|= val2
<< rshift
;
442 return snd_soc_update_bits(codec
, reg
, val_mask
, val
);
445 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
446 struct snd_ctl_elem_value
*ucontrol
)
448 struct soc_mixer_control
*mc
=
449 (struct soc_mixer_control
*)kcontrol
->private_value
;
450 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
451 unsigned int reg
= mc
->reg
;
452 unsigned int reg2
= mc
->rreg
;
453 unsigned int shift
= mc
->shift
;
455 int mask
= (1<<fls(max
))-1;
457 ucontrol
->value
.integer
.value
[0] =
458 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
459 ucontrol
->value
.integer
.value
[1] =
460 (snd_soc_read(codec
, reg2
) >> shift
) & mask
;
462 if (ucontrol
->value
.integer
.value
[0])
463 ucontrol
->value
.integer
.value
[0] =
464 max
+ 1 - ucontrol
->value
.integer
.value
[0];
465 if (ucontrol
->value
.integer
.value
[1])
466 ucontrol
->value
.integer
.value
[1] =
467 max
+ 1 - ucontrol
->value
.integer
.value
[1];
472 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
473 struct snd_ctl_elem_value
*ucontrol
)
475 struct soc_mixer_control
*mc
=
476 (struct soc_mixer_control
*)kcontrol
->private_value
;
477 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
478 unsigned int reg
= mc
->reg
;
479 unsigned int reg2
= mc
->rreg
;
480 unsigned int shift
= mc
->shift
;
482 int mask
= (1 << fls(max
)) - 1;
484 unsigned short val
, val2
, val_mask
;
486 val_mask
= mask
<< shift
;
487 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
488 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
493 val2
= max
+ 1 - val2
;
496 val2
= val2
<< shift
;
498 err
= snd_soc_update_bits(codec
, reg
, val_mask
, val
);
502 err
= snd_soc_update_bits(codec
, reg2
, val_mask
, val2
);
506 static int twl4030_get_left_input(struct snd_kcontrol
*kcontrol
,
507 struct snd_ctl_elem_value
*ucontrol
)
509 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
510 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
513 /* one bit must be set a time */
514 reg
&= TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
515 | TWL4030_MAINMIC_EN
;
518 while ((reg
& 1) == 0) {
524 ucontrol
->value
.integer
.value
[0] = result
;
528 static int twl4030_put_left_input(struct snd_kcontrol
*kcontrol
,
529 struct snd_ctl_elem_value
*ucontrol
)
531 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
532 int value
= ucontrol
->value
.integer
.value
[0];
533 u8 anamicl
, micbias
, avadc_ctl
;
535 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
536 anamicl
&= ~(TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
537 | TWL4030_MAINMIC_EN
);
538 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
539 micbias
&= ~(TWL4030_HSMICBIAS_EN
| TWL4030_MICBIAS1_EN
);
540 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
544 anamicl
|= TWL4030_MAINMIC_EN
;
545 micbias
|= TWL4030_MICBIAS1_EN
;
548 anamicl
|= TWL4030_HSMIC_EN
;
549 micbias
|= TWL4030_HSMICBIAS_EN
;
552 anamicl
|= TWL4030_AUXL_EN
;
555 anamicl
|= TWL4030_CKMIC_EN
;
561 /* If some input is selected, enable amp and ADC */
563 anamicl
|= TWL4030_MICAMPL_EN
;
564 avadc_ctl
|= TWL4030_ADCL_EN
;
566 anamicl
&= ~TWL4030_MICAMPL_EN
;
567 avadc_ctl
&= ~TWL4030_ADCL_EN
;
570 twl4030_write(codec
, TWL4030_REG_ANAMICL
, anamicl
);
571 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
572 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
577 static int twl4030_get_right_input(struct snd_kcontrol
*kcontrol
,
578 struct snd_ctl_elem_value
*ucontrol
)
580 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
581 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
584 reg
&= TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
;
586 case TWL4030_SUBMIC_EN
:
589 case TWL4030_AUXR_EN
:
596 ucontrol
->value
.integer
.value
[0] = value
;
600 static int twl4030_put_right_input(struct snd_kcontrol
*kcontrol
,
601 struct snd_ctl_elem_value
*ucontrol
)
603 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
604 int value
= ucontrol
->value
.integer
.value
[0];
605 u8 anamicr
, micbias
, avadc_ctl
;
607 anamicr
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
608 anamicr
&= ~(TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
);
609 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
610 micbias
&= ~TWL4030_MICBIAS2_EN
;
611 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
615 anamicr
|= TWL4030_SUBMIC_EN
;
616 micbias
|= TWL4030_MICBIAS2_EN
;
619 anamicr
|= TWL4030_AUXR_EN
;
626 anamicr
|= TWL4030_MICAMPR_EN
;
627 avadc_ctl
|= TWL4030_ADCR_EN
;
629 anamicr
&= ~TWL4030_MICAMPR_EN
;
630 avadc_ctl
&= ~TWL4030_ADCR_EN
;
633 twl4030_write(codec
, TWL4030_REG_ANAMICR
, anamicr
);
634 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
635 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
640 static const char *twl4030_left_in_sel
[] = {
648 static const char *twl4030_right_in_sel
[] = {
654 static const struct soc_enum twl4030_left_input_mux
=
655 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel
),
656 twl4030_left_in_sel
);
658 static const struct soc_enum twl4030_right_input_mux
=
659 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel
),
660 twl4030_right_in_sel
);
663 * FGAIN volume control:
664 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
666 static DECLARE_TLV_DB_SCALE(digital_fine_tlv
, -6300, 100, 1);
669 * CGAIN volume control:
670 * 0 dB to 12 dB in 6 dB steps
671 * value 2 and 3 means 12 dB
673 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv
, 0, 600, 0);
676 * Analog playback gain
677 * -24 dB to 12 dB in 2 dB steps
679 static DECLARE_TLV_DB_SCALE(analog_tlv
, -2400, 200, 0);
682 * Gain controls tied to outputs
683 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
685 static DECLARE_TLV_DB_SCALE(output_tvl
, -1200, 600, 1);
688 * Capture gain after the ADCs
689 * from 0 dB to 31 dB in 1 dB steps
691 static DECLARE_TLV_DB_SCALE(digital_capture_tlv
, 0, 100, 0);
694 * Gain control for input amplifiers
695 * 0 dB to 30 dB in 6 dB steps
697 static DECLARE_TLV_DB_SCALE(input_gain_tlv
, 0, 600, 0);
699 static const struct snd_kcontrol_new twl4030_snd_controls
[] = {
700 /* Common playback gain controls */
701 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
702 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
703 0, 0x3f, 0, digital_fine_tlv
),
704 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
705 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
706 0, 0x3f, 0, digital_fine_tlv
),
708 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
709 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
710 6, 0x2, 0, digital_coarse_tlv
),
711 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
712 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
713 6, 0x2, 0, digital_coarse_tlv
),
715 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
716 TWL4030_REG_ARXL1_APGA_CTL
, TWL4030_REG_ARXR1_APGA_CTL
,
717 3, 0x12, 1, analog_tlv
),
718 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
719 TWL4030_REG_ARXL2_APGA_CTL
, TWL4030_REG_ARXR2_APGA_CTL
,
720 3, 0x12, 1, analog_tlv
),
721 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
722 TWL4030_REG_ARXL1_APGA_CTL
, TWL4030_REG_ARXR1_APGA_CTL
,
724 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
725 TWL4030_REG_ARXL2_APGA_CTL
, TWL4030_REG_ARXR2_APGA_CTL
,
728 /* Separate output gain controls */
729 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
730 TWL4030_REG_PREDL_CTL
, TWL4030_REG_PREDR_CTL
,
731 4, 3, 0, output_tvl
),
733 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
734 TWL4030_REG_HS_GAIN_SET
, 0, 2, 3, 0, output_tvl
),
736 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
737 TWL4030_REG_PRECKL_CTL
, TWL4030_REG_PRECKR_CTL
,
738 4, 3, 0, output_tvl
),
740 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
741 TWL4030_REG_EAR_CTL
, 4, 3, 0, output_tvl
),
743 /* Common capture gain controls */
744 SOC_DOUBLE_R_TLV("Capture Volume",
745 TWL4030_REG_ATXL1PGA
, TWL4030_REG_ATXR1PGA
,
746 0, 0x1f, 0, digital_capture_tlv
),
748 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN
,
749 0, 3, 5, 0, input_gain_tlv
),
751 /* Input source controls */
752 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux
,
753 twl4030_get_left_input
, twl4030_put_left_input
),
754 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux
,
755 twl4030_get_right_input
, twl4030_put_right_input
),
758 /* add non dapm controls */
759 static int twl4030_add_controls(struct snd_soc_codec
*codec
)
763 for (i
= 0; i
< ARRAY_SIZE(twl4030_snd_controls
); i
++) {
764 err
= snd_ctl_add(codec
->card
,
765 snd_soc_cnew(&twl4030_snd_controls
[i
],
774 static const struct snd_soc_dapm_widget twl4030_dapm_widgets
[] = {
775 SND_SOC_DAPM_INPUT("INL"),
776 SND_SOC_DAPM_INPUT("INR"),
778 SND_SOC_DAPM_OUTPUT("OUTL"),
779 SND_SOC_DAPM_OUTPUT("OUTR"),
780 SND_SOC_DAPM_OUTPUT("EARPIECE"),
781 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
782 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
783 SND_SOC_DAPM_OUTPUT("HSOL"),
784 SND_SOC_DAPM_OUTPUT("HSOR"),
785 SND_SOC_DAPM_OUTPUT("CARKITL"),
786 SND_SOC_DAPM_OUTPUT("CARKITR"),
787 SND_SOC_DAPM_OUTPUT("HFL"),
788 SND_SOC_DAPM_OUTPUT("HFR"),
791 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
792 TWL4030_REG_AVDAC_CTL
, 0, 0),
793 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
794 TWL4030_REG_AVDAC_CTL
, 1, 0),
795 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
796 TWL4030_REG_AVDAC_CTL
, 2, 0),
797 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
798 TWL4030_REG_AVDAC_CTL
, 3, 0),
801 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL
,
803 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL
,
805 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL
,
807 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL
,
810 /* Output MUX controls */
812 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM
, 0, 0,
813 &twl4030_dapm_earpiece_control
, outmixer_event
,
814 SND_SOC_DAPM_PRE_REG
),
816 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM
, 0, 0,
817 &twl4030_dapm_predrivel_control
, outmixer_event
,
818 SND_SOC_DAPM_PRE_REG
),
819 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM
, 0, 0,
820 &twl4030_dapm_predriver_control
, outmixer_event
,
821 SND_SOC_DAPM_PRE_REG
),
823 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM
, 0, 0,
824 &twl4030_dapm_hsol_control
),
825 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM
, 0, 0,
826 &twl4030_dapm_hsor_control
),
828 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM
, 0, 0,
829 &twl4030_dapm_carkitl_control
),
830 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM
, 0, 0,
831 &twl4030_dapm_carkitr_control
),
833 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL
, 5, 0,
834 &twl4030_dapm_handsfreel_control
, handsfree_event
,
835 SND_SOC_DAPM_POST_PMU
|SND_SOC_DAPM_POST_PMD
),
836 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL
, 5, 0,
837 &twl4030_dapm_handsfreer_control
, handsfree_event
,
838 SND_SOC_DAPM_POST_PMU
|SND_SOC_DAPM_POST_PMD
),
840 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM
, 0, 0),
841 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM
, 0, 0),
844 static const struct snd_soc_dapm_route intercon
[] = {
845 {"ARXL1_APGA", NULL
, "DAC Left1"},
846 {"ARXR1_APGA", NULL
, "DAC Right1"},
847 {"ARXL2_APGA", NULL
, "DAC Left2"},
848 {"ARXR2_APGA", NULL
, "DAC Right2"},
850 /* Internal playback routings */
852 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
853 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
854 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
856 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
857 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
858 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
860 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
861 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
862 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
864 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
865 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
867 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
868 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
870 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
871 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
873 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
874 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
876 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
877 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
878 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
880 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
881 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
882 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
885 {"OUTL", NULL
, "ARXL2_APGA"},
886 {"OUTR", NULL
, "ARXR2_APGA"},
887 {"EARPIECE", NULL
, "Earpiece Mux"},
888 {"PREDRIVEL", NULL
, "PredriveL Mux"},
889 {"PREDRIVER", NULL
, "PredriveR Mux"},
890 {"HSOL", NULL
, "HeadsetL Mux"},
891 {"HSOR", NULL
, "HeadsetR Mux"},
892 {"CARKITL", NULL
, "CarkitL Mux"},
893 {"CARKITR", NULL
, "CarkitR Mux"},
894 {"HFL", NULL
, "HandsfreeL Mux"},
895 {"HFR", NULL
, "HandsfreeR Mux"},
898 {"ADCL", NULL
, "INL"},
899 {"ADCR", NULL
, "INR"},
902 static int twl4030_add_widgets(struct snd_soc_codec
*codec
)
904 snd_soc_dapm_new_controls(codec
, twl4030_dapm_widgets
,
905 ARRAY_SIZE(twl4030_dapm_widgets
));
907 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
909 snd_soc_dapm_new_widgets(codec
);
913 static void twl4030_power_up(struct snd_soc_codec
*codec
)
915 u8 anamicl
, regmisc1
, byte
, popn
;
918 /* set CODECPDZ to turn on codec */
919 twl4030_set_codecpdz(codec
);
921 /* initiate offset cancellation */
922 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
923 twl4030_write(codec
, TWL4030_REG_ANAMICL
,
924 anamicl
| TWL4030_CNCL_OFFSET_START
);
926 /* wait for offset cancellation to complete */
928 /* this takes a little while, so don't slam i2c */
930 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE
, &byte
,
931 TWL4030_REG_ANAMICL
);
932 } while ((i
++ < 100) &&
933 ((byte
& TWL4030_CNCL_OFFSET_START
) ==
934 TWL4030_CNCL_OFFSET_START
));
936 /* anti-pop when changing analog gain */
937 regmisc1
= twl4030_read_reg_cache(codec
, TWL4030_REG_MISC_SET_1
);
938 twl4030_write(codec
, TWL4030_REG_MISC_SET_1
,
939 regmisc1
| TWL4030_SMOOTH_ANAVOL_EN
);
941 /* toggle CODECPDZ as per TRM */
942 twl4030_clear_codecpdz(codec
);
943 twl4030_set_codecpdz(codec
);
945 /* program anti-pop with bias ramp delay */
946 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
947 popn
&= TWL4030_RAMP_DELAY
;
948 popn
|= TWL4030_RAMP_DELAY_645MS
;
949 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
950 popn
|= TWL4030_VMID_EN
;
951 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
953 /* enable anti-pop ramp */
954 popn
|= TWL4030_RAMP_EN
;
955 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
958 static void twl4030_power_down(struct snd_soc_codec
*codec
)
962 /* disable anti-pop ramp */
963 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
964 popn
&= ~TWL4030_RAMP_EN
;
965 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
967 /* disable bias out */
968 popn
&= ~TWL4030_VMID_EN
;
969 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
972 twl4030_clear_codecpdz(codec
);
975 static int twl4030_set_bias_level(struct snd_soc_codec
*codec
,
976 enum snd_soc_bias_level level
)
979 case SND_SOC_BIAS_ON
:
980 twl4030_power_up(codec
);
982 case SND_SOC_BIAS_PREPARE
:
983 /* TODO: develop a twl4030_prepare function */
985 case SND_SOC_BIAS_STANDBY
:
986 /* TODO: develop a twl4030_standby function */
987 twl4030_power_down(codec
);
989 case SND_SOC_BIAS_OFF
:
990 twl4030_power_down(codec
);
993 codec
->bias_level
= level
;
998 static int twl4030_hw_params(struct snd_pcm_substream
*substream
,
999 struct snd_pcm_hw_params
*params
,
1000 struct snd_soc_dai
*dai
)
1002 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1003 struct snd_soc_device
*socdev
= rtd
->socdev
;
1004 struct snd_soc_codec
*codec
= socdev
->codec
;
1005 u8 mode
, old_mode
, format
, old_format
;
1009 old_mode
= twl4030_read_reg_cache(codec
,
1010 TWL4030_REG_CODEC_MODE
) & ~TWL4030_CODECPDZ
;
1011 mode
= old_mode
& ~TWL4030_APLL_RATE
;
1013 switch (params_rate(params
)) {
1015 mode
|= TWL4030_APLL_RATE_8000
;
1018 mode
|= TWL4030_APLL_RATE_11025
;
1021 mode
|= TWL4030_APLL_RATE_12000
;
1024 mode
|= TWL4030_APLL_RATE_16000
;
1027 mode
|= TWL4030_APLL_RATE_22050
;
1030 mode
|= TWL4030_APLL_RATE_24000
;
1033 mode
|= TWL4030_APLL_RATE_32000
;
1036 mode
|= TWL4030_APLL_RATE_44100
;
1039 mode
|= TWL4030_APLL_RATE_48000
;
1042 printk(KERN_ERR
"TWL4030 hw params: unknown rate %d\n",
1043 params_rate(params
));
1047 if (mode
!= old_mode
) {
1048 /* change rate and set CODECPDZ */
1049 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
, mode
);
1050 twl4030_set_codecpdz(codec
);
1054 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
1055 format
= old_format
;
1056 format
&= ~TWL4030_DATA_WIDTH
;
1057 switch (params_format(params
)) {
1058 case SNDRV_PCM_FORMAT_S16_LE
:
1059 format
|= TWL4030_DATA_WIDTH_16S_16W
;
1061 case SNDRV_PCM_FORMAT_S24_LE
:
1062 format
|= TWL4030_DATA_WIDTH_32S_24W
;
1065 printk(KERN_ERR
"TWL4030 hw params: unknown format %d\n",
1066 params_format(params
));
1070 if (format
!= old_format
) {
1072 /* clear CODECPDZ before changing format (codec requirement) */
1073 twl4030_clear_codecpdz(codec
);
1076 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
1078 /* set CODECPDZ afterwards */
1079 twl4030_set_codecpdz(codec
);
1084 static int twl4030_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1085 int clk_id
, unsigned int freq
, int dir
)
1087 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1092 infreq
= TWL4030_APLL_INFREQ_19200KHZ
;
1095 infreq
= TWL4030_APLL_INFREQ_26000KHZ
;
1098 infreq
= TWL4030_APLL_INFREQ_38400KHZ
;
1101 printk(KERN_ERR
"TWL4030 set sysclk: unknown rate %d\n",
1106 infreq
|= TWL4030_APLL_EN
;
1107 twl4030_write(codec
, TWL4030_REG_APLL_CTL
, infreq
);
1112 static int twl4030_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1115 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1116 u8 old_format
, format
;
1119 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
1120 format
= old_format
;
1122 /* set master/slave audio interface */
1123 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1124 case SND_SOC_DAIFMT_CBM_CFM
:
1125 format
&= ~(TWL4030_AIF_SLAVE_EN
);
1126 format
&= ~(TWL4030_CLK256FS_EN
);
1128 case SND_SOC_DAIFMT_CBS_CFS
:
1129 format
|= TWL4030_AIF_SLAVE_EN
;
1130 format
|= TWL4030_CLK256FS_EN
;
1136 /* interface format */
1137 format
&= ~TWL4030_AIF_FORMAT
;
1138 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1139 case SND_SOC_DAIFMT_I2S
:
1140 format
|= TWL4030_AIF_FORMAT_CODEC
;
1146 if (format
!= old_format
) {
1148 /* clear CODECPDZ before changing format (codec requirement) */
1149 twl4030_clear_codecpdz(codec
);
1152 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
1154 /* set CODECPDZ afterwards */
1155 twl4030_set_codecpdz(codec
);
1161 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1162 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1164 struct snd_soc_dai twl4030_dai
= {
1167 .stream_name
= "Playback",
1170 .rates
= TWL4030_RATES
,
1171 .formats
= TWL4030_FORMATS
,},
1173 .stream_name
= "Capture",
1176 .rates
= TWL4030_RATES
,
1177 .formats
= TWL4030_FORMATS
,},
1179 .hw_params
= twl4030_hw_params
,
1180 .set_sysclk
= twl4030_set_dai_sysclk
,
1181 .set_fmt
= twl4030_set_dai_fmt
,
1184 EXPORT_SYMBOL_GPL(twl4030_dai
);
1186 static int twl4030_suspend(struct platform_device
*pdev
, pm_message_t state
)
1188 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1189 struct snd_soc_codec
*codec
= socdev
->codec
;
1191 twl4030_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1196 static int twl4030_resume(struct platform_device
*pdev
)
1198 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1199 struct snd_soc_codec
*codec
= socdev
->codec
;
1201 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1202 twl4030_set_bias_level(codec
, codec
->suspend_bias_level
);
1207 * initialize the driver
1208 * register the mixer and dsp interfaces with the kernel
1211 static int twl4030_init(struct snd_soc_device
*socdev
)
1213 struct snd_soc_codec
*codec
= socdev
->codec
;
1216 printk(KERN_INFO
"TWL4030 Audio Codec init \n");
1218 codec
->name
= "twl4030";
1219 codec
->owner
= THIS_MODULE
;
1220 codec
->read
= twl4030_read_reg_cache
;
1221 codec
->write
= twl4030_write
;
1222 codec
->set_bias_level
= twl4030_set_bias_level
;
1223 codec
->dai
= &twl4030_dai
;
1225 codec
->reg_cache_size
= sizeof(twl4030_reg
);
1226 codec
->reg_cache
= kmemdup(twl4030_reg
, sizeof(twl4030_reg
),
1228 if (codec
->reg_cache
== NULL
)
1232 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1234 printk(KERN_ERR
"twl4030: failed to create pcms\n");
1238 twl4030_init_chip(codec
);
1240 /* power on device */
1241 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1243 twl4030_add_controls(codec
);
1244 twl4030_add_widgets(codec
);
1246 ret
= snd_soc_init_card(socdev
);
1248 printk(KERN_ERR
"twl4030: failed to register card\n");
1255 snd_soc_free_pcms(socdev
);
1256 snd_soc_dapm_free(socdev
);
1258 kfree(codec
->reg_cache
);
1262 static struct snd_soc_device
*twl4030_socdev
;
1264 static int twl4030_probe(struct platform_device
*pdev
)
1266 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1267 struct snd_soc_codec
*codec
;
1269 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1273 socdev
->codec
= codec
;
1274 mutex_init(&codec
->mutex
);
1275 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1276 INIT_LIST_HEAD(&codec
->dapm_paths
);
1278 twl4030_socdev
= socdev
;
1279 twl4030_init(socdev
);
1284 static int twl4030_remove(struct platform_device
*pdev
)
1286 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1287 struct snd_soc_codec
*codec
= socdev
->codec
;
1289 printk(KERN_INFO
"TWL4030 Audio Codec remove\n");
1295 struct snd_soc_codec_device soc_codec_dev_twl4030
= {
1296 .probe
= twl4030_probe
,
1297 .remove
= twl4030_remove
,
1298 .suspend
= twl4030_suspend
,
1299 .resume
= twl4030_resume
,
1301 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030
);
1303 static int __init
twl4030_modinit(void)
1305 return snd_soc_register_dai(&twl4030_dai
);
1307 module_init(twl4030_modinit
);
1309 static void __exit
twl4030_exit(void)
1311 snd_soc_unregister_dai(&twl4030_dai
);
1313 module_exit(twl4030_exit
);
1315 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1316 MODULE_AUTHOR("Steve Sakoman");
1317 MODULE_LICENSE("GPL");