2 * ALSA SoC TWL4030 codec driver
4 * Author: Steve Sakoman, <steve@sakoman.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
41 * twl4030 register cache & default register settings
43 static const u8 twl4030_reg
[TWL4030_CACHEREGNUM
] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
121 * read twl4030 register cache
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec
*codec
,
126 u8
*cache
= codec
->reg_cache
;
132 * write twl4030 register cache
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec
*codec
,
137 u8
*cache
= codec
->reg_cache
;
139 if (reg
>= TWL4030_CACHEREGNUM
)
145 * write to the twl4030 register space
147 static int twl4030_write(struct snd_soc_codec
*codec
,
148 unsigned int reg
, unsigned int value
)
150 twl4030_write_reg_cache(codec
, reg
, value
);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE
, value
, reg
);
154 static void twl4030_clear_codecpdz(struct snd_soc_codec
*codec
)
158 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
159 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
160 mode
& ~TWL4030_CODECPDZ
);
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
167 static void twl4030_set_codecpdz(struct snd_soc_codec
*codec
)
171 mode
= twl4030_read_reg_cache(codec
, TWL4030_REG_CODEC_MODE
);
172 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
,
173 mode
| TWL4030_CODECPDZ
);
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
180 static void twl4030_init_chip(struct snd_soc_codec
*codec
)
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec
);
187 /* set all audio section registers to reasonable defaults */
188 for (i
= TWL4030_REG_OPTION
; i
<= TWL4030_REG_MISC_SET_2
; i
++)
189 twl4030_write(codec
, i
, twl4030_reg
[i
]);
194 static const char *twl4030_earpiece_texts
[] =
195 {"Off", "DACL1", "DACL2", "Invalid",
198 static const struct soc_enum twl4030_earpiece_enum
=
199 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL
, 1,
200 ARRAY_SIZE(twl4030_earpiece_texts
),
201 twl4030_earpiece_texts
);
203 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control
=
204 SOC_DAPM_ENUM("Route", twl4030_earpiece_enum
);
207 static const char *twl4030_predrivel_texts
[] =
208 {"Off", "DACL1", "DACL2", "Invalid",
211 static const struct soc_enum twl4030_predrivel_enum
=
212 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL
, 1,
213 ARRAY_SIZE(twl4030_predrivel_texts
),
214 twl4030_predrivel_texts
);
216 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control
=
217 SOC_DAPM_ENUM("Route", twl4030_predrivel_enum
);
220 static const char *twl4030_predriver_texts
[] =
221 {"Off", "DACR1", "DACR2", "Invalid",
224 static const struct soc_enum twl4030_predriver_enum
=
225 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL
, 1,
226 ARRAY_SIZE(twl4030_predriver_texts
),
227 twl4030_predriver_texts
);
229 static const struct snd_kcontrol_new twl4030_dapm_predriver_control
=
230 SOC_DAPM_ENUM("Route", twl4030_predriver_enum
);
233 static const char *twl4030_hsol_texts
[] =
234 {"Off", "DACL1", "DACL2"};
236 static const struct soc_enum twl4030_hsol_enum
=
237 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL
, 1,
238 ARRAY_SIZE(twl4030_hsol_texts
),
241 static const struct snd_kcontrol_new twl4030_dapm_hsol_control
=
242 SOC_DAPM_ENUM("Route", twl4030_hsol_enum
);
245 static const char *twl4030_hsor_texts
[] =
246 {"Off", "DACR1", "DACR2"};
248 static const struct soc_enum twl4030_hsor_enum
=
249 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL
, 4,
250 ARRAY_SIZE(twl4030_hsor_texts
),
253 static const struct snd_kcontrol_new twl4030_dapm_hsor_control
=
254 SOC_DAPM_ENUM("Route", twl4030_hsor_enum
);
257 static const char *twl4030_carkitl_texts
[] =
258 {"Off", "DACL1", "DACL2"};
260 static const struct soc_enum twl4030_carkitl_enum
=
261 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL
, 1,
262 ARRAY_SIZE(twl4030_carkitl_texts
),
263 twl4030_carkitl_texts
);
265 static const struct snd_kcontrol_new twl4030_dapm_carkitl_control
=
266 SOC_DAPM_ENUM("Route", twl4030_carkitl_enum
);
269 static const char *twl4030_carkitr_texts
[] =
270 {"Off", "DACR1", "DACR2"};
272 static const struct soc_enum twl4030_carkitr_enum
=
273 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL
, 1,
274 ARRAY_SIZE(twl4030_carkitr_texts
),
275 twl4030_carkitr_texts
);
277 static const struct snd_kcontrol_new twl4030_dapm_carkitr_control
=
278 SOC_DAPM_ENUM("Route", twl4030_carkitr_enum
);
281 static const char *twl4030_handsfreel_texts
[] =
282 {"Voice", "DACL1", "DACL2", "DACR2"};
284 static const struct soc_enum twl4030_handsfreel_enum
=
285 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL
, 0,
286 ARRAY_SIZE(twl4030_handsfreel_texts
),
287 twl4030_handsfreel_texts
);
289 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control
=
290 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum
);
292 /* Handsfree Right */
293 static const char *twl4030_handsfreer_texts
[] =
294 {"Voice", "DACR1", "DACR2", "DACL2"};
296 static const struct soc_enum twl4030_handsfreer_enum
=
297 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL
, 0,
298 ARRAY_SIZE(twl4030_handsfreer_texts
),
299 twl4030_handsfreer_texts
);
301 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control
=
302 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum
);
304 static int outmixer_event(struct snd_soc_dapm_widget
*w
,
305 struct snd_kcontrol
*kcontrol
, int event
)
307 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
312 case TWL4030_REG_PREDL_CTL
:
313 case TWL4030_REG_PREDR_CTL
:
314 case TWL4030_REG_EAR_CTL
:
315 val
= w
->value
>> e
->shift_l
;
318 "Invalid MUX setting for register 0x%02x (%d)\n",
329 * Some of the gain controls in TWL (mostly those which are associated with
330 * the outputs) are implemented in an interesting way:
331 * 0x0 : Power down (mute)
335 * Inverting not going to help with these.
336 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
338 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
339 xinvert, tlv_array) \
340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
341 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
342 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
343 .tlv.p = (tlv_array), \
344 .info = snd_soc_info_volsw, \
345 .get = snd_soc_get_volsw_twl4030, \
346 .put = snd_soc_put_volsw_twl4030, \
347 .private_value = (unsigned long)&(struct soc_mixer_control) \
348 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
349 .max = xmax, .invert = xinvert} }
350 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
351 xinvert, tlv_array) \
352 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
353 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
354 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
355 .tlv.p = (tlv_array), \
356 .info = snd_soc_info_volsw_2r, \
357 .get = snd_soc_get_volsw_r2_twl4030,\
358 .put = snd_soc_put_volsw_r2_twl4030, \
359 .private_value = (unsigned long)&(struct soc_mixer_control) \
360 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
361 .rshift = xshift, .max = xmax, .invert = xinvert} }
362 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
363 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
366 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
367 struct snd_ctl_elem_value
*ucontrol
)
369 struct soc_mixer_control
*mc
=
370 (struct soc_mixer_control
*)kcontrol
->private_value
;
371 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
372 unsigned int reg
= mc
->reg
;
373 unsigned int shift
= mc
->shift
;
374 unsigned int rshift
= mc
->rshift
;
376 int mask
= (1 << fls(max
)) - 1;
378 ucontrol
->value
.integer
.value
[0] =
379 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
380 if (ucontrol
->value
.integer
.value
[0])
381 ucontrol
->value
.integer
.value
[0] =
382 max
+ 1 - ucontrol
->value
.integer
.value
[0];
384 if (shift
!= rshift
) {
385 ucontrol
->value
.integer
.value
[1] =
386 (snd_soc_read(codec
, reg
) >> rshift
) & mask
;
387 if (ucontrol
->value
.integer
.value
[1])
388 ucontrol
->value
.integer
.value
[1] =
389 max
+ 1 - ucontrol
->value
.integer
.value
[1];
395 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol
*kcontrol
,
396 struct snd_ctl_elem_value
*ucontrol
)
398 struct soc_mixer_control
*mc
=
399 (struct soc_mixer_control
*)kcontrol
->private_value
;
400 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
401 unsigned int reg
= mc
->reg
;
402 unsigned int shift
= mc
->shift
;
403 unsigned int rshift
= mc
->rshift
;
405 int mask
= (1 << fls(max
)) - 1;
406 unsigned short val
, val2
, val_mask
;
408 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
410 val_mask
= mask
<< shift
;
414 if (shift
!= rshift
) {
415 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
416 val_mask
|= mask
<< rshift
;
418 val2
= max
+ 1 - val2
;
419 val
|= val2
<< rshift
;
421 return snd_soc_update_bits(codec
, reg
, val_mask
, val
);
424 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
425 struct snd_ctl_elem_value
*ucontrol
)
427 struct soc_mixer_control
*mc
=
428 (struct soc_mixer_control
*)kcontrol
->private_value
;
429 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
430 unsigned int reg
= mc
->reg
;
431 unsigned int reg2
= mc
->rreg
;
432 unsigned int shift
= mc
->shift
;
434 int mask
= (1<<fls(max
))-1;
436 ucontrol
->value
.integer
.value
[0] =
437 (snd_soc_read(codec
, reg
) >> shift
) & mask
;
438 ucontrol
->value
.integer
.value
[1] =
439 (snd_soc_read(codec
, reg2
) >> shift
) & mask
;
441 if (ucontrol
->value
.integer
.value
[0])
442 ucontrol
->value
.integer
.value
[0] =
443 max
+ 1 - ucontrol
->value
.integer
.value
[0];
444 if (ucontrol
->value
.integer
.value
[1])
445 ucontrol
->value
.integer
.value
[1] =
446 max
+ 1 - ucontrol
->value
.integer
.value
[1];
451 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol
*kcontrol
,
452 struct snd_ctl_elem_value
*ucontrol
)
454 struct soc_mixer_control
*mc
=
455 (struct soc_mixer_control
*)kcontrol
->private_value
;
456 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
457 unsigned int reg
= mc
->reg
;
458 unsigned int reg2
= mc
->rreg
;
459 unsigned int shift
= mc
->shift
;
461 int mask
= (1 << fls(max
)) - 1;
463 unsigned short val
, val2
, val_mask
;
465 val_mask
= mask
<< shift
;
466 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
467 val2
= (ucontrol
->value
.integer
.value
[1] & mask
);
472 val2
= max
+ 1 - val2
;
475 val2
= val2
<< shift
;
477 err
= snd_soc_update_bits(codec
, reg
, val_mask
, val
);
481 err
= snd_soc_update_bits(codec
, reg2
, val_mask
, val2
);
485 static int twl4030_get_left_input(struct snd_kcontrol
*kcontrol
,
486 struct snd_ctl_elem_value
*ucontrol
)
488 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
489 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
492 /* one bit must be set a time */
493 reg
&= TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
494 | TWL4030_MAINMIC_EN
;
497 while ((reg
& 1) == 0) {
503 ucontrol
->value
.integer
.value
[0] = result
;
507 static int twl4030_put_left_input(struct snd_kcontrol
*kcontrol
,
508 struct snd_ctl_elem_value
*ucontrol
)
510 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
511 int value
= ucontrol
->value
.integer
.value
[0];
512 u8 anamicl
, micbias
, avadc_ctl
;
514 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
515 anamicl
&= ~(TWL4030_CKMIC_EN
| TWL4030_AUXL_EN
| TWL4030_HSMIC_EN
516 | TWL4030_MAINMIC_EN
);
517 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
518 micbias
&= ~(TWL4030_HSMICBIAS_EN
| TWL4030_MICBIAS1_EN
);
519 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
523 anamicl
|= TWL4030_MAINMIC_EN
;
524 micbias
|= TWL4030_MICBIAS1_EN
;
527 anamicl
|= TWL4030_HSMIC_EN
;
528 micbias
|= TWL4030_HSMICBIAS_EN
;
531 anamicl
|= TWL4030_AUXL_EN
;
534 anamicl
|= TWL4030_CKMIC_EN
;
540 /* If some input is selected, enable amp and ADC */
542 anamicl
|= TWL4030_MICAMPL_EN
;
543 avadc_ctl
|= TWL4030_ADCL_EN
;
545 anamicl
&= ~TWL4030_MICAMPL_EN
;
546 avadc_ctl
&= ~TWL4030_ADCL_EN
;
549 twl4030_write(codec
, TWL4030_REG_ANAMICL
, anamicl
);
550 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
551 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
556 static int twl4030_get_right_input(struct snd_kcontrol
*kcontrol
,
557 struct snd_ctl_elem_value
*ucontrol
)
559 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
560 u8 reg
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
563 reg
&= TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
;
565 case TWL4030_SUBMIC_EN
:
568 case TWL4030_AUXR_EN
:
575 ucontrol
->value
.integer
.value
[0] = value
;
579 static int twl4030_put_right_input(struct snd_kcontrol
*kcontrol
,
580 struct snd_ctl_elem_value
*ucontrol
)
582 struct snd_soc_codec
*codec
= kcontrol
->private_data
;
583 int value
= ucontrol
->value
.integer
.value
[0];
584 u8 anamicr
, micbias
, avadc_ctl
;
586 anamicr
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICR
);
587 anamicr
&= ~(TWL4030_SUBMIC_EN
|TWL4030_AUXR_EN
);
588 micbias
= twl4030_read_reg_cache(codec
, TWL4030_REG_MICBIAS_CTL
);
589 micbias
&= ~TWL4030_MICBIAS2_EN
;
590 avadc_ctl
= twl4030_read_reg_cache(codec
, TWL4030_REG_AVADC_CTL
);
594 anamicr
|= TWL4030_SUBMIC_EN
;
595 micbias
|= TWL4030_MICBIAS2_EN
;
598 anamicr
|= TWL4030_AUXR_EN
;
605 anamicr
|= TWL4030_MICAMPR_EN
;
606 avadc_ctl
|= TWL4030_ADCR_EN
;
608 anamicr
&= ~TWL4030_MICAMPR_EN
;
609 avadc_ctl
&= ~TWL4030_ADCR_EN
;
612 twl4030_write(codec
, TWL4030_REG_ANAMICR
, anamicr
);
613 twl4030_write(codec
, TWL4030_REG_MICBIAS_CTL
, micbias
);
614 twl4030_write(codec
, TWL4030_REG_AVADC_CTL
, avadc_ctl
);
619 static const char *twl4030_left_in_sel
[] = {
627 static const char *twl4030_right_in_sel
[] = {
633 static const struct soc_enum twl4030_left_input_mux
=
634 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel
),
635 twl4030_left_in_sel
);
637 static const struct soc_enum twl4030_right_input_mux
=
638 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel
),
639 twl4030_right_in_sel
);
642 * FGAIN volume control:
643 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
645 static DECLARE_TLV_DB_SCALE(digital_fine_tlv
, -6300, 100, 1);
648 * CGAIN volume control:
649 * 0 dB to 12 dB in 6 dB steps
650 * value 2 and 3 means 12 dB
652 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv
, 0, 600, 0);
655 * Analog playback gain
656 * -24 dB to 12 dB in 2 dB steps
658 static DECLARE_TLV_DB_SCALE(analog_tlv
, -2400, 200, 0);
661 * Gain controls tied to outputs
662 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
664 static DECLARE_TLV_DB_SCALE(output_tvl
, -1200, 600, 1);
667 * Capture gain after the ADCs
668 * from 0 dB to 31 dB in 1 dB steps
670 static DECLARE_TLV_DB_SCALE(digital_capture_tlv
, 0, 100, 0);
673 * Gain control for input amplifiers
674 * 0 dB to 30 dB in 6 dB steps
676 static DECLARE_TLV_DB_SCALE(input_gain_tlv
, 0, 600, 0);
678 static const struct snd_kcontrol_new twl4030_snd_controls
[] = {
679 /* Common playback gain controls */
680 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
681 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
682 0, 0x3f, 0, digital_fine_tlv
),
683 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
684 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
685 0, 0x3f, 0, digital_fine_tlv
),
687 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
688 TWL4030_REG_ARXL1PGA
, TWL4030_REG_ARXR1PGA
,
689 6, 0x2, 0, digital_coarse_tlv
),
690 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
691 TWL4030_REG_ARXL2PGA
, TWL4030_REG_ARXR2PGA
,
692 6, 0x2, 0, digital_coarse_tlv
),
694 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
695 TWL4030_REG_ARXL1_APGA_CTL
, TWL4030_REG_ARXR1_APGA_CTL
,
696 3, 0x12, 1, analog_tlv
),
697 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
698 TWL4030_REG_ARXL2_APGA_CTL
, TWL4030_REG_ARXR2_APGA_CTL
,
699 3, 0x12, 1, analog_tlv
),
700 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
701 TWL4030_REG_ARXL1_APGA_CTL
, TWL4030_REG_ARXR1_APGA_CTL
,
703 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
704 TWL4030_REG_ARXL2_APGA_CTL
, TWL4030_REG_ARXR2_APGA_CTL
,
707 /* Separate output gain controls */
708 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
709 TWL4030_REG_PREDL_CTL
, TWL4030_REG_PREDR_CTL
,
710 4, 3, 0, output_tvl
),
712 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
713 TWL4030_REG_HS_GAIN_SET
, 0, 2, 3, 0, output_tvl
),
715 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
716 TWL4030_REG_PRECKL_CTL
, TWL4030_REG_PRECKR_CTL
,
717 4, 3, 0, output_tvl
),
719 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
720 TWL4030_REG_EAR_CTL
, 4, 3, 0, output_tvl
),
722 /* Common capture gain controls */
723 SOC_DOUBLE_R_TLV("Capture Volume",
724 TWL4030_REG_ATXL1PGA
, TWL4030_REG_ATXR1PGA
,
725 0, 0x1f, 0, digital_capture_tlv
),
727 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN
,
728 0, 3, 5, 0, input_gain_tlv
),
730 /* Input source controls */
731 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux
,
732 twl4030_get_left_input
, twl4030_put_left_input
),
733 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux
,
734 twl4030_get_right_input
, twl4030_put_right_input
),
737 /* add non dapm controls */
738 static int twl4030_add_controls(struct snd_soc_codec
*codec
)
742 for (i
= 0; i
< ARRAY_SIZE(twl4030_snd_controls
); i
++) {
743 err
= snd_ctl_add(codec
->card
,
744 snd_soc_cnew(&twl4030_snd_controls
[i
],
753 static const struct snd_soc_dapm_widget twl4030_dapm_widgets
[] = {
754 SND_SOC_DAPM_INPUT("INL"),
755 SND_SOC_DAPM_INPUT("INR"),
757 SND_SOC_DAPM_OUTPUT("OUTL"),
758 SND_SOC_DAPM_OUTPUT("OUTR"),
759 SND_SOC_DAPM_OUTPUT("EARPIECE"),
760 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
761 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
762 SND_SOC_DAPM_OUTPUT("HSOL"),
763 SND_SOC_DAPM_OUTPUT("HSOR"),
764 SND_SOC_DAPM_OUTPUT("CARKITL"),
765 SND_SOC_DAPM_OUTPUT("CARKITR"),
766 SND_SOC_DAPM_OUTPUT("HFL"),
767 SND_SOC_DAPM_OUTPUT("HFR"),
770 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
771 TWL4030_REG_AVDAC_CTL
, 0, 0),
772 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
773 TWL4030_REG_AVDAC_CTL
, 1, 0),
774 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
775 TWL4030_REG_AVDAC_CTL
, 2, 0),
776 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
777 TWL4030_REG_AVDAC_CTL
, 3, 0),
780 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL
,
782 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL
,
784 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL
,
786 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL
,
789 /* Output MUX controls */
791 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM
, 0, 0,
792 &twl4030_dapm_earpiece_control
, outmixer_event
,
793 SND_SOC_DAPM_PRE_REG
),
795 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM
, 0, 0,
796 &twl4030_dapm_predrivel_control
, outmixer_event
,
797 SND_SOC_DAPM_PRE_REG
),
798 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM
, 0, 0,
799 &twl4030_dapm_predriver_control
, outmixer_event
,
800 SND_SOC_DAPM_PRE_REG
),
802 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM
, 0, 0,
803 &twl4030_dapm_hsol_control
),
804 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM
, 0, 0,
805 &twl4030_dapm_hsor_control
),
807 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM
, 0, 0,
808 &twl4030_dapm_carkitl_control
),
809 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM
, 0, 0,
810 &twl4030_dapm_carkitr_control
),
812 SND_SOC_DAPM_MUX("HandsfreeL Mux", TWL4030_REG_HFL_CTL
, 5, 0,
813 &twl4030_dapm_handsfreel_control
),
814 SND_SOC_DAPM_MUX("HandsfreeR Mux", TWL4030_REG_HFR_CTL
, 5, 0,
815 &twl4030_dapm_handsfreer_control
),
817 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM
, 0, 0),
818 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM
, 0, 0),
821 static const struct snd_soc_dapm_route intercon
[] = {
822 {"ARXL1_APGA", NULL
, "DACL1"},
823 {"ARXR1_APGA", NULL
, "DACR1"},
824 {"ARXL2_APGA", NULL
, "DACL2"},
825 {"ARXR2_APGA", NULL
, "DACR2"},
827 /* Internal playback routings */
829 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
830 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
831 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
833 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
834 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
835 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
837 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
838 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
839 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
841 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
842 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
844 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
845 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
847 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
848 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
850 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
851 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
853 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
854 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
855 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
857 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
858 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
859 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
862 {"OUTL", NULL
, "ARXL2_APGA"},
863 {"OUTR", NULL
, "ARXR2_APGA"},
864 {"EARPIECE", NULL
, "Earpiece Mux"},
865 {"PREDRIVEL", NULL
, "PredriveL Mux"},
866 {"PREDRIVER", NULL
, "PredriveR Mux"},
867 {"HSOL", NULL
, "HeadsetL Mux"},
868 {"HSOR", NULL
, "HeadsetR Mux"},
869 {"CARKITL", NULL
, "CarkitL Mux"},
870 {"CARKITR", NULL
, "CarkitR Mux"},
871 {"HFL", NULL
, "HandsfreeL Mux"},
872 {"HFR", NULL
, "HandsfreeR Mux"},
875 {"ADCL", NULL
, "INL"},
876 {"ADCR", NULL
, "INR"},
879 static int twl4030_add_widgets(struct snd_soc_codec
*codec
)
881 snd_soc_dapm_new_controls(codec
, twl4030_dapm_widgets
,
882 ARRAY_SIZE(twl4030_dapm_widgets
));
884 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
886 snd_soc_dapm_new_widgets(codec
);
890 static void twl4030_power_up(struct snd_soc_codec
*codec
)
892 u8 anamicl
, regmisc1
, byte
, popn
;
895 /* set CODECPDZ to turn on codec */
896 twl4030_set_codecpdz(codec
);
898 /* initiate offset cancellation */
899 anamicl
= twl4030_read_reg_cache(codec
, TWL4030_REG_ANAMICL
);
900 twl4030_write(codec
, TWL4030_REG_ANAMICL
,
901 anamicl
| TWL4030_CNCL_OFFSET_START
);
903 /* wait for offset cancellation to complete */
905 /* this takes a little while, so don't slam i2c */
907 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE
, &byte
,
908 TWL4030_REG_ANAMICL
);
909 } while ((i
++ < 100) &&
910 ((byte
& TWL4030_CNCL_OFFSET_START
) ==
911 TWL4030_CNCL_OFFSET_START
));
913 /* anti-pop when changing analog gain */
914 regmisc1
= twl4030_read_reg_cache(codec
, TWL4030_REG_MISC_SET_1
);
915 twl4030_write(codec
, TWL4030_REG_MISC_SET_1
,
916 regmisc1
| TWL4030_SMOOTH_ANAVOL_EN
);
918 /* toggle CODECPDZ as per TRM */
919 twl4030_clear_codecpdz(codec
);
920 twl4030_set_codecpdz(codec
);
922 /* program anti-pop with bias ramp delay */
923 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
924 popn
&= TWL4030_RAMP_DELAY
;
925 popn
|= TWL4030_RAMP_DELAY_645MS
;
926 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
927 popn
|= TWL4030_VMID_EN
;
928 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
930 /* enable anti-pop ramp */
931 popn
|= TWL4030_RAMP_EN
;
932 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
935 static void twl4030_power_down(struct snd_soc_codec
*codec
)
939 /* disable anti-pop ramp */
940 popn
= twl4030_read_reg_cache(codec
, TWL4030_REG_HS_POPN_SET
);
941 popn
&= ~TWL4030_RAMP_EN
;
942 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
944 /* disable bias out */
945 popn
&= ~TWL4030_VMID_EN
;
946 twl4030_write(codec
, TWL4030_REG_HS_POPN_SET
, popn
);
949 twl4030_clear_codecpdz(codec
);
952 static int twl4030_set_bias_level(struct snd_soc_codec
*codec
,
953 enum snd_soc_bias_level level
)
956 case SND_SOC_BIAS_ON
:
957 twl4030_power_up(codec
);
959 case SND_SOC_BIAS_PREPARE
:
960 /* TODO: develop a twl4030_prepare function */
962 case SND_SOC_BIAS_STANDBY
:
963 /* TODO: develop a twl4030_standby function */
964 twl4030_power_down(codec
);
966 case SND_SOC_BIAS_OFF
:
967 twl4030_power_down(codec
);
970 codec
->bias_level
= level
;
975 static int twl4030_hw_params(struct snd_pcm_substream
*substream
,
976 struct snd_pcm_hw_params
*params
,
977 struct snd_soc_dai
*dai
)
979 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
980 struct snd_soc_device
*socdev
= rtd
->socdev
;
981 struct snd_soc_codec
*codec
= socdev
->codec
;
982 u8 mode
, old_mode
, format
, old_format
;
986 old_mode
= twl4030_read_reg_cache(codec
,
987 TWL4030_REG_CODEC_MODE
) & ~TWL4030_CODECPDZ
;
988 mode
= old_mode
& ~TWL4030_APLL_RATE
;
990 switch (params_rate(params
)) {
992 mode
|= TWL4030_APLL_RATE_8000
;
995 mode
|= TWL4030_APLL_RATE_11025
;
998 mode
|= TWL4030_APLL_RATE_12000
;
1001 mode
|= TWL4030_APLL_RATE_16000
;
1004 mode
|= TWL4030_APLL_RATE_22050
;
1007 mode
|= TWL4030_APLL_RATE_24000
;
1010 mode
|= TWL4030_APLL_RATE_32000
;
1013 mode
|= TWL4030_APLL_RATE_44100
;
1016 mode
|= TWL4030_APLL_RATE_48000
;
1019 printk(KERN_ERR
"TWL4030 hw params: unknown rate %d\n",
1020 params_rate(params
));
1024 if (mode
!= old_mode
) {
1025 /* change rate and set CODECPDZ */
1026 twl4030_write(codec
, TWL4030_REG_CODEC_MODE
, mode
);
1027 twl4030_set_codecpdz(codec
);
1031 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
1032 format
= old_format
;
1033 format
&= ~TWL4030_DATA_WIDTH
;
1034 switch (params_format(params
)) {
1035 case SNDRV_PCM_FORMAT_S16_LE
:
1036 format
|= TWL4030_DATA_WIDTH_16S_16W
;
1038 case SNDRV_PCM_FORMAT_S24_LE
:
1039 format
|= TWL4030_DATA_WIDTH_32S_24W
;
1042 printk(KERN_ERR
"TWL4030 hw params: unknown format %d\n",
1043 params_format(params
));
1047 if (format
!= old_format
) {
1049 /* clear CODECPDZ before changing format (codec requirement) */
1050 twl4030_clear_codecpdz(codec
);
1053 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
1055 /* set CODECPDZ afterwards */
1056 twl4030_set_codecpdz(codec
);
1061 static int twl4030_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1062 int clk_id
, unsigned int freq
, int dir
)
1064 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1069 infreq
= TWL4030_APLL_INFREQ_19200KHZ
;
1072 infreq
= TWL4030_APLL_INFREQ_26000KHZ
;
1075 infreq
= TWL4030_APLL_INFREQ_38400KHZ
;
1078 printk(KERN_ERR
"TWL4030 set sysclk: unknown rate %d\n",
1083 infreq
|= TWL4030_APLL_EN
;
1084 twl4030_write(codec
, TWL4030_REG_APLL_CTL
, infreq
);
1089 static int twl4030_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1092 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1093 u8 old_format
, format
;
1096 old_format
= twl4030_read_reg_cache(codec
, TWL4030_REG_AUDIO_IF
);
1097 format
= old_format
;
1099 /* set master/slave audio interface */
1100 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1101 case SND_SOC_DAIFMT_CBM_CFM
:
1102 format
&= ~(TWL4030_AIF_SLAVE_EN
);
1103 format
&= ~(TWL4030_CLK256FS_EN
);
1105 case SND_SOC_DAIFMT_CBS_CFS
:
1106 format
|= TWL4030_AIF_SLAVE_EN
;
1107 format
|= TWL4030_CLK256FS_EN
;
1113 /* interface format */
1114 format
&= ~TWL4030_AIF_FORMAT
;
1115 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1116 case SND_SOC_DAIFMT_I2S
:
1117 format
|= TWL4030_AIF_FORMAT_CODEC
;
1123 if (format
!= old_format
) {
1125 /* clear CODECPDZ before changing format (codec requirement) */
1126 twl4030_clear_codecpdz(codec
);
1129 twl4030_write(codec
, TWL4030_REG_AUDIO_IF
, format
);
1131 /* set CODECPDZ afterwards */
1132 twl4030_set_codecpdz(codec
);
1138 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1139 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1141 struct snd_soc_dai twl4030_dai
= {
1144 .stream_name
= "Playback",
1147 .rates
= TWL4030_RATES
,
1148 .formats
= TWL4030_FORMATS
,},
1150 .stream_name
= "Capture",
1153 .rates
= TWL4030_RATES
,
1154 .formats
= TWL4030_FORMATS
,},
1156 .hw_params
= twl4030_hw_params
,
1157 .set_sysclk
= twl4030_set_dai_sysclk
,
1158 .set_fmt
= twl4030_set_dai_fmt
,
1161 EXPORT_SYMBOL_GPL(twl4030_dai
);
1163 static int twl4030_suspend(struct platform_device
*pdev
, pm_message_t state
)
1165 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1166 struct snd_soc_codec
*codec
= socdev
->codec
;
1168 twl4030_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1173 static int twl4030_resume(struct platform_device
*pdev
)
1175 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1176 struct snd_soc_codec
*codec
= socdev
->codec
;
1178 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1179 twl4030_set_bias_level(codec
, codec
->suspend_bias_level
);
1184 * initialize the driver
1185 * register the mixer and dsp interfaces with the kernel
1188 static int twl4030_init(struct snd_soc_device
*socdev
)
1190 struct snd_soc_codec
*codec
= socdev
->codec
;
1193 printk(KERN_INFO
"TWL4030 Audio Codec init \n");
1195 codec
->name
= "twl4030";
1196 codec
->owner
= THIS_MODULE
;
1197 codec
->read
= twl4030_read_reg_cache
;
1198 codec
->write
= twl4030_write
;
1199 codec
->set_bias_level
= twl4030_set_bias_level
;
1200 codec
->dai
= &twl4030_dai
;
1202 codec
->reg_cache_size
= sizeof(twl4030_reg
);
1203 codec
->reg_cache
= kmemdup(twl4030_reg
, sizeof(twl4030_reg
),
1205 if (codec
->reg_cache
== NULL
)
1209 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1211 printk(KERN_ERR
"twl4030: failed to create pcms\n");
1215 twl4030_init_chip(codec
);
1217 /* power on device */
1218 twl4030_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1220 twl4030_add_controls(codec
);
1221 twl4030_add_widgets(codec
);
1223 ret
= snd_soc_init_card(socdev
);
1225 printk(KERN_ERR
"twl4030: failed to register card\n");
1232 snd_soc_free_pcms(socdev
);
1233 snd_soc_dapm_free(socdev
);
1235 kfree(codec
->reg_cache
);
1239 static struct snd_soc_device
*twl4030_socdev
;
1241 static int twl4030_probe(struct platform_device
*pdev
)
1243 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1244 struct snd_soc_codec
*codec
;
1246 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1250 socdev
->codec
= codec
;
1251 mutex_init(&codec
->mutex
);
1252 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1253 INIT_LIST_HEAD(&codec
->dapm_paths
);
1255 twl4030_socdev
= socdev
;
1256 twl4030_init(socdev
);
1261 static int twl4030_remove(struct platform_device
*pdev
)
1263 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1264 struct snd_soc_codec
*codec
= socdev
->codec
;
1266 printk(KERN_INFO
"TWL4030 Audio Codec remove\n");
1272 struct snd_soc_codec_device soc_codec_dev_twl4030
= {
1273 .probe
= twl4030_probe
,
1274 .remove
= twl4030_remove
,
1275 .suspend
= twl4030_suspend
,
1276 .resume
= twl4030_resume
,
1278 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030
);
1280 static int __init
twl4030_modinit(void)
1282 return snd_soc_register_dai(&twl4030_dai
);
1284 module_init(twl4030_modinit
);
1286 static void __exit
twl4030_exit(void)
1288 snd_soc_unregister_dai(&twl4030_dai
);
1290 module_exit(twl4030_exit
);
1292 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1293 MODULE_AUTHOR("Steve Sakoman");
1294 MODULE_LICENSE("GPL");