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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 };
119
120 /*
121 * read twl4030 register cache
122 */
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125 {
126 u8 *cache = codec->reg_cache;
127
128 return cache[reg];
129 }
130
131 /*
132 * write twl4030 register cache
133 */
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
135 u8 reg, u8 value)
136 {
137 u8 *cache = codec->reg_cache;
138
139 if (reg >= TWL4030_CACHEREGNUM)
140 return;
141 cache[reg] = value;
142 }
143
144 /*
145 * write to the twl4030 register space
146 */
147 static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
149 {
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
152 }
153
154 static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
155 {
156 u8 mode;
157
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
161
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
164 udelay(10);
165 }
166
167 static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
168 {
169 u8 mode;
170
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
174
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
177 udelay(10);
178 }
179
180 static void twl4030_init_chip(struct snd_soc_codec *codec)
181 {
182 int i;
183
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
186
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
190
191 }
192
193 /* Earpiece */
194 static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid", "DACR1"};
196
197 static const struct soc_enum twl4030_earpiece_enum =
198 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
199 ARRAY_SIZE(twl4030_earpiece_texts),
200 twl4030_earpiece_texts);
201
202 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
203 SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
204
205 /* PreDrive Left */
206 static const char *twl4030_predrivel_texts[] =
207 {"Off", "DACL1", "DACL2", "Invalid", "DACR2"};
208
209 static const struct soc_enum twl4030_predrivel_enum =
210 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
211 ARRAY_SIZE(twl4030_predrivel_texts),
212 twl4030_predrivel_texts);
213
214 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
215 SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
216
217 /* PreDrive Right */
218 static const char *twl4030_predriver_texts[] =
219 {"Off", "DACR1", "DACR2", "Invalid", "DACL2"};
220
221 static const struct soc_enum twl4030_predriver_enum =
222 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
223 ARRAY_SIZE(twl4030_predriver_texts),
224 twl4030_predriver_texts);
225
226 static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
227 SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
228
229 /* Headset Left */
230 static const char *twl4030_hsol_texts[] =
231 {"Off", "DACL1", "DACL2"};
232
233 static const struct soc_enum twl4030_hsol_enum =
234 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
235 ARRAY_SIZE(twl4030_hsol_texts),
236 twl4030_hsol_texts);
237
238 static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
239 SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
240
241 /* Headset Right */
242 static const char *twl4030_hsor_texts[] =
243 {"Off", "DACR1", "DACR2"};
244
245 static const struct soc_enum twl4030_hsor_enum =
246 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
247 ARRAY_SIZE(twl4030_hsor_texts),
248 twl4030_hsor_texts);
249
250 static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
251 SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
252
253 /* Carkit Left */
254 static const char *twl4030_carkitl_texts[] =
255 {"Off", "DACL1", "DACL2"};
256
257 static const struct soc_enum twl4030_carkitl_enum =
258 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
259 ARRAY_SIZE(twl4030_carkitl_texts),
260 twl4030_carkitl_texts);
261
262 static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
263 SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
264
265 /* Carkit Right */
266 static const char *twl4030_carkitr_texts[] =
267 {"Off", "DACR1", "DACR2"};
268
269 static const struct soc_enum twl4030_carkitr_enum =
270 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
271 ARRAY_SIZE(twl4030_carkitr_texts),
272 twl4030_carkitr_texts);
273
274 static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
275 SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
276
277 /* Handsfree Left */
278 static const char *twl4030_handsfreel_texts[] =
279 {"Voice", "DACL1", "DACL2", "DACR2"};
280
281 static const struct soc_enum twl4030_handsfreel_enum =
282 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
283 ARRAY_SIZE(twl4030_handsfreel_texts),
284 twl4030_handsfreel_texts);
285
286 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
287 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
288
289 /* Handsfree Right */
290 static const char *twl4030_handsfreer_texts[] =
291 {"Voice", "DACR1", "DACR2", "DACL2"};
292
293 static const struct soc_enum twl4030_handsfreer_enum =
294 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
295 ARRAY_SIZE(twl4030_handsfreer_texts),
296 twl4030_handsfreer_texts);
297
298 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
299 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
300
301 /* Left analog microphone selection */
302 static const char *twl4030_analoglmic_texts[] =
303 {"Off", "Main mic", "Headset mic", "Invalid", "AUXL",
304 "Invalid", "Invalid", "Invalid", "Carkit mic"};
305
306 static const struct soc_enum twl4030_analoglmic_enum =
307 SOC_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0,
308 ARRAY_SIZE(twl4030_analoglmic_texts),
309 twl4030_analoglmic_texts);
310
311 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
312 SOC_DAPM_ENUM("Route", twl4030_analoglmic_enum);
313
314 /* Right analog microphone selection */
315 static const char *twl4030_analogrmic_texts[] =
316 {"Off", "Sub mic", "Invalid", "Invalid", "AUXR"};
317
318 static const struct soc_enum twl4030_analogrmic_enum =
319 SOC_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0,
320 ARRAY_SIZE(twl4030_analogrmic_texts),
321 twl4030_analogrmic_texts);
322
323 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
324 SOC_DAPM_ENUM("Route", twl4030_analogrmic_enum);
325
326 /* TX1 L/R Analog/Digital microphone selection */
327 static const char *twl4030_micpathtx1_texts[] =
328 {"Analog", "Digimic0"};
329
330 static const struct soc_enum twl4030_micpathtx1_enum =
331 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
332 ARRAY_SIZE(twl4030_micpathtx1_texts),
333 twl4030_micpathtx1_texts);
334
335 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
336 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
337
338 /* TX2 L/R Analog/Digital microphone selection */
339 static const char *twl4030_micpathtx2_texts[] =
340 {"Analog", "Digimic1"};
341
342 static const struct soc_enum twl4030_micpathtx2_enum =
343 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
344 ARRAY_SIZE(twl4030_micpathtx2_texts),
345 twl4030_micpathtx2_texts);
346
347 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
348 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
349
350 /*
351 * This function filters out the non valid mux settings, named as "Invalid"
352 * in the enum texts.
353 * Just refuse to set an invalid mux mode.
354 */
355 static int twl4030_enum_event(struct snd_soc_dapm_widget *w,
356 struct snd_kcontrol *kcontrol, int event)
357 {
358 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
359 int ret = 0;
360 int val;
361
362 val = w->value >> e->shift_l;
363 if (!strcmp("Invalid", e->texts[val])) {
364 printk(KERN_WARNING "Invalid MUX setting on 0x%02x (%d)\n",
365 e->reg, val);
366 ret = -1;
367 }
368
369 return ret;
370 }
371
372 static int micpath_event(struct snd_soc_dapm_widget *w,
373 struct snd_kcontrol *kcontrol, int event)
374 {
375 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
376 unsigned char adcmicsel, micbias_ctl;
377
378 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
379 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
380 /* Prepare the bits for the given TX path:
381 * shift_l == 0: TX1 microphone path
382 * shift_l == 2: TX2 microphone path */
383 if (e->shift_l) {
384 /* TX2 microphone path */
385 if (adcmicsel & TWL4030_TX2IN_SEL)
386 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
387 else
388 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
389 } else {
390 /* TX1 microphone path */
391 if (adcmicsel & TWL4030_TX1IN_SEL)
392 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
393 else
394 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
395 }
396
397 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
398
399 return 0;
400 }
401
402 static int handsfree_event(struct snd_soc_dapm_widget *w,
403 struct snd_kcontrol *kcontrol, int event)
404 {
405 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
406 unsigned char hs_ctl;
407
408 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
409
410 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
411 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
412 twl4030_write(w->codec, e->reg, hs_ctl);
413 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
414 twl4030_write(w->codec, e->reg, hs_ctl);
415 hs_ctl |= TWL4030_HF_CTL_HB_EN;
416 twl4030_write(w->codec, e->reg, hs_ctl);
417 } else {
418 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
419 | TWL4030_HF_CTL_HB_EN);
420 twl4030_write(w->codec, e->reg, hs_ctl);
421 }
422
423 return 0;
424 }
425
426 /*
427 * Some of the gain controls in TWL (mostly those which are associated with
428 * the outputs) are implemented in an interesting way:
429 * 0x0 : Power down (mute)
430 * 0x1 : 6dB
431 * 0x2 : 0 dB
432 * 0x3 : -6 dB
433 * Inverting not going to help with these.
434 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
435 */
436 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
437 xinvert, tlv_array) \
438 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
439 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
440 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
441 .tlv.p = (tlv_array), \
442 .info = snd_soc_info_volsw, \
443 .get = snd_soc_get_volsw_twl4030, \
444 .put = snd_soc_put_volsw_twl4030, \
445 .private_value = (unsigned long)&(struct soc_mixer_control) \
446 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
447 .max = xmax, .invert = xinvert} }
448 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
449 xinvert, tlv_array) \
450 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
451 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
452 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
453 .tlv.p = (tlv_array), \
454 .info = snd_soc_info_volsw_2r, \
455 .get = snd_soc_get_volsw_r2_twl4030,\
456 .put = snd_soc_put_volsw_r2_twl4030, \
457 .private_value = (unsigned long)&(struct soc_mixer_control) \
458 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
459 .rshift = xshift, .max = xmax, .invert = xinvert} }
460 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
461 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
462 xinvert, tlv_array)
463
464 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
465 struct snd_ctl_elem_value *ucontrol)
466 {
467 struct soc_mixer_control *mc =
468 (struct soc_mixer_control *)kcontrol->private_value;
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
470 unsigned int reg = mc->reg;
471 unsigned int shift = mc->shift;
472 unsigned int rshift = mc->rshift;
473 int max = mc->max;
474 int mask = (1 << fls(max)) - 1;
475
476 ucontrol->value.integer.value[0] =
477 (snd_soc_read(codec, reg) >> shift) & mask;
478 if (ucontrol->value.integer.value[0])
479 ucontrol->value.integer.value[0] =
480 max + 1 - ucontrol->value.integer.value[0];
481
482 if (shift != rshift) {
483 ucontrol->value.integer.value[1] =
484 (snd_soc_read(codec, reg) >> rshift) & mask;
485 if (ucontrol->value.integer.value[1])
486 ucontrol->value.integer.value[1] =
487 max + 1 - ucontrol->value.integer.value[1];
488 }
489
490 return 0;
491 }
492
493 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495 {
496 struct soc_mixer_control *mc =
497 (struct soc_mixer_control *)kcontrol->private_value;
498 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
499 unsigned int reg = mc->reg;
500 unsigned int shift = mc->shift;
501 unsigned int rshift = mc->rshift;
502 int max = mc->max;
503 int mask = (1 << fls(max)) - 1;
504 unsigned short val, val2, val_mask;
505
506 val = (ucontrol->value.integer.value[0] & mask);
507
508 val_mask = mask << shift;
509 if (val)
510 val = max + 1 - val;
511 val = val << shift;
512 if (shift != rshift) {
513 val2 = (ucontrol->value.integer.value[1] & mask);
514 val_mask |= mask << rshift;
515 if (val2)
516 val2 = max + 1 - val2;
517 val |= val2 << rshift;
518 }
519 return snd_soc_update_bits(codec, reg, val_mask, val);
520 }
521
522 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524 {
525 struct soc_mixer_control *mc =
526 (struct soc_mixer_control *)kcontrol->private_value;
527 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
528 unsigned int reg = mc->reg;
529 unsigned int reg2 = mc->rreg;
530 unsigned int shift = mc->shift;
531 int max = mc->max;
532 int mask = (1<<fls(max))-1;
533
534 ucontrol->value.integer.value[0] =
535 (snd_soc_read(codec, reg) >> shift) & mask;
536 ucontrol->value.integer.value[1] =
537 (snd_soc_read(codec, reg2) >> shift) & mask;
538
539 if (ucontrol->value.integer.value[0])
540 ucontrol->value.integer.value[0] =
541 max + 1 - ucontrol->value.integer.value[0];
542 if (ucontrol->value.integer.value[1])
543 ucontrol->value.integer.value[1] =
544 max + 1 - ucontrol->value.integer.value[1];
545
546 return 0;
547 }
548
549 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
550 struct snd_ctl_elem_value *ucontrol)
551 {
552 struct soc_mixer_control *mc =
553 (struct soc_mixer_control *)kcontrol->private_value;
554 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
555 unsigned int reg = mc->reg;
556 unsigned int reg2 = mc->rreg;
557 unsigned int shift = mc->shift;
558 int max = mc->max;
559 int mask = (1 << fls(max)) - 1;
560 int err;
561 unsigned short val, val2, val_mask;
562
563 val_mask = mask << shift;
564 val = (ucontrol->value.integer.value[0] & mask);
565 val2 = (ucontrol->value.integer.value[1] & mask);
566
567 if (val)
568 val = max + 1 - val;
569 if (val2)
570 val2 = max + 1 - val2;
571
572 val = val << shift;
573 val2 = val2 << shift;
574
575 err = snd_soc_update_bits(codec, reg, val_mask, val);
576 if (err < 0)
577 return err;
578
579 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
580 return err;
581 }
582
583 /*
584 * FGAIN volume control:
585 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
586 */
587 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
588
589 /*
590 * CGAIN volume control:
591 * 0 dB to 12 dB in 6 dB steps
592 * value 2 and 3 means 12 dB
593 */
594 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
595
596 /*
597 * Analog playback gain
598 * -24 dB to 12 dB in 2 dB steps
599 */
600 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
601
602 /*
603 * Gain controls tied to outputs
604 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
605 */
606 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
607
608 /*
609 * Capture gain after the ADCs
610 * from 0 dB to 31 dB in 1 dB steps
611 */
612 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
613
614 /*
615 * Gain control for input amplifiers
616 * 0 dB to 30 dB in 6 dB steps
617 */
618 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
619
620 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
621 /* Common playback gain controls */
622 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
623 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
624 0, 0x3f, 0, digital_fine_tlv),
625 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
626 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
627 0, 0x3f, 0, digital_fine_tlv),
628
629 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
630 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
631 6, 0x2, 0, digital_coarse_tlv),
632 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
633 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
634 6, 0x2, 0, digital_coarse_tlv),
635
636 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
637 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
638 3, 0x12, 1, analog_tlv),
639 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
640 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
641 3, 0x12, 1, analog_tlv),
642 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
643 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
644 1, 1, 0),
645 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
646 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
647 1, 1, 0),
648
649 /* Separate output gain controls */
650 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
651 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
652 4, 3, 0, output_tvl),
653
654 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
655 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
656
657 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
658 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
659 4, 3, 0, output_tvl),
660
661 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
662 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
663
664 /* Common capture gain controls */
665 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
666 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
667 0, 0x1f, 0, digital_capture_tlv),
668 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
669 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
670 0, 0x1f, 0, digital_capture_tlv),
671
672 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
673 0, 3, 5, 0, input_gain_tlv),
674 };
675
676 /* add non dapm controls */
677 static int twl4030_add_controls(struct snd_soc_codec *codec)
678 {
679 int err, i;
680
681 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
682 err = snd_ctl_add(codec->card,
683 snd_soc_cnew(&twl4030_snd_controls[i],
684 codec, NULL));
685 if (err < 0)
686 return err;
687 }
688
689 return 0;
690 }
691
692 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
693 /* Left channel inputs */
694 SND_SOC_DAPM_INPUT("MAINMIC"),
695 SND_SOC_DAPM_INPUT("HSMIC"),
696 SND_SOC_DAPM_INPUT("AUXL"),
697 SND_SOC_DAPM_INPUT("CARKITMIC"),
698 /* Right channel inputs */
699 SND_SOC_DAPM_INPUT("SUBMIC"),
700 SND_SOC_DAPM_INPUT("AUXR"),
701 /* Digital microphones (Stereo) */
702 SND_SOC_DAPM_INPUT("DIGIMIC0"),
703 SND_SOC_DAPM_INPUT("DIGIMIC1"),
704
705 /* Outputs */
706 SND_SOC_DAPM_OUTPUT("OUTL"),
707 SND_SOC_DAPM_OUTPUT("OUTR"),
708 SND_SOC_DAPM_OUTPUT("EARPIECE"),
709 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
710 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
711 SND_SOC_DAPM_OUTPUT("HSOL"),
712 SND_SOC_DAPM_OUTPUT("HSOR"),
713 SND_SOC_DAPM_OUTPUT("CARKITL"),
714 SND_SOC_DAPM_OUTPUT("CARKITR"),
715 SND_SOC_DAPM_OUTPUT("HFL"),
716 SND_SOC_DAPM_OUTPUT("HFR"),
717
718 /* DACs */
719 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
720 TWL4030_REG_AVDAC_CTL, 0, 0),
721 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
722 TWL4030_REG_AVDAC_CTL, 1, 0),
723 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
724 TWL4030_REG_AVDAC_CTL, 2, 0),
725 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
726 TWL4030_REG_AVDAC_CTL, 3, 0),
727
728 /* Analog PGAs */
729 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
730 0, 0, NULL, 0),
731 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
732 0, 0, NULL, 0),
733 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
734 0, 0, NULL, 0),
735 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
736 0, 0, NULL, 0),
737
738 /* Output MUX controls */
739 /* Earpiece */
740 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
741 &twl4030_dapm_earpiece_control, twl4030_enum_event,
742 SND_SOC_DAPM_PRE_REG),
743 /* PreDrivL/R */
744 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
745 &twl4030_dapm_predrivel_control, twl4030_enum_event,
746 SND_SOC_DAPM_PRE_REG),
747 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
748 &twl4030_dapm_predriver_control, twl4030_enum_event,
749 SND_SOC_DAPM_PRE_REG),
750 /* HeadsetL/R */
751 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
752 &twl4030_dapm_hsol_control),
753 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
754 &twl4030_dapm_hsor_control),
755 /* CarkitL/R */
756 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
757 &twl4030_dapm_carkitl_control),
758 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
759 &twl4030_dapm_carkitr_control),
760 /* HandsfreeL/R */
761 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
762 &twl4030_dapm_handsfreel_control, handsfree_event,
763 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
764 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
765 &twl4030_dapm_handsfreer_control, handsfree_event,
766 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
767
768 /* Introducing four virtual ADC, since TWL4030 have four channel for
769 capture */
770 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
771 SND_SOC_NOPM, 0, 0),
772 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
773 SND_SOC_NOPM, 0, 0),
774 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
775 SND_SOC_NOPM, 0, 0),
776 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
777 SND_SOC_NOPM, 0, 0),
778
779 /* Analog/Digital mic path selection.
780 TX1 Left/Right: either analog Left/Right or Digimic0
781 TX2 Left/Right: either analog Left/Right or Digimic1 */
782 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
783 &twl4030_dapm_micpathtx1_control, micpath_event,
784 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
785 SND_SOC_DAPM_POST_REG),
786 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
787 &twl4030_dapm_micpathtx2_control, micpath_event,
788 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
789 SND_SOC_DAPM_POST_REG),
790
791 /* Analog input muxes with power switch for the physical ADCL/R */
792 SND_SOC_DAPM_MUX_E("Analog Left Capture Route",
793 TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control,
794 twl4030_enum_event, SND_SOC_DAPM_PRE_REG),
795 SND_SOC_DAPM_MUX_E("Analog Right Capture Route",
796 TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control,
797 twl4030_enum_event, SND_SOC_DAPM_PRE_REG),
798
799 SND_SOC_DAPM_PGA("Analog Left Amplifier",
800 TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
801 SND_SOC_DAPM_PGA("Analog Right Amplifier",
802 TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
803
804 SND_SOC_DAPM_PGA("Digimic0 Enable",
805 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
806 SND_SOC_DAPM_PGA("Digimic1 Enable",
807 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
808
809 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
810 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
811 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
812 };
813
814 static const struct snd_soc_dapm_route intercon[] = {
815 {"ARXL1_APGA", NULL, "DAC Left1"},
816 {"ARXR1_APGA", NULL, "DAC Right1"},
817 {"ARXL2_APGA", NULL, "DAC Left2"},
818 {"ARXR2_APGA", NULL, "DAC Right2"},
819
820 /* Internal playback routings */
821 /* Earpiece */
822 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
823 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
824 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
825 /* PreDrivL */
826 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
827 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
828 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
829 /* PreDrivR */
830 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
831 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
832 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
833 /* HeadsetL */
834 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
835 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
836 /* HeadsetR */
837 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
838 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
839 /* CarkitL */
840 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
841 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
842 /* CarkitR */
843 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
844 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
845 /* HandsfreeL */
846 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
847 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
848 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
849 /* HandsfreeR */
850 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
851 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
852 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
853
854 /* outputs */
855 {"OUTL", NULL, "ARXL2_APGA"},
856 {"OUTR", NULL, "ARXR2_APGA"},
857 {"EARPIECE", NULL, "Earpiece Mux"},
858 {"PREDRIVEL", NULL, "PredriveL Mux"},
859 {"PREDRIVER", NULL, "PredriveR Mux"},
860 {"HSOL", NULL, "HeadsetL Mux"},
861 {"HSOR", NULL, "HeadsetR Mux"},
862 {"CARKITL", NULL, "CarkitL Mux"},
863 {"CARKITR", NULL, "CarkitR Mux"},
864 {"HFL", NULL, "HandsfreeL Mux"},
865 {"HFR", NULL, "HandsfreeR Mux"},
866
867 /* Capture path */
868 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
869 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
870 {"Analog Left Capture Route", "AUXL", "AUXL"},
871 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
872
873 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
874 {"Analog Right Capture Route", "AUXR", "AUXR"},
875
876 {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
877 {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
878
879 {"Digimic0 Enable", NULL, "DIGIMIC0"},
880 {"Digimic1 Enable", NULL, "DIGIMIC1"},
881
882 /* TX1 Left capture path */
883 {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
884 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
885 /* TX1 Right capture path */
886 {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
887 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
888 /* TX2 Left capture path */
889 {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
890 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
891 /* TX2 Right capture path */
892 {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
893 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
894
895 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
896 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
897 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
898 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
899
900 };
901
902 static int twl4030_add_widgets(struct snd_soc_codec *codec)
903 {
904 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
905 ARRAY_SIZE(twl4030_dapm_widgets));
906
907 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
908
909 snd_soc_dapm_new_widgets(codec);
910 return 0;
911 }
912
913 static void twl4030_power_up(struct snd_soc_codec *codec)
914 {
915 u8 anamicl, regmisc1, byte, popn;
916 int i = 0;
917
918 /* set CODECPDZ to turn on codec */
919 twl4030_set_codecpdz(codec);
920
921 /* initiate offset cancellation */
922 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
923 twl4030_write(codec, TWL4030_REG_ANAMICL,
924 anamicl | TWL4030_CNCL_OFFSET_START);
925
926
927 /* wait for offset cancellation to complete */
928 do {
929 /* this takes a little while, so don't slam i2c */
930 udelay(2000);
931 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
932 TWL4030_REG_ANAMICL);
933 } while ((i++ < 100) &&
934 ((byte & TWL4030_CNCL_OFFSET_START) ==
935 TWL4030_CNCL_OFFSET_START));
936
937 /* anti-pop when changing analog gain */
938 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
939 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
940 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
941
942 /* toggle CODECPDZ as per TRM */
943 twl4030_clear_codecpdz(codec);
944 twl4030_set_codecpdz(codec);
945
946 /* program anti-pop with bias ramp delay */
947 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
948 popn &= TWL4030_RAMP_DELAY;
949 popn |= TWL4030_RAMP_DELAY_645MS;
950 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
951 popn |= TWL4030_VMID_EN;
952 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
953
954 /* enable anti-pop ramp */
955 popn |= TWL4030_RAMP_EN;
956 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
957 }
958
959 static void twl4030_power_down(struct snd_soc_codec *codec)
960 {
961 u8 popn;
962
963 /* disable anti-pop ramp */
964 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
965 popn &= ~TWL4030_RAMP_EN;
966 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
967
968 /* disable bias out */
969 popn &= ~TWL4030_VMID_EN;
970 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
971
972 /* power down */
973 twl4030_clear_codecpdz(codec);
974 }
975
976 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
977 enum snd_soc_bias_level level)
978 {
979 switch (level) {
980 case SND_SOC_BIAS_ON:
981 twl4030_power_up(codec);
982 break;
983 case SND_SOC_BIAS_PREPARE:
984 /* TODO: develop a twl4030_prepare function */
985 break;
986 case SND_SOC_BIAS_STANDBY:
987 /* TODO: develop a twl4030_standby function */
988 twl4030_power_down(codec);
989 break;
990 case SND_SOC_BIAS_OFF:
991 twl4030_power_down(codec);
992 break;
993 }
994 codec->bias_level = level;
995
996 return 0;
997 }
998
999 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1000 struct snd_pcm_hw_params *params,
1001 struct snd_soc_dai *dai)
1002 {
1003 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1004 struct snd_soc_device *socdev = rtd->socdev;
1005 struct snd_soc_codec *codec = socdev->codec;
1006 u8 mode, old_mode, format, old_format;
1007
1008
1009 /* bit rate */
1010 old_mode = twl4030_read_reg_cache(codec,
1011 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1012 mode = old_mode & ~TWL4030_APLL_RATE;
1013
1014 switch (params_rate(params)) {
1015 case 8000:
1016 mode |= TWL4030_APLL_RATE_8000;
1017 break;
1018 case 11025:
1019 mode |= TWL4030_APLL_RATE_11025;
1020 break;
1021 case 12000:
1022 mode |= TWL4030_APLL_RATE_12000;
1023 break;
1024 case 16000:
1025 mode |= TWL4030_APLL_RATE_16000;
1026 break;
1027 case 22050:
1028 mode |= TWL4030_APLL_RATE_22050;
1029 break;
1030 case 24000:
1031 mode |= TWL4030_APLL_RATE_24000;
1032 break;
1033 case 32000:
1034 mode |= TWL4030_APLL_RATE_32000;
1035 break;
1036 case 44100:
1037 mode |= TWL4030_APLL_RATE_44100;
1038 break;
1039 case 48000:
1040 mode |= TWL4030_APLL_RATE_48000;
1041 break;
1042 default:
1043 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1044 params_rate(params));
1045 return -EINVAL;
1046 }
1047
1048 if (mode != old_mode) {
1049 /* change rate and set CODECPDZ */
1050 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1051 twl4030_set_codecpdz(codec);
1052 }
1053
1054 /* sample size */
1055 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1056 format = old_format;
1057 format &= ~TWL4030_DATA_WIDTH;
1058 switch (params_format(params)) {
1059 case SNDRV_PCM_FORMAT_S16_LE:
1060 format |= TWL4030_DATA_WIDTH_16S_16W;
1061 break;
1062 case SNDRV_PCM_FORMAT_S24_LE:
1063 format |= TWL4030_DATA_WIDTH_32S_24W;
1064 break;
1065 default:
1066 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1067 params_format(params));
1068 return -EINVAL;
1069 }
1070
1071 if (format != old_format) {
1072
1073 /* clear CODECPDZ before changing format (codec requirement) */
1074 twl4030_clear_codecpdz(codec);
1075
1076 /* change format */
1077 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1078
1079 /* set CODECPDZ afterwards */
1080 twl4030_set_codecpdz(codec);
1081 }
1082 return 0;
1083 }
1084
1085 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1086 int clk_id, unsigned int freq, int dir)
1087 {
1088 struct snd_soc_codec *codec = codec_dai->codec;
1089 u8 infreq;
1090
1091 switch (freq) {
1092 case 19200000:
1093 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1094 break;
1095 case 26000000:
1096 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1097 break;
1098 case 38400000:
1099 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1100 break;
1101 default:
1102 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1103 freq);
1104 return -EINVAL;
1105 }
1106
1107 infreq |= TWL4030_APLL_EN;
1108 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1109
1110 return 0;
1111 }
1112
1113 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1114 unsigned int fmt)
1115 {
1116 struct snd_soc_codec *codec = codec_dai->codec;
1117 u8 old_format, format;
1118
1119 /* get format */
1120 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1121 format = old_format;
1122
1123 /* set master/slave audio interface */
1124 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1125 case SND_SOC_DAIFMT_CBM_CFM:
1126 format &= ~(TWL4030_AIF_SLAVE_EN);
1127 format &= ~(TWL4030_CLK256FS_EN);
1128 break;
1129 case SND_SOC_DAIFMT_CBS_CFS:
1130 format |= TWL4030_AIF_SLAVE_EN;
1131 format |= TWL4030_CLK256FS_EN;
1132 break;
1133 default:
1134 return -EINVAL;
1135 }
1136
1137 /* interface format */
1138 format &= ~TWL4030_AIF_FORMAT;
1139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1140 case SND_SOC_DAIFMT_I2S:
1141 format |= TWL4030_AIF_FORMAT_CODEC;
1142 break;
1143 default:
1144 return -EINVAL;
1145 }
1146
1147 if (format != old_format) {
1148
1149 /* clear CODECPDZ before changing format (codec requirement) */
1150 twl4030_clear_codecpdz(codec);
1151
1152 /* change format */
1153 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1154
1155 /* set CODECPDZ afterwards */
1156 twl4030_set_codecpdz(codec);
1157 }
1158
1159 return 0;
1160 }
1161
1162 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1163 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1164
1165 struct snd_soc_dai twl4030_dai = {
1166 .name = "twl4030",
1167 .playback = {
1168 .stream_name = "Playback",
1169 .channels_min = 2,
1170 .channels_max = 2,
1171 .rates = TWL4030_RATES,
1172 .formats = TWL4030_FORMATS,},
1173 .capture = {
1174 .stream_name = "Capture",
1175 .channels_min = 2,
1176 .channels_max = 2,
1177 .rates = TWL4030_RATES,
1178 .formats = TWL4030_FORMATS,},
1179 .ops = {
1180 .hw_params = twl4030_hw_params,
1181 .set_sysclk = twl4030_set_dai_sysclk,
1182 .set_fmt = twl4030_set_dai_fmt,
1183 }
1184 };
1185 EXPORT_SYMBOL_GPL(twl4030_dai);
1186
1187 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1188 {
1189 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1190 struct snd_soc_codec *codec = socdev->codec;
1191
1192 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1193
1194 return 0;
1195 }
1196
1197 static int twl4030_resume(struct platform_device *pdev)
1198 {
1199 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1200 struct snd_soc_codec *codec = socdev->codec;
1201
1202 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1203 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1204 return 0;
1205 }
1206
1207 /*
1208 * initialize the driver
1209 * register the mixer and dsp interfaces with the kernel
1210 */
1211
1212 static int twl4030_init(struct snd_soc_device *socdev)
1213 {
1214 struct snd_soc_codec *codec = socdev->codec;
1215 int ret = 0;
1216
1217 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1218
1219 codec->name = "twl4030";
1220 codec->owner = THIS_MODULE;
1221 codec->read = twl4030_read_reg_cache;
1222 codec->write = twl4030_write;
1223 codec->set_bias_level = twl4030_set_bias_level;
1224 codec->dai = &twl4030_dai;
1225 codec->num_dai = 1;
1226 codec->reg_cache_size = sizeof(twl4030_reg);
1227 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1228 GFP_KERNEL);
1229 if (codec->reg_cache == NULL)
1230 return -ENOMEM;
1231
1232 /* register pcms */
1233 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1234 if (ret < 0) {
1235 printk(KERN_ERR "twl4030: failed to create pcms\n");
1236 goto pcm_err;
1237 }
1238
1239 twl4030_init_chip(codec);
1240
1241 /* power on device */
1242 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1243
1244 twl4030_add_controls(codec);
1245 twl4030_add_widgets(codec);
1246
1247 ret = snd_soc_init_card(socdev);
1248 if (ret < 0) {
1249 printk(KERN_ERR "twl4030: failed to register card\n");
1250 goto card_err;
1251 }
1252
1253 return ret;
1254
1255 card_err:
1256 snd_soc_free_pcms(socdev);
1257 snd_soc_dapm_free(socdev);
1258 pcm_err:
1259 kfree(codec->reg_cache);
1260 return ret;
1261 }
1262
1263 static struct snd_soc_device *twl4030_socdev;
1264
1265 static int twl4030_probe(struct platform_device *pdev)
1266 {
1267 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1268 struct snd_soc_codec *codec;
1269
1270 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1271 if (codec == NULL)
1272 return -ENOMEM;
1273
1274 socdev->codec = codec;
1275 mutex_init(&codec->mutex);
1276 INIT_LIST_HEAD(&codec->dapm_widgets);
1277 INIT_LIST_HEAD(&codec->dapm_paths);
1278
1279 twl4030_socdev = socdev;
1280 twl4030_init(socdev);
1281
1282 return 0;
1283 }
1284
1285 static int twl4030_remove(struct platform_device *pdev)
1286 {
1287 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1288 struct snd_soc_codec *codec = socdev->codec;
1289
1290 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1291 kfree(codec);
1292
1293 return 0;
1294 }
1295
1296 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1297 .probe = twl4030_probe,
1298 .remove = twl4030_remove,
1299 .suspend = twl4030_suspend,
1300 .resume = twl4030_resume,
1301 };
1302 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1303
1304 static int __init twl4030_modinit(void)
1305 {
1306 return snd_soc_register_dai(&twl4030_dai);
1307 }
1308 module_init(twl4030_modinit);
1309
1310 static void __exit twl4030_exit(void)
1311 {
1312 snd_soc_unregister_dai(&twl4030_dai);
1313 }
1314 module_exit(twl4030_exit);
1315
1316 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1317 MODULE_AUTHOR("Steve Sakoman");
1318 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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