sound/soc/codecs/uda1380.c

   1 /*
   2  * uda1380.c - Philips UDA1380 ALSA SoC audio driver
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
   9  *
  10  * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
  11  * codec model.
  12  *
  13  * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
  14  * Copyright 2005 Openedhand Ltd.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/types.h>
  20 #include <linux/slab.h>
  21 #include <linux/errno.h>
  22 #include <linux/gpio.h>
  23 #include <linux/delay.h>
  24 #include <linux/i2c.h>
  25 #include <linux/workqueue.h>
  26 #include <sound/core.h>
  27 #include <sound/control.h>
  28 #include <sound/initval.h>
  29 #include <sound/soc.h>
  30 #include <sound/tlv.h>
  31 #include <sound/uda1380.h>
  32
  33 #include "uda1380.h"
  34
  35 /* codec private data */
  36 struct uda1380_priv {
  37         struct snd_soc_codec *codec;
  38         unsigned int dac_clk;
  39         struct work_struct work;
  40         void *control_data;
  41 };
  42
  43 /*
  44  * uda1380 register cache
  45  */
  46 static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
  47         0x0502, 0x0000, 0x0000, 0x3f3f,
  48         0x0202, 0x0000, 0x0000, 0x0000,
  49         0x0000, 0x0000, 0x0000, 0x0000,
  50         0x0000, 0x0000, 0x0000, 0x0000,
  51         0x0000, 0xff00, 0x0000, 0x4800,
  52         0x0000, 0x0000, 0x0000, 0x0000,
  53         0x0000, 0x0000, 0x0000, 0x0000,
  54         0x0000, 0x0000, 0x0000, 0x0000,
  55         0x0000, 0x8000, 0x0002, 0x0000,
  56 };
  57
  58 static unsigned long uda1380_cache_dirty;
  59
  60 /*
  61  * read uda1380 register cache
  62  */
  63 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
  64         unsigned int reg)
  65 {
  66         u16 *cache = codec->reg_cache;
  67         if (reg == UDA1380_RESET)
  68                 return 0;
  69         if (reg >= UDA1380_CACHEREGNUM)
  70                 return -1;
  71         return cache[reg];
  72 }
  73
  74 /*
  75  * write uda1380 register cache
  76  */
  77 static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
  78         u16 reg, unsigned int value)
  79 {
  80         u16 *cache = codec->reg_cache;
  81
  82         if (reg >= UDA1380_CACHEREGNUM)
  83                 return;
  84         if ((reg >= 0x10) && (cache[reg] != value))
  85                 set_bit(reg - 0x10, &uda1380_cache_dirty);
  86         cache[reg] = value;
  87 }
  88
  89 /*
  90  * write to the UDA1380 register space
  91  */
  92 static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
  93         unsigned int value)
  94 {
  95         u8 data[3];
  96
  97         /* data is
  98          *   data[0] is register offset
  99          *   data[1] is MS byte
 100          *   data[2] is LS byte
 101          */
 102         data[0] = reg;
 103         data[1] = (value & 0xff00) >> 8;
 104         data[2] = value & 0x00ff;
 105
 106         uda1380_write_reg_cache(codec, reg, value);
 107
 108         /* the interpolator & decimator regs must only be written when the
 109          * codec DAI is active.
 110          */
 111         if (!codec->active && (reg >= UDA1380_MVOL))
 112                 return 0;
 113         pr_debug("uda1380: hw write %x val %x\n", reg, value);
 114         if (codec->hw_write(codec->control_data, data, 3) == 3) {
 115                 unsigned int val;
 116                 i2c_master_send(codec->control_data, data, 1);
 117                 i2c_master_recv(codec->control_data, data, 2);
 118                 val = (data[0]<<8) | data[1];
 119                 if (val != value) {
 120                         pr_debug("uda1380: READ BACK VAL %x\n",
 121                                         (data[0]<<8) | data[1]);
 122                         return -EIO;
 123                 }
 124                 if (reg >= 0x10)
 125                         clear_bit(reg - 0x10, &uda1380_cache_dirty);
 126                 return 0;
 127         } else
 128                 return -EIO;
 129 }
 130
 131 static void uda1380_sync_cache(struct snd_soc_codec *codec)
 132 {
 133         int reg;
 134         u8 data[3];
 135         u16 *cache = codec->reg_cache;
 136
 137         /* Sync reg_cache with the hardware */
 138         for (reg = 0; reg < UDA1380_MVOL; reg++) {
 139                 data[0] = reg;
 140                 data[1] = (cache[reg] & 0xff00) >> 8;
 141                 data[2] = cache[reg] & 0x00ff;
 142                 if (codec->hw_write(codec->control_data, data, 3) != 3)
 143                         dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
 144                                 __func__, reg);
 145         }
 146 }
 147
 148 static int uda1380_reset(struct snd_soc_codec *codec)
 149 {
 150         struct uda1380_platform_data *pdata = codec->dev->platform_data;
 151
 152         if (gpio_is_valid(pdata->gpio_reset)) {
 153                 gpio_set_value(pdata->gpio_reset, 1);
 154                 mdelay(1);
 155                 gpio_set_value(pdata->gpio_reset, 0);
 156         } else {
 157                 u8 data[3];
 158
 159                 data[0] = UDA1380_RESET;
 160                 data[1] = 0;
 161                 data[2] = 0;
 162
 163                 if (codec->hw_write(codec->control_data, data, 3) != 3) {
 164                         dev_err(codec->dev, "%s: failed\n", __func__);
 165                         return -EIO;
 166                 }
 167         }
 168
 169         return 0;
 170 }
 171
 172 static void uda1380_flush_work(struct work_struct *work)
 173 {
 174         struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
 175         struct snd_soc_codec *uda1380_codec = uda1380->codec;
 176         int bit, reg;
 177
 178         for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
 179                 reg = 0x10 + bit;
 180                 pr_debug("uda1380: flush reg %x val %x:\n", reg,
 181                                 uda1380_read_reg_cache(uda1380_codec, reg));
 182                 uda1380_write(uda1380_codec, reg,
 183                                 uda1380_read_reg_cache(uda1380_codec, reg));
 184                 clear_bit(bit, &uda1380_cache_dirty);
 185         }
 186
 187 }
 188
 189 /* declarations of ALSA reg_elem_REAL controls */
 190 static const char *uda1380_deemp[] = {
 191         "None",
 192         "32kHz",
 193         "44.1kHz",
 194         "48kHz",
 195         "96kHz",
 196 };
 197 static const char *uda1380_input_sel[] = {
 198         "Line",
 199         "Mic + Line R",
 200         "Line L",
 201         "Mic",
 202 };
 203 static const char *uda1380_output_sel[] = {
 204         "DAC",
 205         "Analog Mixer",
 206 };
 207 static const char *uda1380_spf_mode[] = {
 208         "Flat",
 209         "Minimum1",
 210         "Minimum2",
 211         "Maximum"
 212 };
 213 static const char *uda1380_capture_sel[] = {
 214         "ADC",
 215         "Digital Mixer"
 216 };
 217 static const char *uda1380_sel_ns[] = {
 218         "3rd-order",
 219         "5th-order"
 220 };
 221 static const char *uda1380_mix_control[] = {
 222         "off",
 223         "PCM only",
 224         "before sound processing",
 225         "after sound processing"
 226 };
 227 static const char *uda1380_sdet_setting[] = {
 228         "3200",
 229         "4800",
 230         "9600",
 231         "19200"
 232 };
 233 static const char *uda1380_os_setting[] = {
 234         "single-speed",
 235         "double-speed (no mixing)",
 236         "quad-speed (no mixing)"
 237 };
 238
 239 static const struct soc_enum uda1380_deemp_enum[] = {
 240         SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
 241         SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
 242 };
 243 static const struct soc_enum uda1380_input_sel_enum =
 244         SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel);          /* SEL_MIC, SEL_LNA */
 245 static const struct soc_enum uda1380_output_sel_enum =
 246         SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel);          /* R02_EN_AVC */
 247 static const struct soc_enum uda1380_spf_enum =
 248         SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode);         /* M */
 249 static const struct soc_enum uda1380_capture_sel_enum =
 250         SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel);      /* SEL_SOURCE */
 251 static const struct soc_enum uda1380_sel_ns_enum =
 252         SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns);          /* SEL_NS */
 253 static const struct soc_enum uda1380_mix_enum =
 254         SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control);     /* MIX, MIX_POS */
 255 static const struct soc_enum uda1380_sdet_enum =
 256         SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting);     /* SD_VALUE */
 257 static const struct soc_enum uda1380_os_enum =
 258         SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting);       /* OS */
 259
 260 /*
 261  * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
 262  */
 263 static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
 264
 265 /*
 266  * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
 267  * from -66 dB in 0.5 dB steps (2 dB steps, really) and
 268  * from -52 dB in 0.25 dB steps
 269  */
 270 static const unsigned int mvol_tlv[] = {
 271         TLV_DB_RANGE_HEAD(3),
 272         0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
 273         16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
 274         44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
 275 };
 276
 277 /*
 278  * from -72 dB in 1.5 dB steps (6 dB steps really),
 279  * from -66 dB in 0.75 dB steps (3 dB steps really),
 280  * from -60 dB in 0.5 dB steps (2 dB steps really) and
 281  * from -46 dB in 0.25 dB steps
 282  */
 283 static const unsigned int vc_tlv[] = {
 284         TLV_DB_RANGE_HEAD(4),
 285         0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
 286         8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
 287         16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
 288         44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
 289 };
 290
 291 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
 292 static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
 293
 294 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
 295  * off at 18 dB max) */
 296 static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
 297
 298 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
 299 static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
 300
 301 /* from 0 to 24 dB in 3 dB steps */
 302 static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
 303
 304 /* from 0 to 30 dB in 2 dB steps */
 305 static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
 306
 307 static const struct snd_kcontrol_new uda1380_snd_controls[] = {
 308         SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv),     /* AVCR, AVCL */
 309         SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
 310         SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv),       /* VC2 */
 311         SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv),       /* VC1 */
 312         SOC_ENUM("Sound Processing Filter", uda1380_spf_enum),                          /* M */
 313         SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv),     /* TRL, TRR */
 314         SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv),       /* BBL, BBR */
 315 /**/    SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1),          /* MTM */
 316         SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1),             /* MT2 from decimation filter */
 317         SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]),            /* DE2 */
 318         SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1),              /* MT1, from digital data input */
 319         SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]),            /* DE1 */
 320         SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0),   /* DA_POL_INV */
 321         SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum),                          /* SEL_NS */
 322         SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum),             /* MIX_POS, MIX */
 323         SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0),          /* SDET_ON */
 324         SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum),                /* SD_VALUE */
 325         SOC_ENUM("Oversampling Input", uda1380_os_enum),                        /* OS */
 326         SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv),        /* ML_DEC, MR_DEC */
 327 /**/    SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1),                /* MT_ADC */
 328         SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
 329         SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0),     /* ADCPOL_INV */
 330         SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv),   /* VGA_CTRL */
 331         SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0),            /* SKIP_DCFIL (before decimator) */
 332         SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0),            /* EN_DCFIL (at output of decimator) */
 333         SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0),                 /* TODO: enum, see table 62 */
 334         SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1),                   /* AGC_LEVEL */
 335         /* -5.5, -8, -11.5, -14 dBFS */
 336         SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
 337 };
 338
 339 /* Input mux */
 340 static const struct snd_kcontrol_new uda1380_input_mux_control =
 341         SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
 342
 343 /* Output mux */
 344 static const struct snd_kcontrol_new uda1380_output_mux_control =
 345         SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
 346
 347 /* Capture mux */
 348 static const struct snd_kcontrol_new uda1380_capture_mux_control =
 349         SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
 350
 351
 352 static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
 353         SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
 354                 &uda1380_input_mux_control),
 355         SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
 356                 &uda1380_output_mux_control),
 357         SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
 358                 &uda1380_capture_mux_control),
 359         SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
 360         SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
 361         SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
 362         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
 363         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
 364         SND_SOC_DAPM_INPUT("VINM"),
 365         SND_SOC_DAPM_INPUT("VINL"),
 366         SND_SOC_DAPM_INPUT("VINR"),
 367         SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
 368         SND_SOC_DAPM_OUTPUT("VOUTLHP"),
 369         SND_SOC_DAPM_OUTPUT("VOUTRHP"),
 370         SND_SOC_DAPM_OUTPUT("VOUTL"),
 371         SND_SOC_DAPM_OUTPUT("VOUTR"),
 372         SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
 373         SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
 374 };
 375
 376 static const struct snd_soc_dapm_route audio_map[] = {
 377
 378         /* output mux */
 379         {"HeadPhone Driver", NULL, "Output Mux"},
 380         {"VOUTR", NULL, "Output Mux"},
 381         {"VOUTL", NULL, "Output Mux"},
 382
 383         {"Analog Mixer", NULL, "VINR"},
 384         {"Analog Mixer", NULL, "VINL"},
 385         {"Analog Mixer", NULL, "DAC"},
 386
 387         {"Output Mux", "DAC", "DAC"},
 388         {"Output Mux", "Analog Mixer", "Analog Mixer"},
 389
 390         /* {"DAC", "Digital Mixer", "I2S" } */
 391
 392         /* headphone driver */
 393         {"VOUTLHP", NULL, "HeadPhone Driver"},
 394         {"VOUTRHP", NULL, "HeadPhone Driver"},
 395
 396         /* input mux */
 397         {"Left ADC", NULL, "Input Mux"},
 398         {"Input Mux", "Mic", "Mic LNA"},
 399         {"Input Mux", "Mic + Line R", "Mic LNA"},
 400         {"Input Mux", "Line L", "Left PGA"},
 401         {"Input Mux", "Line", "Left PGA"},
 402
 403         /* right input */
 404         {"Right ADC", "Mic + Line R", "Right PGA"},
 405         {"Right ADC", "Line", "Right PGA"},
 406
 407         /* inputs */
 408         {"Mic LNA", NULL, "VINM"},
 409         {"Left PGA", NULL, "VINL"},
 410         {"Right PGA", NULL, "VINR"},
 411 };
 412
 413 static int uda1380_add_widgets(struct snd_soc_codec *codec)
 414 {
 415         struct snd_soc_dapm_context *dapm = &codec->dapm;
 416
 417         snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets,
 418                                   ARRAY_SIZE(uda1380_dapm_widgets));
 419         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 420
 421         return 0;
 422 }
 423
 424 static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
 425                 unsigned int fmt)
 426 {
 427         struct snd_soc_codec *codec = codec_dai->codec;
 428         int iface;
 429
 430         /* set up DAI based upon fmt */
 431         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 432         iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
 433
 434         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 435         case SND_SOC_DAIFMT_I2S:
 436                 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
 437                 break;
 438         case SND_SOC_DAIFMT_LSB:
 439                 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
 440                 break;
 441         case SND_SOC_DAIFMT_MSB:
 442                 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
 443         }
 444
 445         /* DATAI is slave only, so in single-link mode, this has to be slave */
 446         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
 447                 return -EINVAL;
 448
 449         uda1380_write(codec, UDA1380_IFACE, iface);
 450
 451         return 0;
 452 }
 453
 454 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
 455                 unsigned int fmt)
 456 {
 457         struct snd_soc_codec *codec = codec_dai->codec;
 458         int iface;
 459
 460         /* set up DAI based upon fmt */
 461         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 462         iface &= ~R01_SFORI_MASK;
 463
 464         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 465         case SND_SOC_DAIFMT_I2S:
 466                 iface |= R01_SFORI_I2S;
 467                 break;
 468         case SND_SOC_DAIFMT_LSB:
 469                 iface |= R01_SFORI_LSB16;
 470                 break;
 471         case SND_SOC_DAIFMT_MSB:
 472                 iface |= R01_SFORI_MSB;
 473         }
 474
 475         /* DATAI is slave only, so this has to be slave */
 476         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
 477                 return -EINVAL;
 478
 479         uda1380_write(codec, UDA1380_IFACE, iface);
 480
 481         return 0;
 482 }
 483
 484 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
 485                 unsigned int fmt)
 486 {
 487         struct snd_soc_codec *codec = codec_dai->codec;
 488         int iface;
 489
 490         /* set up DAI based upon fmt */
 491         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 492         iface &= ~(R01_SIM | R01_SFORO_MASK);
 493
 494         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 495         case SND_SOC_DAIFMT_I2S:
 496                 iface |= R01_SFORO_I2S;
 497                 break;
 498         case SND_SOC_DAIFMT_LSB:
 499                 iface |= R01_SFORO_LSB16;
 500                 break;
 501         case SND_SOC_DAIFMT_MSB:
 502                 iface |= R01_SFORO_MSB;
 503         }
 504
 505         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
 506                 iface |= R01_SIM;
 507
 508         uda1380_write(codec, UDA1380_IFACE, iface);
 509
 510         return 0;
 511 }
 512
 513 static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
 514                 struct snd_soc_dai *dai)
 515 {
 516         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 517         struct snd_soc_codec *codec = rtd->codec;
 518         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
 519         int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
 520
 521         switch (cmd) {
 522         case SNDRV_PCM_TRIGGER_START:
 523         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 524                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
 525                                         mixer & ~R14_SILENCE);
 526                 schedule_work(&uda1380->work);
 527                 break;
 528         case SNDRV_PCM_TRIGGER_STOP:
 529         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 530                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
 531                                         mixer | R14_SILENCE);
 532                 schedule_work(&uda1380->work);
 533                 break;
 534         }
 535         return 0;
 536 }
 537
 538 static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
 539                                  struct snd_pcm_hw_params *params,
 540                                  struct snd_soc_dai *dai)
 541 {
 542         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 543         struct snd_soc_codec *codec = rtd->codec;
 544         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 545
 546         /* set WSPLL power and divider if running from this clock */
 547         if (clk & R00_DAC_CLK) {
 548                 int rate = params_rate(params);
 549                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 550                 clk &= ~0x3; /* clear SEL_LOOP_DIV */
 551                 switch (rate) {
 552                 case 6250 ... 12500:
 553                         clk |= 0x0;
 554                         break;
 555                 case 12501 ... 25000:
 556                         clk |= 0x1;
 557                         break;
 558                 case 25001 ... 50000:
 559                         clk |= 0x2;
 560                         break;
 561                 case 50001 ... 100000:
 562                         clk |= 0x3;
 563                         break;
 564                 }
 565                 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
 566         }
 567
 568         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 569                 clk |= R00_EN_DAC | R00_EN_INT;
 570         else
 571                 clk |= R00_EN_ADC | R00_EN_DEC;
 572
 573         uda1380_write(codec, UDA1380_CLK, clk);
 574         return 0;
 575 }
 576
 577 static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
 578                                  struct snd_soc_dai *dai)
 579 {
 580         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 581         struct snd_soc_codec *codec = rtd->codec;
 582         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 583
 584         /* shut down WSPLL power if running from this clock */
 585         if (clk & R00_DAC_CLK) {
 586                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 587                 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
 588         }
 589
 590         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 591                 clk &= ~(R00_EN_DAC | R00_EN_INT);
 592         else
 593                 clk &= ~(R00_EN_ADC | R00_EN_DEC);
 594
 595         uda1380_write(codec, UDA1380_CLK, clk);
 596 }
 597
 598 static int uda1380_set_bias_level(struct snd_soc_codec *codec,
 599         enum snd_soc_bias_level level)
 600 {
 601         int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 602         int reg;
 603         struct uda1380_platform_data *pdata = codec->dev->platform_data;
 604
 605         if (codec->dapm.bias_level == level)
 606                 return 0;
 607
 608         switch (level) {
 609         case SND_SOC_BIAS_ON:
 610         case SND_SOC_BIAS_PREPARE:
 611                 /* ADC, DAC on */
 612                 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
 613                 break;
 614         case SND_SOC_BIAS_STANDBY:
 615                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 616                         if (gpio_is_valid(pdata->gpio_power)) {
 617                                 gpio_set_value(pdata->gpio_power, 1);
 618                                 mdelay(1);
 619                                 uda1380_reset(codec);
 620                         }
 621
 622                         uda1380_sync_cache(codec);
 623                 }
 624                 uda1380_write(codec, UDA1380_PM, 0x0);
 625                 break;
 626         case SND_SOC_BIAS_OFF:
 627                 if (!gpio_is_valid(pdata->gpio_power))
 628                         break;
 629
 630                 gpio_set_value(pdata->gpio_power, 0);
 631
 632                 /* Mark mixer regs cache dirty to sync them with
 633                  * codec regs on power on.
 634                  */
 635                 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
 636                         set_bit(reg - 0x10, &uda1380_cache_dirty);
 637         }
 638         codec->dapm.bias_level = level;
 639         return 0;
 640 }
 641
 642 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 643                        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
 644                        SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 645
 646 static struct snd_soc_dai_ops uda1380_dai_ops = {
 647         .hw_params      = uda1380_pcm_hw_params,
 648         .shutdown       = uda1380_pcm_shutdown,
 649         .trigger        = uda1380_trigger,
 650         .set_fmt        = uda1380_set_dai_fmt_both,
 651 };
 652
 653 static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
 654         .hw_params      = uda1380_pcm_hw_params,
 655         .shutdown       = uda1380_pcm_shutdown,
 656         .trigger        = uda1380_trigger,
 657         .set_fmt        = uda1380_set_dai_fmt_playback,
 658 };
 659
 660 static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
 661         .hw_params      = uda1380_pcm_hw_params,
 662         .shutdown       = uda1380_pcm_shutdown,
 663         .trigger        = uda1380_trigger,
 664         .set_fmt        = uda1380_set_dai_fmt_capture,
 665 };
 666
 667 static struct snd_soc_dai_driver uda1380_dai[] = {
 668 {
 669         .name = "uda1380-hifi",
 670         .playback = {
 671                 .stream_name = "Playback",
 672                 .channels_min = 1,
 673                 .channels_max = 2,
 674                 .rates = UDA1380_RATES,
 675                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 676         .capture = {
 677                 .stream_name = "Capture",
 678                 .channels_min = 1,
 679                 .channels_max = 2,
 680                 .rates = UDA1380_RATES,
 681                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 682         .ops = &uda1380_dai_ops,
 683 },
 684 { /* playback only - dual interface */
 685         .name = "uda1380-hifi-playback",
 686         .playback = {
 687                 .stream_name = "Playback",
 688                 .channels_min = 1,
 689                 .channels_max = 2,
 690                 .rates = UDA1380_RATES,
 691                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 692         },
 693         .ops = &uda1380_dai_ops_playback,
 694 },
 695 { /* capture only - dual interface*/
 696         .name = "uda1380-hifi-capture",
 697         .capture = {
 698                 .stream_name = "Capture",
 699                 .channels_min = 1,
 700                 .channels_max = 2,
 701                 .rates = UDA1380_RATES,
 702                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 703         },
 704         .ops = &uda1380_dai_ops_capture,
 705 },
 706 };
 707
 708 static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
 709 {
 710         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
 711         return 0;
 712 }
 713
 714 static int uda1380_resume(struct snd_soc_codec *codec)
 715 {
 716         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 717         return 0;
 718 }
 719
 720 static int uda1380_probe(struct snd_soc_codec *codec)
 721 {
 722         struct uda1380_platform_data *pdata =codec->dev->platform_data;
 723         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
 724         int ret;
 725
 726         uda1380->codec = codec;
 727
 728         codec->hw_write = (hw_write_t)i2c_master_send;
 729         codec->control_data = uda1380->control_data;
 730
 731         if (!pdata)
 732                 return -EINVAL;
 733
 734         if (gpio_is_valid(pdata->gpio_reset)) {
 735                 ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
 736                 if (ret)
 737                         goto err_out;
 738                 ret = gpio_direction_output(pdata->gpio_reset, 0);
 739                 if (ret)
 740                         goto err_gpio_reset_conf;
 741         }
 742
 743         if (gpio_is_valid(pdata->gpio_power)) {
 744                 ret = gpio_request(pdata->gpio_power, "uda1380 power");
 745                 if (ret)
 746                         goto err_gpio;
 747                 ret = gpio_direction_output(pdata->gpio_power, 0);
 748                 if (ret)
 749                         goto err_gpio_power_conf;
 750         } else {
 751                 ret = uda1380_reset(codec);
 752                 if (ret) {
 753                         dev_err(codec->dev, "Failed to issue reset\n");
 754                         goto err_reset;
 755                 }
 756         }
 757
 758         INIT_WORK(&uda1380->work, uda1380_flush_work);
 759
 760         /* power on device */
 761         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 762         /* set clock input */
 763         switch (pdata->dac_clk) {
 764         case UDA1380_DAC_CLK_SYSCLK:
 765                 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
 766                 break;
 767         case UDA1380_DAC_CLK_WSPLL:
 768                 uda1380_write_reg_cache(codec, UDA1380_CLK,
 769                         R00_DAC_CLK);
 770                 break;
 771         }
 772
 773         snd_soc_add_controls(codec, uda1380_snd_controls,
 774                                 ARRAY_SIZE(uda1380_snd_controls));
 775         uda1380_add_widgets(codec);
 776
 777         return 0;
 778
 779 err_reset:
 780 err_gpio_power_conf:
 781         if (gpio_is_valid(pdata->gpio_power))
 782                 gpio_free(pdata->gpio_power);
 783
 784 err_gpio_reset_conf:
 785 err_gpio:
 786         if (gpio_is_valid(pdata->gpio_reset))
 787                 gpio_free(pdata->gpio_reset);
 788 err_out:
 789         return ret;
 790 }
 791
 792 /* power down chip */
 793 static int uda1380_remove(struct snd_soc_codec *codec)
 794 {
 795         struct uda1380_platform_data *pdata =codec->dev->platform_data;
 796
 797         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
 798
 799         gpio_free(pdata->gpio_reset);
 800         gpio_free(pdata->gpio_power);
 801
 802         return 0;
 803 }
 804
 805 static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
 806         .probe =        uda1380_probe,
 807         .remove =       uda1380_remove,
 808         .suspend =      uda1380_suspend,
 809         .resume =       uda1380_resume,
 810         .read =         uda1380_read_reg_cache,
 811         .write =        uda1380_write,
 812         .set_bias_level = uda1380_set_bias_level,
 813         .reg_cache_size = ARRAY_SIZE(uda1380_reg),
 814         .reg_word_size = sizeof(u16),
 815         .reg_cache_default = uda1380_reg,
 816         .reg_cache_step = 1,
 817 };
 818
 819 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 820 static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
 821                                       const struct i2c_device_id *id)
 822 {
 823         struct uda1380_priv *uda1380;
 824         int ret;
 825
 826         uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
 827         if (uda1380 == NULL)
 828                 return -ENOMEM;
 829
 830         i2c_set_clientdata(i2c, uda1380);
 831         uda1380->control_data = i2c;
 832
 833         ret =  snd_soc_register_codec(&i2c->dev,
 834                         &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
 835         if (ret < 0)
 836                 kfree(uda1380);
 837         return ret;
 838 }
 839
 840 static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
 841 {
 842         snd_soc_unregister_codec(&i2c->dev);
 843         kfree(i2c_get_clientdata(i2c));
 844         return 0;
 845 }
 846
 847 static const struct i2c_device_id uda1380_i2c_id[] = {
 848         { "uda1380", 0 },
 849         { }
 850 };
 851 MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
 852
 853 static struct i2c_driver uda1380_i2c_driver = {
 854         .driver = {
 855                 .name =  "uda1380-codec",
 856                 .owner = THIS_MODULE,
 857         },
 858         .probe =    uda1380_i2c_probe,
 859         .remove =   __devexit_p(uda1380_i2c_remove),
 860         .id_table = uda1380_i2c_id,
 861 };
 862 #endif
 863
 864 static int __init uda1380_modinit(void)
 865 {
 866         int ret;
 867 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 868         ret = i2c_add_driver(&uda1380_i2c_driver);
 869         if (ret != 0)
 870                 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
 871 #endif
 872         return 0;
 873 }
 874 module_init(uda1380_modinit);
 875
 876 static void __exit uda1380_exit(void)
 877 {
 878 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 879         i2c_del_driver(&uda1380_i2c_driver);
 880 #endif
 881 }
 882 module_exit(uda1380_exit);
 883
 884 MODULE_AUTHOR("Giorgio Padrin");
 885 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
 886 MODULE_LICENSE("GPL");