2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
14 * Copyright 2005 Openedhand Ltd.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/gpio.h>
23 #include <linux/delay.h>
24 #include <linux/i2c.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/control.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
30 #include <sound/tlv.h>
31 #include <sound/uda1380.h>
35 /* codec private data */
37 struct snd_soc_codec
*codec
;
39 struct work_struct work
;
44 * uda1380 register cache
46 static const u16 uda1380_reg
[UDA1380_CACHEREGNUM
] = {
47 0x0502, 0x0000, 0x0000, 0x3f3f,
48 0x0202, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0x0000, 0x0000, 0x0000,
51 0x0000, 0xff00, 0x0000, 0x4800,
52 0x0000, 0x0000, 0x0000, 0x0000,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0000, 0x8000, 0x0002, 0x0000,
58 static unsigned long uda1380_cache_dirty
;
61 * read uda1380 register cache
63 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec
*codec
,
66 u16
*cache
= codec
->reg_cache
;
67 if (reg
== UDA1380_RESET
)
69 if (reg
>= UDA1380_CACHEREGNUM
)
75 * write uda1380 register cache
77 static inline void uda1380_write_reg_cache(struct snd_soc_codec
*codec
,
78 u16 reg
, unsigned int value
)
80 u16
*cache
= codec
->reg_cache
;
82 if (reg
>= UDA1380_CACHEREGNUM
)
84 if ((reg
>= 0x10) && (cache
[reg
] != value
))
85 set_bit(reg
- 0x10, &uda1380_cache_dirty
);
90 * write to the UDA1380 register space
92 static int uda1380_write(struct snd_soc_codec
*codec
, unsigned int reg
,
98 * data[0] is register offset
103 data
[1] = (value
& 0xff00) >> 8;
104 data
[2] = value
& 0x00ff;
106 uda1380_write_reg_cache(codec
, reg
, value
);
108 /* the interpolator & decimator regs must only be written when the
109 * codec DAI is active.
111 if (!snd_soc_codec_is_active(codec
) && (reg
>= UDA1380_MVOL
))
113 pr_debug("uda1380: hw write %x val %x\n", reg
, value
);
114 if (codec
->hw_write(codec
->control_data
, data
, 3) == 3) {
116 i2c_master_send(codec
->control_data
, data
, 1);
117 i2c_master_recv(codec
->control_data
, data
, 2);
118 val
= (data
[0]<<8) | data
[1];
120 pr_debug("uda1380: READ BACK VAL %x\n",
121 (data
[0]<<8) | data
[1]);
125 clear_bit(reg
- 0x10, &uda1380_cache_dirty
);
131 static void uda1380_sync_cache(struct snd_soc_codec
*codec
)
135 u16
*cache
= codec
->reg_cache
;
137 /* Sync reg_cache with the hardware */
138 for (reg
= 0; reg
< UDA1380_MVOL
; reg
++) {
140 data
[1] = (cache
[reg
] & 0xff00) >> 8;
141 data
[2] = cache
[reg
] & 0x00ff;
142 if (codec
->hw_write(codec
->control_data
, data
, 3) != 3)
143 dev_err(codec
->dev
, "%s: write to reg 0x%x failed\n",
148 static int uda1380_reset(struct snd_soc_codec
*codec
)
150 struct uda1380_platform_data
*pdata
= codec
->dev
->platform_data
;
152 if (gpio_is_valid(pdata
->gpio_reset
)) {
153 gpio_set_value(pdata
->gpio_reset
, 1);
155 gpio_set_value(pdata
->gpio_reset
, 0);
159 data
[0] = UDA1380_RESET
;
163 if (codec
->hw_write(codec
->control_data
, data
, 3) != 3) {
164 dev_err(codec
->dev
, "%s: failed\n", __func__
);
172 static void uda1380_flush_work(struct work_struct
*work
)
174 struct uda1380_priv
*uda1380
= container_of(work
, struct uda1380_priv
, work
);
175 struct snd_soc_codec
*uda1380_codec
= uda1380
->codec
;
178 for_each_set_bit(bit
, &uda1380_cache_dirty
, UDA1380_CACHEREGNUM
- 0x10) {
180 pr_debug("uda1380: flush reg %x val %x:\n", reg
,
181 uda1380_read_reg_cache(uda1380_codec
, reg
));
182 uda1380_write(uda1380_codec
, reg
,
183 uda1380_read_reg_cache(uda1380_codec
, reg
));
184 clear_bit(bit
, &uda1380_cache_dirty
);
189 /* declarations of ALSA reg_elem_REAL controls */
190 static const char *uda1380_deemp
[] = {
197 static const char *uda1380_input_sel
[] = {
203 static const char *uda1380_output_sel
[] = {
207 static const char *uda1380_spf_mode
[] = {
213 static const char *uda1380_capture_sel
[] = {
217 static const char *uda1380_sel_ns
[] = {
221 static const char *uda1380_mix_control
[] = {
224 "before sound processing",
225 "after sound processing"
227 static const char *uda1380_sdet_setting
[] = {
233 static const char *uda1380_os_setting
[] = {
235 "double-speed (no mixing)",
236 "quad-speed (no mixing)"
239 static const struct soc_enum uda1380_deemp_enum
[] = {
240 SOC_ENUM_SINGLE(UDA1380_DEEMP
, 8, ARRAY_SIZE(uda1380_deemp
),
242 SOC_ENUM_SINGLE(UDA1380_DEEMP
, 0, ARRAY_SIZE(uda1380_deemp
),
245 static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum
,
246 UDA1380_ADC
, 2, uda1380_input_sel
); /* SEL_MIC, SEL_LNA */
247 static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum
,
248 UDA1380_PM
, 7, uda1380_output_sel
); /* R02_EN_AVC */
249 static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum
,
250 UDA1380_MODE
, 14, uda1380_spf_mode
); /* M */
251 static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum
,
252 UDA1380_IFACE
, 6, uda1380_capture_sel
); /* SEL_SOURCE */
253 static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum
,
254 UDA1380_MIXER
, 14, uda1380_sel_ns
); /* SEL_NS */
255 static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum
,
256 UDA1380_MIXER
, 12, uda1380_mix_control
); /* MIX, MIX_POS */
257 static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum
,
258 UDA1380_MIXER
, 4, uda1380_sdet_setting
); /* SD_VALUE */
259 static SOC_ENUM_SINGLE_DECL(uda1380_os_enum
,
260 UDA1380_MIXER
, 0, uda1380_os_setting
); /* OS */
263 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
265 static DECLARE_TLV_DB_SCALE(amix_tlv
, -4950, 150, 1);
268 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
269 * from -66 dB in 0.5 dB steps (2 dB steps, really) and
270 * from -52 dB in 0.25 dB steps
272 static const unsigned int mvol_tlv
[] = {
273 TLV_DB_RANGE_HEAD(3),
274 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
275 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
276 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
280 * from -72 dB in 1.5 dB steps (6 dB steps really),
281 * from -66 dB in 0.75 dB steps (3 dB steps really),
282 * from -60 dB in 0.5 dB steps (2 dB steps really) and
283 * from -46 dB in 0.25 dB steps
285 static const unsigned int vc_tlv
[] = {
286 TLV_DB_RANGE_HEAD(4),
287 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
288 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
289 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
290 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
293 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
294 static DECLARE_TLV_DB_SCALE(tr_tlv
, 0, 200, 0);
296 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
297 * off at 18 dB max) */
298 static DECLARE_TLV_DB_SCALE(bb_tlv
, 0, 200, 0);
300 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
301 static DECLARE_TLV_DB_SCALE(dec_tlv
, -6400, 50, 1);
303 /* from 0 to 24 dB in 3 dB steps */
304 static DECLARE_TLV_DB_SCALE(pga_tlv
, 0, 300, 0);
306 /* from 0 to 30 dB in 2 dB steps */
307 static DECLARE_TLV_DB_SCALE(vga_tlv
, 0, 200, 0);
309 static const struct snd_kcontrol_new uda1380_snd_controls
[] = {
310 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX
, 0, 8, 44, 1, amix_tlv
), /* AVCR, AVCL */
311 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL
, 0, 8, 252, 1, mvol_tlv
), /* MVCL, MVCR */
312 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL
, 8, 228, 1, vc_tlv
), /* VC2 */
313 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL
, 0, 228, 1, vc_tlv
), /* VC1 */
314 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum
), /* M */
315 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE
, 4, 12, 3, 0, tr_tlv
), /* TRL, TRR */
316 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE
, 0, 8, 15, 0, bb_tlv
), /* BBL, BBR */
317 /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP
, 14, 1, 1), /* MTM */
318 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP
, 11, 1, 1), /* MT2 from decimation filter */
319 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum
[0]), /* DE2 */
320 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP
, 3, 1, 1), /* MT1, from digital data input */
321 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum
[1]), /* DE1 */
322 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER
, 15, 1, 0), /* DA_POL_INV */
323 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum
), /* SEL_NS */
324 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum
), /* MIX_POS, MIX */
325 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER
, 6, 1, 0), /* SDET_ON */
326 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum
), /* SD_VALUE */
327 SOC_ENUM("Oversampling Input", uda1380_os_enum
), /* OS */
328 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC
, -128, 48, dec_tlv
), /* ML_DEC, MR_DEC */
329 /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA
, 15, 1, 1), /* MT_ADC */
330 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA
, 0, 8, 8, 0, pga_tlv
), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
331 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC
, 12, 1, 0), /* ADCPOL_INV */
332 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC
, 8, 15, 0, vga_tlv
), /* VGA_CTRL */
333 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC
, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
334 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC
, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
335 SOC_SINGLE("AGC Timing", UDA1380_AGC
, 8, 7, 0), /* TODO: enum, see table 62 */
336 SOC_SINGLE("AGC Target level", UDA1380_AGC
, 2, 3, 1), /* AGC_LEVEL */
337 /* -5.5, -8, -11.5, -14 dBFS */
338 SOC_SINGLE("AGC Switch", UDA1380_AGC
, 0, 1, 0),
342 static const struct snd_kcontrol_new uda1380_input_mux_control
=
343 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum
);
346 static const struct snd_kcontrol_new uda1380_output_mux_control
=
347 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum
);
350 static const struct snd_kcontrol_new uda1380_capture_mux_control
=
351 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum
);
354 static const struct snd_soc_dapm_widget uda1380_dapm_widgets
[] = {
355 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM
, 0, 0,
356 &uda1380_input_mux_control
),
357 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM
, 0, 0,
358 &uda1380_output_mux_control
),
359 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM
, 0, 0,
360 &uda1380_capture_mux_control
),
361 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM
, 3, 0, NULL
, 0),
362 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM
, 1, 0, NULL
, 0),
363 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM
, 4, 0, NULL
, 0),
364 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM
, 2, 0),
365 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM
, 0, 0),
366 SND_SOC_DAPM_INPUT("VINM"),
367 SND_SOC_DAPM_INPUT("VINL"),
368 SND_SOC_DAPM_INPUT("VINR"),
369 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM
, 6, 0, NULL
, 0),
370 SND_SOC_DAPM_OUTPUT("VOUTLHP"),
371 SND_SOC_DAPM_OUTPUT("VOUTRHP"),
372 SND_SOC_DAPM_OUTPUT("VOUTL"),
373 SND_SOC_DAPM_OUTPUT("VOUTR"),
374 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM
, 10, 0),
375 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM
, 13, 0, NULL
, 0),
378 static const struct snd_soc_dapm_route uda1380_dapm_routes
[] = {
381 {"HeadPhone Driver", NULL
, "Output Mux"},
382 {"VOUTR", NULL
, "Output Mux"},
383 {"VOUTL", NULL
, "Output Mux"},
385 {"Analog Mixer", NULL
, "VINR"},
386 {"Analog Mixer", NULL
, "VINL"},
387 {"Analog Mixer", NULL
, "DAC"},
389 {"Output Mux", "DAC", "DAC"},
390 {"Output Mux", "Analog Mixer", "Analog Mixer"},
392 /* {"DAC", "Digital Mixer", "I2S" } */
394 /* headphone driver */
395 {"VOUTLHP", NULL
, "HeadPhone Driver"},
396 {"VOUTRHP", NULL
, "HeadPhone Driver"},
399 {"Left ADC", NULL
, "Input Mux"},
400 {"Input Mux", "Mic", "Mic LNA"},
401 {"Input Mux", "Mic + Line R", "Mic LNA"},
402 {"Input Mux", "Line L", "Left PGA"},
403 {"Input Mux", "Line", "Left PGA"},
406 {"Right ADC", "Mic + Line R", "Right PGA"},
407 {"Right ADC", "Line", "Right PGA"},
410 {"Mic LNA", NULL
, "VINM"},
411 {"Left PGA", NULL
, "VINL"},
412 {"Right PGA", NULL
, "VINR"},
415 static int uda1380_set_dai_fmt_both(struct snd_soc_dai
*codec_dai
,
418 struct snd_soc_codec
*codec
= codec_dai
->codec
;
421 /* set up DAI based upon fmt */
422 iface
= uda1380_read_reg_cache(codec
, UDA1380_IFACE
);
423 iface
&= ~(R01_SFORI_MASK
| R01_SIM
| R01_SFORO_MASK
);
425 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
426 case SND_SOC_DAIFMT_I2S
:
427 iface
|= R01_SFORI_I2S
| R01_SFORO_I2S
;
429 case SND_SOC_DAIFMT_LSB
:
430 iface
|= R01_SFORI_LSB16
| R01_SFORO_LSB16
;
432 case SND_SOC_DAIFMT_MSB
:
433 iface
|= R01_SFORI_MSB
| R01_SFORO_MSB
;
436 /* DATAI is slave only, so in single-link mode, this has to be slave */
437 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
) != SND_SOC_DAIFMT_CBS_CFS
)
440 uda1380_write(codec
, UDA1380_IFACE
, iface
);
445 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai
*codec_dai
,
448 struct snd_soc_codec
*codec
= codec_dai
->codec
;
451 /* set up DAI based upon fmt */
452 iface
= uda1380_read_reg_cache(codec
, UDA1380_IFACE
);
453 iface
&= ~R01_SFORI_MASK
;
455 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
456 case SND_SOC_DAIFMT_I2S
:
457 iface
|= R01_SFORI_I2S
;
459 case SND_SOC_DAIFMT_LSB
:
460 iface
|= R01_SFORI_LSB16
;
462 case SND_SOC_DAIFMT_MSB
:
463 iface
|= R01_SFORI_MSB
;
466 /* DATAI is slave only, so this has to be slave */
467 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
) != SND_SOC_DAIFMT_CBS_CFS
)
470 uda1380_write(codec
, UDA1380_IFACE
, iface
);
475 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai
*codec_dai
,
478 struct snd_soc_codec
*codec
= codec_dai
->codec
;
481 /* set up DAI based upon fmt */
482 iface
= uda1380_read_reg_cache(codec
, UDA1380_IFACE
);
483 iface
&= ~(R01_SIM
| R01_SFORO_MASK
);
485 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
486 case SND_SOC_DAIFMT_I2S
:
487 iface
|= R01_SFORO_I2S
;
489 case SND_SOC_DAIFMT_LSB
:
490 iface
|= R01_SFORO_LSB16
;
492 case SND_SOC_DAIFMT_MSB
:
493 iface
|= R01_SFORO_MSB
;
496 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
) == SND_SOC_DAIFMT_CBM_CFM
)
499 uda1380_write(codec
, UDA1380_IFACE
, iface
);
504 static int uda1380_trigger(struct snd_pcm_substream
*substream
, int cmd
,
505 struct snd_soc_dai
*dai
)
507 struct snd_soc_codec
*codec
= dai
->codec
;
508 struct uda1380_priv
*uda1380
= snd_soc_codec_get_drvdata(codec
);
509 int mixer
= uda1380_read_reg_cache(codec
, UDA1380_MIXER
);
512 case SNDRV_PCM_TRIGGER_START
:
513 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
514 uda1380_write_reg_cache(codec
, UDA1380_MIXER
,
515 mixer
& ~R14_SILENCE
);
516 schedule_work(&uda1380
->work
);
518 case SNDRV_PCM_TRIGGER_STOP
:
519 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
520 uda1380_write_reg_cache(codec
, UDA1380_MIXER
,
521 mixer
| R14_SILENCE
);
522 schedule_work(&uda1380
->work
);
528 static int uda1380_pcm_hw_params(struct snd_pcm_substream
*substream
,
529 struct snd_pcm_hw_params
*params
,
530 struct snd_soc_dai
*dai
)
532 struct snd_soc_codec
*codec
= dai
->codec
;
533 u16 clk
= uda1380_read_reg_cache(codec
, UDA1380_CLK
);
535 /* set WSPLL power and divider if running from this clock */
536 if (clk
& R00_DAC_CLK
) {
537 int rate
= params_rate(params
);
538 u16 pm
= uda1380_read_reg_cache(codec
, UDA1380_PM
);
539 clk
&= ~0x3; /* clear SEL_LOOP_DIV */
544 case 12501 ... 25000:
547 case 25001 ... 50000:
550 case 50001 ... 100000:
554 uda1380_write(codec
, UDA1380_PM
, R02_PON_PLL
| pm
);
557 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
558 clk
|= R00_EN_DAC
| R00_EN_INT
;
560 clk
|= R00_EN_ADC
| R00_EN_DEC
;
562 uda1380_write(codec
, UDA1380_CLK
, clk
);
566 static void uda1380_pcm_shutdown(struct snd_pcm_substream
*substream
,
567 struct snd_soc_dai
*dai
)
569 struct snd_soc_codec
*codec
= dai
->codec
;
570 u16 clk
= uda1380_read_reg_cache(codec
, UDA1380_CLK
);
572 /* shut down WSPLL power if running from this clock */
573 if (clk
& R00_DAC_CLK
) {
574 u16 pm
= uda1380_read_reg_cache(codec
, UDA1380_PM
);
575 uda1380_write(codec
, UDA1380_PM
, ~R02_PON_PLL
& pm
);
578 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
579 clk
&= ~(R00_EN_DAC
| R00_EN_INT
);
581 clk
&= ~(R00_EN_ADC
| R00_EN_DEC
);
583 uda1380_write(codec
, UDA1380_CLK
, clk
);
586 static int uda1380_set_bias_level(struct snd_soc_codec
*codec
,
587 enum snd_soc_bias_level level
)
589 int pm
= uda1380_read_reg_cache(codec
, UDA1380_PM
);
591 struct uda1380_platform_data
*pdata
= codec
->dev
->platform_data
;
594 case SND_SOC_BIAS_ON
:
595 case SND_SOC_BIAS_PREPARE
:
597 uda1380_write(codec
, UDA1380_PM
, R02_PON_BIAS
| pm
);
599 case SND_SOC_BIAS_STANDBY
:
600 if (snd_soc_codec_get_bias_level(codec
) == SND_SOC_BIAS_OFF
) {
601 if (gpio_is_valid(pdata
->gpio_power
)) {
602 gpio_set_value(pdata
->gpio_power
, 1);
604 uda1380_reset(codec
);
607 uda1380_sync_cache(codec
);
609 uda1380_write(codec
, UDA1380_PM
, 0x0);
611 case SND_SOC_BIAS_OFF
:
612 if (!gpio_is_valid(pdata
->gpio_power
))
615 gpio_set_value(pdata
->gpio_power
, 0);
617 /* Mark mixer regs cache dirty to sync them with
618 * codec regs on power on.
620 for (reg
= UDA1380_MVOL
; reg
< UDA1380_CACHEREGNUM
; reg
++)
621 set_bit(reg
- 0x10, &uda1380_cache_dirty
);
626 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
627 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
628 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
630 static const struct snd_soc_dai_ops uda1380_dai_ops
= {
631 .hw_params
= uda1380_pcm_hw_params
,
632 .shutdown
= uda1380_pcm_shutdown
,
633 .trigger
= uda1380_trigger
,
634 .set_fmt
= uda1380_set_dai_fmt_both
,
637 static const struct snd_soc_dai_ops uda1380_dai_ops_playback
= {
638 .hw_params
= uda1380_pcm_hw_params
,
639 .shutdown
= uda1380_pcm_shutdown
,
640 .trigger
= uda1380_trigger
,
641 .set_fmt
= uda1380_set_dai_fmt_playback
,
644 static const struct snd_soc_dai_ops uda1380_dai_ops_capture
= {
645 .hw_params
= uda1380_pcm_hw_params
,
646 .shutdown
= uda1380_pcm_shutdown
,
647 .trigger
= uda1380_trigger
,
648 .set_fmt
= uda1380_set_dai_fmt_capture
,
651 static struct snd_soc_dai_driver uda1380_dai
[] = {
653 .name
= "uda1380-hifi",
655 .stream_name
= "Playback",
658 .rates
= UDA1380_RATES
,
659 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,},
661 .stream_name
= "Capture",
664 .rates
= UDA1380_RATES
,
665 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,},
666 .ops
= &uda1380_dai_ops
,
668 { /* playback only - dual interface */
669 .name
= "uda1380-hifi-playback",
671 .stream_name
= "Playback",
674 .rates
= UDA1380_RATES
,
675 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
677 .ops
= &uda1380_dai_ops_playback
,
679 { /* capture only - dual interface*/
680 .name
= "uda1380-hifi-capture",
682 .stream_name
= "Capture",
685 .rates
= UDA1380_RATES
,
686 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
688 .ops
= &uda1380_dai_ops_capture
,
692 static int uda1380_probe(struct snd_soc_codec
*codec
)
694 struct uda1380_platform_data
*pdata
=codec
->dev
->platform_data
;
695 struct uda1380_priv
*uda1380
= snd_soc_codec_get_drvdata(codec
);
698 uda1380
->codec
= codec
;
700 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
701 codec
->control_data
= uda1380
->control_data
;
706 if (gpio_is_valid(pdata
->gpio_reset
)) {
707 ret
= gpio_request_one(pdata
->gpio_reset
, GPIOF_OUT_INIT_LOW
,
713 if (gpio_is_valid(pdata
->gpio_power
)) {
714 ret
= gpio_request_one(pdata
->gpio_power
, GPIOF_OUT_INIT_LOW
,
719 ret
= uda1380_reset(codec
);
724 INIT_WORK(&uda1380
->work
, uda1380_flush_work
);
726 /* set clock input */
727 switch (pdata
->dac_clk
) {
728 case UDA1380_DAC_CLK_SYSCLK
:
729 uda1380_write_reg_cache(codec
, UDA1380_CLK
, 0);
731 case UDA1380_DAC_CLK_WSPLL
:
732 uda1380_write_reg_cache(codec
, UDA1380_CLK
,
740 if (gpio_is_valid(pdata
->gpio_reset
))
741 gpio_free(pdata
->gpio_reset
);
746 /* power down chip */
747 static int uda1380_remove(struct snd_soc_codec
*codec
)
749 struct uda1380_platform_data
*pdata
=codec
->dev
->platform_data
;
751 gpio_free(pdata
->gpio_reset
);
752 gpio_free(pdata
->gpio_power
);
757 static struct snd_soc_codec_driver soc_codec_dev_uda1380
= {
758 .probe
= uda1380_probe
,
759 .remove
= uda1380_remove
,
760 .read
= uda1380_read_reg_cache
,
761 .write
= uda1380_write
,
762 .set_bias_level
= uda1380_set_bias_level
,
763 .suspend_bias_off
= true,
765 .reg_cache_size
= ARRAY_SIZE(uda1380_reg
),
766 .reg_word_size
= sizeof(u16
),
767 .reg_cache_default
= uda1380_reg
,
770 .controls
= uda1380_snd_controls
,
771 .num_controls
= ARRAY_SIZE(uda1380_snd_controls
),
772 .dapm_widgets
= uda1380_dapm_widgets
,
773 .num_dapm_widgets
= ARRAY_SIZE(uda1380_dapm_widgets
),
774 .dapm_routes
= uda1380_dapm_routes
,
775 .num_dapm_routes
= ARRAY_SIZE(uda1380_dapm_routes
),
778 #if IS_ENABLED(CONFIG_I2C)
779 static int uda1380_i2c_probe(struct i2c_client
*i2c
,
780 const struct i2c_device_id
*id
)
782 struct uda1380_priv
*uda1380
;
785 uda1380
= devm_kzalloc(&i2c
->dev
, sizeof(struct uda1380_priv
),
790 i2c_set_clientdata(i2c
, uda1380
);
791 uda1380
->control_data
= i2c
;
793 ret
= snd_soc_register_codec(&i2c
->dev
,
794 &soc_codec_dev_uda1380
, uda1380_dai
, ARRAY_SIZE(uda1380_dai
));
798 static int uda1380_i2c_remove(struct i2c_client
*i2c
)
800 snd_soc_unregister_codec(&i2c
->dev
);
804 static const struct i2c_device_id uda1380_i2c_id
[] = {
808 MODULE_DEVICE_TABLE(i2c
, uda1380_i2c_id
);
810 static struct i2c_driver uda1380_i2c_driver
= {
812 .name
= "uda1380-codec",
813 .owner
= THIS_MODULE
,
815 .probe
= uda1380_i2c_probe
,
816 .remove
= uda1380_i2c_remove
,
817 .id_table
= uda1380_i2c_id
,
821 static int __init
uda1380_modinit(void)
824 #if IS_ENABLED(CONFIG_I2C)
825 ret
= i2c_add_driver(&uda1380_i2c_driver
);
827 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret
);
831 module_init(uda1380_modinit
);
833 static void __exit
uda1380_exit(void)
835 #if IS_ENABLED(CONFIG_I2C)
836 i2c_del_driver(&uda1380_i2c_driver
);
839 module_exit(uda1380_exit
);
841 MODULE_AUTHOR("Giorgio Padrin");
842 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
843 MODULE_LICENSE("GPL");