2 * wm5100.c -- WM5100 ALSA SoC Audio driver
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/gcd.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/regulator/fixed.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/wm5100.h>
36 #define WM5100_NUM_CORE_SUPPLIES 2
37 static const char *wm5100_core_supply_names
[WM5100_NUM_CORE_SUPPLIES
] = {
39 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
43 #define WM5100_SYNC_SRS 3
49 struct completion lock
;
52 /* codec private data */
54 struct regmap
*regmap
;
55 struct snd_soc_codec
*codec
;
57 struct regulator_bulk_data core_supplies
[WM5100_NUM_CORE_SUPPLIES
];
58 struct regulator
*cpvdd
;
59 struct regulator
*dbvdd2
;
60 struct regulator
*dbvdd3
;
67 bool aif_async
[WM5100_AIFS
];
68 bool aif_symmetric
[WM5100_AIFS
];
69 int sr_ref
[WM5100_SYNC_SRS
];
73 struct snd_soc_jack
*jack
;
78 struct wm5100_fll fll
[2];
80 struct wm5100_pdata pdata
;
83 struct gpio_chip gpio_chip
;
87 static int wm5100_sr_code
[] = {
114 static int wm5100_sr_regs
[WM5100_SYNC_SRS
] = {
120 static int wm5100_alloc_sr(struct snd_soc_codec
*codec
, int rate
)
122 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
123 int sr_code
, sr_free
, i
;
125 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
126 if (wm5100_sr_code
[i
] == rate
)
128 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
129 dev_err(codec
->dev
, "Unsupported sample rate: %dHz\n", rate
);
134 if ((wm5100
->sysclk
% rate
) == 0) {
135 /* Is this rate already in use? */
137 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_regs
); i
++) {
138 if (!wm5100
->sr_ref
[i
] && sr_free
== -1) {
142 if ((snd_soc_read(codec
, wm5100_sr_regs
[i
]) &
143 WM5100_SAMPLE_RATE_1_MASK
) == sr_code
)
147 if (i
< ARRAY_SIZE(wm5100_sr_regs
)) {
149 dev_dbg(codec
->dev
, "SR %dHz, slot %d, ref %d\n",
150 rate
, i
, wm5100
->sr_ref
[i
]);
155 dev_err(codec
->dev
, "All SR slots already in use\n");
159 dev_dbg(codec
->dev
, "Allocating SR slot %d for %dHz\n",
161 wm5100
->sr_ref
[sr_free
]++;
162 snd_soc_update_bits(codec
, wm5100_sr_regs
[sr_free
],
163 WM5100_SAMPLE_RATE_1_MASK
,
170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171 rate
, wm5100
->sysclk
, wm5100
->asyncclk
);
176 static void wm5100_free_sr(struct snd_soc_codec
*codec
, int rate
)
178 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
181 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
182 if (wm5100_sr_code
[i
] == rate
)
184 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
185 dev_err(codec
->dev
, "Unsupported sample rate: %dHz\n", rate
);
188 sr_code
= wm5100_sr_code
[i
];
190 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_regs
); i
++) {
191 if (!wm5100
->sr_ref
[i
])
194 if ((snd_soc_read(codec
, wm5100_sr_regs
[i
]) &
195 WM5100_SAMPLE_RATE_1_MASK
) == sr_code
)
198 if (i
< ARRAY_SIZE(wm5100_sr_regs
)) {
200 dev_dbg(codec
->dev
, "Dereference SR %dHz, count now %d\n",
201 rate
, wm5100
->sr_ref
[i
]);
203 dev_warn(codec
->dev
, "Freeing unreferenced sample rate %dHz\n",
208 static int wm5100_reset(struct wm5100_priv
*wm5100
)
210 if (wm5100
->pdata
.reset
) {
211 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 0);
212 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 1);
216 return regmap_write(wm5100
->regmap
, WM5100_SOFTWARE_RESET
, 0);
220 static DECLARE_TLV_DB_SCALE(in_tlv
, -6300, 100, 0);
221 static DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
222 static DECLARE_TLV_DB_SCALE(mixer_tlv
, -3200, 100, 0);
223 static DECLARE_TLV_DB_SCALE(out_tlv
, -6400, 100, 0);
224 static DECLARE_TLV_DB_SCALE(digital_tlv
, -6400, 50, 0);
226 static const char *wm5100_mixer_texts
[] = {
301 static int wm5100_mixer_values
[] = {
324 0x30, /* AIF3 - check */
359 0xa0, /* ISRC1DEC1 */
363 0xa4, /* ISRC1INT1 */
367 0xa8, /* ISRC2DEC1 */
371 0xac, /* ISRC2INT1 */
377 #define WM5100_MIXER_CONTROLS(name, base) \
378 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
387 #define WM5100_MUX_ENUM_DECL(name, reg) \
388 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
389 wm5100_mixer_texts, wm5100_mixer_values)
391 #define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \
393 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
395 #define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
397 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
398 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
399 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
400 static WM5100_MUX_CTL_DECL(name##_in1); \
401 static WM5100_MUX_CTL_DECL(name##_in2); \
402 static WM5100_MUX_CTL_DECL(name##_in3); \
403 static WM5100_MUX_CTL_DECL(name##_in4)
405 WM5100_MIXER_ENUMS(HPOUT1L
, WM5100_OUT1LMIX_INPUT_1_SOURCE
);
406 WM5100_MIXER_ENUMS(HPOUT1R
, WM5100_OUT1RMIX_INPUT_1_SOURCE
);
407 WM5100_MIXER_ENUMS(HPOUT2L
, WM5100_OUT2LMIX_INPUT_1_SOURCE
);
408 WM5100_MIXER_ENUMS(HPOUT2R
, WM5100_OUT2RMIX_INPUT_1_SOURCE
);
409 WM5100_MIXER_ENUMS(HPOUT3L
, WM5100_OUT3LMIX_INPUT_1_SOURCE
);
410 WM5100_MIXER_ENUMS(HPOUT3R
, WM5100_OUT3RMIX_INPUT_1_SOURCE
);
412 WM5100_MIXER_ENUMS(SPKOUTL
, WM5100_OUT4LMIX_INPUT_1_SOURCE
);
413 WM5100_MIXER_ENUMS(SPKOUTR
, WM5100_OUT4RMIX_INPUT_1_SOURCE
);
414 WM5100_MIXER_ENUMS(SPKDAT1L
, WM5100_OUT5LMIX_INPUT_1_SOURCE
);
415 WM5100_MIXER_ENUMS(SPKDAT1R
, WM5100_OUT5RMIX_INPUT_1_SOURCE
);
416 WM5100_MIXER_ENUMS(SPKDAT2L
, WM5100_OUT6LMIX_INPUT_1_SOURCE
);
417 WM5100_MIXER_ENUMS(SPKDAT2R
, WM5100_OUT6RMIX_INPUT_1_SOURCE
);
419 WM5100_MIXER_ENUMS(PWM1
, WM5100_PWM1MIX_INPUT_1_SOURCE
);
420 WM5100_MIXER_ENUMS(PWM2
, WM5100_PWM1MIX_INPUT_1_SOURCE
);
422 WM5100_MIXER_ENUMS(AIF1TX1
, WM5100_AIF1TX1MIX_INPUT_1_SOURCE
);
423 WM5100_MIXER_ENUMS(AIF1TX2
, WM5100_AIF1TX2MIX_INPUT_1_SOURCE
);
424 WM5100_MIXER_ENUMS(AIF1TX3
, WM5100_AIF1TX3MIX_INPUT_1_SOURCE
);
425 WM5100_MIXER_ENUMS(AIF1TX4
, WM5100_AIF1TX4MIX_INPUT_1_SOURCE
);
426 WM5100_MIXER_ENUMS(AIF1TX5
, WM5100_AIF1TX5MIX_INPUT_1_SOURCE
);
427 WM5100_MIXER_ENUMS(AIF1TX6
, WM5100_AIF1TX6MIX_INPUT_1_SOURCE
);
428 WM5100_MIXER_ENUMS(AIF1TX7
, WM5100_AIF1TX7MIX_INPUT_1_SOURCE
);
429 WM5100_MIXER_ENUMS(AIF1TX8
, WM5100_AIF1TX8MIX_INPUT_1_SOURCE
);
431 WM5100_MIXER_ENUMS(AIF2TX1
, WM5100_AIF2TX1MIX_INPUT_1_SOURCE
);
432 WM5100_MIXER_ENUMS(AIF2TX2
, WM5100_AIF2TX2MIX_INPUT_1_SOURCE
);
434 WM5100_MIXER_ENUMS(AIF3TX1
, WM5100_AIF1TX1MIX_INPUT_1_SOURCE
);
435 WM5100_MIXER_ENUMS(AIF3TX2
, WM5100_AIF1TX2MIX_INPUT_1_SOURCE
);
437 WM5100_MIXER_ENUMS(EQ1
, WM5100_EQ1MIX_INPUT_1_SOURCE
);
438 WM5100_MIXER_ENUMS(EQ2
, WM5100_EQ2MIX_INPUT_1_SOURCE
);
439 WM5100_MIXER_ENUMS(EQ3
, WM5100_EQ3MIX_INPUT_1_SOURCE
);
440 WM5100_MIXER_ENUMS(EQ4
, WM5100_EQ4MIX_INPUT_1_SOURCE
);
442 WM5100_MIXER_ENUMS(DRC1L
, WM5100_DRC1LMIX_INPUT_1_SOURCE
);
443 WM5100_MIXER_ENUMS(DRC1R
, WM5100_DRC1RMIX_INPUT_1_SOURCE
);
445 WM5100_MIXER_ENUMS(LHPF1
, WM5100_HPLP1MIX_INPUT_1_SOURCE
);
446 WM5100_MIXER_ENUMS(LHPF2
, WM5100_HPLP2MIX_INPUT_1_SOURCE
);
447 WM5100_MIXER_ENUMS(LHPF3
, WM5100_HPLP3MIX_INPUT_1_SOURCE
);
448 WM5100_MIXER_ENUMS(LHPF4
, WM5100_HPLP4MIX_INPUT_1_SOURCE
);
450 #define WM5100_MUX(name, ctrl) \
451 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
453 #define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
460 #define WM5100_MIXER_INPUT_ROUTES(name) \
461 { name, "Tone Generator 1", "Tone Generator 1" }, \
462 { name, "Tone Generator 2", "Tone Generator 2" }, \
463 { name, "IN1L", "IN1L PGA" }, \
464 { name, "IN1R", "IN1R PGA" }, \
465 { name, "IN2L", "IN2L PGA" }, \
466 { name, "IN2R", "IN2R PGA" }, \
467 { name, "IN3L", "IN3L PGA" }, \
468 { name, "IN3R", "IN3R PGA" }, \
469 { name, "IN4L", "IN4L PGA" }, \
470 { name, "IN4R", "IN4R PGA" }, \
471 { name, "AIF1RX1", "AIF1RX1" }, \
472 { name, "AIF1RX2", "AIF1RX2" }, \
473 { name, "AIF1RX3", "AIF1RX3" }, \
474 { name, "AIF1RX4", "AIF1RX4" }, \
475 { name, "AIF1RX5", "AIF1RX5" }, \
476 { name, "AIF1RX6", "AIF1RX6" }, \
477 { name, "AIF1RX7", "AIF1RX7" }, \
478 { name, "AIF1RX8", "AIF1RX8" }, \
479 { name, "AIF2RX1", "AIF2RX1" }, \
480 { name, "AIF2RX2", "AIF2RX2" }, \
481 { name, "AIF3RX1", "AIF3RX1" }, \
482 { name, "AIF3RX2", "AIF3RX2" }, \
483 { name, "EQ1", "EQ1" }, \
484 { name, "EQ2", "EQ2" }, \
485 { name, "EQ3", "EQ3" }, \
486 { name, "EQ4", "EQ4" }, \
487 { name, "DRC1L", "DRC1L" }, \
488 { name, "DRC1R", "DRC1R" }, \
489 { name, "LHPF1", "LHPF1" }, \
490 { name, "LHPF2", "LHPF2" }, \
491 { name, "LHPF3", "LHPF3" }, \
492 { name, "LHPF4", "LHPF4" }
494 #define WM5100_MIXER_ROUTES(widget, name) \
495 { widget, NULL, name " Mixer" }, \
496 { name " Mixer", NULL, name " Input 1" }, \
497 { name " Mixer", NULL, name " Input 2" }, \
498 { name " Mixer", NULL, name " Input 3" }, \
499 { name " Mixer", NULL, name " Input 4" }, \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
505 static const char *wm5100_lhpf_mode_text
[] = {
506 "Low-pass", "High-pass"
509 static const struct soc_enum wm5100_lhpf1_mode
=
510 SOC_ENUM_SINGLE(WM5100_HPLPF1_1
, WM5100_LHPF1_MODE_SHIFT
, 2,
511 wm5100_lhpf_mode_text
);
513 static const struct soc_enum wm5100_lhpf2_mode
=
514 SOC_ENUM_SINGLE(WM5100_HPLPF2_1
, WM5100_LHPF2_MODE_SHIFT
, 2,
515 wm5100_lhpf_mode_text
);
517 static const struct soc_enum wm5100_lhpf3_mode
=
518 SOC_ENUM_SINGLE(WM5100_HPLPF3_1
, WM5100_LHPF3_MODE_SHIFT
, 2,
519 wm5100_lhpf_mode_text
);
521 static const struct soc_enum wm5100_lhpf4_mode
=
522 SOC_ENUM_SINGLE(WM5100_HPLPF4_1
, WM5100_LHPF4_MODE_SHIFT
, 2,
523 wm5100_lhpf_mode_text
);
525 static const struct snd_kcontrol_new wm5100_snd_controls
[] = {
526 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL
,
527 WM5100_IN1_OSR_SHIFT
, 1, 0),
528 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL
,
529 WM5100_IN2_OSR_SHIFT
, 1, 0),
530 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL
,
531 WM5100_IN3_OSR_SHIFT
, 1, 0),
532 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL
,
533 WM5100_IN4_OSR_SHIFT
, 1, 0),
535 /* Only applicable for analogue inputs */
536 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL
, WM5100_IN1R_CONTROL
,
537 WM5100_IN1L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
538 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL
, WM5100_IN2R_CONTROL
,
539 WM5100_IN2L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
540 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL
, WM5100_IN3R_CONTROL
,
541 WM5100_IN3L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
542 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL
, WM5100_IN4R_CONTROL
,
543 WM5100_IN4L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
545 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L
,
546 WM5100_ADC_DIGITAL_VOLUME_1R
, WM5100_IN1L_VOL_SHIFT
, 191,
548 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L
,
549 WM5100_ADC_DIGITAL_VOLUME_2R
, WM5100_IN2L_VOL_SHIFT
, 191,
551 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L
,
552 WM5100_ADC_DIGITAL_VOLUME_3R
, WM5100_IN3L_VOL_SHIFT
, 191,
554 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L
,
555 WM5100_ADC_DIGITAL_VOLUME_4R
, WM5100_IN4L_VOL_SHIFT
, 191,
558 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L
,
559 WM5100_ADC_DIGITAL_VOLUME_1R
, WM5100_IN1L_MUTE_SHIFT
, 1, 1),
560 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L
,
561 WM5100_ADC_DIGITAL_VOLUME_2R
, WM5100_IN2L_MUTE_SHIFT
, 1, 1),
562 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L
,
563 WM5100_ADC_DIGITAL_VOLUME_3R
, WM5100_IN3L_MUTE_SHIFT
, 1, 1),
564 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L
,
565 WM5100_ADC_DIGITAL_VOLUME_4R
, WM5100_IN4L_MUTE_SHIFT
, 1, 1),
567 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L
,
568 WM5100_OUT1_OSR_SHIFT
, 1, 0),
569 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L
,
570 WM5100_OUT2_OSR_SHIFT
, 1, 0),
571 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L
,
572 WM5100_OUT3_OSR_SHIFT
, 1, 0),
573 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L
,
574 WM5100_OUT4_OSR_SHIFT
, 1, 0),
575 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L
,
576 WM5100_OUT5_OSR_SHIFT
, 1, 0),
577 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L
,
578 WM5100_OUT6_OSR_SHIFT
, 1, 0),
580 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L
,
581 WM5100_DAC_DIGITAL_VOLUME_1R
, WM5100_OUT1L_VOL_SHIFT
, 159, 0,
583 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L
,
584 WM5100_DAC_DIGITAL_VOLUME_2R
, WM5100_OUT2L_VOL_SHIFT
, 159, 0,
586 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L
,
587 WM5100_DAC_DIGITAL_VOLUME_3R
, WM5100_OUT3L_VOL_SHIFT
, 159, 0,
589 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L
,
590 WM5100_DAC_DIGITAL_VOLUME_4R
, WM5100_OUT4L_VOL_SHIFT
, 159, 0,
592 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L
,
593 WM5100_DAC_DIGITAL_VOLUME_5R
, WM5100_OUT5L_VOL_SHIFT
, 159, 0,
595 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L
,
596 WM5100_DAC_DIGITAL_VOLUME_6R
, WM5100_OUT6L_VOL_SHIFT
, 159, 0,
599 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L
,
600 WM5100_DAC_DIGITAL_VOLUME_1R
, WM5100_OUT1L_MUTE_SHIFT
, 1, 1),
601 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L
,
602 WM5100_DAC_DIGITAL_VOLUME_2R
, WM5100_OUT2L_MUTE_SHIFT
, 1, 1),
603 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L
,
604 WM5100_DAC_DIGITAL_VOLUME_3R
, WM5100_OUT3L_MUTE_SHIFT
, 1, 1),
605 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L
,
606 WM5100_DAC_DIGITAL_VOLUME_4R
, WM5100_OUT4L_MUTE_SHIFT
, 1, 1),
607 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L
,
608 WM5100_DAC_DIGITAL_VOLUME_5R
, WM5100_OUT5L_MUTE_SHIFT
, 1, 1),
609 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L
,
610 WM5100_DAC_DIGITAL_VOLUME_6R
, WM5100_OUT6L_MUTE_SHIFT
, 1, 1),
612 /* FIXME: Only valid from -12dB to 0dB (52-64) */
613 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L
, WM5100_OUT_VOLUME_1R
,
614 WM5100_OUT1L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
615 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L
, WM5100_OUT_VOLUME_2R
,
616 WM5100_OUT2L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
617 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L
, WM5100_OUT_VOLUME_3R
,
618 WM5100_OUT2L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
620 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1
, WM5100_SPK1L_MUTE_SHIFT
,
621 WM5100_SPK1R_MUTE_SHIFT
, 1, 1),
622 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1
, WM5100_SPK2L_MUTE_SHIFT
,
623 WM5100_SPK2R_MUTE_SHIFT
, 1, 1),
625 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1
, WM5100_EQ1_B1_GAIN_SHIFT
,
627 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1
, WM5100_EQ1_B2_GAIN_SHIFT
,
629 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1
, WM5100_EQ1_B3_GAIN_SHIFT
,
631 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2
, WM5100_EQ1_B4_GAIN_SHIFT
,
633 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2
, WM5100_EQ1_B5_GAIN_SHIFT
,
636 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1
, WM5100_EQ2_B1_GAIN_SHIFT
,
638 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1
, WM5100_EQ2_B2_GAIN_SHIFT
,
640 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1
, WM5100_EQ2_B3_GAIN_SHIFT
,
642 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2
, WM5100_EQ2_B4_GAIN_SHIFT
,
644 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2
, WM5100_EQ2_B5_GAIN_SHIFT
,
647 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1
, WM5100_EQ3_B1_GAIN_SHIFT
,
649 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1
, WM5100_EQ3_B2_GAIN_SHIFT
,
651 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1
, WM5100_EQ3_B3_GAIN_SHIFT
,
653 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2
, WM5100_EQ3_B4_GAIN_SHIFT
,
655 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2
, WM5100_EQ3_B5_GAIN_SHIFT
,
658 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1
, WM5100_EQ4_B1_GAIN_SHIFT
,
660 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1
, WM5100_EQ4_B2_GAIN_SHIFT
,
662 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1
, WM5100_EQ4_B3_GAIN_SHIFT
,
664 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2
, WM5100_EQ4_B4_GAIN_SHIFT
,
666 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2
, WM5100_EQ4_B5_GAIN_SHIFT
,
669 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode
),
670 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode
),
671 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode
),
672 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode
),
674 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE
),
675 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE
),
676 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE
),
677 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE
),
678 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE
),
679 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE
),
681 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE
),
682 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE
),
683 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE
),
684 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE
),
685 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE
),
686 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE
),
688 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE
),
689 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE
),
691 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE
),
692 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE
),
693 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE
),
694 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE
),
695 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE
),
696 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE
),
697 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE
),
698 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE
),
700 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE
),
701 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE
),
703 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE
),
704 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE
),
706 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE
),
707 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE
),
708 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE
),
709 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE
),
711 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE
),
712 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE
),
714 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE
),
715 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE
),
716 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE
),
717 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE
),
720 static void wm5100_seq_notifier(struct snd_soc_dapm_context
*dapm
,
721 enum snd_soc_dapm_type event
, int subseq
)
723 struct snd_soc_codec
*codec
= container_of(dapm
,
724 struct snd_soc_codec
, dapm
);
725 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
728 /* Wait for the outputs to flag themselves as enabled */
729 if (wm5100
->out_ena
[0]) {
730 expect
= snd_soc_read(codec
, WM5100_CHANNEL_ENABLES_1
);
731 for (i
= 0; i
< 200; i
++) {
732 val
= snd_soc_read(codec
, WM5100_OUTPUT_STATUS_1
);
734 wm5100
->out_ena
[0] = false;
739 dev_err(codec
->dev
, "Timeout waiting for OUTPUT1 %x\n",
744 if (wm5100
->out_ena
[1]) {
745 expect
= snd_soc_read(codec
, WM5100_OUTPUT_ENABLES_2
);
746 for (i
= 0; i
< 200; i
++) {
747 val
= snd_soc_read(codec
, WM5100_OUTPUT_STATUS_2
);
749 wm5100
->out_ena
[1] = false;
754 dev_err(codec
->dev
, "Timeout waiting for OUTPUT2 %x\n",
760 static int wm5100_out_ev(struct snd_soc_dapm_widget
*w
,
761 struct snd_kcontrol
*kcontrol
,
764 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(w
->codec
);
767 case WM5100_CHANNEL_ENABLES_1
:
768 wm5100
->out_ena
[0] = true;
770 case WM5100_OUTPUT_ENABLES_2
:
771 wm5100
->out_ena
[0] = true;
780 static int wm5100_cp_ev(struct snd_soc_dapm_widget
*w
,
781 struct snd_kcontrol
*kcontrol
,
784 struct snd_soc_codec
*codec
= w
->codec
;
785 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
789 case SND_SOC_DAPM_PRE_PMU
:
790 ret
= regulator_enable(wm5100
->cpvdd
);
792 dev_err(codec
->dev
, "Failed to enable CPVDD: %d\n",
798 case SND_SOC_DAPM_POST_PMD
:
799 ret
= regulator_disable_deferred(wm5100
->cpvdd
, 20);
801 dev_err(codec
->dev
, "Failed to disable CPVDD: %d\n",
813 static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget
*w
,
814 struct snd_kcontrol
*kcontrol
,
817 struct snd_soc_codec
*codec
= w
->codec
;
818 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
819 struct regulator
*regulator
;
824 regulator
= wm5100
->dbvdd2
;
827 regulator
= wm5100
->dbvdd3
;
835 case SND_SOC_DAPM_PRE_PMU
:
836 ret
= regulator_enable(regulator
);
838 dev_err(codec
->dev
, "Failed to enable DBVDD%d: %d\n",
844 case SND_SOC_DAPM_POST_PMD
:
845 ret
= regulator_disable(regulator
);
847 dev_err(codec
->dev
, "Failed to enable DBVDD%d: %d\n",
859 static void wm5100_log_status3(struct snd_soc_codec
*codec
, int val
)
861 if (val
& WM5100_SPK_SHUTDOWN_WARN_EINT
)
862 dev_crit(codec
->dev
, "Speaker shutdown warning\n");
863 if (val
& WM5100_SPK_SHUTDOWN_EINT
)
864 dev_crit(codec
->dev
, "Speaker shutdown\n");
865 if (val
& WM5100_CLKGEN_ERR_EINT
)
866 dev_crit(codec
->dev
, "SYSCLK underclocked\n");
867 if (val
& WM5100_CLKGEN_ERR_ASYNC_EINT
)
868 dev_crit(codec
->dev
, "ASYNCCLK underclocked\n");
871 static void wm5100_log_status4(struct snd_soc_codec
*codec
, int val
)
873 if (val
& WM5100_AIF3_ERR_EINT
)
874 dev_err(codec
->dev
, "AIF3 configuration error\n");
875 if (val
& WM5100_AIF2_ERR_EINT
)
876 dev_err(codec
->dev
, "AIF2 configuration error\n");
877 if (val
& WM5100_AIF1_ERR_EINT
)
878 dev_err(codec
->dev
, "AIF1 configuration error\n");
879 if (val
& WM5100_CTRLIF_ERR_EINT
)
880 dev_err(codec
->dev
, "Control interface error\n");
881 if (val
& WM5100_ISRC2_UNDERCLOCKED_EINT
)
882 dev_err(codec
->dev
, "ISRC2 underclocked\n");
883 if (val
& WM5100_ISRC1_UNDERCLOCKED_EINT
)
884 dev_err(codec
->dev
, "ISRC1 underclocked\n");
885 if (val
& WM5100_FX_UNDERCLOCKED_EINT
)
886 dev_err(codec
->dev
, "FX underclocked\n");
887 if (val
& WM5100_AIF3_UNDERCLOCKED_EINT
)
888 dev_err(codec
->dev
, "AIF3 underclocked\n");
889 if (val
& WM5100_AIF2_UNDERCLOCKED_EINT
)
890 dev_err(codec
->dev
, "AIF2 underclocked\n");
891 if (val
& WM5100_AIF1_UNDERCLOCKED_EINT
)
892 dev_err(codec
->dev
, "AIF1 underclocked\n");
893 if (val
& WM5100_ASRC_UNDERCLOCKED_EINT
)
894 dev_err(codec
->dev
, "ASRC underclocked\n");
895 if (val
& WM5100_DAC_UNDERCLOCKED_EINT
)
896 dev_err(codec
->dev
, "DAC underclocked\n");
897 if (val
& WM5100_ADC_UNDERCLOCKED_EINT
)
898 dev_err(codec
->dev
, "ADC underclocked\n");
899 if (val
& WM5100_MIXER_UNDERCLOCKED_EINT
)
900 dev_err(codec
->dev
, "Mixer underclocked\n");
903 static int wm5100_post_ev(struct snd_soc_dapm_widget
*w
,
904 struct snd_kcontrol
*kcontrol
,
907 struct snd_soc_codec
*codec
= w
->codec
;
910 ret
= snd_soc_read(codec
, WM5100_INTERRUPT_RAW_STATUS_3
);
911 ret
&= WM5100_SPK_SHUTDOWN_WARN_STS
|
912 WM5100_SPK_SHUTDOWN_STS
| WM5100_CLKGEN_ERR_STS
|
913 WM5100_CLKGEN_ERR_ASYNC_STS
;
914 wm5100_log_status3(codec
, ret
);
916 ret
= snd_soc_read(codec
, WM5100_INTERRUPT_RAW_STATUS_4
);
917 wm5100_log_status4(codec
, ret
);
922 static const struct snd_soc_dapm_widget wm5100_dapm_widgets
[] = {
923 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3
, WM5100_SYSCLK_ENA_SHIFT
, 0,
925 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6
, WM5100_ASYNC_CLK_ENA_SHIFT
,
928 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1
, WM5100_CP1_ENA_SHIFT
, 0,
930 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
931 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1
, WM5100_CP2_ENA_SHIFT
, 0,
933 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1
,
934 WM5100_CP2_BYPASS_SHIFT
, 1, wm5100_cp_ev
,
935 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
936 SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM
, 2, 0, wm5100_dbvdd_ev
,
937 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
938 SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM
, 3, 0, wm5100_dbvdd_ev
,
939 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
941 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1
, WM5100_MICB1_ENA_SHIFT
,
943 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2
, WM5100_MICB2_ENA_SHIFT
,
945 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3
, WM5100_MICB3_ENA_SHIFT
,
948 SND_SOC_DAPM_INPUT("IN1L"),
949 SND_SOC_DAPM_INPUT("IN1R"),
950 SND_SOC_DAPM_INPUT("IN2L"),
951 SND_SOC_DAPM_INPUT("IN2R"),
952 SND_SOC_DAPM_INPUT("IN3L"),
953 SND_SOC_DAPM_INPUT("IN3R"),
954 SND_SOC_DAPM_INPUT("IN4L"),
955 SND_SOC_DAPM_INPUT("IN4R"),
956 SND_SOC_DAPM_INPUT("TONE"),
958 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES
, WM5100_IN1L_ENA_SHIFT
, 0,
959 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
960 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES
, WM5100_IN1R_ENA_SHIFT
, 0,
961 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
962 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES
, WM5100_IN2L_ENA_SHIFT
, 0,
963 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
964 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES
, WM5100_IN2R_ENA_SHIFT
, 0,
965 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
966 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES
, WM5100_IN3L_ENA_SHIFT
, 0,
967 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
968 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES
, WM5100_IN3R_ENA_SHIFT
, 0,
969 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
970 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES
, WM5100_IN4L_ENA_SHIFT
, 0,
971 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
972 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES
, WM5100_IN4R_ENA_SHIFT
, 0,
973 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
975 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1
,
976 WM5100_TONE1_ENA_SHIFT
, 0, NULL
, 0),
977 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1
,
978 WM5100_TONE2_ENA_SHIFT
, 0, NULL
, 0),
980 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
981 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX1_ENA_SHIFT
, 0),
982 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
983 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX2_ENA_SHIFT
, 0),
984 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
985 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX3_ENA_SHIFT
, 0),
986 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
987 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX4_ENA_SHIFT
, 0),
988 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
989 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX5_ENA_SHIFT
, 0),
990 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
991 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX6_ENA_SHIFT
, 0),
992 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
993 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX7_ENA_SHIFT
, 0),
994 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
995 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX8_ENA_SHIFT
, 0),
997 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
998 WM5100_AUDIO_IF_2_27
, WM5100_AIF2RX1_ENA_SHIFT
, 0),
999 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1000 WM5100_AUDIO_IF_2_27
, WM5100_AIF2RX2_ENA_SHIFT
, 0),
1002 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1003 WM5100_AUDIO_IF_3_27
, WM5100_AIF3RX1_ENA_SHIFT
, 0),
1004 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1005 WM5100_AUDIO_IF_3_27
, WM5100_AIF3RX2_ENA_SHIFT
, 0),
1007 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1008 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX1_ENA_SHIFT
, 0),
1009 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1010 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX2_ENA_SHIFT
, 0),
1011 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1012 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX3_ENA_SHIFT
, 0),
1013 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1014 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX4_ENA_SHIFT
, 0),
1015 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1016 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX5_ENA_SHIFT
, 0),
1017 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1018 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX6_ENA_SHIFT
, 0),
1019 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1020 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX7_ENA_SHIFT
, 0),
1021 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1022 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX8_ENA_SHIFT
, 0),
1024 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1025 WM5100_AUDIO_IF_2_26
, WM5100_AIF2TX1_ENA_SHIFT
, 0),
1026 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1027 WM5100_AUDIO_IF_2_26
, WM5100_AIF2TX2_ENA_SHIFT
, 0),
1029 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1030 WM5100_AUDIO_IF_3_26
, WM5100_AIF3TX1_ENA_SHIFT
, 0),
1031 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1032 WM5100_AUDIO_IF_3_26
, WM5100_AIF3TX2_ENA_SHIFT
, 0),
1034 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT6L_ENA_SHIFT
, 0,
1035 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1036 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT6R_ENA_SHIFT
, 0,
1037 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1038 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT5L_ENA_SHIFT
, 0,
1039 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1040 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT5R_ENA_SHIFT
, 0,
1041 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1042 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT4L_ENA_SHIFT
, 0,
1043 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1044 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT4R_ENA_SHIFT
, 0,
1045 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1046 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP3L_ENA_SHIFT
, 0,
1047 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1048 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP3R_ENA_SHIFT
, 0,
1049 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1050 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP2L_ENA_SHIFT
, 0,
1051 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1052 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP2R_ENA_SHIFT
, 0,
1053 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1054 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP1L_ENA_SHIFT
, 0,
1055 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1056 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP1R_ENA_SHIFT
, 0,
1057 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1058 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1
, WM5100_PWM1_ENA_SHIFT
, 0,
1059 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1060 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1
, WM5100_PWM2_ENA_SHIFT
, 0,
1061 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1063 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1
, WM5100_EQ1_ENA_SHIFT
, 0, NULL
, 0),
1064 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1
, WM5100_EQ2_ENA_SHIFT
, 0, NULL
, 0),
1065 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1
, WM5100_EQ3_ENA_SHIFT
, 0, NULL
, 0),
1066 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1
, WM5100_EQ4_ENA_SHIFT
, 0, NULL
, 0),
1068 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1
, WM5100_DRCL_ENA_SHIFT
, 0,
1070 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1
, WM5100_DRCR_ENA_SHIFT
, 0,
1073 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1
, WM5100_LHPF1_ENA_SHIFT
, 0,
1075 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1
, WM5100_LHPF2_ENA_SHIFT
, 0,
1077 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1
, WM5100_LHPF3_ENA_SHIFT
, 0,
1079 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1
, WM5100_LHPF4_ENA_SHIFT
, 0,
1082 WM5100_MIXER_WIDGETS(EQ1
, "EQ1"),
1083 WM5100_MIXER_WIDGETS(EQ2
, "EQ2"),
1084 WM5100_MIXER_WIDGETS(EQ3
, "EQ3"),
1085 WM5100_MIXER_WIDGETS(EQ4
, "EQ4"),
1087 WM5100_MIXER_WIDGETS(DRC1L
, "DRC1L"),
1088 WM5100_MIXER_WIDGETS(DRC1R
, "DRC1R"),
1090 WM5100_MIXER_WIDGETS(LHPF1
, "LHPF1"),
1091 WM5100_MIXER_WIDGETS(LHPF2
, "LHPF2"),
1092 WM5100_MIXER_WIDGETS(LHPF3
, "LHPF3"),
1093 WM5100_MIXER_WIDGETS(LHPF4
, "LHPF4"),
1095 WM5100_MIXER_WIDGETS(AIF1TX1
, "AIF1TX1"),
1096 WM5100_MIXER_WIDGETS(AIF1TX2
, "AIF1TX2"),
1097 WM5100_MIXER_WIDGETS(AIF1TX3
, "AIF1TX3"),
1098 WM5100_MIXER_WIDGETS(AIF1TX4
, "AIF1TX4"),
1099 WM5100_MIXER_WIDGETS(AIF1TX5
, "AIF1TX5"),
1100 WM5100_MIXER_WIDGETS(AIF1TX6
, "AIF1TX6"),
1101 WM5100_MIXER_WIDGETS(AIF1TX7
, "AIF1TX7"),
1102 WM5100_MIXER_WIDGETS(AIF1TX8
, "AIF1TX8"),
1104 WM5100_MIXER_WIDGETS(AIF2TX1
, "AIF2TX1"),
1105 WM5100_MIXER_WIDGETS(AIF2TX2
, "AIF2TX2"),
1107 WM5100_MIXER_WIDGETS(AIF3TX1
, "AIF3TX1"),
1108 WM5100_MIXER_WIDGETS(AIF3TX2
, "AIF3TX2"),
1110 WM5100_MIXER_WIDGETS(HPOUT1L
, "HPOUT1L"),
1111 WM5100_MIXER_WIDGETS(HPOUT1R
, "HPOUT1R"),
1112 WM5100_MIXER_WIDGETS(HPOUT2L
, "HPOUT2L"),
1113 WM5100_MIXER_WIDGETS(HPOUT2R
, "HPOUT2R"),
1114 WM5100_MIXER_WIDGETS(HPOUT3L
, "HPOUT3L"),
1115 WM5100_MIXER_WIDGETS(HPOUT3R
, "HPOUT3R"),
1117 WM5100_MIXER_WIDGETS(SPKOUTL
, "SPKOUTL"),
1118 WM5100_MIXER_WIDGETS(SPKOUTR
, "SPKOUTR"),
1119 WM5100_MIXER_WIDGETS(SPKDAT1L
, "SPKDAT1L"),
1120 WM5100_MIXER_WIDGETS(SPKDAT1R
, "SPKDAT1R"),
1121 WM5100_MIXER_WIDGETS(SPKDAT2L
, "SPKDAT2L"),
1122 WM5100_MIXER_WIDGETS(SPKDAT2R
, "SPKDAT2R"),
1124 WM5100_MIXER_WIDGETS(PWM1
, "PWM1"),
1125 WM5100_MIXER_WIDGETS(PWM2
, "PWM2"),
1127 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1128 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1129 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1130 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1131 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1132 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1133 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1134 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1135 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1136 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1137 SND_SOC_DAPM_OUTPUT("PWM1"),
1138 SND_SOC_DAPM_OUTPUT("PWM2"),
1141 /* We register a _POST event if we don't have IRQ support so we can
1142 * look at the error status from the CODEC - if we've got the IRQ
1143 * hooked up then we will get prompted to look by an interrupt.
1145 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq
[] = {
1146 SND_SOC_DAPM_POST("Post", wm5100_post_ev
),
1149 static const struct snd_soc_dapm_route wm5100_dapm_routes
[] = {
1150 { "IN1L", NULL
, "SYSCLK" },
1151 { "IN1R", NULL
, "SYSCLK" },
1152 { "IN2L", NULL
, "SYSCLK" },
1153 { "IN2R", NULL
, "SYSCLK" },
1154 { "IN3L", NULL
, "SYSCLK" },
1155 { "IN3R", NULL
, "SYSCLK" },
1156 { "IN4L", NULL
, "SYSCLK" },
1157 { "IN4R", NULL
, "SYSCLK" },
1159 { "OUT1L", NULL
, "SYSCLK" },
1160 { "OUT1R", NULL
, "SYSCLK" },
1161 { "OUT2L", NULL
, "SYSCLK" },
1162 { "OUT2R", NULL
, "SYSCLK" },
1163 { "OUT3L", NULL
, "SYSCLK" },
1164 { "OUT3R", NULL
, "SYSCLK" },
1165 { "OUT4L", NULL
, "SYSCLK" },
1166 { "OUT4R", NULL
, "SYSCLK" },
1167 { "OUT5L", NULL
, "SYSCLK" },
1168 { "OUT5R", NULL
, "SYSCLK" },
1169 { "OUT6L", NULL
, "SYSCLK" },
1170 { "OUT6R", NULL
, "SYSCLK" },
1172 { "AIF1RX1", NULL
, "SYSCLK" },
1173 { "AIF1RX2", NULL
, "SYSCLK" },
1174 { "AIF1RX3", NULL
, "SYSCLK" },
1175 { "AIF1RX4", NULL
, "SYSCLK" },
1176 { "AIF1RX5", NULL
, "SYSCLK" },
1177 { "AIF1RX6", NULL
, "SYSCLK" },
1178 { "AIF1RX7", NULL
, "SYSCLK" },
1179 { "AIF1RX8", NULL
, "SYSCLK" },
1181 { "AIF2RX1", NULL
, "SYSCLK" },
1182 { "AIF2RX1", NULL
, "DBVDD2" },
1183 { "AIF2RX2", NULL
, "SYSCLK" },
1184 { "AIF2RX2", NULL
, "DBVDD2" },
1186 { "AIF3RX1", NULL
, "SYSCLK" },
1187 { "AIF3RX1", NULL
, "DBVDD3" },
1188 { "AIF3RX2", NULL
, "SYSCLK" },
1189 { "AIF3RX2", NULL
, "DBVDD3" },
1191 { "AIF1TX1", NULL
, "SYSCLK" },
1192 { "AIF1TX2", NULL
, "SYSCLK" },
1193 { "AIF1TX3", NULL
, "SYSCLK" },
1194 { "AIF1TX4", NULL
, "SYSCLK" },
1195 { "AIF1TX5", NULL
, "SYSCLK" },
1196 { "AIF1TX6", NULL
, "SYSCLK" },
1197 { "AIF1TX7", NULL
, "SYSCLK" },
1198 { "AIF1TX8", NULL
, "SYSCLK" },
1200 { "AIF2TX1", NULL
, "SYSCLK" },
1201 { "AIF2TX1", NULL
, "DBVDD2" },
1202 { "AIF2TX2", NULL
, "SYSCLK" },
1203 { "AIF2TX2", NULL
, "DBVDD2" },
1205 { "AIF3TX1", NULL
, "SYSCLK" },
1206 { "AIF3TX1", NULL
, "DBVDD3" },
1207 { "AIF3TX2", NULL
, "SYSCLK" },
1208 { "AIF3TX2", NULL
, "DBVDD3" },
1210 { "MICBIAS1", NULL
, "CP2" },
1211 { "MICBIAS2", NULL
, "CP2" },
1212 { "MICBIAS3", NULL
, "CP2" },
1214 { "IN1L PGA", NULL
, "CP2" },
1215 { "IN1R PGA", NULL
, "CP2" },
1216 { "IN2L PGA", NULL
, "CP2" },
1217 { "IN2R PGA", NULL
, "CP2" },
1218 { "IN3L PGA", NULL
, "CP2" },
1219 { "IN3R PGA", NULL
, "CP2" },
1220 { "IN4L PGA", NULL
, "CP2" },
1221 { "IN4R PGA", NULL
, "CP2" },
1223 { "IN1L PGA", NULL
, "CP2 Active" },
1224 { "IN1R PGA", NULL
, "CP2 Active" },
1225 { "IN2L PGA", NULL
, "CP2 Active" },
1226 { "IN2R PGA", NULL
, "CP2 Active" },
1227 { "IN3L PGA", NULL
, "CP2 Active" },
1228 { "IN3R PGA", NULL
, "CP2 Active" },
1229 { "IN4L PGA", NULL
, "CP2 Active" },
1230 { "IN4R PGA", NULL
, "CP2 Active" },
1232 { "OUT1L", NULL
, "CP1" },
1233 { "OUT1R", NULL
, "CP1" },
1234 { "OUT2L", NULL
, "CP1" },
1235 { "OUT2R", NULL
, "CP1" },
1236 { "OUT3L", NULL
, "CP1" },
1237 { "OUT3R", NULL
, "CP1" },
1239 { "Tone Generator 1", NULL
, "TONE" },
1240 { "Tone Generator 2", NULL
, "TONE" },
1242 { "IN1L PGA", NULL
, "IN1L" },
1243 { "IN1R PGA", NULL
, "IN1R" },
1244 { "IN2L PGA", NULL
, "IN2L" },
1245 { "IN2R PGA", NULL
, "IN2R" },
1246 { "IN3L PGA", NULL
, "IN3L" },
1247 { "IN3R PGA", NULL
, "IN3R" },
1248 { "IN4L PGA", NULL
, "IN4L" },
1249 { "IN4R PGA", NULL
, "IN4R" },
1251 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1252 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1253 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1254 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1255 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1256 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1258 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1259 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1260 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1261 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1262 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1263 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1265 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1266 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1268 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1269 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1270 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1271 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1272 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1273 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1274 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1275 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1277 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1278 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1280 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1281 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1283 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1284 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1285 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1286 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1288 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1289 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1291 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1292 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1293 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1294 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1296 { "HPOUT1L", NULL
, "OUT1L" },
1297 { "HPOUT1R", NULL
, "OUT1R" },
1298 { "HPOUT2L", NULL
, "OUT2L" },
1299 { "HPOUT2R", NULL
, "OUT2R" },
1300 { "HPOUT3L", NULL
, "OUT3L" },
1301 { "HPOUT3R", NULL
, "OUT3R" },
1302 { "SPKOUTL", NULL
, "OUT4L" },
1303 { "SPKOUTR", NULL
, "OUT4R" },
1304 { "SPKDAT1", NULL
, "OUT5L" },
1305 { "SPKDAT1", NULL
, "OUT5R" },
1306 { "SPKDAT2", NULL
, "OUT6L" },
1307 { "SPKDAT2", NULL
, "OUT6R" },
1308 { "PWM1", NULL
, "PWM1 Driver" },
1309 { "PWM2", NULL
, "PWM2 Driver" },
1315 } wm5100_reva_patches
[] = {
1316 { WM5100_AUDIO_IF_1_10
, 0 },
1317 { WM5100_AUDIO_IF_1_11
, 1 },
1318 { WM5100_AUDIO_IF_1_12
, 2 },
1319 { WM5100_AUDIO_IF_1_13
, 3 },
1320 { WM5100_AUDIO_IF_1_14
, 4 },
1321 { WM5100_AUDIO_IF_1_15
, 5 },
1322 { WM5100_AUDIO_IF_1_16
, 6 },
1323 { WM5100_AUDIO_IF_1_17
, 7 },
1325 { WM5100_AUDIO_IF_1_18
, 0 },
1326 { WM5100_AUDIO_IF_1_19
, 1 },
1327 { WM5100_AUDIO_IF_1_20
, 2 },
1328 { WM5100_AUDIO_IF_1_21
, 3 },
1329 { WM5100_AUDIO_IF_1_22
, 4 },
1330 { WM5100_AUDIO_IF_1_23
, 5 },
1331 { WM5100_AUDIO_IF_1_24
, 6 },
1332 { WM5100_AUDIO_IF_1_25
, 7 },
1334 { WM5100_AUDIO_IF_2_10
, 0 },
1335 { WM5100_AUDIO_IF_2_11
, 1 },
1337 { WM5100_AUDIO_IF_2_18
, 0 },
1338 { WM5100_AUDIO_IF_2_19
, 1 },
1340 { WM5100_AUDIO_IF_3_10
, 0 },
1341 { WM5100_AUDIO_IF_3_11
, 1 },
1343 { WM5100_AUDIO_IF_3_18
, 0 },
1344 { WM5100_AUDIO_IF_3_19
, 1 },
1347 static int wm5100_set_bias_level(struct snd_soc_codec
*codec
,
1348 enum snd_soc_bias_level level
)
1350 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1354 case SND_SOC_BIAS_ON
:
1357 case SND_SOC_BIAS_PREPARE
:
1360 case SND_SOC_BIAS_STANDBY
:
1361 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1362 ret
= regulator_bulk_enable(ARRAY_SIZE(wm5100
->core_supplies
),
1363 wm5100
->core_supplies
);
1366 "Failed to enable supplies: %d\n",
1371 if (wm5100
->pdata
.ldo_ena
) {
1372 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
,
1377 regcache_cache_only(wm5100
->regmap
, false);
1379 switch (wm5100
->rev
) {
1381 snd_soc_write(codec
, 0x11, 0x3);
1382 snd_soc_write(codec
, 0x203, 0xc);
1383 snd_soc_write(codec
, 0x206, 0);
1384 snd_soc_write(codec
, 0x207, 0xf0);
1385 snd_soc_write(codec
, 0x208, 0x3c);
1386 snd_soc_write(codec
, 0x209, 0);
1387 snd_soc_write(codec
, 0x211, 0x20d8);
1388 snd_soc_write(codec
, 0x11, 0);
1391 i
< ARRAY_SIZE(wm5100_reva_patches
);
1393 snd_soc_write(codec
,
1394 wm5100_reva_patches
[i
].reg
,
1395 wm5100_reva_patches
[i
].val
);
1401 regcache_sync(wm5100
->regmap
);
1405 case SND_SOC_BIAS_OFF
:
1406 if (wm5100
->pdata
.ldo_ena
)
1407 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
1408 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
1409 wm5100
->core_supplies
);
1412 codec
->dapm
.bias_level
= level
;
1417 static int wm5100_dai_to_base(struct snd_soc_dai
*dai
)
1421 return WM5100_AUDIO_IF_1_1
- 1;
1423 return WM5100_AUDIO_IF_2_1
- 1;
1425 return WM5100_AUDIO_IF_3_1
- 1;
1432 static int wm5100_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1434 struct snd_soc_codec
*codec
= dai
->codec
;
1435 int lrclk
, bclk
, mask
, base
;
1437 base
= wm5100_dai_to_base(dai
);
1444 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1445 case SND_SOC_DAIFMT_DSP_A
:
1448 case SND_SOC_DAIFMT_DSP_B
:
1451 case SND_SOC_DAIFMT_I2S
:
1454 case SND_SOC_DAIFMT_LEFT_J
:
1458 dev_err(codec
->dev
, "Unsupported DAI format %d\n",
1459 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1463 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1464 case SND_SOC_DAIFMT_CBS_CFS
:
1466 case SND_SOC_DAIFMT_CBS_CFM
:
1467 lrclk
|= WM5100_AIF1TX_LRCLK_MSTR
;
1469 case SND_SOC_DAIFMT_CBM_CFS
:
1470 bclk
|= WM5100_AIF1_BCLK_MSTR
;
1472 case SND_SOC_DAIFMT_CBM_CFM
:
1473 lrclk
|= WM5100_AIF1TX_LRCLK_MSTR
;
1474 bclk
|= WM5100_AIF1_BCLK_MSTR
;
1477 dev_err(codec
->dev
, "Unsupported master mode %d\n",
1478 fmt
& SND_SOC_DAIFMT_MASTER_MASK
);
1482 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1483 case SND_SOC_DAIFMT_NB_NF
:
1485 case SND_SOC_DAIFMT_IB_IF
:
1486 bclk
|= WM5100_AIF1_BCLK_INV
;
1487 lrclk
|= WM5100_AIF1TX_LRCLK_INV
;
1489 case SND_SOC_DAIFMT_IB_NF
:
1490 bclk
|= WM5100_AIF1_BCLK_INV
;
1492 case SND_SOC_DAIFMT_NB_IF
:
1493 lrclk
|= WM5100_AIF1TX_LRCLK_INV
;
1499 snd_soc_update_bits(codec
, base
+ 1, WM5100_AIF1_BCLK_MSTR
|
1500 WM5100_AIF1_BCLK_INV
, bclk
);
1501 snd_soc_update_bits(codec
, base
+ 2, WM5100_AIF1TX_LRCLK_MSTR
|
1502 WM5100_AIF1TX_LRCLK_INV
, lrclk
);
1503 snd_soc_update_bits(codec
, base
+ 3, WM5100_AIF1TX_LRCLK_MSTR
|
1504 WM5100_AIF1TX_LRCLK_INV
, lrclk
);
1505 snd_soc_update_bits(codec
, base
+ 5, WM5100_AIF1_FMT_MASK
, mask
);
1510 #define WM5100_NUM_BCLK_RATES 19
1512 static int wm5100_bclk_rates_dat
[WM5100_NUM_BCLK_RATES
] = {
1534 static int wm5100_bclk_rates_cd
[WM5100_NUM_BCLK_RATES
] = {
1556 static int wm5100_hw_params(struct snd_pcm_substream
*substream
,
1557 struct snd_pcm_hw_params
*params
,
1558 struct snd_soc_dai
*dai
)
1560 struct snd_soc_codec
*codec
= dai
->codec
;
1561 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1562 bool async
= wm5100
->aif_async
[dai
->id
];
1563 int i
, base
, bclk
, aif_rate
, lrclk
, wl
, fl
, sr
;
1566 base
= wm5100_dai_to_base(dai
);
1570 /* Data sizes if not using TDM */
1571 wl
= snd_pcm_format_width(params_format(params
));
1574 fl
= snd_soc_params_to_frame_size(params
);
1578 dev_dbg(codec
->dev
, "Word length %d bits, frame length %d bits\n",
1581 /* Target BCLK rate */
1582 bclk
= snd_soc_params_to_bclk(params
);
1586 /* Root for BCLK depends on SYS/ASYNCCLK */
1588 aif_rate
= wm5100
->sysclk
;
1589 sr
= wm5100_alloc_sr(codec
, params_rate(params
));
1593 /* If we're in ASYNCCLK set the ASYNC sample rate */
1594 aif_rate
= wm5100
->asyncclk
;
1597 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
1598 if (params_rate(params
) == wm5100_sr_code
[i
])
1600 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
1601 dev_err(codec
->dev
, "Invalid rate %dHzn",
1602 params_rate(params
));
1606 /* TODO: We should really check for symmetry */
1607 snd_soc_update_bits(codec
, WM5100_CLOCKING_8
,
1608 WM5100_ASYNC_SAMPLE_RATE_MASK
, i
);
1612 dev_err(codec
->dev
, "%s has no rate set\n",
1613 async
? "ASYNCCLK" : "SYSCLK");
1617 dev_dbg(codec
->dev
, "Target BCLK is %dHz, using %dHz %s\n",
1618 bclk
, aif_rate
, async
? "ASYNCCLK" : "SYSCLK");
1620 if (aif_rate
% 4000)
1621 bclk_rates
= wm5100_bclk_rates_cd
;
1623 bclk_rates
= wm5100_bclk_rates_dat
;
1625 for (i
= 0; i
< WM5100_NUM_BCLK_RATES
; i
++)
1626 if (bclk_rates
[i
] >= bclk
&& (bclk_rates
[i
] % bclk
== 0))
1628 if (i
== WM5100_NUM_BCLK_RATES
) {
1630 "No valid BCLK for %dHz found from %dHz %s\n",
1631 bclk
, aif_rate
, async
? "ASYNCCLK" : "SYSCLK");
1636 dev_dbg(codec
->dev
, "Setting %dHz BCLK\n", bclk_rates
[bclk
]);
1637 snd_soc_update_bits(codec
, base
+ 1, WM5100_AIF1_BCLK_FREQ_MASK
, bclk
);
1639 lrclk
= bclk_rates
[bclk
] / params_rate(params
);
1640 dev_dbg(codec
->dev
, "Setting %dHz LRCLK\n", bclk_rates
[bclk
] / lrclk
);
1641 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1642 wm5100
->aif_symmetric
[dai
->id
])
1643 snd_soc_update_bits(codec
, base
+ 7,
1644 WM5100_AIF1RX_BCPF_MASK
, lrclk
);
1646 snd_soc_update_bits(codec
, base
+ 6,
1647 WM5100_AIF1TX_BCPF_MASK
, lrclk
);
1649 i
= (wl
<< WM5100_AIF1TX_WL_SHIFT
) | fl
;
1650 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1651 snd_soc_update_bits(codec
, base
+ 9,
1652 WM5100_AIF1RX_WL_MASK
|
1653 WM5100_AIF1RX_SLOT_LEN_MASK
, i
);
1655 snd_soc_update_bits(codec
, base
+ 8,
1656 WM5100_AIF1TX_WL_MASK
|
1657 WM5100_AIF1TX_SLOT_LEN_MASK
, i
);
1659 snd_soc_update_bits(codec
, base
+ 4, WM5100_AIF1_RATE_MASK
, sr
);
1664 static const struct snd_soc_dai_ops wm5100_dai_ops
= {
1665 .set_fmt
= wm5100_set_fmt
,
1666 .hw_params
= wm5100_hw_params
,
1669 static int wm5100_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
1670 int source
, unsigned int freq
, int dir
)
1672 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1674 int fval
, audio_rate
, ret
, reg
;
1677 case WM5100_CLK_SYSCLK
:
1678 reg
= WM5100_CLOCKING_3
;
1679 rate_store
= &wm5100
->sysclk
;
1681 case WM5100_CLK_ASYNCCLK
:
1682 reg
= WM5100_CLOCKING_7
;
1683 rate_store
= &wm5100
->asyncclk
;
1685 case WM5100_CLK_32KHZ
:
1686 /* The 32kHz clock is slightly different to the others */
1688 case WM5100_CLKSRC_MCLK1
:
1689 case WM5100_CLKSRC_MCLK2
:
1690 case WM5100_CLKSRC_SYSCLK
:
1691 snd_soc_update_bits(codec
, WM5100_CLOCKING_1
,
1692 WM5100_CLK_32K_SRC_MASK
,
1700 case WM5100_CLK_AIF1
:
1701 case WM5100_CLK_AIF2
:
1702 case WM5100_CLK_AIF3
:
1703 /* Not real clocks, record which clock domain they're in */
1705 case WM5100_CLKSRC_SYSCLK
:
1706 wm5100
->aif_async
[clk_id
- 1] = false;
1708 case WM5100_CLKSRC_ASYNCCLK
:
1709 wm5100
->aif_async
[clk_id
- 1] = true;
1712 dev_err(codec
->dev
, "Invalid source %d\n", source
);
1717 case WM5100_CLK_OPCLK
:
1721 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1722 WM5100_OPCLK_SEL_MASK
, 0);
1726 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1727 WM5100_OPCLK_SEL_MASK
, 0);
1731 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1732 WM5100_OPCLK_SEL_MASK
, 0);
1735 dev_err(codec
->dev
, "Unsupported OPCLK %dHz\n",
1742 dev_err(codec
->dev
, "Unknown clock %d\n", clk_id
);
1747 case WM5100_CLKSRC_SYSCLK
:
1748 case WM5100_CLKSRC_ASYNCCLK
:
1749 dev_err(codec
->dev
, "Invalid source %d\n", source
);
1767 dev_err(codec
->dev
, "Invalid clock rate: %d\n", freq
);
1790 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1794 snd_soc_update_bits(codec
, reg
, WM5100_SYSCLK_FREQ_MASK
|
1795 WM5100_SYSCLK_SRC_MASK
,
1796 fval
<< WM5100_SYSCLK_FREQ_SHIFT
| source
);
1798 /* If this is SYSCLK then configure the clock rate for the
1799 * internal audio functions to the natural sample rate for
1802 if (clk_id
== WM5100_CLK_SYSCLK
) {
1803 dev_dbg(codec
->dev
, "Setting primary audio rate to %dHz",
1805 if (0 && *rate_store
)
1806 wm5100_free_sr(codec
, audio_rate
);
1807 ret
= wm5100_alloc_sr(codec
, audio_rate
);
1809 dev_warn(codec
->dev
, "Primary audio slot is %d\n",
1833 { 0, 64000, 4, 16 },
1834 { 64000, 128000, 3, 8 },
1835 { 128000, 256000, 2, 4 },
1836 { 256000, 1000000, 1, 2 },
1837 { 1000000, 13500000, 0, 1 },
1840 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
1843 unsigned int target
;
1845 unsigned int fratio
, gcd_fll
;
1848 /* Fref must be <=13.5MHz */
1850 fll_div
->fll_refclk_div
= 0;
1851 while ((Fref
/ div
) > 13500000) {
1853 fll_div
->fll_refclk_div
++;
1856 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1862 pr_debug("FLL Fref=%u Fout=%u\n", Fref
, Fout
);
1864 /* Apply the division for our remaining calculations */
1867 /* Fvco should be 90-100MHz; don't check the upper bound */
1869 while (Fout
* div
< 90000000) {
1872 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1877 target
= Fout
* div
;
1878 fll_div
->fll_outdiv
= div
- 1;
1880 pr_debug("FLL Fvco=%dHz\n", target
);
1882 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1883 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1884 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1885 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
1886 fratio
= fll_fratios
[i
].ratio
;
1890 if (i
== ARRAY_SIZE(fll_fratios
)) {
1891 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
1895 fll_div
->n
= target
/ (fratio
* Fref
);
1897 if (target
% Fref
== 0) {
1899 fll_div
->lambda
= 0;
1901 gcd_fll
= gcd(target
, fratio
* Fref
);
1903 fll_div
->theta
= (target
- (fll_div
->n
* fratio
* Fref
))
1905 fll_div
->lambda
= (fratio
* Fref
) / gcd_fll
;
1908 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1909 fll_div
->n
, fll_div
->theta
, fll_div
->lambda
);
1910 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1911 fll_div
->fll_fratio
, fratio
, fll_div
->fll_outdiv
,
1912 fll_div
->fll_refclk_div
);
1917 static int wm5100_set_fll(struct snd_soc_codec
*codec
, int fll_id
, int source
,
1918 unsigned int Fref
, unsigned int Fout
)
1920 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
1921 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1922 struct _fll_div factors
;
1923 struct wm5100_fll
*fll
;
1924 int ret
, base
, lock
, i
, timeout
;
1928 fll
= &wm5100
->fll
[0];
1929 base
= WM5100_FLL1_CONTROL_1
- 1;
1930 lock
= WM5100_FLL1_LOCK_STS
;
1933 fll
= &wm5100
->fll
[1];
1934 base
= WM5100_FLL2_CONTROL_2
- 1;
1935 lock
= WM5100_FLL2_LOCK_STS
;
1938 dev_err(codec
->dev
, "Unknown FLL %d\n",fll_id
);
1943 dev_dbg(codec
->dev
, "FLL%d disabled", fll_id
);
1945 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, 0);
1950 case WM5100_FLL_SRC_MCLK1
:
1951 case WM5100_FLL_SRC_MCLK2
:
1952 case WM5100_FLL_SRC_FLL1
:
1953 case WM5100_FLL_SRC_FLL2
:
1954 case WM5100_FLL_SRC_AIF1BCLK
:
1955 case WM5100_FLL_SRC_AIF2BCLK
:
1956 case WM5100_FLL_SRC_AIF3BCLK
:
1959 dev_err(codec
->dev
, "Invalid FLL source %d\n", source
);
1963 ret
= fll_factors(&factors
, Fref
, Fout
);
1967 /* Disable the FLL while we reconfigure */
1968 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, 0);
1970 snd_soc_update_bits(codec
, base
+ 2,
1971 WM5100_FLL1_OUTDIV_MASK
| WM5100_FLL1_FRATIO_MASK
,
1972 (factors
.fll_outdiv
<< WM5100_FLL1_OUTDIV_SHIFT
) |
1973 factors
.fll_fratio
);
1974 snd_soc_update_bits(codec
, base
+ 3, WM5100_FLL1_THETA_MASK
,
1976 snd_soc_update_bits(codec
, base
+ 5, WM5100_FLL1_N_MASK
, factors
.n
);
1977 snd_soc_update_bits(codec
, base
+ 6,
1978 WM5100_FLL1_REFCLK_DIV_MASK
|
1979 WM5100_FLL1_REFCLK_SRC_MASK
,
1980 (factors
.fll_refclk_div
1981 << WM5100_FLL1_REFCLK_DIV_SHIFT
) | source
);
1982 snd_soc_update_bits(codec
, base
+ 7, WM5100_FLL1_LAMBDA_MASK
,
1985 /* Clear any pending completions */
1986 try_wait_for_completion(&fll
->lock
);
1988 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, WM5100_FLL1_ENA
);
1995 snd_soc_update_bits(codec
, WM5100_CLOCKING_3
, WM5100_SYSCLK_ENA
,
1998 /* Poll for the lock; will use interrupt when we can test */
1999 for (i
= 0; i
< timeout
; i
++) {
2001 ret
= wait_for_completion_timeout(&fll
->lock
,
2002 msecs_to_jiffies(25));
2009 ret
= snd_soc_read(codec
,
2010 WM5100_INTERRUPT_RAW_STATUS_3
);
2013 "Failed to read FLL status: %d\n",
2021 dev_err(codec
->dev
, "FLL%d lock timed out\n", fll_id
);
2029 dev_dbg(codec
->dev
, "FLL%d running %dHz->%dHz\n", fll_id
,
2035 /* Actually go much higher */
2036 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2038 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2039 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2041 static struct snd_soc_dai_driver wm5100_dai
[] = {
2043 .name
= "wm5100-aif1",
2045 .stream_name
= "AIF1 Playback",
2048 .rates
= WM5100_RATES
,
2049 .formats
= WM5100_FORMATS
,
2052 .stream_name
= "AIF1 Capture",
2055 .rates
= WM5100_RATES
,
2056 .formats
= WM5100_FORMATS
,
2058 .ops
= &wm5100_dai_ops
,
2061 .name
= "wm5100-aif2",
2064 .stream_name
= "AIF2 Playback",
2067 .rates
= WM5100_RATES
,
2068 .formats
= WM5100_FORMATS
,
2071 .stream_name
= "AIF2 Capture",
2074 .rates
= WM5100_RATES
,
2075 .formats
= WM5100_FORMATS
,
2077 .ops
= &wm5100_dai_ops
,
2080 .name
= "wm5100-aif3",
2083 .stream_name
= "AIF3 Playback",
2086 .rates
= WM5100_RATES
,
2087 .formats
= WM5100_FORMATS
,
2090 .stream_name
= "AIF3 Capture",
2093 .rates
= WM5100_RATES
,
2094 .formats
= WM5100_FORMATS
,
2096 .ops
= &wm5100_dai_ops
,
2100 static int wm5100_dig_vu
[] = {
2101 WM5100_ADC_DIGITAL_VOLUME_1L
,
2102 WM5100_ADC_DIGITAL_VOLUME_1R
,
2103 WM5100_ADC_DIGITAL_VOLUME_2L
,
2104 WM5100_ADC_DIGITAL_VOLUME_2R
,
2105 WM5100_ADC_DIGITAL_VOLUME_3L
,
2106 WM5100_ADC_DIGITAL_VOLUME_3R
,
2107 WM5100_ADC_DIGITAL_VOLUME_4L
,
2108 WM5100_ADC_DIGITAL_VOLUME_4R
,
2110 WM5100_DAC_DIGITAL_VOLUME_1L
,
2111 WM5100_DAC_DIGITAL_VOLUME_1R
,
2112 WM5100_DAC_DIGITAL_VOLUME_2L
,
2113 WM5100_DAC_DIGITAL_VOLUME_2R
,
2114 WM5100_DAC_DIGITAL_VOLUME_3L
,
2115 WM5100_DAC_DIGITAL_VOLUME_3R
,
2116 WM5100_DAC_DIGITAL_VOLUME_4L
,
2117 WM5100_DAC_DIGITAL_VOLUME_4R
,
2118 WM5100_DAC_DIGITAL_VOLUME_5L
,
2119 WM5100_DAC_DIGITAL_VOLUME_5R
,
2120 WM5100_DAC_DIGITAL_VOLUME_6L
,
2121 WM5100_DAC_DIGITAL_VOLUME_6R
,
2124 static void wm5100_set_detect_mode(struct snd_soc_codec
*codec
, int the_mode
)
2126 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2127 struct wm5100_jack_mode
*mode
= &wm5100
->pdata
.jack_modes
[the_mode
];
2129 BUG_ON(the_mode
>= ARRAY_SIZE(wm5100
->pdata
.jack_modes
));
2131 gpio_set_value_cansleep(wm5100
->pdata
.hp_pol
, mode
->hp_pol
);
2132 snd_soc_update_bits(codec
, WM5100_ACCESSORY_DETECT_MODE_1
,
2133 WM5100_ACCDET_BIAS_SRC_MASK
|
2135 (mode
->bias
<< WM5100_ACCDET_BIAS_SRC_SHIFT
) |
2136 mode
->micd_src
<< WM5100_ACCDET_SRC_SHIFT
);
2137 snd_soc_update_bits(codec
, WM5100_MISC_CONTROL
,
2139 mode
->micd_src
<< WM5100_HPCOM_SRC_SHIFT
);
2141 wm5100
->jack_mode
= the_mode
;
2143 dev_dbg(codec
->dev
, "Set microphone polarity to %d\n",
2147 static void wm5100_micd_irq(struct snd_soc_codec
*codec
)
2149 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2152 val
= snd_soc_read(codec
, WM5100_MIC_DETECT_3
);
2154 dev_dbg(codec
->dev
, "Microphone event: %x\n", val
);
2156 if (!(val
& WM5100_ACCDET_VALID
)) {
2157 dev_warn(codec
->dev
, "Microphone detection state invalid\n");
2161 /* No accessory, reset everything and report removal */
2162 if (!(val
& WM5100_ACCDET_STS
)) {
2163 dev_dbg(codec
->dev
, "Jack removal detected\n");
2164 wm5100
->jack_mic
= false;
2165 wm5100
->jack_detecting
= true;
2166 snd_soc_jack_report(wm5100
->jack
, 0,
2167 SND_JACK_LINEOUT
| SND_JACK_HEADSET
|
2170 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2171 WM5100_ACCDET_RATE_MASK
,
2172 WM5100_ACCDET_RATE_MASK
);
2176 /* If the measurement is very high we've got a microphone,
2177 * either we just detected one or if we already reported then
2178 * we've got a button release event.
2181 if (wm5100
->jack_detecting
) {
2182 dev_dbg(codec
->dev
, "Microphone detected\n");
2183 wm5100
->jack_mic
= true;
2184 snd_soc_jack_report(wm5100
->jack
,
2186 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2188 /* Increase poll rate to give better responsiveness
2190 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2191 WM5100_ACCDET_RATE_MASK
,
2192 5 << WM5100_ACCDET_RATE_SHIFT
);
2194 dev_dbg(codec
->dev
, "Mic button up\n");
2195 snd_soc_jack_report(wm5100
->jack
, 0, SND_JACK_BTN_0
);
2201 /* If we detected a lower impedence during initial startup
2202 * then we probably have the wrong polarity, flip it. Don't
2203 * do this for the lowest impedences to speed up detection of
2206 if (wm5100
->jack_detecting
&& (val
& 0x3f8)) {
2207 wm5100_set_detect_mode(codec
, !wm5100
->jack_mode
);
2212 /* Don't distinguish between buttons, just report any low
2213 * impedence as BTN_0.
2216 if (wm5100
->jack_mic
) {
2217 dev_dbg(codec
->dev
, "Mic button detected\n");
2218 snd_soc_jack_report(wm5100
->jack
, SND_JACK_BTN_0
,
2220 } else if (wm5100
->jack_detecting
) {
2221 dev_dbg(codec
->dev
, "Headphone detected\n");
2222 snd_soc_jack_report(wm5100
->jack
, SND_JACK_HEADPHONE
,
2223 SND_JACK_HEADPHONE
);
2225 /* Increase the detection rate a bit for
2228 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2229 WM5100_ACCDET_RATE_MASK
,
2230 7 << WM5100_ACCDET_RATE_SHIFT
);
2235 int wm5100_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
)
2237 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2240 wm5100
->jack
= jack
;
2241 wm5100
->jack_detecting
= true;
2243 wm5100_set_detect_mode(codec
, 0);
2245 /* Slowest detection rate, gives debounce for initial
2247 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2248 WM5100_ACCDET_BIAS_STARTTIME_MASK
|
2249 WM5100_ACCDET_RATE_MASK
,
2250 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT
) |
2251 WM5100_ACCDET_RATE_MASK
);
2253 /* We need the charge pump to power MICBIAS */
2254 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CP2");
2255 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "SYSCLK");
2256 snd_soc_dapm_sync(&codec
->dapm
);
2258 /* We start off just enabling microphone detection - even a
2259 * plain headphone will trigger detection.
2261 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2262 WM5100_ACCDET_ENA
, WM5100_ACCDET_ENA
);
2264 snd_soc_update_bits(codec
, WM5100_INTERRUPT_STATUS_3_MASK
,
2265 WM5100_IM_ACCDET_EINT
, 0);
2267 snd_soc_update_bits(codec
, WM5100_INTERRUPT_STATUS_3_MASK
,
2268 WM5100_IM_HPDET_EINT
|
2269 WM5100_IM_ACCDET_EINT
,
2270 WM5100_IM_HPDET_EINT
|
2271 WM5100_IM_ACCDET_EINT
);
2272 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2273 WM5100_ACCDET_ENA
, 0);
2274 wm5100
->jack
= NULL
;
2280 static irqreturn_t
wm5100_irq(int irq
, void *data
)
2282 struct snd_soc_codec
*codec
= data
;
2283 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2284 irqreturn_t status
= IRQ_NONE
;
2287 irq_val
= snd_soc_read(codec
, WM5100_INTERRUPT_STATUS_3
);
2289 dev_err(codec
->dev
, "Failed to read IRQ status 3: %d\n",
2293 irq_val
&= ~snd_soc_read(codec
, WM5100_INTERRUPT_STATUS_3_MASK
);
2295 snd_soc_write(codec
, WM5100_INTERRUPT_STATUS_3
, irq_val
);
2298 status
= IRQ_HANDLED
;
2300 wm5100_log_status3(codec
, irq_val
);
2302 if (irq_val
& WM5100_FLL1_LOCK_EINT
) {
2303 dev_dbg(codec
->dev
, "FLL1 locked\n");
2304 complete(&wm5100
->fll
[0].lock
);
2306 if (irq_val
& WM5100_FLL2_LOCK_EINT
) {
2307 dev_dbg(codec
->dev
, "FLL2 locked\n");
2308 complete(&wm5100
->fll
[1].lock
);
2311 if (irq_val
& WM5100_ACCDET_EINT
)
2312 wm5100_micd_irq(codec
);
2314 irq_val
= snd_soc_read(codec
, WM5100_INTERRUPT_STATUS_4
);
2316 dev_err(codec
->dev
, "Failed to read IRQ status 4: %d\n",
2320 irq_val
&= ~snd_soc_read(codec
, WM5100_INTERRUPT_STATUS_4_MASK
);
2323 status
= IRQ_HANDLED
;
2325 snd_soc_write(codec
, WM5100_INTERRUPT_STATUS_4
, irq_val
);
2327 wm5100_log_status4(codec
, irq_val
);
2332 static irqreturn_t
wm5100_edge_irq(int irq
, void *data
)
2334 irqreturn_t ret
= IRQ_NONE
;
2338 val
= wm5100_irq(irq
, data
);
2339 if (val
!= IRQ_NONE
)
2341 } while (val
!= IRQ_NONE
);
2346 #ifdef CONFIG_GPIOLIB
2347 static inline struct wm5100_priv
*gpio_to_wm5100(struct gpio_chip
*chip
)
2349 return container_of(chip
, struct wm5100_priv
, gpio_chip
);
2352 static void wm5100_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
2354 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2356 regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2357 WM5100_GP1_LVL
, !!value
<< WM5100_GP1_LVL_SHIFT
);
2360 static int wm5100_gpio_direction_out(struct gpio_chip
*chip
,
2361 unsigned offset
, int value
)
2363 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2366 val
= (1 << WM5100_GP1_FN_SHIFT
) | (!!value
<< WM5100_GP1_LVL_SHIFT
);
2368 ret
= regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2369 WM5100_GP1_FN_MASK
| WM5100_GP1_DIR
|
2370 WM5100_GP1_LVL
, val
);
2377 static int wm5100_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
2379 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2383 ret
= regmap_read(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
, ®
);
2387 return (reg
& WM5100_GP1_LVL
) != 0;
2390 static int wm5100_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
2392 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2394 return regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2395 WM5100_GP1_FN_MASK
| WM5100_GP1_DIR
,
2396 (1 << WM5100_GP1_FN_SHIFT
) |
2397 (1 << WM5100_GP1_DIR_SHIFT
));
2400 static struct gpio_chip wm5100_template_chip
= {
2402 .owner
= THIS_MODULE
,
2403 .direction_output
= wm5100_gpio_direction_out
,
2404 .set
= wm5100_gpio_set
,
2405 .direction_input
= wm5100_gpio_direction_in
,
2406 .get
= wm5100_gpio_get
,
2410 static void wm5100_init_gpio(struct i2c_client
*i2c
)
2412 struct wm5100_priv
*wm5100
= i2c_get_clientdata(i2c
);
2415 wm5100
->gpio_chip
= wm5100_template_chip
;
2416 wm5100
->gpio_chip
.ngpio
= 6;
2417 wm5100
->gpio_chip
.dev
= &i2c
->dev
;
2419 if (wm5100
->pdata
.gpio_base
)
2420 wm5100
->gpio_chip
.base
= wm5100
->pdata
.gpio_base
;
2422 wm5100
->gpio_chip
.base
= -1;
2424 ret
= gpiochip_add(&wm5100
->gpio_chip
);
2426 dev_err(&i2c
->dev
, "Failed to add GPIOs: %d\n", ret
);
2429 static void wm5100_free_gpio(struct i2c_client
*i2c
)
2431 struct wm5100_priv
*wm5100
= i2c_get_clientdata(i2c
);
2434 ret
= gpiochip_remove(&wm5100
->gpio_chip
);
2436 dev_err(&i2c
->dev
, "Failed to remove GPIOs: %d\n", ret
);
2439 static void wm5100_init_gpio(struct i2c_client
*i2c
)
2443 static void wm5100_free_gpio(struct i2c_client
*i2c
)
2448 static int wm5100_probe(struct snd_soc_codec
*codec
)
2450 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2451 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2452 int ret
, i
, irq_flags
;
2454 wm5100
->codec
= codec
;
2455 codec
->control_data
= wm5100
->regmap
;
2457 ret
= snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
2459 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2463 regcache_cache_only(wm5100
->regmap
, true);
2466 for (i
= 0; i
< ARRAY_SIZE(wm5100_dig_vu
); i
++)
2467 snd_soc_update_bits(codec
, wm5100_dig_vu
[i
], WM5100_OUT_VU
,
2470 /* Don't debounce interrupts to support use of SYSCLK only */
2471 snd_soc_write(codec
, WM5100_IRQ_DEBOUNCE_1
, 0);
2472 snd_soc_write(codec
, WM5100_IRQ_DEBOUNCE_2
, 0);
2474 /* TODO: check if we're symmetric */
2477 if (wm5100
->pdata
.irq_flags
)
2478 irq_flags
= wm5100
->pdata
.irq_flags
;
2480 irq_flags
= IRQF_TRIGGER_LOW
;
2482 irq_flags
|= IRQF_ONESHOT
;
2484 if (irq_flags
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
))
2485 ret
= request_threaded_irq(i2c
->irq
, NULL
,
2487 irq_flags
, "wm5100", codec
);
2489 ret
= request_threaded_irq(i2c
->irq
, NULL
, wm5100_irq
,
2490 irq_flags
, "wm5100", codec
);
2493 dev_err(codec
->dev
, "Failed to request IRQ %d: %d\n",
2496 /* Enable default interrupts */
2497 snd_soc_update_bits(codec
,
2498 WM5100_INTERRUPT_STATUS_3_MASK
,
2499 WM5100_IM_SPK_SHUTDOWN_WARN_EINT
|
2500 WM5100_IM_SPK_SHUTDOWN_EINT
|
2501 WM5100_IM_ASRC2_LOCK_EINT
|
2502 WM5100_IM_ASRC1_LOCK_EINT
|
2503 WM5100_IM_FLL2_LOCK_EINT
|
2504 WM5100_IM_FLL1_LOCK_EINT
|
2505 WM5100_CLKGEN_ERR_EINT
|
2506 WM5100_CLKGEN_ERR_ASYNC_EINT
, 0);
2508 snd_soc_update_bits(codec
,
2509 WM5100_INTERRUPT_STATUS_4_MASK
,
2510 WM5100_AIF3_ERR_EINT
|
2511 WM5100_AIF2_ERR_EINT
|
2512 WM5100_AIF1_ERR_EINT
|
2513 WM5100_CTRLIF_ERR_EINT
|
2514 WM5100_ISRC2_UNDERCLOCKED_EINT
|
2515 WM5100_ISRC1_UNDERCLOCKED_EINT
|
2516 WM5100_FX_UNDERCLOCKED_EINT
|
2517 WM5100_AIF3_UNDERCLOCKED_EINT
|
2518 WM5100_AIF2_UNDERCLOCKED_EINT
|
2519 WM5100_AIF1_UNDERCLOCKED_EINT
|
2520 WM5100_ASRC_UNDERCLOCKED_EINT
|
2521 WM5100_DAC_UNDERCLOCKED_EINT
|
2522 WM5100_ADC_UNDERCLOCKED_EINT
|
2523 WM5100_MIXER_UNDERCLOCKED_EINT
, 0);
2526 snd_soc_dapm_new_controls(&codec
->dapm
,
2527 wm5100_dapm_widgets_noirq
,
2528 ARRAY_SIZE(wm5100_dapm_widgets_noirq
));
2531 if (wm5100
->pdata
.hp_pol
) {
2532 ret
= gpio_request_one(wm5100
->pdata
.hp_pol
,
2533 GPIOF_OUT_INIT_HIGH
, "WM5100 HP_POL");
2535 dev_err(&i2c
->dev
, "Failed to request HP_POL %d: %d\n",
2536 wm5100
->pdata
.hp_pol
, ret
);
2541 /* We'll get woken up again when the system has something useful
2544 if (wm5100
->pdata
.ldo_ena
)
2545 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2546 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
2547 wm5100
->core_supplies
);
2553 free_irq(i2c
->irq
, codec
);
2558 static int wm5100_remove(struct snd_soc_codec
*codec
)
2560 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2561 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2563 wm5100_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2564 if (wm5100
->pdata
.hp_pol
) {
2565 gpio_free(wm5100
->pdata
.hp_pol
);
2568 free_irq(i2c
->irq
, codec
);
2572 static struct snd_soc_codec_driver soc_codec_dev_wm5100
= {
2573 .probe
= wm5100_probe
,
2574 .remove
= wm5100_remove
,
2576 .set_sysclk
= wm5100_set_sysclk
,
2577 .set_pll
= wm5100_set_fll
,
2578 .set_bias_level
= wm5100_set_bias_level
,
2581 .seq_notifier
= wm5100_seq_notifier
,
2582 .controls
= wm5100_snd_controls
,
2583 .num_controls
= ARRAY_SIZE(wm5100_snd_controls
),
2584 .dapm_widgets
= wm5100_dapm_widgets
,
2585 .num_dapm_widgets
= ARRAY_SIZE(wm5100_dapm_widgets
),
2586 .dapm_routes
= wm5100_dapm_routes
,
2587 .num_dapm_routes
= ARRAY_SIZE(wm5100_dapm_routes
),
2590 static const struct regmap_config wm5100_regmap
= {
2594 .max_register
= WM5100_MAX_REGISTER
,
2595 .reg_defaults
= wm5100_reg_defaults
,
2596 .num_reg_defaults
= ARRAY_SIZE(wm5100_reg_defaults
),
2597 .volatile_reg
= wm5100_volatile_register
,
2598 .readable_reg
= wm5100_readable_register
,
2599 .cache_type
= REGCACHE_RBTREE
,
2602 static __devinit
int wm5100_i2c_probe(struct i2c_client
*i2c
,
2603 const struct i2c_device_id
*id
)
2605 struct wm5100_pdata
*pdata
= dev_get_platdata(&i2c
->dev
);
2606 struct wm5100_priv
*wm5100
;
2610 wm5100
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm5100_priv
),
2615 wm5100
->regmap
= regmap_init_i2c(i2c
, &wm5100_regmap
);
2616 if (IS_ERR(wm5100
->regmap
)) {
2617 ret
= PTR_ERR(wm5100
->regmap
);
2618 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2623 for (i
= 0; i
< ARRAY_SIZE(wm5100
->fll
); i
++)
2624 init_completion(&wm5100
->fll
[i
].lock
);
2627 wm5100
->pdata
= *pdata
;
2629 i2c_set_clientdata(i2c
, wm5100
);
2631 for (i
= 0; i
< ARRAY_SIZE(wm5100
->core_supplies
); i
++)
2632 wm5100
->core_supplies
[i
].supply
= wm5100_core_supply_names
[i
];
2634 ret
= regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(wm5100
->core_supplies
),
2635 wm5100
->core_supplies
);
2637 dev_err(&i2c
->dev
, "Failed to request core supplies: %d\n",
2642 wm5100
->cpvdd
= regulator_get(&i2c
->dev
, "CPVDD");
2643 if (IS_ERR(wm5100
->cpvdd
)) {
2644 ret
= PTR_ERR(wm5100
->cpvdd
);
2645 dev_err(&i2c
->dev
, "Failed to get CPVDD: %d\n", ret
);
2649 wm5100
->dbvdd2
= regulator_get(&i2c
->dev
, "DBVDD2");
2650 if (IS_ERR(wm5100
->dbvdd2
)) {
2651 ret
= PTR_ERR(wm5100
->dbvdd2
);
2652 dev_err(&i2c
->dev
, "Failed to get DBVDD2: %d\n", ret
);
2656 wm5100
->dbvdd3
= regulator_get(&i2c
->dev
, "DBVDD3");
2657 if (IS_ERR(wm5100
->dbvdd3
)) {
2658 ret
= PTR_ERR(wm5100
->dbvdd3
);
2659 dev_err(&i2c
->dev
, "Failed to get DBVDD2: %d\n", ret
);
2663 ret
= regulator_bulk_enable(ARRAY_SIZE(wm5100
->core_supplies
),
2664 wm5100
->core_supplies
);
2666 dev_err(&i2c
->dev
, "Failed to enable core supplies: %d\n",
2671 if (wm5100
->pdata
.ldo_ena
) {
2672 ret
= gpio_request_one(wm5100
->pdata
.ldo_ena
,
2673 GPIOF_OUT_INIT_HIGH
, "WM5100 LDOENA");
2675 dev_err(&i2c
->dev
, "Failed to request LDOENA %d: %d\n",
2676 wm5100
->pdata
.ldo_ena
, ret
);
2682 if (wm5100
->pdata
.reset
) {
2683 ret
= gpio_request_one(wm5100
->pdata
.reset
,
2684 GPIOF_OUT_INIT_HIGH
, "WM5100 /RESET");
2686 dev_err(&i2c
->dev
, "Failed to request /RESET %d: %d\n",
2687 wm5100
->pdata
.reset
, ret
);
2692 ret
= regmap_read(wm5100
->regmap
, WM5100_SOFTWARE_RESET
, ®
);
2694 dev_err(&i2c
->dev
, "Failed to read ID register\n");
2703 dev_err(&i2c
->dev
, "Device is not a WM5100, ID is %x\n", reg
);
2708 ret
= regmap_read(wm5100
->regmap
, WM5100_DEVICE_REVISION
, ®
);
2710 dev_err(&i2c
->dev
, "Failed to read revision register\n");
2713 wm5100
->rev
= reg
& WM5100_DEVICE_REVISION_MASK
;
2715 dev_info(&i2c
->dev
, "revision %c\n", wm5100
->rev
+ 'A');
2717 ret
= wm5100_reset(wm5100
);
2719 dev_err(&i2c
->dev
, "Failed to issue reset\n");
2723 wm5100_init_gpio(i2c
);
2725 for (i
= 0; i
< ARRAY_SIZE(wm5100
->pdata
.gpio_defaults
); i
++) {
2726 if (!wm5100
->pdata
.gpio_defaults
[i
])
2729 regmap_write(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ i
,
2730 wm5100
->pdata
.gpio_defaults
[i
]);
2733 for (i
= 0; i
< ARRAY_SIZE(wm5100
->pdata
.in_mode
); i
++) {
2734 regmap_update_bits(wm5100
->regmap
, WM5100_IN1L_CONTROL
,
2735 WM5100_IN1_MODE_MASK
|
2736 WM5100_IN1_DMIC_SUP_MASK
,
2737 (wm5100
->pdata
.in_mode
[i
] <<
2738 WM5100_IN1_MODE_SHIFT
) |
2739 (wm5100
->pdata
.dmic_sup
[i
] <<
2740 WM5100_IN1_DMIC_SUP_SHIFT
));
2743 ret
= snd_soc_register_codec(&i2c
->dev
,
2744 &soc_codec_dev_wm5100
, wm5100_dai
,
2745 ARRAY_SIZE(wm5100_dai
));
2747 dev_err(&i2c
->dev
, "Failed to register WM5100: %d\n", ret
);
2754 wm5100_free_gpio(i2c
);
2755 if (wm5100
->pdata
.reset
) {
2756 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 1);
2757 gpio_free(wm5100
->pdata
.reset
);
2760 if (wm5100
->pdata
.ldo_ena
) {
2761 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2762 gpio_free(wm5100
->pdata
.ldo_ena
);
2765 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
2766 wm5100
->core_supplies
);
2768 regulator_put(wm5100
->dbvdd3
);
2770 regulator_put(wm5100
->dbvdd2
);
2772 regulator_put(wm5100
->cpvdd
);
2774 regulator_bulk_free(ARRAY_SIZE(wm5100
->core_supplies
),
2775 wm5100
->core_supplies
);
2777 regmap_exit(wm5100
->regmap
);
2782 static __devexit
int wm5100_i2c_remove(struct i2c_client
*client
)
2784 struct wm5100_priv
*wm5100
= i2c_get_clientdata(client
);
2786 snd_soc_unregister_codec(&client
->dev
);
2787 wm5100_free_gpio(client
);
2788 if (wm5100
->pdata
.reset
) {
2789 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 1);
2790 gpio_free(wm5100
->pdata
.reset
);
2792 if (wm5100
->pdata
.ldo_ena
) {
2793 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2794 gpio_free(wm5100
->pdata
.ldo_ena
);
2796 regulator_put(wm5100
->dbvdd3
);
2797 regulator_put(wm5100
->dbvdd2
);
2798 regulator_put(wm5100
->cpvdd
);
2799 regulator_bulk_free(ARRAY_SIZE(wm5100
->core_supplies
),
2800 wm5100
->core_supplies
);
2801 regmap_exit(wm5100
->regmap
);
2806 static const struct i2c_device_id wm5100_i2c_id
[] = {
2810 MODULE_DEVICE_TABLE(i2c
, wm5100_i2c_id
);
2812 static struct i2c_driver wm5100_i2c_driver
= {
2815 .owner
= THIS_MODULE
,
2817 .probe
= wm5100_i2c_probe
,
2818 .remove
= __devexit_p(wm5100_i2c_remove
),
2819 .id_table
= wm5100_i2c_id
,
2822 static int __init
wm5100_modinit(void)
2824 return i2c_add_driver(&wm5100_i2c_driver
);
2826 module_init(wm5100_modinit
);
2828 static void __exit
wm5100_exit(void)
2830 i2c_del_driver(&wm5100_i2c_driver
);
2832 module_exit(wm5100_exit
);
2834 MODULE_DESCRIPTION("ASoC WM5100 driver");
2835 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2836 MODULE_LICENSE("GPL");