2 * wm5100.c -- WM5100 ALSA SoC Audio driver
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/gcd.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/regulator/fixed.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/jack.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <sound/wm5100.h>
35 #define WM5100_NUM_CORE_SUPPLIES 2
36 static const char *wm5100_core_supply_names
[WM5100_NUM_CORE_SUPPLIES
] = {
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
42 #define WM5100_SYNC_SRS 3
48 struct completion lock
;
51 /* codec private data */
54 struct regmap
*regmap
;
55 struct snd_soc_codec
*codec
;
57 struct regulator_bulk_data core_supplies
[WM5100_NUM_CORE_SUPPLIES
];
58 struct regulator
*cpvdd
;
59 struct regulator
*dbvdd2
;
60 struct regulator
*dbvdd3
;
67 bool aif_async
[WM5100_AIFS
];
68 bool aif_symmetric
[WM5100_AIFS
];
69 int sr_ref
[WM5100_SYNC_SRS
];
73 struct snd_soc_jack
*jack
;
78 struct wm5100_fll fll
[2];
80 struct wm5100_pdata pdata
;
83 struct gpio_chip gpio_chip
;
87 static int wm5100_sr_code
[] = {
114 static int wm5100_sr_regs
[WM5100_SYNC_SRS
] = {
120 static int wm5100_alloc_sr(struct snd_soc_codec
*codec
, int rate
)
122 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
123 int sr_code
, sr_free
, i
;
125 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
126 if (wm5100_sr_code
[i
] == rate
)
128 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
129 dev_err(codec
->dev
, "Unsupported sample rate: %dHz\n", rate
);
134 if ((wm5100
->sysclk
% rate
) == 0) {
135 /* Is this rate already in use? */
137 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_regs
); i
++) {
138 if (!wm5100
->sr_ref
[i
] && sr_free
== -1) {
142 if ((snd_soc_read(codec
, wm5100_sr_regs
[i
]) &
143 WM5100_SAMPLE_RATE_1_MASK
) == sr_code
)
147 if (i
< ARRAY_SIZE(wm5100_sr_regs
)) {
149 dev_dbg(codec
->dev
, "SR %dHz, slot %d, ref %d\n",
150 rate
, i
, wm5100
->sr_ref
[i
]);
155 dev_err(codec
->dev
, "All SR slots already in use\n");
159 dev_dbg(codec
->dev
, "Allocating SR slot %d for %dHz\n",
161 wm5100
->sr_ref
[sr_free
]++;
162 snd_soc_update_bits(codec
, wm5100_sr_regs
[sr_free
],
163 WM5100_SAMPLE_RATE_1_MASK
,
170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171 rate
, wm5100
->sysclk
, wm5100
->asyncclk
);
176 static void wm5100_free_sr(struct snd_soc_codec
*codec
, int rate
)
178 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
181 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
182 if (wm5100_sr_code
[i
] == rate
)
184 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
185 dev_err(codec
->dev
, "Unsupported sample rate: %dHz\n", rate
);
188 sr_code
= wm5100_sr_code
[i
];
190 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_regs
); i
++) {
191 if (!wm5100
->sr_ref
[i
])
194 if ((snd_soc_read(codec
, wm5100_sr_regs
[i
]) &
195 WM5100_SAMPLE_RATE_1_MASK
) == sr_code
)
198 if (i
< ARRAY_SIZE(wm5100_sr_regs
)) {
200 dev_dbg(codec
->dev
, "Dereference SR %dHz, count now %d\n",
201 rate
, wm5100
->sr_ref
[i
]);
203 dev_warn(codec
->dev
, "Freeing unreferenced sample rate %dHz\n",
208 static int wm5100_reset(struct wm5100_priv
*wm5100
)
210 if (wm5100
->pdata
.reset
) {
211 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 0);
212 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 1);
216 return regmap_write(wm5100
->regmap
, WM5100_SOFTWARE_RESET
, 0);
220 static DECLARE_TLV_DB_SCALE(in_tlv
, -6300, 100, 0);
221 static DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
222 static DECLARE_TLV_DB_SCALE(mixer_tlv
, -3200, 100, 0);
223 static DECLARE_TLV_DB_SCALE(out_tlv
, -6400, 100, 0);
224 static DECLARE_TLV_DB_SCALE(digital_tlv
, -6400, 50, 0);
226 static const char *wm5100_mixer_texts
[] = {
301 static int wm5100_mixer_values
[] = {
324 0x30, /* AIF3 - check */
359 0xa0, /* ISRC1DEC1 */
363 0xa4, /* ISRC1INT1 */
367 0xa8, /* ISRC2DEC1 */
371 0xac, /* ISRC2INT1 */
377 #define WM5100_MIXER_CONTROLS(name, base) \
378 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
387 #define WM5100_MUX_ENUM_DECL(name, reg) \
388 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
389 wm5100_mixer_texts, wm5100_mixer_values)
391 #define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \
393 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
395 #define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
397 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
398 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
399 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
400 static WM5100_MUX_CTL_DECL(name##_in1); \
401 static WM5100_MUX_CTL_DECL(name##_in2); \
402 static WM5100_MUX_CTL_DECL(name##_in3); \
403 static WM5100_MUX_CTL_DECL(name##_in4)
405 WM5100_MIXER_ENUMS(HPOUT1L
, WM5100_OUT1LMIX_INPUT_1_SOURCE
);
406 WM5100_MIXER_ENUMS(HPOUT1R
, WM5100_OUT1RMIX_INPUT_1_SOURCE
);
407 WM5100_MIXER_ENUMS(HPOUT2L
, WM5100_OUT2LMIX_INPUT_1_SOURCE
);
408 WM5100_MIXER_ENUMS(HPOUT2R
, WM5100_OUT2RMIX_INPUT_1_SOURCE
);
409 WM5100_MIXER_ENUMS(HPOUT3L
, WM5100_OUT3LMIX_INPUT_1_SOURCE
);
410 WM5100_MIXER_ENUMS(HPOUT3R
, WM5100_OUT3RMIX_INPUT_1_SOURCE
);
412 WM5100_MIXER_ENUMS(SPKOUTL
, WM5100_OUT4LMIX_INPUT_1_SOURCE
);
413 WM5100_MIXER_ENUMS(SPKOUTR
, WM5100_OUT4RMIX_INPUT_1_SOURCE
);
414 WM5100_MIXER_ENUMS(SPKDAT1L
, WM5100_OUT5LMIX_INPUT_1_SOURCE
);
415 WM5100_MIXER_ENUMS(SPKDAT1R
, WM5100_OUT5RMIX_INPUT_1_SOURCE
);
416 WM5100_MIXER_ENUMS(SPKDAT2L
, WM5100_OUT6LMIX_INPUT_1_SOURCE
);
417 WM5100_MIXER_ENUMS(SPKDAT2R
, WM5100_OUT6RMIX_INPUT_1_SOURCE
);
419 WM5100_MIXER_ENUMS(PWM1
, WM5100_PWM1MIX_INPUT_1_SOURCE
);
420 WM5100_MIXER_ENUMS(PWM2
, WM5100_PWM1MIX_INPUT_1_SOURCE
);
422 WM5100_MIXER_ENUMS(AIF1TX1
, WM5100_AIF1TX1MIX_INPUT_1_SOURCE
);
423 WM5100_MIXER_ENUMS(AIF1TX2
, WM5100_AIF1TX2MIX_INPUT_1_SOURCE
);
424 WM5100_MIXER_ENUMS(AIF1TX3
, WM5100_AIF1TX3MIX_INPUT_1_SOURCE
);
425 WM5100_MIXER_ENUMS(AIF1TX4
, WM5100_AIF1TX4MIX_INPUT_1_SOURCE
);
426 WM5100_MIXER_ENUMS(AIF1TX5
, WM5100_AIF1TX5MIX_INPUT_1_SOURCE
);
427 WM5100_MIXER_ENUMS(AIF1TX6
, WM5100_AIF1TX6MIX_INPUT_1_SOURCE
);
428 WM5100_MIXER_ENUMS(AIF1TX7
, WM5100_AIF1TX7MIX_INPUT_1_SOURCE
);
429 WM5100_MIXER_ENUMS(AIF1TX8
, WM5100_AIF1TX8MIX_INPUT_1_SOURCE
);
431 WM5100_MIXER_ENUMS(AIF2TX1
, WM5100_AIF2TX1MIX_INPUT_1_SOURCE
);
432 WM5100_MIXER_ENUMS(AIF2TX2
, WM5100_AIF2TX2MIX_INPUT_1_SOURCE
);
434 WM5100_MIXER_ENUMS(AIF3TX1
, WM5100_AIF1TX1MIX_INPUT_1_SOURCE
);
435 WM5100_MIXER_ENUMS(AIF3TX2
, WM5100_AIF1TX2MIX_INPUT_1_SOURCE
);
437 WM5100_MIXER_ENUMS(EQ1
, WM5100_EQ1MIX_INPUT_1_SOURCE
);
438 WM5100_MIXER_ENUMS(EQ2
, WM5100_EQ2MIX_INPUT_1_SOURCE
);
439 WM5100_MIXER_ENUMS(EQ3
, WM5100_EQ3MIX_INPUT_1_SOURCE
);
440 WM5100_MIXER_ENUMS(EQ4
, WM5100_EQ4MIX_INPUT_1_SOURCE
);
442 WM5100_MIXER_ENUMS(DRC1L
, WM5100_DRC1LMIX_INPUT_1_SOURCE
);
443 WM5100_MIXER_ENUMS(DRC1R
, WM5100_DRC1RMIX_INPUT_1_SOURCE
);
445 WM5100_MIXER_ENUMS(LHPF1
, WM5100_HPLP1MIX_INPUT_1_SOURCE
);
446 WM5100_MIXER_ENUMS(LHPF2
, WM5100_HPLP2MIX_INPUT_1_SOURCE
);
447 WM5100_MIXER_ENUMS(LHPF3
, WM5100_HPLP3MIX_INPUT_1_SOURCE
);
448 WM5100_MIXER_ENUMS(LHPF4
, WM5100_HPLP4MIX_INPUT_1_SOURCE
);
450 #define WM5100_MUX(name, ctrl) \
451 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
453 #define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
460 #define WM5100_MIXER_INPUT_ROUTES(name) \
461 { name, "Tone Generator 1", "Tone Generator 1" }, \
462 { name, "Tone Generator 2", "Tone Generator 2" }, \
463 { name, "IN1L", "IN1L PGA" }, \
464 { name, "IN1R", "IN1R PGA" }, \
465 { name, "IN2L", "IN2L PGA" }, \
466 { name, "IN2R", "IN2R PGA" }, \
467 { name, "IN3L", "IN3L PGA" }, \
468 { name, "IN3R", "IN3R PGA" }, \
469 { name, "IN4L", "IN4L PGA" }, \
470 { name, "IN4R", "IN4R PGA" }, \
471 { name, "AIF1RX1", "AIF1RX1" }, \
472 { name, "AIF1RX2", "AIF1RX2" }, \
473 { name, "AIF1RX3", "AIF1RX3" }, \
474 { name, "AIF1RX4", "AIF1RX4" }, \
475 { name, "AIF1RX5", "AIF1RX5" }, \
476 { name, "AIF1RX6", "AIF1RX6" }, \
477 { name, "AIF1RX7", "AIF1RX7" }, \
478 { name, "AIF1RX8", "AIF1RX8" }, \
479 { name, "AIF2RX1", "AIF2RX1" }, \
480 { name, "AIF2RX2", "AIF2RX2" }, \
481 { name, "AIF3RX1", "AIF3RX1" }, \
482 { name, "AIF3RX2", "AIF3RX2" }, \
483 { name, "EQ1", "EQ1" }, \
484 { name, "EQ2", "EQ2" }, \
485 { name, "EQ3", "EQ3" }, \
486 { name, "EQ4", "EQ4" }, \
487 { name, "DRC1L", "DRC1L" }, \
488 { name, "DRC1R", "DRC1R" }, \
489 { name, "LHPF1", "LHPF1" }, \
490 { name, "LHPF2", "LHPF2" }, \
491 { name, "LHPF3", "LHPF3" }, \
492 { name, "LHPF4", "LHPF4" }
494 #define WM5100_MIXER_ROUTES(widget, name) \
495 { widget, NULL, name " Mixer" }, \
496 { name " Mixer", NULL, name " Input 1" }, \
497 { name " Mixer", NULL, name " Input 2" }, \
498 { name " Mixer", NULL, name " Input 3" }, \
499 { name " Mixer", NULL, name " Input 4" }, \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
505 static const char *wm5100_lhpf_mode_text
[] = {
506 "Low-pass", "High-pass"
509 static const struct soc_enum wm5100_lhpf1_mode
=
510 SOC_ENUM_SINGLE(WM5100_HPLPF1_1
, WM5100_LHPF1_MODE_SHIFT
, 2,
511 wm5100_lhpf_mode_text
);
513 static const struct soc_enum wm5100_lhpf2_mode
=
514 SOC_ENUM_SINGLE(WM5100_HPLPF2_1
, WM5100_LHPF2_MODE_SHIFT
, 2,
515 wm5100_lhpf_mode_text
);
517 static const struct soc_enum wm5100_lhpf3_mode
=
518 SOC_ENUM_SINGLE(WM5100_HPLPF3_1
, WM5100_LHPF3_MODE_SHIFT
, 2,
519 wm5100_lhpf_mode_text
);
521 static const struct soc_enum wm5100_lhpf4_mode
=
522 SOC_ENUM_SINGLE(WM5100_HPLPF4_1
, WM5100_LHPF4_MODE_SHIFT
, 2,
523 wm5100_lhpf_mode_text
);
525 static const struct snd_kcontrol_new wm5100_snd_controls
[] = {
526 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL
,
527 WM5100_IN1_OSR_SHIFT
, 1, 0),
528 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL
,
529 WM5100_IN2_OSR_SHIFT
, 1, 0),
530 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL
,
531 WM5100_IN3_OSR_SHIFT
, 1, 0),
532 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL
,
533 WM5100_IN4_OSR_SHIFT
, 1, 0),
535 /* Only applicable for analogue inputs */
536 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL
, WM5100_IN1R_CONTROL
,
537 WM5100_IN1L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
538 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL
, WM5100_IN2R_CONTROL
,
539 WM5100_IN2L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
540 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL
, WM5100_IN3R_CONTROL
,
541 WM5100_IN3L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
542 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL
, WM5100_IN4R_CONTROL
,
543 WM5100_IN4L_PGA_VOL_SHIFT
, 94, 0, in_tlv
),
545 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L
,
546 WM5100_ADC_DIGITAL_VOLUME_1R
, WM5100_IN1L_VOL_SHIFT
, 191,
548 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L
,
549 WM5100_ADC_DIGITAL_VOLUME_2R
, WM5100_IN2L_VOL_SHIFT
, 191,
551 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L
,
552 WM5100_ADC_DIGITAL_VOLUME_3R
, WM5100_IN3L_VOL_SHIFT
, 191,
554 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L
,
555 WM5100_ADC_DIGITAL_VOLUME_4R
, WM5100_IN4L_VOL_SHIFT
, 191,
558 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L
,
559 WM5100_ADC_DIGITAL_VOLUME_1R
, WM5100_IN1L_MUTE_SHIFT
, 1, 1),
560 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L
,
561 WM5100_ADC_DIGITAL_VOLUME_2R
, WM5100_IN2L_MUTE_SHIFT
, 1, 1),
562 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L
,
563 WM5100_ADC_DIGITAL_VOLUME_3R
, WM5100_IN3L_MUTE_SHIFT
, 1, 1),
564 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L
,
565 WM5100_ADC_DIGITAL_VOLUME_4R
, WM5100_IN4L_MUTE_SHIFT
, 1, 1),
567 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L
,
568 WM5100_OUT1_OSR_SHIFT
, 1, 0),
569 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L
,
570 WM5100_OUT2_OSR_SHIFT
, 1, 0),
571 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L
,
572 WM5100_OUT3_OSR_SHIFT
, 1, 0),
573 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L
,
574 WM5100_OUT4_OSR_SHIFT
, 1, 0),
575 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L
,
576 WM5100_OUT5_OSR_SHIFT
, 1, 0),
577 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L
,
578 WM5100_OUT6_OSR_SHIFT
, 1, 0),
580 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L
,
581 WM5100_DAC_DIGITAL_VOLUME_1R
, WM5100_OUT1L_VOL_SHIFT
, 159, 0,
583 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L
,
584 WM5100_DAC_DIGITAL_VOLUME_2R
, WM5100_OUT2L_VOL_SHIFT
, 159, 0,
586 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L
,
587 WM5100_DAC_DIGITAL_VOLUME_3R
, WM5100_OUT3L_VOL_SHIFT
, 159, 0,
589 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L
,
590 WM5100_DAC_DIGITAL_VOLUME_4R
, WM5100_OUT4L_VOL_SHIFT
, 159, 0,
592 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L
,
593 WM5100_DAC_DIGITAL_VOLUME_5R
, WM5100_OUT5L_VOL_SHIFT
, 159, 0,
595 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L
,
596 WM5100_DAC_DIGITAL_VOLUME_6R
, WM5100_OUT6L_VOL_SHIFT
, 159, 0,
599 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L
,
600 WM5100_DAC_DIGITAL_VOLUME_1R
, WM5100_OUT1L_MUTE_SHIFT
, 1, 1),
601 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L
,
602 WM5100_DAC_DIGITAL_VOLUME_2R
, WM5100_OUT2L_MUTE_SHIFT
, 1, 1),
603 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L
,
604 WM5100_DAC_DIGITAL_VOLUME_3R
, WM5100_OUT3L_MUTE_SHIFT
, 1, 1),
605 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L
,
606 WM5100_DAC_DIGITAL_VOLUME_4R
, WM5100_OUT4L_MUTE_SHIFT
, 1, 1),
607 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L
,
608 WM5100_DAC_DIGITAL_VOLUME_5R
, WM5100_OUT5L_MUTE_SHIFT
, 1, 1),
609 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L
,
610 WM5100_DAC_DIGITAL_VOLUME_6R
, WM5100_OUT6L_MUTE_SHIFT
, 1, 1),
612 /* FIXME: Only valid from -12dB to 0dB (52-64) */
613 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L
, WM5100_OUT_VOLUME_1R
,
614 WM5100_OUT1L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
615 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L
, WM5100_OUT_VOLUME_2R
,
616 WM5100_OUT2L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
617 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L
, WM5100_OUT_VOLUME_3R
,
618 WM5100_OUT2L_PGA_VOL_SHIFT
, 64, 0, out_tlv
),
620 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1
, WM5100_SPK1L_MUTE_SHIFT
,
621 WM5100_SPK1R_MUTE_SHIFT
, 1, 1),
622 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1
, WM5100_SPK2L_MUTE_SHIFT
,
623 WM5100_SPK2R_MUTE_SHIFT
, 1, 1),
625 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1
, WM5100_EQ1_B1_GAIN_SHIFT
,
627 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1
, WM5100_EQ1_B2_GAIN_SHIFT
,
629 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1
, WM5100_EQ1_B3_GAIN_SHIFT
,
631 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2
, WM5100_EQ1_B4_GAIN_SHIFT
,
633 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2
, WM5100_EQ1_B5_GAIN_SHIFT
,
636 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1
, WM5100_EQ2_B1_GAIN_SHIFT
,
638 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1
, WM5100_EQ2_B2_GAIN_SHIFT
,
640 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1
, WM5100_EQ2_B3_GAIN_SHIFT
,
642 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2
, WM5100_EQ2_B4_GAIN_SHIFT
,
644 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2
, WM5100_EQ2_B5_GAIN_SHIFT
,
647 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1
, WM5100_EQ3_B1_GAIN_SHIFT
,
649 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1
, WM5100_EQ3_B2_GAIN_SHIFT
,
651 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1
, WM5100_EQ3_B3_GAIN_SHIFT
,
653 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2
, WM5100_EQ3_B4_GAIN_SHIFT
,
655 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2
, WM5100_EQ3_B5_GAIN_SHIFT
,
658 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1
, WM5100_EQ4_B1_GAIN_SHIFT
,
660 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1
, WM5100_EQ4_B2_GAIN_SHIFT
,
662 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1
, WM5100_EQ4_B3_GAIN_SHIFT
,
664 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2
, WM5100_EQ4_B4_GAIN_SHIFT
,
666 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2
, WM5100_EQ4_B5_GAIN_SHIFT
,
669 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode
),
670 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode
),
671 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode
),
672 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode
),
674 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE
),
675 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE
),
676 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE
),
677 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE
),
678 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE
),
679 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE
),
681 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE
),
682 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE
),
683 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE
),
684 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE
),
685 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE
),
686 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE
),
688 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE
),
689 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE
),
691 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE
),
692 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE
),
693 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE
),
694 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE
),
695 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE
),
696 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE
),
697 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE
),
698 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE
),
700 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE
),
701 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE
),
703 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE
),
704 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE
),
706 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE
),
707 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE
),
708 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE
),
709 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE
),
711 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE
),
712 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE
),
714 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE
),
715 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE
),
716 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE
),
717 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE
),
720 static void wm5100_seq_notifier(struct snd_soc_dapm_context
*dapm
,
721 enum snd_soc_dapm_type event
, int subseq
)
723 struct snd_soc_codec
*codec
= container_of(dapm
,
724 struct snd_soc_codec
, dapm
);
725 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
728 /* Wait for the outputs to flag themselves as enabled */
729 if (wm5100
->out_ena
[0]) {
730 expect
= snd_soc_read(codec
, WM5100_CHANNEL_ENABLES_1
);
731 for (i
= 0; i
< 200; i
++) {
732 val
= snd_soc_read(codec
, WM5100_OUTPUT_STATUS_1
);
734 wm5100
->out_ena
[0] = false;
739 dev_err(codec
->dev
, "Timeout waiting for OUTPUT1 %x\n",
744 if (wm5100
->out_ena
[1]) {
745 expect
= snd_soc_read(codec
, WM5100_OUTPUT_ENABLES_2
);
746 for (i
= 0; i
< 200; i
++) {
747 val
= snd_soc_read(codec
, WM5100_OUTPUT_STATUS_2
);
749 wm5100
->out_ena
[1] = false;
754 dev_err(codec
->dev
, "Timeout waiting for OUTPUT2 %x\n",
760 static int wm5100_out_ev(struct snd_soc_dapm_widget
*w
,
761 struct snd_kcontrol
*kcontrol
,
764 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(w
->codec
);
767 case WM5100_CHANNEL_ENABLES_1
:
768 wm5100
->out_ena
[0] = true;
770 case WM5100_OUTPUT_ENABLES_2
:
771 wm5100
->out_ena
[0] = true;
780 static int wm5100_cp_ev(struct snd_soc_dapm_widget
*w
,
781 struct snd_kcontrol
*kcontrol
,
784 struct snd_soc_codec
*codec
= w
->codec
;
785 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
789 case SND_SOC_DAPM_PRE_PMU
:
790 ret
= regulator_enable(wm5100
->cpvdd
);
792 dev_err(codec
->dev
, "Failed to enable CPVDD: %d\n",
798 case SND_SOC_DAPM_POST_PMD
:
799 ret
= regulator_disable_deferred(wm5100
->cpvdd
, 20);
801 dev_err(codec
->dev
, "Failed to disable CPVDD: %d\n",
813 static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget
*w
,
814 struct snd_kcontrol
*kcontrol
,
817 struct snd_soc_codec
*codec
= w
->codec
;
818 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
819 struct regulator
*regulator
;
824 regulator
= wm5100
->dbvdd2
;
827 regulator
= wm5100
->dbvdd3
;
835 case SND_SOC_DAPM_PRE_PMU
:
836 ret
= regulator_enable(regulator
);
838 dev_err(codec
->dev
, "Failed to enable DBVDD%d: %d\n",
844 case SND_SOC_DAPM_POST_PMD
:
845 ret
= regulator_disable(regulator
);
847 dev_err(codec
->dev
, "Failed to enable DBVDD%d: %d\n",
859 static void wm5100_log_status3(struct wm5100_priv
*wm5100
, int val
)
861 if (val
& WM5100_SPK_SHUTDOWN_WARN_EINT
)
862 dev_crit(wm5100
->dev
, "Speaker shutdown warning\n");
863 if (val
& WM5100_SPK_SHUTDOWN_EINT
)
864 dev_crit(wm5100
->dev
, "Speaker shutdown\n");
865 if (val
& WM5100_CLKGEN_ERR_EINT
)
866 dev_crit(wm5100
->dev
, "SYSCLK underclocked\n");
867 if (val
& WM5100_CLKGEN_ERR_ASYNC_EINT
)
868 dev_crit(wm5100
->dev
, "ASYNCCLK underclocked\n");
871 static void wm5100_log_status4(struct wm5100_priv
*wm5100
, int val
)
873 if (val
& WM5100_AIF3_ERR_EINT
)
874 dev_err(wm5100
->dev
, "AIF3 configuration error\n");
875 if (val
& WM5100_AIF2_ERR_EINT
)
876 dev_err(wm5100
->dev
, "AIF2 configuration error\n");
877 if (val
& WM5100_AIF1_ERR_EINT
)
878 dev_err(wm5100
->dev
, "AIF1 configuration error\n");
879 if (val
& WM5100_CTRLIF_ERR_EINT
)
880 dev_err(wm5100
->dev
, "Control interface error\n");
881 if (val
& WM5100_ISRC2_UNDERCLOCKED_EINT
)
882 dev_err(wm5100
->dev
, "ISRC2 underclocked\n");
883 if (val
& WM5100_ISRC1_UNDERCLOCKED_EINT
)
884 dev_err(wm5100
->dev
, "ISRC1 underclocked\n");
885 if (val
& WM5100_FX_UNDERCLOCKED_EINT
)
886 dev_err(wm5100
->dev
, "FX underclocked\n");
887 if (val
& WM5100_AIF3_UNDERCLOCKED_EINT
)
888 dev_err(wm5100
->dev
, "AIF3 underclocked\n");
889 if (val
& WM5100_AIF2_UNDERCLOCKED_EINT
)
890 dev_err(wm5100
->dev
, "AIF2 underclocked\n");
891 if (val
& WM5100_AIF1_UNDERCLOCKED_EINT
)
892 dev_err(wm5100
->dev
, "AIF1 underclocked\n");
893 if (val
& WM5100_ASRC_UNDERCLOCKED_EINT
)
894 dev_err(wm5100
->dev
, "ASRC underclocked\n");
895 if (val
& WM5100_DAC_UNDERCLOCKED_EINT
)
896 dev_err(wm5100
->dev
, "DAC underclocked\n");
897 if (val
& WM5100_ADC_UNDERCLOCKED_EINT
)
898 dev_err(wm5100
->dev
, "ADC underclocked\n");
899 if (val
& WM5100_MIXER_UNDERCLOCKED_EINT
)
900 dev_err(wm5100
->dev
, "Mixer underclocked\n");
903 static int wm5100_post_ev(struct snd_soc_dapm_widget
*w
,
904 struct snd_kcontrol
*kcontrol
,
907 struct snd_soc_codec
*codec
= w
->codec
;
908 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
911 ret
= snd_soc_read(codec
, WM5100_INTERRUPT_RAW_STATUS_3
);
912 ret
&= WM5100_SPK_SHUTDOWN_WARN_STS
|
913 WM5100_SPK_SHUTDOWN_STS
| WM5100_CLKGEN_ERR_STS
|
914 WM5100_CLKGEN_ERR_ASYNC_STS
;
915 wm5100_log_status3(wm5100
, ret
);
917 ret
= snd_soc_read(codec
, WM5100_INTERRUPT_RAW_STATUS_4
);
918 wm5100_log_status4(wm5100
, ret
);
923 static const struct snd_soc_dapm_widget wm5100_dapm_widgets
[] = {
924 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3
, WM5100_SYSCLK_ENA_SHIFT
, 0,
926 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6
, WM5100_ASYNC_CLK_ENA_SHIFT
,
929 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1
, WM5100_CP1_ENA_SHIFT
, 0,
931 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
932 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1
, WM5100_CP2_ENA_SHIFT
, 0,
934 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1
,
935 WM5100_CP2_BYPASS_SHIFT
, 1, wm5100_cp_ev
,
936 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
937 SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM
, 2, 0, wm5100_dbvdd_ev
,
938 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
939 SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM
, 3, 0, wm5100_dbvdd_ev
,
940 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
942 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1
, WM5100_MICB1_ENA_SHIFT
,
944 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2
, WM5100_MICB2_ENA_SHIFT
,
946 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3
, WM5100_MICB3_ENA_SHIFT
,
949 SND_SOC_DAPM_INPUT("IN1L"),
950 SND_SOC_DAPM_INPUT("IN1R"),
951 SND_SOC_DAPM_INPUT("IN2L"),
952 SND_SOC_DAPM_INPUT("IN2R"),
953 SND_SOC_DAPM_INPUT("IN3L"),
954 SND_SOC_DAPM_INPUT("IN3R"),
955 SND_SOC_DAPM_INPUT("IN4L"),
956 SND_SOC_DAPM_INPUT("IN4R"),
957 SND_SOC_DAPM_SIGGEN("TONE"),
959 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES
, WM5100_IN1L_ENA_SHIFT
, 0,
960 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
961 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES
, WM5100_IN1R_ENA_SHIFT
, 0,
962 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
963 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES
, WM5100_IN2L_ENA_SHIFT
, 0,
964 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
965 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES
, WM5100_IN2R_ENA_SHIFT
, 0,
966 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
967 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES
, WM5100_IN3L_ENA_SHIFT
, 0,
968 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
969 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES
, WM5100_IN3R_ENA_SHIFT
, 0,
970 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
971 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES
, WM5100_IN4L_ENA_SHIFT
, 0,
972 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
973 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES
, WM5100_IN4R_ENA_SHIFT
, 0,
974 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
976 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1
,
977 WM5100_TONE1_ENA_SHIFT
, 0, NULL
, 0),
978 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1
,
979 WM5100_TONE2_ENA_SHIFT
, 0, NULL
, 0),
981 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
982 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX1_ENA_SHIFT
, 0),
983 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
984 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX2_ENA_SHIFT
, 0),
985 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
986 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX3_ENA_SHIFT
, 0),
987 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
988 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX4_ENA_SHIFT
, 0),
989 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
990 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX5_ENA_SHIFT
, 0),
991 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
992 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX6_ENA_SHIFT
, 0),
993 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
994 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX7_ENA_SHIFT
, 0),
995 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
996 WM5100_AUDIO_IF_1_27
, WM5100_AIF1RX8_ENA_SHIFT
, 0),
998 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
999 WM5100_AUDIO_IF_2_27
, WM5100_AIF2RX1_ENA_SHIFT
, 0),
1000 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1001 WM5100_AUDIO_IF_2_27
, WM5100_AIF2RX2_ENA_SHIFT
, 0),
1003 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1004 WM5100_AUDIO_IF_3_27
, WM5100_AIF3RX1_ENA_SHIFT
, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1006 WM5100_AUDIO_IF_3_27
, WM5100_AIF3RX2_ENA_SHIFT
, 0),
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1009 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX1_ENA_SHIFT
, 0),
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1011 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX2_ENA_SHIFT
, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1013 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX3_ENA_SHIFT
, 0),
1014 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1015 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX4_ENA_SHIFT
, 0),
1016 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1017 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX5_ENA_SHIFT
, 0),
1018 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1019 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX6_ENA_SHIFT
, 0),
1020 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1021 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX7_ENA_SHIFT
, 0),
1022 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1023 WM5100_AUDIO_IF_1_26
, WM5100_AIF1TX8_ENA_SHIFT
, 0),
1025 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1026 WM5100_AUDIO_IF_2_26
, WM5100_AIF2TX1_ENA_SHIFT
, 0),
1027 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1028 WM5100_AUDIO_IF_2_26
, WM5100_AIF2TX2_ENA_SHIFT
, 0),
1030 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1031 WM5100_AUDIO_IF_3_26
, WM5100_AIF3TX1_ENA_SHIFT
, 0),
1032 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1033 WM5100_AUDIO_IF_3_26
, WM5100_AIF3TX2_ENA_SHIFT
, 0),
1035 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT6L_ENA_SHIFT
, 0,
1036 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1037 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT6R_ENA_SHIFT
, 0,
1038 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1039 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT5L_ENA_SHIFT
, 0,
1040 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1041 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT5R_ENA_SHIFT
, 0,
1042 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1043 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT4L_ENA_SHIFT
, 0,
1044 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1045 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2
, WM5100_OUT4R_ENA_SHIFT
, 0,
1046 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1047 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP3L_ENA_SHIFT
, 0,
1048 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1049 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP3R_ENA_SHIFT
, 0,
1050 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1051 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP2L_ENA_SHIFT
, 0,
1052 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1053 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP2R_ENA_SHIFT
, 0,
1054 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1055 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1
, WM5100_HP1L_ENA_SHIFT
, 0,
1056 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1057 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1
, WM5100_HP1R_ENA_SHIFT
, 0,
1058 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1059 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1
, WM5100_PWM1_ENA_SHIFT
, 0,
1060 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1061 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1
, WM5100_PWM2_ENA_SHIFT
, 0,
1062 NULL
, 0, wm5100_out_ev
, SND_SOC_DAPM_POST_PMU
),
1064 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1
, WM5100_EQ1_ENA_SHIFT
, 0, NULL
, 0),
1065 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1
, WM5100_EQ2_ENA_SHIFT
, 0, NULL
, 0),
1066 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1
, WM5100_EQ3_ENA_SHIFT
, 0, NULL
, 0),
1067 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1
, WM5100_EQ4_ENA_SHIFT
, 0, NULL
, 0),
1069 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1
, WM5100_DRCL_ENA_SHIFT
, 0,
1071 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1
, WM5100_DRCR_ENA_SHIFT
, 0,
1074 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1
, WM5100_LHPF1_ENA_SHIFT
, 0,
1076 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1
, WM5100_LHPF2_ENA_SHIFT
, 0,
1078 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1
, WM5100_LHPF3_ENA_SHIFT
, 0,
1080 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1
, WM5100_LHPF4_ENA_SHIFT
, 0,
1083 WM5100_MIXER_WIDGETS(EQ1
, "EQ1"),
1084 WM5100_MIXER_WIDGETS(EQ2
, "EQ2"),
1085 WM5100_MIXER_WIDGETS(EQ3
, "EQ3"),
1086 WM5100_MIXER_WIDGETS(EQ4
, "EQ4"),
1088 WM5100_MIXER_WIDGETS(DRC1L
, "DRC1L"),
1089 WM5100_MIXER_WIDGETS(DRC1R
, "DRC1R"),
1091 WM5100_MIXER_WIDGETS(LHPF1
, "LHPF1"),
1092 WM5100_MIXER_WIDGETS(LHPF2
, "LHPF2"),
1093 WM5100_MIXER_WIDGETS(LHPF3
, "LHPF3"),
1094 WM5100_MIXER_WIDGETS(LHPF4
, "LHPF4"),
1096 WM5100_MIXER_WIDGETS(AIF1TX1
, "AIF1TX1"),
1097 WM5100_MIXER_WIDGETS(AIF1TX2
, "AIF1TX2"),
1098 WM5100_MIXER_WIDGETS(AIF1TX3
, "AIF1TX3"),
1099 WM5100_MIXER_WIDGETS(AIF1TX4
, "AIF1TX4"),
1100 WM5100_MIXER_WIDGETS(AIF1TX5
, "AIF1TX5"),
1101 WM5100_MIXER_WIDGETS(AIF1TX6
, "AIF1TX6"),
1102 WM5100_MIXER_WIDGETS(AIF1TX7
, "AIF1TX7"),
1103 WM5100_MIXER_WIDGETS(AIF1TX8
, "AIF1TX8"),
1105 WM5100_MIXER_WIDGETS(AIF2TX1
, "AIF2TX1"),
1106 WM5100_MIXER_WIDGETS(AIF2TX2
, "AIF2TX2"),
1108 WM5100_MIXER_WIDGETS(AIF3TX1
, "AIF3TX1"),
1109 WM5100_MIXER_WIDGETS(AIF3TX2
, "AIF3TX2"),
1111 WM5100_MIXER_WIDGETS(HPOUT1L
, "HPOUT1L"),
1112 WM5100_MIXER_WIDGETS(HPOUT1R
, "HPOUT1R"),
1113 WM5100_MIXER_WIDGETS(HPOUT2L
, "HPOUT2L"),
1114 WM5100_MIXER_WIDGETS(HPOUT2R
, "HPOUT2R"),
1115 WM5100_MIXER_WIDGETS(HPOUT3L
, "HPOUT3L"),
1116 WM5100_MIXER_WIDGETS(HPOUT3R
, "HPOUT3R"),
1118 WM5100_MIXER_WIDGETS(SPKOUTL
, "SPKOUTL"),
1119 WM5100_MIXER_WIDGETS(SPKOUTR
, "SPKOUTR"),
1120 WM5100_MIXER_WIDGETS(SPKDAT1L
, "SPKDAT1L"),
1121 WM5100_MIXER_WIDGETS(SPKDAT1R
, "SPKDAT1R"),
1122 WM5100_MIXER_WIDGETS(SPKDAT2L
, "SPKDAT2L"),
1123 WM5100_MIXER_WIDGETS(SPKDAT2R
, "SPKDAT2R"),
1125 WM5100_MIXER_WIDGETS(PWM1
, "PWM1"),
1126 WM5100_MIXER_WIDGETS(PWM2
, "PWM2"),
1128 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1129 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1130 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1131 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1132 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1133 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1134 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1135 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1136 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1137 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1138 SND_SOC_DAPM_OUTPUT("PWM1"),
1139 SND_SOC_DAPM_OUTPUT("PWM2"),
1142 /* We register a _POST event if we don't have IRQ support so we can
1143 * look at the error status from the CODEC - if we've got the IRQ
1144 * hooked up then we will get prompted to look by an interrupt.
1146 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq
[] = {
1147 SND_SOC_DAPM_POST("Post", wm5100_post_ev
),
1150 static const struct snd_soc_dapm_route wm5100_dapm_routes
[] = {
1151 { "IN1L", NULL
, "SYSCLK" },
1152 { "IN1R", NULL
, "SYSCLK" },
1153 { "IN2L", NULL
, "SYSCLK" },
1154 { "IN2R", NULL
, "SYSCLK" },
1155 { "IN3L", NULL
, "SYSCLK" },
1156 { "IN3R", NULL
, "SYSCLK" },
1157 { "IN4L", NULL
, "SYSCLK" },
1158 { "IN4R", NULL
, "SYSCLK" },
1160 { "OUT1L", NULL
, "SYSCLK" },
1161 { "OUT1R", NULL
, "SYSCLK" },
1162 { "OUT2L", NULL
, "SYSCLK" },
1163 { "OUT2R", NULL
, "SYSCLK" },
1164 { "OUT3L", NULL
, "SYSCLK" },
1165 { "OUT3R", NULL
, "SYSCLK" },
1166 { "OUT4L", NULL
, "SYSCLK" },
1167 { "OUT4R", NULL
, "SYSCLK" },
1168 { "OUT5L", NULL
, "SYSCLK" },
1169 { "OUT5R", NULL
, "SYSCLK" },
1170 { "OUT6L", NULL
, "SYSCLK" },
1171 { "OUT6R", NULL
, "SYSCLK" },
1173 { "AIF1RX1", NULL
, "SYSCLK" },
1174 { "AIF1RX2", NULL
, "SYSCLK" },
1175 { "AIF1RX3", NULL
, "SYSCLK" },
1176 { "AIF1RX4", NULL
, "SYSCLK" },
1177 { "AIF1RX5", NULL
, "SYSCLK" },
1178 { "AIF1RX6", NULL
, "SYSCLK" },
1179 { "AIF1RX7", NULL
, "SYSCLK" },
1180 { "AIF1RX8", NULL
, "SYSCLK" },
1182 { "AIF2RX1", NULL
, "SYSCLK" },
1183 { "AIF2RX1", NULL
, "DBVDD2" },
1184 { "AIF2RX2", NULL
, "SYSCLK" },
1185 { "AIF2RX2", NULL
, "DBVDD2" },
1187 { "AIF3RX1", NULL
, "SYSCLK" },
1188 { "AIF3RX1", NULL
, "DBVDD3" },
1189 { "AIF3RX2", NULL
, "SYSCLK" },
1190 { "AIF3RX2", NULL
, "DBVDD3" },
1192 { "AIF1TX1", NULL
, "SYSCLK" },
1193 { "AIF1TX2", NULL
, "SYSCLK" },
1194 { "AIF1TX3", NULL
, "SYSCLK" },
1195 { "AIF1TX4", NULL
, "SYSCLK" },
1196 { "AIF1TX5", NULL
, "SYSCLK" },
1197 { "AIF1TX6", NULL
, "SYSCLK" },
1198 { "AIF1TX7", NULL
, "SYSCLK" },
1199 { "AIF1TX8", NULL
, "SYSCLK" },
1201 { "AIF2TX1", NULL
, "SYSCLK" },
1202 { "AIF2TX1", NULL
, "DBVDD2" },
1203 { "AIF2TX2", NULL
, "SYSCLK" },
1204 { "AIF2TX2", NULL
, "DBVDD2" },
1206 { "AIF3TX1", NULL
, "SYSCLK" },
1207 { "AIF3TX1", NULL
, "DBVDD3" },
1208 { "AIF3TX2", NULL
, "SYSCLK" },
1209 { "AIF3TX2", NULL
, "DBVDD3" },
1211 { "MICBIAS1", NULL
, "CP2" },
1212 { "MICBIAS2", NULL
, "CP2" },
1213 { "MICBIAS3", NULL
, "CP2" },
1215 { "IN1L PGA", NULL
, "CP2" },
1216 { "IN1R PGA", NULL
, "CP2" },
1217 { "IN2L PGA", NULL
, "CP2" },
1218 { "IN2R PGA", NULL
, "CP2" },
1219 { "IN3L PGA", NULL
, "CP2" },
1220 { "IN3R PGA", NULL
, "CP2" },
1221 { "IN4L PGA", NULL
, "CP2" },
1222 { "IN4R PGA", NULL
, "CP2" },
1224 { "IN1L PGA", NULL
, "CP2 Active" },
1225 { "IN1R PGA", NULL
, "CP2 Active" },
1226 { "IN2L PGA", NULL
, "CP2 Active" },
1227 { "IN2R PGA", NULL
, "CP2 Active" },
1228 { "IN3L PGA", NULL
, "CP2 Active" },
1229 { "IN3R PGA", NULL
, "CP2 Active" },
1230 { "IN4L PGA", NULL
, "CP2 Active" },
1231 { "IN4R PGA", NULL
, "CP2 Active" },
1233 { "OUT1L", NULL
, "CP1" },
1234 { "OUT1R", NULL
, "CP1" },
1235 { "OUT2L", NULL
, "CP1" },
1236 { "OUT2R", NULL
, "CP1" },
1237 { "OUT3L", NULL
, "CP1" },
1238 { "OUT3R", NULL
, "CP1" },
1240 { "Tone Generator 1", NULL
, "TONE" },
1241 { "Tone Generator 2", NULL
, "TONE" },
1243 { "IN1L PGA", NULL
, "IN1L" },
1244 { "IN1R PGA", NULL
, "IN1R" },
1245 { "IN2L PGA", NULL
, "IN2L" },
1246 { "IN2R PGA", NULL
, "IN2R" },
1247 { "IN3L PGA", NULL
, "IN3L" },
1248 { "IN3R PGA", NULL
, "IN3R" },
1249 { "IN4L PGA", NULL
, "IN4L" },
1250 { "IN4R PGA", NULL
, "IN4R" },
1252 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1253 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1254 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1255 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1256 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1257 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1259 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1260 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1261 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1262 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1263 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1264 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1266 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1267 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1269 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1270 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1271 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1272 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1273 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1274 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1275 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1276 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1278 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1279 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1281 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1282 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1284 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1285 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1286 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1287 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1289 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1290 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1292 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1293 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1294 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1295 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1297 { "HPOUT1L", NULL
, "OUT1L" },
1298 { "HPOUT1R", NULL
, "OUT1R" },
1299 { "HPOUT2L", NULL
, "OUT2L" },
1300 { "HPOUT2R", NULL
, "OUT2R" },
1301 { "HPOUT3L", NULL
, "OUT3L" },
1302 { "HPOUT3R", NULL
, "OUT3R" },
1303 { "SPKOUTL", NULL
, "OUT4L" },
1304 { "SPKOUTR", NULL
, "OUT4R" },
1305 { "SPKDAT1", NULL
, "OUT5L" },
1306 { "SPKDAT1", NULL
, "OUT5R" },
1307 { "SPKDAT2", NULL
, "OUT6L" },
1308 { "SPKDAT2", NULL
, "OUT6R" },
1309 { "PWM1", NULL
, "PWM1 Driver" },
1310 { "PWM2", NULL
, "PWM2 Driver" },
1313 static const __devinitdata
struct reg_default wm5100_reva_patches
[] = {
1314 { WM5100_AUDIO_IF_1_10
, 0 },
1315 { WM5100_AUDIO_IF_1_11
, 1 },
1316 { WM5100_AUDIO_IF_1_12
, 2 },
1317 { WM5100_AUDIO_IF_1_13
, 3 },
1318 { WM5100_AUDIO_IF_1_14
, 4 },
1319 { WM5100_AUDIO_IF_1_15
, 5 },
1320 { WM5100_AUDIO_IF_1_16
, 6 },
1321 { WM5100_AUDIO_IF_1_17
, 7 },
1323 { WM5100_AUDIO_IF_1_18
, 0 },
1324 { WM5100_AUDIO_IF_1_19
, 1 },
1325 { WM5100_AUDIO_IF_1_20
, 2 },
1326 { WM5100_AUDIO_IF_1_21
, 3 },
1327 { WM5100_AUDIO_IF_1_22
, 4 },
1328 { WM5100_AUDIO_IF_1_23
, 5 },
1329 { WM5100_AUDIO_IF_1_24
, 6 },
1330 { WM5100_AUDIO_IF_1_25
, 7 },
1332 { WM5100_AUDIO_IF_2_10
, 0 },
1333 { WM5100_AUDIO_IF_2_11
, 1 },
1335 { WM5100_AUDIO_IF_2_18
, 0 },
1336 { WM5100_AUDIO_IF_2_19
, 1 },
1338 { WM5100_AUDIO_IF_3_10
, 0 },
1339 { WM5100_AUDIO_IF_3_11
, 1 },
1341 { WM5100_AUDIO_IF_3_18
, 0 },
1342 { WM5100_AUDIO_IF_3_19
, 1 },
1345 static int wm5100_set_bias_level(struct snd_soc_codec
*codec
,
1346 enum snd_soc_bias_level level
)
1348 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1352 case SND_SOC_BIAS_ON
:
1355 case SND_SOC_BIAS_PREPARE
:
1358 case SND_SOC_BIAS_STANDBY
:
1359 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1360 ret
= regulator_bulk_enable(ARRAY_SIZE(wm5100
->core_supplies
),
1361 wm5100
->core_supplies
);
1364 "Failed to enable supplies: %d\n",
1369 if (wm5100
->pdata
.ldo_ena
) {
1370 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
,
1375 regcache_cache_only(wm5100
->regmap
, false);
1376 regcache_sync(wm5100
->regmap
);
1380 case SND_SOC_BIAS_OFF
:
1381 regcache_cache_only(wm5100
->regmap
, true);
1382 if (wm5100
->pdata
.ldo_ena
)
1383 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
1384 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
1385 wm5100
->core_supplies
);
1388 codec
->dapm
.bias_level
= level
;
1393 static int wm5100_dai_to_base(struct snd_soc_dai
*dai
)
1397 return WM5100_AUDIO_IF_1_1
- 1;
1399 return WM5100_AUDIO_IF_2_1
- 1;
1401 return WM5100_AUDIO_IF_3_1
- 1;
1408 static int wm5100_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1410 struct snd_soc_codec
*codec
= dai
->codec
;
1411 int lrclk
, bclk
, mask
, base
;
1413 base
= wm5100_dai_to_base(dai
);
1420 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1421 case SND_SOC_DAIFMT_DSP_A
:
1424 case SND_SOC_DAIFMT_DSP_B
:
1427 case SND_SOC_DAIFMT_I2S
:
1430 case SND_SOC_DAIFMT_LEFT_J
:
1434 dev_err(codec
->dev
, "Unsupported DAI format %d\n",
1435 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1439 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1440 case SND_SOC_DAIFMT_CBS_CFS
:
1442 case SND_SOC_DAIFMT_CBS_CFM
:
1443 lrclk
|= WM5100_AIF1TX_LRCLK_MSTR
;
1445 case SND_SOC_DAIFMT_CBM_CFS
:
1446 bclk
|= WM5100_AIF1_BCLK_MSTR
;
1448 case SND_SOC_DAIFMT_CBM_CFM
:
1449 lrclk
|= WM5100_AIF1TX_LRCLK_MSTR
;
1450 bclk
|= WM5100_AIF1_BCLK_MSTR
;
1453 dev_err(codec
->dev
, "Unsupported master mode %d\n",
1454 fmt
& SND_SOC_DAIFMT_MASTER_MASK
);
1458 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1459 case SND_SOC_DAIFMT_NB_NF
:
1461 case SND_SOC_DAIFMT_IB_IF
:
1462 bclk
|= WM5100_AIF1_BCLK_INV
;
1463 lrclk
|= WM5100_AIF1TX_LRCLK_INV
;
1465 case SND_SOC_DAIFMT_IB_NF
:
1466 bclk
|= WM5100_AIF1_BCLK_INV
;
1468 case SND_SOC_DAIFMT_NB_IF
:
1469 lrclk
|= WM5100_AIF1TX_LRCLK_INV
;
1475 snd_soc_update_bits(codec
, base
+ 1, WM5100_AIF1_BCLK_MSTR
|
1476 WM5100_AIF1_BCLK_INV
, bclk
);
1477 snd_soc_update_bits(codec
, base
+ 2, WM5100_AIF1TX_LRCLK_MSTR
|
1478 WM5100_AIF1TX_LRCLK_INV
, lrclk
);
1479 snd_soc_update_bits(codec
, base
+ 3, WM5100_AIF1TX_LRCLK_MSTR
|
1480 WM5100_AIF1TX_LRCLK_INV
, lrclk
);
1481 snd_soc_update_bits(codec
, base
+ 5, WM5100_AIF1_FMT_MASK
, mask
);
1486 #define WM5100_NUM_BCLK_RATES 19
1488 static int wm5100_bclk_rates_dat
[WM5100_NUM_BCLK_RATES
] = {
1510 static int wm5100_bclk_rates_cd
[WM5100_NUM_BCLK_RATES
] = {
1532 static int wm5100_hw_params(struct snd_pcm_substream
*substream
,
1533 struct snd_pcm_hw_params
*params
,
1534 struct snd_soc_dai
*dai
)
1536 struct snd_soc_codec
*codec
= dai
->codec
;
1537 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1538 bool async
= wm5100
->aif_async
[dai
->id
];
1539 int i
, base
, bclk
, aif_rate
, lrclk
, wl
, fl
, sr
;
1542 base
= wm5100_dai_to_base(dai
);
1546 /* Data sizes if not using TDM */
1547 wl
= snd_pcm_format_width(params_format(params
));
1550 fl
= snd_soc_params_to_frame_size(params
);
1554 dev_dbg(codec
->dev
, "Word length %d bits, frame length %d bits\n",
1557 /* Target BCLK rate */
1558 bclk
= snd_soc_params_to_bclk(params
);
1562 /* Root for BCLK depends on SYS/ASYNCCLK */
1564 aif_rate
= wm5100
->sysclk
;
1565 sr
= wm5100_alloc_sr(codec
, params_rate(params
));
1569 /* If we're in ASYNCCLK set the ASYNC sample rate */
1570 aif_rate
= wm5100
->asyncclk
;
1573 for (i
= 0; i
< ARRAY_SIZE(wm5100_sr_code
); i
++)
1574 if (params_rate(params
) == wm5100_sr_code
[i
])
1576 if (i
== ARRAY_SIZE(wm5100_sr_code
)) {
1577 dev_err(codec
->dev
, "Invalid rate %dHzn",
1578 params_rate(params
));
1582 /* TODO: We should really check for symmetry */
1583 snd_soc_update_bits(codec
, WM5100_CLOCKING_8
,
1584 WM5100_ASYNC_SAMPLE_RATE_MASK
, i
);
1588 dev_err(codec
->dev
, "%s has no rate set\n",
1589 async
? "ASYNCCLK" : "SYSCLK");
1593 dev_dbg(codec
->dev
, "Target BCLK is %dHz, using %dHz %s\n",
1594 bclk
, aif_rate
, async
? "ASYNCCLK" : "SYSCLK");
1596 if (aif_rate
% 4000)
1597 bclk_rates
= wm5100_bclk_rates_cd
;
1599 bclk_rates
= wm5100_bclk_rates_dat
;
1601 for (i
= 0; i
< WM5100_NUM_BCLK_RATES
; i
++)
1602 if (bclk_rates
[i
] >= bclk
&& (bclk_rates
[i
] % bclk
== 0))
1604 if (i
== WM5100_NUM_BCLK_RATES
) {
1606 "No valid BCLK for %dHz found from %dHz %s\n",
1607 bclk
, aif_rate
, async
? "ASYNCCLK" : "SYSCLK");
1612 dev_dbg(codec
->dev
, "Setting %dHz BCLK\n", bclk_rates
[bclk
]);
1613 snd_soc_update_bits(codec
, base
+ 1, WM5100_AIF1_BCLK_FREQ_MASK
, bclk
);
1615 lrclk
= bclk_rates
[bclk
] / params_rate(params
);
1616 dev_dbg(codec
->dev
, "Setting %dHz LRCLK\n", bclk_rates
[bclk
] / lrclk
);
1617 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1618 wm5100
->aif_symmetric
[dai
->id
])
1619 snd_soc_update_bits(codec
, base
+ 7,
1620 WM5100_AIF1RX_BCPF_MASK
, lrclk
);
1622 snd_soc_update_bits(codec
, base
+ 6,
1623 WM5100_AIF1TX_BCPF_MASK
, lrclk
);
1625 i
= (wl
<< WM5100_AIF1TX_WL_SHIFT
) | fl
;
1626 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1627 snd_soc_update_bits(codec
, base
+ 9,
1628 WM5100_AIF1RX_WL_MASK
|
1629 WM5100_AIF1RX_SLOT_LEN_MASK
, i
);
1631 snd_soc_update_bits(codec
, base
+ 8,
1632 WM5100_AIF1TX_WL_MASK
|
1633 WM5100_AIF1TX_SLOT_LEN_MASK
, i
);
1635 snd_soc_update_bits(codec
, base
+ 4, WM5100_AIF1_RATE_MASK
, sr
);
1640 static const struct snd_soc_dai_ops wm5100_dai_ops
= {
1641 .set_fmt
= wm5100_set_fmt
,
1642 .hw_params
= wm5100_hw_params
,
1645 static int wm5100_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
1646 int source
, unsigned int freq
, int dir
)
1648 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1650 int fval
, audio_rate
, ret
, reg
;
1653 case WM5100_CLK_SYSCLK
:
1654 reg
= WM5100_CLOCKING_3
;
1655 rate_store
= &wm5100
->sysclk
;
1657 case WM5100_CLK_ASYNCCLK
:
1658 reg
= WM5100_CLOCKING_7
;
1659 rate_store
= &wm5100
->asyncclk
;
1661 case WM5100_CLK_32KHZ
:
1662 /* The 32kHz clock is slightly different to the others */
1664 case WM5100_CLKSRC_MCLK1
:
1665 case WM5100_CLKSRC_MCLK2
:
1666 case WM5100_CLKSRC_SYSCLK
:
1667 snd_soc_update_bits(codec
, WM5100_CLOCKING_1
,
1668 WM5100_CLK_32K_SRC_MASK
,
1676 case WM5100_CLK_AIF1
:
1677 case WM5100_CLK_AIF2
:
1678 case WM5100_CLK_AIF3
:
1679 /* Not real clocks, record which clock domain they're in */
1681 case WM5100_CLKSRC_SYSCLK
:
1682 wm5100
->aif_async
[clk_id
- 1] = false;
1684 case WM5100_CLKSRC_ASYNCCLK
:
1685 wm5100
->aif_async
[clk_id
- 1] = true;
1688 dev_err(codec
->dev
, "Invalid source %d\n", source
);
1693 case WM5100_CLK_OPCLK
:
1697 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1698 WM5100_OPCLK_SEL_MASK
, 0);
1702 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1703 WM5100_OPCLK_SEL_MASK
, 0);
1707 snd_soc_update_bits(codec
, WM5100_MISC_GPIO_1
,
1708 WM5100_OPCLK_SEL_MASK
, 0);
1711 dev_err(codec
->dev
, "Unsupported OPCLK %dHz\n",
1718 dev_err(codec
->dev
, "Unknown clock %d\n", clk_id
);
1723 case WM5100_CLKSRC_SYSCLK
:
1724 case WM5100_CLKSRC_ASYNCCLK
:
1725 dev_err(codec
->dev
, "Invalid source %d\n", source
);
1743 dev_err(codec
->dev
, "Invalid clock rate: %d\n", freq
);
1766 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1770 snd_soc_update_bits(codec
, reg
, WM5100_SYSCLK_FREQ_MASK
|
1771 WM5100_SYSCLK_SRC_MASK
,
1772 fval
<< WM5100_SYSCLK_FREQ_SHIFT
| source
);
1774 /* If this is SYSCLK then configure the clock rate for the
1775 * internal audio functions to the natural sample rate for
1778 if (clk_id
== WM5100_CLK_SYSCLK
) {
1779 dev_dbg(codec
->dev
, "Setting primary audio rate to %dHz",
1781 if (0 && *rate_store
)
1782 wm5100_free_sr(codec
, audio_rate
);
1783 ret
= wm5100_alloc_sr(codec
, audio_rate
);
1785 dev_warn(codec
->dev
, "Primary audio slot is %d\n",
1809 { 0, 64000, 4, 16 },
1810 { 64000, 128000, 3, 8 },
1811 { 128000, 256000, 2, 4 },
1812 { 256000, 1000000, 1, 2 },
1813 { 1000000, 13500000, 0, 1 },
1816 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
1819 unsigned int target
;
1821 unsigned int fratio
, gcd_fll
;
1824 /* Fref must be <=13.5MHz */
1826 fll_div
->fll_refclk_div
= 0;
1827 while ((Fref
/ div
) > 13500000) {
1829 fll_div
->fll_refclk_div
++;
1832 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1838 pr_debug("FLL Fref=%u Fout=%u\n", Fref
, Fout
);
1840 /* Apply the division for our remaining calculations */
1843 /* Fvco should be 90-100MHz; don't check the upper bound */
1845 while (Fout
* div
< 90000000) {
1848 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1853 target
= Fout
* div
;
1854 fll_div
->fll_outdiv
= div
- 1;
1856 pr_debug("FLL Fvco=%dHz\n", target
);
1858 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1859 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1860 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1861 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
1862 fratio
= fll_fratios
[i
].ratio
;
1866 if (i
== ARRAY_SIZE(fll_fratios
)) {
1867 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
1871 fll_div
->n
= target
/ (fratio
* Fref
);
1873 if (target
% Fref
== 0) {
1875 fll_div
->lambda
= 0;
1877 gcd_fll
= gcd(target
, fratio
* Fref
);
1879 fll_div
->theta
= (target
- (fll_div
->n
* fratio
* Fref
))
1881 fll_div
->lambda
= (fratio
* Fref
) / gcd_fll
;
1884 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1885 fll_div
->n
, fll_div
->theta
, fll_div
->lambda
);
1886 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1887 fll_div
->fll_fratio
, fratio
, fll_div
->fll_outdiv
,
1888 fll_div
->fll_refclk_div
);
1893 static int wm5100_set_fll(struct snd_soc_codec
*codec
, int fll_id
, int source
,
1894 unsigned int Fref
, unsigned int Fout
)
1896 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
1897 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
1898 struct _fll_div factors
;
1899 struct wm5100_fll
*fll
;
1900 int ret
, base
, lock
, i
, timeout
;
1904 fll
= &wm5100
->fll
[0];
1905 base
= WM5100_FLL1_CONTROL_1
- 1;
1906 lock
= WM5100_FLL1_LOCK_STS
;
1909 fll
= &wm5100
->fll
[1];
1910 base
= WM5100_FLL2_CONTROL_2
- 1;
1911 lock
= WM5100_FLL2_LOCK_STS
;
1914 dev_err(codec
->dev
, "Unknown FLL %d\n",fll_id
);
1919 dev_dbg(codec
->dev
, "FLL%d disabled", fll_id
);
1921 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, 0);
1926 case WM5100_FLL_SRC_MCLK1
:
1927 case WM5100_FLL_SRC_MCLK2
:
1928 case WM5100_FLL_SRC_FLL1
:
1929 case WM5100_FLL_SRC_FLL2
:
1930 case WM5100_FLL_SRC_AIF1BCLK
:
1931 case WM5100_FLL_SRC_AIF2BCLK
:
1932 case WM5100_FLL_SRC_AIF3BCLK
:
1935 dev_err(codec
->dev
, "Invalid FLL source %d\n", source
);
1939 ret
= fll_factors(&factors
, Fref
, Fout
);
1943 /* Disable the FLL while we reconfigure */
1944 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, 0);
1946 snd_soc_update_bits(codec
, base
+ 2,
1947 WM5100_FLL1_OUTDIV_MASK
| WM5100_FLL1_FRATIO_MASK
,
1948 (factors
.fll_outdiv
<< WM5100_FLL1_OUTDIV_SHIFT
) |
1949 factors
.fll_fratio
);
1950 snd_soc_update_bits(codec
, base
+ 3, WM5100_FLL1_THETA_MASK
,
1952 snd_soc_update_bits(codec
, base
+ 5, WM5100_FLL1_N_MASK
, factors
.n
);
1953 snd_soc_update_bits(codec
, base
+ 6,
1954 WM5100_FLL1_REFCLK_DIV_MASK
|
1955 WM5100_FLL1_REFCLK_SRC_MASK
,
1956 (factors
.fll_refclk_div
1957 << WM5100_FLL1_REFCLK_DIV_SHIFT
) | source
);
1958 snd_soc_update_bits(codec
, base
+ 7, WM5100_FLL1_LAMBDA_MASK
,
1961 /* Clear any pending completions */
1962 try_wait_for_completion(&fll
->lock
);
1964 snd_soc_update_bits(codec
, base
+ 1, WM5100_FLL1_ENA
, WM5100_FLL1_ENA
);
1971 snd_soc_update_bits(codec
, WM5100_CLOCKING_3
, WM5100_SYSCLK_ENA
,
1974 /* Poll for the lock; will use interrupt when we can test */
1975 for (i
= 0; i
< timeout
; i
++) {
1977 ret
= wait_for_completion_timeout(&fll
->lock
,
1978 msecs_to_jiffies(25));
1985 ret
= snd_soc_read(codec
,
1986 WM5100_INTERRUPT_RAW_STATUS_3
);
1989 "Failed to read FLL status: %d\n",
1997 dev_err(codec
->dev
, "FLL%d lock timed out\n", fll_id
);
2005 dev_dbg(codec
->dev
, "FLL%d running %dHz->%dHz\n", fll_id
,
2011 /* Actually go much higher */
2012 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2014 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2015 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2017 static struct snd_soc_dai_driver wm5100_dai
[] = {
2019 .name
= "wm5100-aif1",
2021 .stream_name
= "AIF1 Playback",
2024 .rates
= WM5100_RATES
,
2025 .formats
= WM5100_FORMATS
,
2028 .stream_name
= "AIF1 Capture",
2031 .rates
= WM5100_RATES
,
2032 .formats
= WM5100_FORMATS
,
2034 .ops
= &wm5100_dai_ops
,
2037 .name
= "wm5100-aif2",
2040 .stream_name
= "AIF2 Playback",
2043 .rates
= WM5100_RATES
,
2044 .formats
= WM5100_FORMATS
,
2047 .stream_name
= "AIF2 Capture",
2050 .rates
= WM5100_RATES
,
2051 .formats
= WM5100_FORMATS
,
2053 .ops
= &wm5100_dai_ops
,
2056 .name
= "wm5100-aif3",
2059 .stream_name
= "AIF3 Playback",
2062 .rates
= WM5100_RATES
,
2063 .formats
= WM5100_FORMATS
,
2066 .stream_name
= "AIF3 Capture",
2069 .rates
= WM5100_RATES
,
2070 .formats
= WM5100_FORMATS
,
2072 .ops
= &wm5100_dai_ops
,
2076 static int wm5100_dig_vu
[] = {
2077 WM5100_ADC_DIGITAL_VOLUME_1L
,
2078 WM5100_ADC_DIGITAL_VOLUME_1R
,
2079 WM5100_ADC_DIGITAL_VOLUME_2L
,
2080 WM5100_ADC_DIGITAL_VOLUME_2R
,
2081 WM5100_ADC_DIGITAL_VOLUME_3L
,
2082 WM5100_ADC_DIGITAL_VOLUME_3R
,
2083 WM5100_ADC_DIGITAL_VOLUME_4L
,
2084 WM5100_ADC_DIGITAL_VOLUME_4R
,
2086 WM5100_DAC_DIGITAL_VOLUME_1L
,
2087 WM5100_DAC_DIGITAL_VOLUME_1R
,
2088 WM5100_DAC_DIGITAL_VOLUME_2L
,
2089 WM5100_DAC_DIGITAL_VOLUME_2R
,
2090 WM5100_DAC_DIGITAL_VOLUME_3L
,
2091 WM5100_DAC_DIGITAL_VOLUME_3R
,
2092 WM5100_DAC_DIGITAL_VOLUME_4L
,
2093 WM5100_DAC_DIGITAL_VOLUME_4R
,
2094 WM5100_DAC_DIGITAL_VOLUME_5L
,
2095 WM5100_DAC_DIGITAL_VOLUME_5R
,
2096 WM5100_DAC_DIGITAL_VOLUME_6L
,
2097 WM5100_DAC_DIGITAL_VOLUME_6R
,
2100 static void wm5100_set_detect_mode(struct wm5100_priv
*wm5100
, int the_mode
)
2102 struct wm5100_jack_mode
*mode
= &wm5100
->pdata
.jack_modes
[the_mode
];
2104 BUG_ON(the_mode
>= ARRAY_SIZE(wm5100
->pdata
.jack_modes
));
2106 gpio_set_value_cansleep(wm5100
->pdata
.hp_pol
, mode
->hp_pol
);
2107 regmap_update_bits(wm5100
->regmap
, WM5100_ACCESSORY_DETECT_MODE_1
,
2108 WM5100_ACCDET_BIAS_SRC_MASK
|
2110 (mode
->bias
<< WM5100_ACCDET_BIAS_SRC_SHIFT
) |
2111 mode
->micd_src
<< WM5100_ACCDET_SRC_SHIFT
);
2112 regmap_update_bits(wm5100
->regmap
, WM5100_MISC_CONTROL
,
2114 mode
->micd_src
<< WM5100_HPCOM_SRC_SHIFT
);
2116 wm5100
->jack_mode
= the_mode
;
2118 dev_dbg(wm5100
->dev
, "Set microphone polarity to %d\n",
2122 static void wm5100_micd_irq(struct wm5100_priv
*wm5100
)
2127 ret
= regmap_read(wm5100
->regmap
, WM5100_MIC_DETECT_3
, &val
);
2129 dev_err(wm5100
->dev
, "Failed to read micropone status: %d\n",
2134 dev_dbg(wm5100
->dev
, "Microphone event: %x\n", val
);
2136 if (!(val
& WM5100_ACCDET_VALID
)) {
2137 dev_warn(wm5100
->dev
, "Microphone detection state invalid\n");
2141 /* No accessory, reset everything and report removal */
2142 if (!(val
& WM5100_ACCDET_STS
)) {
2143 dev_dbg(wm5100
->dev
, "Jack removal detected\n");
2144 wm5100
->jack_mic
= false;
2145 wm5100
->jack_detecting
= true;
2146 snd_soc_jack_report(wm5100
->jack
, 0,
2147 SND_JACK_LINEOUT
| SND_JACK_HEADSET
|
2150 regmap_update_bits(wm5100
->regmap
, WM5100_MIC_DETECT_1
,
2151 WM5100_ACCDET_RATE_MASK
,
2152 WM5100_ACCDET_RATE_MASK
);
2156 /* If the measurement is very high we've got a microphone,
2157 * either we just detected one or if we already reported then
2158 * we've got a button release event.
2161 if (wm5100
->jack_detecting
) {
2162 dev_dbg(wm5100
->dev
, "Microphone detected\n");
2163 wm5100
->jack_mic
= true;
2164 snd_soc_jack_report(wm5100
->jack
,
2166 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2168 /* Increase poll rate to give better responsiveness
2170 regmap_update_bits(wm5100
->regmap
, WM5100_MIC_DETECT_1
,
2171 WM5100_ACCDET_RATE_MASK
,
2172 5 << WM5100_ACCDET_RATE_SHIFT
);
2174 dev_dbg(wm5100
->dev
, "Mic button up\n");
2175 snd_soc_jack_report(wm5100
->jack
, 0, SND_JACK_BTN_0
);
2181 /* If we detected a lower impedence during initial startup
2182 * then we probably have the wrong polarity, flip it. Don't
2183 * do this for the lowest impedences to speed up detection of
2186 if (wm5100
->jack_detecting
&& (val
& 0x3f8)) {
2187 wm5100_set_detect_mode(wm5100
, !wm5100
->jack_mode
);
2192 /* Don't distinguish between buttons, just report any low
2193 * impedence as BTN_0.
2196 if (wm5100
->jack_mic
) {
2197 dev_dbg(wm5100
->dev
, "Mic button detected\n");
2198 snd_soc_jack_report(wm5100
->jack
, SND_JACK_BTN_0
,
2200 } else if (wm5100
->jack_detecting
) {
2201 dev_dbg(wm5100
->dev
, "Headphone detected\n");
2202 snd_soc_jack_report(wm5100
->jack
, SND_JACK_HEADPHONE
,
2203 SND_JACK_HEADPHONE
);
2205 /* Increase the detection rate a bit for
2208 regmap_update_bits(wm5100
->regmap
, WM5100_MIC_DETECT_1
,
2209 WM5100_ACCDET_RATE_MASK
,
2210 7 << WM5100_ACCDET_RATE_SHIFT
);
2215 int wm5100_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
)
2217 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2220 wm5100
->jack
= jack
;
2221 wm5100
->jack_detecting
= true;
2223 wm5100_set_detect_mode(wm5100
, 0);
2225 /* Slowest detection rate, gives debounce for initial
2227 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2228 WM5100_ACCDET_BIAS_STARTTIME_MASK
|
2229 WM5100_ACCDET_RATE_MASK
,
2230 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT
) |
2231 WM5100_ACCDET_RATE_MASK
);
2233 /* We need the charge pump to power MICBIAS */
2234 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CP2");
2235 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "SYSCLK");
2236 snd_soc_dapm_sync(&codec
->dapm
);
2238 /* We start off just enabling microphone detection - even a
2239 * plain headphone will trigger detection.
2241 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2242 WM5100_ACCDET_ENA
, WM5100_ACCDET_ENA
);
2244 snd_soc_update_bits(codec
, WM5100_INTERRUPT_STATUS_3_MASK
,
2245 WM5100_IM_ACCDET_EINT
, 0);
2247 snd_soc_update_bits(codec
, WM5100_INTERRUPT_STATUS_3_MASK
,
2248 WM5100_IM_HPDET_EINT
|
2249 WM5100_IM_ACCDET_EINT
,
2250 WM5100_IM_HPDET_EINT
|
2251 WM5100_IM_ACCDET_EINT
);
2252 snd_soc_update_bits(codec
, WM5100_MIC_DETECT_1
,
2253 WM5100_ACCDET_ENA
, 0);
2254 wm5100
->jack
= NULL
;
2260 static irqreturn_t
wm5100_irq(int irq
, void *data
)
2262 struct wm5100_priv
*wm5100
= data
;
2263 irqreturn_t status
= IRQ_NONE
;
2264 unsigned int irq_val
, mask_val
;
2267 ret
= regmap_read(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_3
, &irq_val
);
2269 dev_err(wm5100
->dev
, "Failed to read IRQ status 3: %d\n",
2274 ret
= regmap_read(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_3_MASK
,
2277 dev_err(wm5100
->dev
, "Failed to read IRQ mask 3: %d\n",
2282 irq_val
&= ~mask_val
;
2284 regmap_write(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_3
, irq_val
);
2287 status
= IRQ_HANDLED
;
2289 wm5100_log_status3(wm5100
, irq_val
);
2291 if (irq_val
& WM5100_FLL1_LOCK_EINT
) {
2292 dev_dbg(wm5100
->dev
, "FLL1 locked\n");
2293 complete(&wm5100
->fll
[0].lock
);
2295 if (irq_val
& WM5100_FLL2_LOCK_EINT
) {
2296 dev_dbg(wm5100
->dev
, "FLL2 locked\n");
2297 complete(&wm5100
->fll
[1].lock
);
2300 if (irq_val
& WM5100_ACCDET_EINT
)
2301 wm5100_micd_irq(wm5100
);
2303 ret
= regmap_read(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_4
, &irq_val
);
2305 dev_err(wm5100
->dev
, "Failed to read IRQ status 4: %d\n",
2310 ret
= regmap_read(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_4_MASK
,
2313 dev_err(wm5100
->dev
, "Failed to read IRQ mask 4: %d\n",
2318 irq_val
&= ~mask_val
;
2321 status
= IRQ_HANDLED
;
2323 regmap_write(wm5100
->regmap
, WM5100_INTERRUPT_STATUS_4
, irq_val
);
2325 wm5100_log_status4(wm5100
, irq_val
);
2330 static irqreturn_t
wm5100_edge_irq(int irq
, void *data
)
2332 irqreturn_t ret
= IRQ_NONE
;
2336 val
= wm5100_irq(irq
, data
);
2337 if (val
!= IRQ_NONE
)
2339 } while (val
!= IRQ_NONE
);
2344 #ifdef CONFIG_GPIOLIB
2345 static inline struct wm5100_priv
*gpio_to_wm5100(struct gpio_chip
*chip
)
2347 return container_of(chip
, struct wm5100_priv
, gpio_chip
);
2350 static void wm5100_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
2352 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2354 regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2355 WM5100_GP1_LVL
, !!value
<< WM5100_GP1_LVL_SHIFT
);
2358 static int wm5100_gpio_direction_out(struct gpio_chip
*chip
,
2359 unsigned offset
, int value
)
2361 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2364 val
= (1 << WM5100_GP1_FN_SHIFT
) | (!!value
<< WM5100_GP1_LVL_SHIFT
);
2366 ret
= regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2367 WM5100_GP1_FN_MASK
| WM5100_GP1_DIR
|
2368 WM5100_GP1_LVL
, val
);
2375 static int wm5100_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
2377 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2381 ret
= regmap_read(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
, ®
);
2385 return (reg
& WM5100_GP1_LVL
) != 0;
2388 static int wm5100_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
2390 struct wm5100_priv
*wm5100
= gpio_to_wm5100(chip
);
2392 return regmap_update_bits(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ offset
,
2393 WM5100_GP1_FN_MASK
| WM5100_GP1_DIR
,
2394 (1 << WM5100_GP1_FN_SHIFT
) |
2395 (1 << WM5100_GP1_DIR_SHIFT
));
2398 static struct gpio_chip wm5100_template_chip
= {
2400 .owner
= THIS_MODULE
,
2401 .direction_output
= wm5100_gpio_direction_out
,
2402 .set
= wm5100_gpio_set
,
2403 .direction_input
= wm5100_gpio_direction_in
,
2404 .get
= wm5100_gpio_get
,
2408 static void wm5100_init_gpio(struct i2c_client
*i2c
)
2410 struct wm5100_priv
*wm5100
= i2c_get_clientdata(i2c
);
2413 wm5100
->gpio_chip
= wm5100_template_chip
;
2414 wm5100
->gpio_chip
.ngpio
= 6;
2415 wm5100
->gpio_chip
.dev
= &i2c
->dev
;
2417 if (wm5100
->pdata
.gpio_base
)
2418 wm5100
->gpio_chip
.base
= wm5100
->pdata
.gpio_base
;
2420 wm5100
->gpio_chip
.base
= -1;
2422 ret
= gpiochip_add(&wm5100
->gpio_chip
);
2424 dev_err(&i2c
->dev
, "Failed to add GPIOs: %d\n", ret
);
2427 static void wm5100_free_gpio(struct i2c_client
*i2c
)
2429 struct wm5100_priv
*wm5100
= i2c_get_clientdata(i2c
);
2432 ret
= gpiochip_remove(&wm5100
->gpio_chip
);
2434 dev_err(&i2c
->dev
, "Failed to remove GPIOs: %d\n", ret
);
2437 static void wm5100_init_gpio(struct i2c_client
*i2c
)
2441 static void wm5100_free_gpio(struct i2c_client
*i2c
)
2446 static int wm5100_probe(struct snd_soc_codec
*codec
)
2448 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2449 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2452 wm5100
->codec
= codec
;
2453 codec
->control_data
= wm5100
->regmap
;
2455 ret
= snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
2457 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2461 regcache_cache_only(wm5100
->regmap
, true);
2464 for (i
= 0; i
< ARRAY_SIZE(wm5100_dig_vu
); i
++)
2465 snd_soc_update_bits(codec
, wm5100_dig_vu
[i
], WM5100_OUT_VU
,
2468 /* Don't debounce interrupts to support use of SYSCLK only */
2469 snd_soc_write(codec
, WM5100_IRQ_DEBOUNCE_1
, 0);
2470 snd_soc_write(codec
, WM5100_IRQ_DEBOUNCE_2
, 0);
2472 /* TODO: check if we're symmetric */
2475 snd_soc_dapm_new_controls(&codec
->dapm
,
2476 wm5100_dapm_widgets_noirq
,
2477 ARRAY_SIZE(wm5100_dapm_widgets_noirq
));
2479 if (wm5100
->pdata
.hp_pol
) {
2480 ret
= gpio_request_one(wm5100
->pdata
.hp_pol
,
2481 GPIOF_OUT_INIT_HIGH
, "WM5100 HP_POL");
2483 dev_err(&i2c
->dev
, "Failed to request HP_POL %d: %d\n",
2484 wm5100
->pdata
.hp_pol
, ret
);
2489 /* We'll get woken up again when the system has something useful
2492 if (wm5100
->pdata
.ldo_ena
)
2493 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2494 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
2495 wm5100
->core_supplies
);
2504 static int wm5100_remove(struct snd_soc_codec
*codec
)
2506 struct wm5100_priv
*wm5100
= snd_soc_codec_get_drvdata(codec
);
2507 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2509 if (wm5100
->pdata
.hp_pol
) {
2510 gpio_free(wm5100
->pdata
.hp_pol
);
2516 static int wm5100_soc_volatile(struct snd_soc_codec
*codec
,
2523 static struct snd_soc_codec_driver soc_codec_dev_wm5100
= {
2524 .probe
= wm5100_probe
,
2525 .remove
= wm5100_remove
,
2527 .set_sysclk
= wm5100_set_sysclk
,
2528 .set_pll
= wm5100_set_fll
,
2529 .set_bias_level
= wm5100_set_bias_level
,
2531 .reg_cache_size
= WM5100_MAX_REGISTER
,
2532 .volatile_register
= wm5100_soc_volatile
,
2534 .seq_notifier
= wm5100_seq_notifier
,
2535 .controls
= wm5100_snd_controls
,
2536 .num_controls
= ARRAY_SIZE(wm5100_snd_controls
),
2537 .dapm_widgets
= wm5100_dapm_widgets
,
2538 .num_dapm_widgets
= ARRAY_SIZE(wm5100_dapm_widgets
),
2539 .dapm_routes
= wm5100_dapm_routes
,
2540 .num_dapm_routes
= ARRAY_SIZE(wm5100_dapm_routes
),
2543 static const struct regmap_config wm5100_regmap
= {
2547 .max_register
= WM5100_MAX_REGISTER
,
2548 .reg_defaults
= wm5100_reg_defaults
,
2549 .num_reg_defaults
= ARRAY_SIZE(wm5100_reg_defaults
),
2550 .volatile_reg
= wm5100_volatile_register
,
2551 .readable_reg
= wm5100_readable_register
,
2552 .cache_type
= REGCACHE_RBTREE
,
2555 static __devinit
int wm5100_i2c_probe(struct i2c_client
*i2c
,
2556 const struct i2c_device_id
*id
)
2558 struct wm5100_pdata
*pdata
= dev_get_platdata(&i2c
->dev
);
2559 struct wm5100_priv
*wm5100
;
2561 int ret
, i
, irq_flags
;
2563 wm5100
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm5100_priv
),
2568 wm5100
->dev
= &i2c
->dev
;
2570 wm5100
->regmap
= regmap_init_i2c(i2c
, &wm5100_regmap
);
2571 if (IS_ERR(wm5100
->regmap
)) {
2572 ret
= PTR_ERR(wm5100
->regmap
);
2573 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2578 for (i
= 0; i
< ARRAY_SIZE(wm5100
->fll
); i
++)
2579 init_completion(&wm5100
->fll
[i
].lock
);
2582 wm5100
->pdata
= *pdata
;
2584 i2c_set_clientdata(i2c
, wm5100
);
2586 for (i
= 0; i
< ARRAY_SIZE(wm5100
->core_supplies
); i
++)
2587 wm5100
->core_supplies
[i
].supply
= wm5100_core_supply_names
[i
];
2589 ret
= regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(wm5100
->core_supplies
),
2590 wm5100
->core_supplies
);
2592 dev_err(&i2c
->dev
, "Failed to request core supplies: %d\n",
2597 wm5100
->cpvdd
= regulator_get(&i2c
->dev
, "CPVDD");
2598 if (IS_ERR(wm5100
->cpvdd
)) {
2599 ret
= PTR_ERR(wm5100
->cpvdd
);
2600 dev_err(&i2c
->dev
, "Failed to get CPVDD: %d\n", ret
);
2604 wm5100
->dbvdd2
= regulator_get(&i2c
->dev
, "DBVDD2");
2605 if (IS_ERR(wm5100
->dbvdd2
)) {
2606 ret
= PTR_ERR(wm5100
->dbvdd2
);
2607 dev_err(&i2c
->dev
, "Failed to get DBVDD2: %d\n", ret
);
2611 wm5100
->dbvdd3
= regulator_get(&i2c
->dev
, "DBVDD3");
2612 if (IS_ERR(wm5100
->dbvdd3
)) {
2613 ret
= PTR_ERR(wm5100
->dbvdd3
);
2614 dev_err(&i2c
->dev
, "Failed to get DBVDD2: %d\n", ret
);
2618 ret
= regulator_bulk_enable(ARRAY_SIZE(wm5100
->core_supplies
),
2619 wm5100
->core_supplies
);
2621 dev_err(&i2c
->dev
, "Failed to enable core supplies: %d\n",
2626 if (wm5100
->pdata
.ldo_ena
) {
2627 ret
= gpio_request_one(wm5100
->pdata
.ldo_ena
,
2628 GPIOF_OUT_INIT_HIGH
, "WM5100 LDOENA");
2630 dev_err(&i2c
->dev
, "Failed to request LDOENA %d: %d\n",
2631 wm5100
->pdata
.ldo_ena
, ret
);
2637 if (wm5100
->pdata
.reset
) {
2638 ret
= gpio_request_one(wm5100
->pdata
.reset
,
2639 GPIOF_OUT_INIT_HIGH
, "WM5100 /RESET");
2641 dev_err(&i2c
->dev
, "Failed to request /RESET %d: %d\n",
2642 wm5100
->pdata
.reset
, ret
);
2647 ret
= regmap_read(wm5100
->regmap
, WM5100_SOFTWARE_RESET
, ®
);
2649 dev_err(&i2c
->dev
, "Failed to read ID register: %d\n", ret
);
2658 dev_err(&i2c
->dev
, "Device is not a WM5100, ID is %x\n", reg
);
2663 ret
= regmap_read(wm5100
->regmap
, WM5100_DEVICE_REVISION
, ®
);
2665 dev_err(&i2c
->dev
, "Failed to read revision register\n");
2668 wm5100
->rev
= reg
& WM5100_DEVICE_REVISION_MASK
;
2670 dev_info(&i2c
->dev
, "revision %c\n", wm5100
->rev
+ 'A');
2672 ret
= wm5100_reset(wm5100
);
2674 dev_err(&i2c
->dev
, "Failed to issue reset\n");
2678 switch (wm5100
->rev
) {
2680 ret
= regmap_register_patch(wm5100
->regmap
,
2681 wm5100_reva_patches
,
2682 ARRAY_SIZE(wm5100_reva_patches
));
2684 dev_err(&i2c
->dev
, "Failed to register patches: %d\n",
2694 wm5100_init_gpio(i2c
);
2696 for (i
= 0; i
< ARRAY_SIZE(wm5100
->pdata
.gpio_defaults
); i
++) {
2697 if (!wm5100
->pdata
.gpio_defaults
[i
])
2700 regmap_write(wm5100
->regmap
, WM5100_GPIO_CTRL_1
+ i
,
2701 wm5100
->pdata
.gpio_defaults
[i
]);
2704 for (i
= 0; i
< ARRAY_SIZE(wm5100
->pdata
.in_mode
); i
++) {
2705 regmap_update_bits(wm5100
->regmap
, WM5100_IN1L_CONTROL
,
2706 WM5100_IN1_MODE_MASK
|
2707 WM5100_IN1_DMIC_SUP_MASK
,
2708 (wm5100
->pdata
.in_mode
[i
] <<
2709 WM5100_IN1_MODE_SHIFT
) |
2710 (wm5100
->pdata
.dmic_sup
[i
] <<
2711 WM5100_IN1_DMIC_SUP_SHIFT
));
2715 if (wm5100
->pdata
.irq_flags
)
2716 irq_flags
= wm5100
->pdata
.irq_flags
;
2718 irq_flags
= IRQF_TRIGGER_LOW
;
2720 irq_flags
|= IRQF_ONESHOT
;
2722 if (irq_flags
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
))
2723 ret
= request_threaded_irq(i2c
->irq
, NULL
,
2724 wm5100_edge_irq
, irq_flags
,
2727 ret
= request_threaded_irq(i2c
->irq
, NULL
, wm5100_irq
,
2728 irq_flags
, "wm5100",
2732 dev_err(&i2c
->dev
, "Failed to request IRQ %d: %d\n",
2735 /* Enable default interrupts */
2736 regmap_update_bits(wm5100
->regmap
,
2737 WM5100_INTERRUPT_STATUS_3_MASK
,
2738 WM5100_IM_SPK_SHUTDOWN_WARN_EINT
|
2739 WM5100_IM_SPK_SHUTDOWN_EINT
|
2740 WM5100_IM_ASRC2_LOCK_EINT
|
2741 WM5100_IM_ASRC1_LOCK_EINT
|
2742 WM5100_IM_FLL2_LOCK_EINT
|
2743 WM5100_IM_FLL1_LOCK_EINT
|
2744 WM5100_CLKGEN_ERR_EINT
|
2745 WM5100_CLKGEN_ERR_ASYNC_EINT
, 0);
2747 regmap_update_bits(wm5100
->regmap
,
2748 WM5100_INTERRUPT_STATUS_4_MASK
,
2749 WM5100_AIF3_ERR_EINT
|
2750 WM5100_AIF2_ERR_EINT
|
2751 WM5100_AIF1_ERR_EINT
|
2752 WM5100_CTRLIF_ERR_EINT
|
2753 WM5100_ISRC2_UNDERCLOCKED_EINT
|
2754 WM5100_ISRC1_UNDERCLOCKED_EINT
|
2755 WM5100_FX_UNDERCLOCKED_EINT
|
2756 WM5100_AIF3_UNDERCLOCKED_EINT
|
2757 WM5100_AIF2_UNDERCLOCKED_EINT
|
2758 WM5100_AIF1_UNDERCLOCKED_EINT
|
2759 WM5100_ASRC_UNDERCLOCKED_EINT
|
2760 WM5100_DAC_UNDERCLOCKED_EINT
|
2761 WM5100_ADC_UNDERCLOCKED_EINT
|
2762 WM5100_MIXER_UNDERCLOCKED_EINT
, 0);
2766 ret
= snd_soc_register_codec(&i2c
->dev
,
2767 &soc_codec_dev_wm5100
, wm5100_dai
,
2768 ARRAY_SIZE(wm5100_dai
));
2770 dev_err(&i2c
->dev
, "Failed to register WM5100: %d\n", ret
);
2778 free_irq(i2c
->irq
, wm5100
);
2779 wm5100_free_gpio(i2c
);
2780 if (wm5100
->pdata
.reset
) {
2781 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 0);
2782 gpio_free(wm5100
->pdata
.reset
);
2785 if (wm5100
->pdata
.ldo_ena
) {
2786 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2787 gpio_free(wm5100
->pdata
.ldo_ena
);
2790 regulator_bulk_disable(ARRAY_SIZE(wm5100
->core_supplies
),
2791 wm5100
->core_supplies
);
2793 regulator_put(wm5100
->dbvdd3
);
2795 regulator_put(wm5100
->dbvdd2
);
2797 regulator_put(wm5100
->cpvdd
);
2799 regulator_bulk_free(ARRAY_SIZE(wm5100
->core_supplies
),
2800 wm5100
->core_supplies
);
2802 regmap_exit(wm5100
->regmap
);
2807 static __devexit
int wm5100_i2c_remove(struct i2c_client
*i2c
)
2809 struct wm5100_priv
*wm5100
= i2c_get_clientdata(i2c
);
2811 snd_soc_unregister_codec(&i2c
->dev
);
2813 free_irq(i2c
->irq
, wm5100
);
2814 wm5100_free_gpio(i2c
);
2815 if (wm5100
->pdata
.reset
) {
2816 gpio_set_value_cansleep(wm5100
->pdata
.reset
, 0);
2817 gpio_free(wm5100
->pdata
.reset
);
2819 if (wm5100
->pdata
.ldo_ena
) {
2820 gpio_set_value_cansleep(wm5100
->pdata
.ldo_ena
, 0);
2821 gpio_free(wm5100
->pdata
.ldo_ena
);
2823 regulator_put(wm5100
->dbvdd3
);
2824 regulator_put(wm5100
->dbvdd2
);
2825 regulator_put(wm5100
->cpvdd
);
2826 regulator_bulk_free(ARRAY_SIZE(wm5100
->core_supplies
),
2827 wm5100
->core_supplies
);
2828 regmap_exit(wm5100
->regmap
);
2833 static const struct i2c_device_id wm5100_i2c_id
[] = {
2837 MODULE_DEVICE_TABLE(i2c
, wm5100_i2c_id
);
2839 static struct i2c_driver wm5100_i2c_driver
= {
2842 .owner
= THIS_MODULE
,
2844 .probe
= wm5100_i2c_probe
,
2845 .remove
= __devexit_p(wm5100_i2c_remove
),
2846 .id_table
= wm5100_i2c_id
,
2849 static int __init
wm5100_modinit(void)
2851 return i2c_add_driver(&wm5100_i2c_driver
);
2853 module_init(wm5100_modinit
);
2855 static void __exit
wm5100_exit(void)
2857 i2c_del_driver(&wm5100_i2c_driver
);
2859 module_exit(wm5100_exit
);
2861 MODULE_DESCRIPTION("ASoC WM5100 driver");
2862 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2863 MODULE_LICENSE("GPL");