sound/soc/codecs/wm8400.c

   1 /*
   2  * wm8400.c  --  WM8400 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008-11 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/pm.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/mfd/wm8400-audio.h>
  24 #include <linux/mfd/wm8400-private.h>
  25 #include <linux/mfd/core.h>
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32
  33 #include "wm8400.h"
  34
  35 static struct regulator_bulk_data power[] = {
  36         {
  37                 .supply = "I2S1VDD",
  38         },
  39         {
  40                 .supply = "I2S2VDD",
  41         },
  42         {
  43                 .supply = "DCVDD",
  44         },
  45         {
  46                 .supply = "AVDD",
  47         },
  48         {
  49                 .supply = "FLLVDD",
  50         },
  51         {
  52                 .supply = "HPVDD",
  53         },
  54         {
  55                 .supply = "SPKVDD",
  56         },
  57 };
  58
  59 /* codec private data */
  60 struct wm8400_priv {
  61         struct wm8400 *wm8400;
  62         u16 fake_register;
  63         unsigned int sysclk;
  64         unsigned int pcmclk;
  65         int fll_in, fll_out;
  66 };
  67
  68 static void wm8400_codec_reset(struct snd_soc_codec *codec)
  69 {
  70         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
  71
  72         wm8400_reset_codec_reg_cache(wm8400->wm8400);
  73 }
  74
  75 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
  76
  77 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
  78
  79 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
  80
  81 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
  82
  83 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
  84
  85 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
  86
  87 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
  88
  89 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
  90
  91 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
  92         struct snd_ctl_elem_value *ucontrol)
  93 {
  94         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  95         struct soc_mixer_control *mc =
  96                 (struct soc_mixer_control *)kcontrol->private_value;
  97         int reg = mc->reg;
  98         int ret;
  99         u16 val;
 100
 101         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 102         if (ret < 0)
 103                 return ret;
 104
 105         /* now hit the volume update bits (always bit 8) */
 106         val = snd_soc_read(codec, reg);
 107         return snd_soc_write(codec, reg, val | 0x0100);
 108 }
 109
 110 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
 111         SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
 112                 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
 113
 114
 115 static const char *wm8400_digital_sidetone[] =
 116         {"None", "Left ADC", "Right ADC", "Reserved"};
 117
 118 static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
 119                             WM8400_DIGITAL_SIDE_TONE,
 120                             WM8400_ADC_TO_DACL_SHIFT,
 121                             wm8400_digital_sidetone);
 122
 123 static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
 124                             WM8400_DIGITAL_SIDE_TONE,
 125                             WM8400_ADC_TO_DACR_SHIFT,
 126                             wm8400_digital_sidetone);
 127
 128 static const char *wm8400_adcmode[] =
 129         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
 130
 131 static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
 132                             WM8400_ADC_CTRL,
 133                             WM8400_ADC_HPF_CUT_SHIFT,
 134                             wm8400_adcmode);
 135
 136 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
 137 /* INMIXL */
 138 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
 139            1, 0),
 140 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
 141            1, 0),
 142 /* INMIXR */
 143 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
 144            1, 0),
 145 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
 146            1, 0),
 147
 148 /* LOMIX */
 149 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
 150         WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
 151 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
 152         WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
 153 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
 154         WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
 155 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
 156         WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
 157 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
 158         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
 159 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
 160         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
 161
 162 /* ROMIX */
 163 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
 164         WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
 165 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
 166         WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
 167 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
 168         WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
 169 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
 170         WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
 171 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
 172         WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
 173 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
 174         WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
 175
 176 /* LOUT */
 177 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
 178         WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
 179 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
 180
 181 /* ROUT */
 182 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
 183         WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
 184 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
 185
 186 /* LOPGA */
 187 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
 188         WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
 189 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
 190         WM8400_LOPGAZC_SHIFT, 1, 0),
 191
 192 /* ROPGA */
 193 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
 194         WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
 195 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
 196         WM8400_ROPGAZC_SHIFT, 1, 0),
 197
 198 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 199         WM8400_LONMUTE_SHIFT, 1, 0),
 200 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 201         WM8400_LOPMUTE_SHIFT, 1, 0),
 202 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
 203         WM8400_LOATTN_SHIFT, 1, 0),
 204 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 205         WM8400_RONMUTE_SHIFT, 1, 0),
 206 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 207         WM8400_ROPMUTE_SHIFT, 1, 0),
 208 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
 209         WM8400_ROATTN_SHIFT, 1, 0),
 210
 211 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
 212         WM8400_OUT3MUTE_SHIFT, 1, 0),
 213 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
 214         WM8400_OUT3ATTN_SHIFT, 1, 0),
 215
 216 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
 217         WM8400_OUT4MUTE_SHIFT, 1, 0),
 218 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
 219         WM8400_OUT4ATTN_SHIFT, 1, 0),
 220
 221 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
 222         WM8400_CDMODE_SHIFT, 1, 0),
 223
 224 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
 225         WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
 226 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
 227         WM8400_DCGAIN_SHIFT, 6, 0),
 228 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
 229         WM8400_ACGAIN_SHIFT, 6, 0),
 230
 231 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
 232         WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
 233         127, 0, out_dac_tlv),
 234
 235 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
 236         WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
 237         127, 0, out_dac_tlv),
 238
 239 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
 240 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
 241
 242 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
 243         WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
 244 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
 245         WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
 246
 247 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
 248         WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
 249
 250 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
 251
 252 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
 253         WM8400_LEFT_ADC_DIGITAL_VOLUME,
 254         WM8400_ADCL_VOL_SHIFT,
 255         WM8400_ADCL_VOL_MASK,
 256         0,
 257         in_adc_tlv),
 258
 259 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
 260         WM8400_RIGHT_ADC_DIGITAL_VOLUME,
 261         WM8400_ADCR_VOL_SHIFT,
 262         WM8400_ADCR_VOL_MASK,
 263         0,
 264         in_adc_tlv),
 265
 266 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
 267         WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 268         WM8400_LIN12VOL_SHIFT,
 269         WM8400_LIN12VOL_MASK,
 270         0,
 271         in_pga_tlv),
 272
 273 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 274         WM8400_LI12ZC_SHIFT, 1, 0),
 275
 276 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 277         WM8400_LI12MUTE_SHIFT, 1, 0),
 278
 279 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
 280         WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 281         WM8400_LIN34VOL_SHIFT,
 282         WM8400_LIN34VOL_MASK,
 283         0,
 284         in_pga_tlv),
 285
 286 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 287         WM8400_LI34ZC_SHIFT, 1, 0),
 288
 289 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 290         WM8400_LI34MUTE_SHIFT, 1, 0),
 291
 292 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
 293         WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 294         WM8400_RIN12VOL_SHIFT,
 295         WM8400_RIN12VOL_MASK,
 296         0,
 297         in_pga_tlv),
 298
 299 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 300         WM8400_RI12ZC_SHIFT, 1, 0),
 301
 302 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 303         WM8400_RI12MUTE_SHIFT, 1, 0),
 304
 305 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
 306         WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 307         WM8400_RIN34VOL_SHIFT,
 308         WM8400_RIN34VOL_MASK,
 309         0,
 310         in_pga_tlv),
 311
 312 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 313         WM8400_RI34ZC_SHIFT, 1, 0),
 314
 315 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 316         WM8400_RI34MUTE_SHIFT, 1, 0),
 317
 318 };
 319
 320 /*
 321  * _DAPM_ Controls
 322  */
 323
 324 static int outmixer_event (struct snd_soc_dapm_widget *w,
 325         struct snd_kcontrol * kcontrol, int event)
 326 {
 327         struct soc_mixer_control *mc =
 328                 (struct soc_mixer_control *)kcontrol->private_value;
 329         u32 reg_shift = mc->shift;
 330         int ret = 0;
 331         u16 reg;
 332
 333         switch (reg_shift) {
 334         case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
 335                 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1);
 336                 if (reg & WM8400_LDLO) {
 337                         printk(KERN_WARNING
 338                         "Cannot set as Output Mixer 1 LDLO Set\n");
 339                         ret = -1;
 340                 }
 341                 break;
 342         case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
 343                 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2);
 344                 if (reg & WM8400_RDRO) {
 345                         printk(KERN_WARNING
 346                         "Cannot set as Output Mixer 2 RDRO Set\n");
 347                         ret = -1;
 348                 }
 349                 break;
 350         case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
 351                 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
 352                 if (reg & WM8400_LDSPK) {
 353                         printk(KERN_WARNING
 354                         "Cannot set as Speaker Mixer LDSPK Set\n");
 355                         ret = -1;
 356                 }
 357                 break;
 358         case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
 359                 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
 360                 if (reg & WM8400_RDSPK) {
 361                         printk(KERN_WARNING
 362                         "Cannot set as Speaker Mixer RDSPK Set\n");
 363                         ret = -1;
 364                 }
 365                 break;
 366         }
 367
 368         return ret;
 369 }
 370
 371 /* INMIX dB values */
 372 static const unsigned int in_mix_tlv[] = {
 373         TLV_DB_RANGE_HEAD(1),
 374         0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
 375 };
 376
 377 /* Left In PGA Connections */
 378 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
 379 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
 380 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
 381 };
 382
 383 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
 384 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
 385 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
 386 };
 387
 388 /* Right In PGA Connections */
 389 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
 390 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
 391 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
 392 };
 393
 394 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
 395 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
 396 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
 397 };
 398
 399 /* INMIXL */
 400 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
 401 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
 402         WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
 403 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
 404         7, 0, in_mix_tlv),
 405 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
 406                 1, 0),
 407 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
 408                 1, 0),
 409 };
 410
 411 /* INMIXR */
 412 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
 413 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
 414         WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
 415 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
 416         7, 0, in_mix_tlv),
 417 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
 418         1, 0),
 419 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
 420         1, 0),
 421 };
 422
 423 /* AINLMUX */
 424 static const char *wm8400_ainlmux[] =
 425         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
 426
 427 static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
 428                             WM8400_INPUT_MIXER1,
 429                             WM8400_AINLMODE_SHIFT,
 430                             wm8400_ainlmux);
 431
 432 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
 433 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
 434
 435 /* DIFFINL */
 436
 437 /* AINRMUX */
 438 static const char *wm8400_ainrmux[] =
 439         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
 440
 441 static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
 442                             WM8400_INPUT_MIXER1,
 443                             WM8400_AINRMODE_SHIFT,
 444                             wm8400_ainrmux);
 445
 446 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
 447 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
 448
 449 /* RXVOICE */
 450 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
 451 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
 452                         WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
 453 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
 454                         WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
 455 };
 456
 457 /* LOMIX */
 458 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
 459 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
 460         WM8400_LRBLO_SHIFT, 1, 0),
 461 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
 462         WM8400_LLBLO_SHIFT, 1, 0),
 463 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
 464         WM8400_LRI3LO_SHIFT, 1, 0),
 465 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
 466         WM8400_LLI3LO_SHIFT, 1, 0),
 467 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
 468         WM8400_LR12LO_SHIFT, 1, 0),
 469 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
 470         WM8400_LL12LO_SHIFT, 1, 0),
 471 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
 472         WM8400_LDLO_SHIFT, 1, 0),
 473 };
 474
 475 /* ROMIX */
 476 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
 477 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
 478         WM8400_RLBRO_SHIFT, 1, 0),
 479 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
 480         WM8400_RRBRO_SHIFT, 1, 0),
 481 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
 482         WM8400_RLI3RO_SHIFT, 1, 0),
 483 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
 484         WM8400_RRI3RO_SHIFT, 1, 0),
 485 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
 486         WM8400_RL12RO_SHIFT, 1, 0),
 487 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
 488         WM8400_RR12RO_SHIFT, 1, 0),
 489 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
 490         WM8400_RDRO_SHIFT, 1, 0),
 491 };
 492
 493 /* LONMIX */
 494 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
 495 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
 496         WM8400_LLOPGALON_SHIFT, 1, 0),
 497 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
 498         WM8400_LROPGALON_SHIFT, 1, 0),
 499 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
 500         WM8400_LOPLON_SHIFT, 1, 0),
 501 };
 502
 503 /* LOPMIX */
 504 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
 505 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
 506         WM8400_LR12LOP_SHIFT, 1, 0),
 507 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
 508         WM8400_LL12LOP_SHIFT, 1, 0),
 509 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
 510         WM8400_LLOPGALOP_SHIFT, 1, 0),
 511 };
 512
 513 /* RONMIX */
 514 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
 515 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
 516         WM8400_RROPGARON_SHIFT, 1, 0),
 517 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
 518         WM8400_RLOPGARON_SHIFT, 1, 0),
 519 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
 520         WM8400_ROPRON_SHIFT, 1, 0),
 521 };
 522
 523 /* ROPMIX */
 524 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
 525 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
 526         WM8400_RL12ROP_SHIFT, 1, 0),
 527 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
 528         WM8400_RR12ROP_SHIFT, 1, 0),
 529 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
 530         WM8400_RROPGAROP_SHIFT, 1, 0),
 531 };
 532
 533 /* OUT3MIX */
 534 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
 535 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
 536         WM8400_LI4O3_SHIFT, 1, 0),
 537 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
 538         WM8400_LPGAO3_SHIFT, 1, 0),
 539 };
 540
 541 /* OUT4MIX */
 542 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
 543 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
 544         WM8400_RPGAO4_SHIFT, 1, 0),
 545 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
 546         WM8400_RI4O4_SHIFT, 1, 0),
 547 };
 548
 549 /* SPKMIX */
 550 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
 551 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
 552         WM8400_LI2SPK_SHIFT, 1, 0),
 553 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
 554         WM8400_LB2SPK_SHIFT, 1, 0),
 555 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
 556         WM8400_LOPGASPK_SHIFT, 1, 0),
 557 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
 558         WM8400_LDSPK_SHIFT, 1, 0),
 559 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
 560         WM8400_RDSPK_SHIFT, 1, 0),
 561 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
 562         WM8400_ROPGASPK_SHIFT, 1, 0),
 563 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
 564         WM8400_RL12ROP_SHIFT, 1, 0),
 565 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
 566         WM8400_RI2SPK_SHIFT, 1, 0),
 567 };
 568
 569 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
 570 /* Input Side */
 571 /* Input Lines */
 572 SND_SOC_DAPM_INPUT("LIN1"),
 573 SND_SOC_DAPM_INPUT("LIN2"),
 574 SND_SOC_DAPM_INPUT("LIN3"),
 575 SND_SOC_DAPM_INPUT("LIN4/RXN"),
 576 SND_SOC_DAPM_INPUT("RIN3"),
 577 SND_SOC_DAPM_INPUT("RIN4/RXP"),
 578 SND_SOC_DAPM_INPUT("RIN1"),
 579 SND_SOC_DAPM_INPUT("RIN2"),
 580 SND_SOC_DAPM_INPUT("Internal ADC Source"),
 581
 582 /* DACs */
 583 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
 584         WM8400_ADCL_ENA_SHIFT, 0),
 585 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
 586         WM8400_ADCR_ENA_SHIFT, 0),
 587
 588 /* Input PGAs */
 589 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
 590                    WM8400_LIN12_ENA_SHIFT,
 591                    0, &wm8400_dapm_lin12_pga_controls[0],
 592                    ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
 593 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
 594                    WM8400_LIN34_ENA_SHIFT,
 595                    0, &wm8400_dapm_lin34_pga_controls[0],
 596                    ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
 597 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
 598                    WM8400_RIN12_ENA_SHIFT,
 599                    0, &wm8400_dapm_rin12_pga_controls[0],
 600                    ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
 601 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
 602                    WM8400_RIN34_ENA_SHIFT,
 603                    0, &wm8400_dapm_rin34_pga_controls[0],
 604                    ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
 605
 606 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
 607                     0, NULL, 0),
 608 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
 609                     0, NULL, 0),
 610
 611 /* INMIXL */
 612 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
 613         &wm8400_dapm_inmixl_controls[0],
 614         ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
 615
 616 /* AINLMUX */
 617 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
 618
 619 /* INMIXR */
 620 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
 621         &wm8400_dapm_inmixr_controls[0],
 622         ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
 623
 624 /* AINRMUX */
 625 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
 626
 627 /* Output Side */
 628 /* DACs */
 629 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
 630         WM8400_DACL_ENA_SHIFT, 0),
 631 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
 632         WM8400_DACR_ENA_SHIFT, 0),
 633
 634 /* LOMIX */
 635 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
 636                      WM8400_LOMIX_ENA_SHIFT,
 637                      0, &wm8400_dapm_lomix_controls[0],
 638                      ARRAY_SIZE(wm8400_dapm_lomix_controls),
 639                      outmixer_event, SND_SOC_DAPM_PRE_REG),
 640
 641 /* LONMIX */
 642 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
 643                    0, &wm8400_dapm_lonmix_controls[0],
 644                    ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
 645
 646 /* LOPMIX */
 647 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
 648                    0, &wm8400_dapm_lopmix_controls[0],
 649                    ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
 650
 651 /* OUT3MIX */
 652 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
 653                    0, &wm8400_dapm_out3mix_controls[0],
 654                    ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
 655
 656 /* SPKMIX */
 657 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
 658                      0, &wm8400_dapm_spkmix_controls[0],
 659                      ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
 660                      SND_SOC_DAPM_PRE_REG),
 661
 662 /* OUT4MIX */
 663 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
 664         0, &wm8400_dapm_out4mix_controls[0],
 665         ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
 666
 667 /* ROPMIX */
 668 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
 669                    0, &wm8400_dapm_ropmix_controls[0],
 670                    ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
 671
 672 /* RONMIX */
 673 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
 674                    0, &wm8400_dapm_ronmix_controls[0],
 675                    ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
 676
 677 /* ROMIX */
 678 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
 679                      WM8400_ROMIX_ENA_SHIFT,
 680                      0, &wm8400_dapm_romix_controls[0],
 681                      ARRAY_SIZE(wm8400_dapm_romix_controls),
 682                      outmixer_event, SND_SOC_DAPM_PRE_REG),
 683
 684 /* LOUT PGA */
 685 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
 686                  0, NULL, 0),
 687
 688 /* ROUT PGA */
 689 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
 690                  0, NULL, 0),
 691
 692 /* LOPGA */
 693 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
 694         NULL, 0),
 695
 696 /* ROPGA */
 697 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
 698         NULL, 0),
 699
 700 /* MICBIAS */
 701 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
 702                     WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
 703
 704 SND_SOC_DAPM_OUTPUT("LON"),
 705 SND_SOC_DAPM_OUTPUT("LOP"),
 706 SND_SOC_DAPM_OUTPUT("OUT3"),
 707 SND_SOC_DAPM_OUTPUT("LOUT"),
 708 SND_SOC_DAPM_OUTPUT("SPKN"),
 709 SND_SOC_DAPM_OUTPUT("SPKP"),
 710 SND_SOC_DAPM_OUTPUT("ROUT"),
 711 SND_SOC_DAPM_OUTPUT("OUT4"),
 712 SND_SOC_DAPM_OUTPUT("ROP"),
 713 SND_SOC_DAPM_OUTPUT("RON"),
 714
 715 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
 716 };
 717
 718 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
 719         /* Make DACs turn on when playing even if not mixed into any outputs */
 720         {"Internal DAC Sink", NULL, "Left DAC"},
 721         {"Internal DAC Sink", NULL, "Right DAC"},
 722
 723         /* Make ADCs turn on when recording
 724          * even if not mixed from any inputs */
 725         {"Left ADC", NULL, "Internal ADC Source"},
 726         {"Right ADC", NULL, "Internal ADC Source"},
 727
 728         /* Input Side */
 729         /* LIN12 PGA */
 730         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
 731         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
 732         /* LIN34 PGA */
 733         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
 734         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
 735         /* INMIXL */
 736         {"INMIXL", NULL, "INL"},
 737         {"INMIXL", "Record Left Volume", "LOMIX"},
 738         {"INMIXL", "LIN2 Volume", "LIN2"},
 739         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
 740         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
 741         /* AILNMUX */
 742         {"AILNMUX", NULL, "INL"},
 743         {"AILNMUX", "INMIXL Mix", "INMIXL"},
 744         {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
 745         {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
 746         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
 747         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
 748         /* ADC */
 749         {"Left ADC", NULL, "AILNMUX"},
 750
 751         /* RIN12 PGA */
 752         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
 753         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
 754         /* RIN34 PGA */
 755         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
 756         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
 757         /* INMIXR */
 758         {"INMIXR", NULL, "INR"},
 759         {"INMIXR", "Record Right Volume", "ROMIX"},
 760         {"INMIXR", "RIN2 Volume", "RIN2"},
 761         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
 762         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
 763         /* AIRNMUX */
 764         {"AIRNMUX", NULL, "INR"},
 765         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
 766         {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
 767         {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
 768         {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
 769         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
 770         /* ADC */
 771         {"Right ADC", NULL, "AIRNMUX"},
 772
 773         /* LOMIX */
 774         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
 775         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
 776         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 777         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 778         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
 779         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
 780         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
 781
 782         /* ROMIX */
 783         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
 784         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
 785         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 786         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 787         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
 788         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
 789         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
 790
 791         /* SPKMIX */
 792         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
 793         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
 794         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
 795         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
 796         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
 797         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
 798         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
 799         {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
 800
 801         /* LONMIX */
 802         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
 803         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
 804         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
 805
 806         /* LOPMIX */
 807         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 808         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 809         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
 810
 811         /* OUT3MIX */
 812         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
 813         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
 814
 815         /* OUT4MIX */
 816         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
 817         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
 818
 819         /* RONMIX */
 820         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
 821         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
 822         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
 823
 824         /* ROPMIX */
 825         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 826         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 827         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
 828
 829         /* Out Mixer PGAs */
 830         {"LOPGA", NULL, "LOMIX"},
 831         {"ROPGA", NULL, "ROMIX"},
 832
 833         {"LOUT PGA", NULL, "LOMIX"},
 834         {"ROUT PGA", NULL, "ROMIX"},
 835
 836         /* Output Pins */
 837         {"LON", NULL, "LONMIX"},
 838         {"LOP", NULL, "LOPMIX"},
 839         {"OUT3", NULL, "OUT3MIX"},
 840         {"LOUT", NULL, "LOUT PGA"},
 841         {"SPKN", NULL, "SPKMIX"},
 842         {"ROUT", NULL, "ROUT PGA"},
 843         {"OUT4", NULL, "OUT4MIX"},
 844         {"ROP", NULL, "ROPMIX"},
 845         {"RON", NULL, "RONMIX"},
 846 };
 847
 848 /*
 849  * Clock after FLL and dividers
 850  */
 851 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 852                 int clk_id, unsigned int freq, int dir)
 853 {
 854         struct snd_soc_codec *codec = codec_dai->codec;
 855         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
 856
 857         wm8400->sysclk = freq;
 858         return 0;
 859 }
 860
 861 struct fll_factors {
 862         u16 n;
 863         u16 k;
 864         u16 outdiv;
 865         u16 fratio;
 866         u16 freq_ref;
 867 };
 868
 869 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 870
 871 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
 872                        unsigned int Fref, unsigned int Fout)
 873 {
 874         u64 Kpart;
 875         unsigned int K, Nmod, target;
 876
 877         factors->outdiv = 2;
 878         while (Fout * factors->outdiv <  90000000 ||
 879                Fout * factors->outdiv > 100000000) {
 880                 factors->outdiv *= 2;
 881                 if (factors->outdiv > 32) {
 882                         dev_err(wm8400->wm8400->dev,
 883                                 "Unsupported FLL output frequency %uHz\n",
 884                                 Fout);
 885                         return -EINVAL;
 886                 }
 887         }
 888         target = Fout * factors->outdiv;
 889         factors->outdiv = factors->outdiv >> 2;
 890
 891         if (Fref < 48000)
 892                 factors->freq_ref = 1;
 893         else
 894                 factors->freq_ref = 0;
 895
 896         if (Fref < 1000000)
 897                 factors->fratio = 9;
 898         else
 899                 factors->fratio = 0;
 900
 901         /* Ensure we have a fractional part */
 902         do {
 903                 if (Fref < 1000000)
 904                         factors->fratio--;
 905                 else
 906                         factors->fratio++;
 907
 908                 if (factors->fratio < 1 || factors->fratio > 8) {
 909                         dev_err(wm8400->wm8400->dev,
 910                                 "Unable to calculate FRATIO\n");
 911                         return -EINVAL;
 912                 }
 913
 914                 factors->n = target / (Fref * factors->fratio);
 915                 Nmod = target % (Fref * factors->fratio);
 916         } while (Nmod == 0);
 917
 918         /* Calculate fractional part - scale up so we can round. */
 919         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
 920
 921         do_div(Kpart, (Fref * factors->fratio));
 922
 923         K = Kpart & 0xFFFFFFFF;
 924
 925         if ((K % 10) >= 5)
 926                 K += 5;
 927
 928         /* Move down to proper range now rounding is done */
 929         factors->k = K / 10;
 930
 931         dev_dbg(wm8400->wm8400->dev,
 932                 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
 933                 Fref, Fout,
 934                 factors->n, factors->k, factors->fratio, factors->outdiv);
 935
 936         return 0;
 937 }
 938
 939 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 940                               int source, unsigned int freq_in,
 941                               unsigned int freq_out)
 942 {
 943         struct snd_soc_codec *codec = codec_dai->codec;
 944         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
 945         struct fll_factors factors;
 946         int ret;
 947         u16 reg;
 948
 949         if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
 950                 return 0;
 951
 952         if (freq_out) {
 953                 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
 954                 if (ret != 0)
 955                         return ret;
 956         } else {
 957                 /* Bodge GCC 4.4.0 uninitialised variable warning - it
 958                  * doesn't seem capable of working out that we exit if
 959                  * freq_out is 0 before any of the uses. */
 960                 memset(&factors, 0, sizeof(factors));
 961         }
 962
 963         wm8400->fll_out = freq_out;
 964         wm8400->fll_in = freq_in;
 965
 966         /* We *must* disable the FLL before any changes */
 967         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
 968         reg &= ~WM8400_FLL_ENA;
 969         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
 970
 971         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
 972         reg &= ~WM8400_FLL_OSC_ENA;
 973         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
 974
 975         if (!freq_out)
 976                 return 0;
 977
 978         reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
 979         reg |= WM8400_FLL_FRAC | factors.fratio;
 980         reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
 981         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
 982
 983         snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
 984         snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
 985
 986         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
 987         reg &= ~WM8400_FLL_OUTDIV_MASK;
 988         reg |= factors.outdiv;
 989         snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
 990
 991         return 0;
 992 }
 993
 994 /*
 995  * Sets ADC and Voice DAC format.
 996  */
 997 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
 998                 unsigned int fmt)
 999 {
1000         struct snd_soc_codec *codec = codec_dai->codec;
1001         u16 audio1, audio3;
1002
1003         audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1004         audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
1005
1006         /* set master/slave audio interface */
1007         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1008         case SND_SOC_DAIFMT_CBS_CFS:
1009                 audio3 &= ~WM8400_AIF_MSTR1;
1010                 break;
1011         case SND_SOC_DAIFMT_CBM_CFM:
1012                 audio3 |= WM8400_AIF_MSTR1;
1013                 break;
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         audio1 &= ~WM8400_AIF_FMT_MASK;
1019
1020         /* interface format */
1021         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1022         case SND_SOC_DAIFMT_I2S:
1023                 audio1 |= WM8400_AIF_FMT_I2S;
1024                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1025                 break;
1026         case SND_SOC_DAIFMT_RIGHT_J:
1027                 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1028                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1029                 break;
1030         case SND_SOC_DAIFMT_LEFT_J:
1031                 audio1 |= WM8400_AIF_FMT_LEFTJ;
1032                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1033                 break;
1034         case SND_SOC_DAIFMT_DSP_A:
1035                 audio1 |= WM8400_AIF_FMT_DSP;
1036                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1037                 break;
1038         case SND_SOC_DAIFMT_DSP_B:
1039                 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1040                 break;
1041         default:
1042                 return -EINVAL;
1043         }
1044
1045         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1046         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1047         return 0;
1048 }
1049
1050 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1051                 int div_id, int div)
1052 {
1053         struct snd_soc_codec *codec = codec_dai->codec;
1054         u16 reg;
1055
1056         switch (div_id) {
1057         case WM8400_MCLK_DIV:
1058                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1059                         ~WM8400_MCLK_DIV_MASK;
1060                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1061                 break;
1062         case WM8400_DACCLK_DIV:
1063                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1064                         ~WM8400_DAC_CLKDIV_MASK;
1065                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1066                 break;
1067         case WM8400_ADCCLK_DIV:
1068                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1069                         ~WM8400_ADC_CLKDIV_MASK;
1070                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1071                 break;
1072         case WM8400_BCLK_DIV:
1073                 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
1074                         ~WM8400_BCLK_DIV_MASK;
1075                 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
1076                 break;
1077         default:
1078                 return -EINVAL;
1079         }
1080
1081         return 0;
1082 }
1083
1084 /*
1085  * Set PCM DAI bit size and sample rate.
1086  */
1087 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1088         struct snd_pcm_hw_params *params,
1089         struct snd_soc_dai *dai)
1090 {
1091         struct snd_soc_codec *codec = dai->codec;
1092         u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1093
1094         audio1 &= ~WM8400_AIF_WL_MASK;
1095         /* bit size */
1096         switch (params_width(params)) {
1097         case 16:
1098                 break;
1099         case 20:
1100                 audio1 |= WM8400_AIF_WL_20BITS;
1101                 break;
1102         case 24:
1103                 audio1 |= WM8400_AIF_WL_24BITS;
1104                 break;
1105         case 32:
1106                 audio1 |= WM8400_AIF_WL_32BITS;
1107                 break;
1108         }
1109
1110         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1111         return 0;
1112 }
1113
1114 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1115 {
1116         struct snd_soc_codec *codec = dai->codec;
1117         u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1118
1119         if (mute)
1120                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1121         else
1122                 snd_soc_write(codec, WM8400_DAC_CTRL, val);
1123
1124         return 0;
1125 }
1126
1127 /* TODO: set bias for best performance at standby */
1128 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1129                                  enum snd_soc_bias_level level)
1130 {
1131         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1132         u16 val;
1133         int ret;
1134
1135         switch (level) {
1136         case SND_SOC_BIAS_ON:
1137                 break;
1138
1139         case SND_SOC_BIAS_PREPARE:
1140                 /* VMID=2*50k */
1141                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1142                         ~WM8400_VMID_MODE_MASK;
1143                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1144                 break;
1145
1146         case SND_SOC_BIAS_STANDBY:
1147                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1148                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
1149                                                     &power[0]);
1150                         if (ret != 0) {
1151                                 dev_err(wm8400->wm8400->dev,
1152                                         "Failed to enable regulators: %d\n",
1153                                         ret);
1154                                 return ret;
1155                         }
1156
1157                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1158                                      WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1159
1160                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1161                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1162                                      WM8400_BUFDCOPEN | WM8400_POBCTRL);
1163
1164                         msleep(50);
1165
1166                         /* Enable VREF & VMID at 2x50k */
1167                         val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1168                         val |= 0x2 | WM8400_VREF_ENA;
1169                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1170
1171                         /* Enable BUFIOEN */
1172                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1173                                      WM8400_BUFDCOPEN | WM8400_POBCTRL |
1174                                      WM8400_BUFIOEN);
1175
1176                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1177                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1178                 }
1179
1180                 /* VMID=2*300k */
1181                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1182                         ~WM8400_VMID_MODE_MASK;
1183                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1184                 break;
1185
1186         case SND_SOC_BIAS_OFF:
1187                 /* Enable POBCTRL and SOFT_ST */
1188                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1189                         WM8400_POBCTRL | WM8400_BUFIOEN);
1190
1191                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1192                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1193                         WM8400_BUFDCOPEN | WM8400_POBCTRL |
1194                         WM8400_BUFIOEN);
1195
1196                 /* mute DAC */
1197                 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1198                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1199
1200                 /* Enable any disabled outputs */
1201                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1202                 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1203                         WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1204                         WM8400_ROUT_ENA;
1205                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1206
1207                 /* Disable VMID */
1208                 val &= ~WM8400_VMID_MODE_MASK;
1209                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1210
1211                 msleep(300);
1212
1213                 /* Enable all output discharge bits */
1214                 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1215                         WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1216                         WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1217                         WM8400_DIS_ROUT);
1218
1219                 /* Disable VREF */
1220                 val &= ~WM8400_VREF_ENA;
1221                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1222
1223                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1224                 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
1225
1226                 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1227                                              &power[0]);
1228                 if (ret != 0)
1229                         return ret;
1230
1231                 break;
1232         }
1233
1234         codec->dapm.bias_level = level;
1235         return 0;
1236 }
1237
1238 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1239
1240 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1241         SNDRV_PCM_FMTBIT_S24_LE)
1242
1243 static const struct snd_soc_dai_ops wm8400_dai_ops = {
1244         .hw_params = wm8400_hw_params,
1245         .digital_mute = wm8400_mute,
1246         .set_fmt = wm8400_set_dai_fmt,
1247         .set_clkdiv = wm8400_set_dai_clkdiv,
1248         .set_sysclk = wm8400_set_dai_sysclk,
1249         .set_pll = wm8400_set_dai_pll,
1250 };
1251
1252 /*
1253  * The WM8400 supports 2 different and mutually exclusive DAI
1254  * configurations.
1255  *
1256  * 1. ADC/DAC on Primary Interface
1257  * 2. ADC on Primary Interface/DAC on secondary
1258  */
1259 static struct snd_soc_dai_driver wm8400_dai = {
1260 /* ADC/DAC on primary */
1261         .name = "wm8400-hifi",
1262         .playback = {
1263                 .stream_name = "Playback",
1264                 .channels_min = 1,
1265                 .channels_max = 2,
1266                 .rates = WM8400_RATES,
1267                 .formats = WM8400_FORMATS,
1268         },
1269         .capture = {
1270                 .stream_name = "Capture",
1271                 .channels_min = 1,
1272                 .channels_max = 2,
1273                 .rates = WM8400_RATES,
1274                 .formats = WM8400_FORMATS,
1275         },
1276         .ops = &wm8400_dai_ops,
1277 };
1278
1279 static int wm8400_codec_probe(struct snd_soc_codec *codec)
1280 {
1281         struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
1282         struct wm8400_priv *priv;
1283         int ret;
1284         u16 reg;
1285
1286         priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv),
1287                             GFP_KERNEL);
1288         if (priv == NULL)
1289                 return -ENOMEM;
1290
1291         snd_soc_codec_set_drvdata(codec, priv);
1292         priv->wm8400 = wm8400;
1293
1294         ret = devm_regulator_bulk_get(wm8400->dev,
1295                                  ARRAY_SIZE(power), &power[0]);
1296         if (ret != 0) {
1297                 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
1298                 return ret;
1299         }
1300
1301         wm8400_codec_reset(codec);
1302
1303         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1304         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1305
1306         /* Latch volume update bits */
1307         reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1308         snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1309                      reg & WM8400_IPVU);
1310         reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1311         snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1312                      reg & WM8400_IPVU);
1313
1314         snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1315         snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1316
1317         return 0;
1318 }
1319
1320 static int  wm8400_codec_remove(struct snd_soc_codec *codec)
1321 {
1322         u16 reg;
1323
1324         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1325         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1326                      reg & (~WM8400_CODEC_ENA));
1327
1328         return 0;
1329 }
1330
1331 static struct regmap *wm8400_get_regmap(struct device *dev)
1332 {
1333         struct wm8400 *wm8400 = dev_get_platdata(dev);
1334
1335         return wm8400->regmap;
1336 }
1337
1338 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1339         .probe =        wm8400_codec_probe,
1340         .remove =       wm8400_codec_remove,
1341         .get_regmap =   wm8400_get_regmap,
1342         .set_bias_level = wm8400_set_bias_level,
1343         .suspend_bias_off = true,
1344
1345         .controls = wm8400_snd_controls,
1346         .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1347         .dapm_widgets = wm8400_dapm_widgets,
1348         .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1349         .dapm_routes = wm8400_dapm_routes,
1350         .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1351 };
1352
1353 static int wm8400_probe(struct platform_device *pdev)
1354 {
1355         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1356                         &wm8400_dai, 1);
1357 }
1358
1359 static int wm8400_remove(struct platform_device *pdev)
1360 {
1361         snd_soc_unregister_codec(&pdev->dev);
1362         return 0;
1363 }
1364
1365 static struct platform_driver wm8400_codec_driver = {
1366         .driver = {
1367                    .name = "wm8400-codec",
1368                    .owner = THIS_MODULE,
1369                    },
1370         .probe = wm8400_probe,
1371         .remove = wm8400_remove,
1372 };
1373
1374 module_platform_driver(wm8400_codec_driver);
1375
1376 MODULE_DESCRIPTION("ASoC WM8400 driver");
1377 MODULE_AUTHOR("Mark Brown");
1378 MODULE_LICENSE("GPL");
1379 MODULE_ALIAS("platform:wm8400-codec");