sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29
  30 #include <sound/core.h>
  31 #include <sound/pcm.h>
  32 #include <sound/pcm_params.h>
  33 #include <sound/soc.h>
  34 #include <sound/tlv.h>
  35 #include <sound/initval.h>
  36 #include <asm/div64.h>
  37
  38 #include "wm8580.h"
  39
  40 /* WM8580 register space */
  41 #define WM8580_PLLA1                         0x00
  42 #define WM8580_PLLA2                         0x01
  43 #define WM8580_PLLA3                         0x02
  44 #define WM8580_PLLA4                         0x03
  45 #define WM8580_PLLB1                         0x04
  46 #define WM8580_PLLB2                         0x05
  47 #define WM8580_PLLB3                         0x06
  48 #define WM8580_PLLB4                         0x07
  49 #define WM8580_CLKSEL                        0x08
  50 #define WM8580_PAIF1                         0x09
  51 #define WM8580_PAIF2                         0x0A
  52 #define WM8580_SAIF1                         0x0B
  53 #define WM8580_PAIF3                         0x0C
  54 #define WM8580_PAIF4                         0x0D
  55 #define WM8580_SAIF2                         0x0E
  56 #define WM8580_DAC_CONTROL1                  0x0F
  57 #define WM8580_DAC_CONTROL2                  0x10
  58 #define WM8580_DAC_CONTROL3                  0x11
  59 #define WM8580_DAC_CONTROL4                  0x12
  60 #define WM8580_DAC_CONTROL5                  0x13
  61 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  62 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  63 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  64 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  65 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  66 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  67 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  68 #define WM8580_ADC_CONTROL1                  0x1D
  69 #define WM8580_SPDTXCHAN0                    0x1E
  70 #define WM8580_SPDTXCHAN1                    0x1F
  71 #define WM8580_SPDTXCHAN2                    0x20
  72 #define WM8580_SPDTXCHAN3                    0x21
  73 #define WM8580_SPDTXCHAN4                    0x22
  74 #define WM8580_SPDTXCHAN5                    0x23
  75 #define WM8580_SPDMODE                       0x24
  76 #define WM8580_INTMASK                       0x25
  77 #define WM8580_GPO1                          0x26
  78 #define WM8580_GPO2                          0x27
  79 #define WM8580_GPO3                          0x28
  80 #define WM8580_GPO4                          0x29
  81 #define WM8580_GPO5                          0x2A
  82 #define WM8580_INTSTAT                       0x2B
  83 #define WM8580_SPDRXCHAN1                    0x2C
  84 #define WM8580_SPDRXCHAN2                    0x2D
  85 #define WM8580_SPDRXCHAN3                    0x2E
  86 #define WM8580_SPDRXCHAN4                    0x2F
  87 #define WM8580_SPDRXCHAN5                    0x30
  88 #define WM8580_SPDSTAT                       0x31
  89 #define WM8580_PWRDN1                        0x32
  90 #define WM8580_PWRDN2                        0x33
  91 #define WM8580_READBACK                      0x34
  92 #define WM8580_RESET                         0x35
  93
  94 #define WM8580_MAX_REGISTER                  0x35
  95
  96 #define WM8580_DACOSR 0x40
  97
  98 /* PLLB4 (register 7h) */
  99 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 100 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 101 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 102 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 103
 104 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 105 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 106 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 107 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 108
 109 /* CLKSEL (register 8h) */
 110 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 111 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 113
 114 /* AIF control 1 (registers 9h-bh) */
 115 #define WM8580_AIF_RATE_MASK       0x7
 116 #define WM8580_AIF_BCLKSEL_MASK   0x18
 117
 118 #define WM8580_AIF_MS             0x20
 119
 120 #define WM8580_AIF_CLKSRC_MASK    0xc0
 121 #define WM8580_AIF_CLKSRC_PLLA    0x40
 122 #define WM8580_AIF_CLKSRC_PLLB    0x40
 123 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 124
 125 /* AIF control 2 (registers ch-eh) */
 126 #define WM8580_AIF_FMT_MASK    0x03
 127 #define WM8580_AIF_FMT_RIGHTJ  0x00
 128 #define WM8580_AIF_FMT_LEFTJ   0x01
 129 #define WM8580_AIF_FMT_I2S     0x02
 130 #define WM8580_AIF_FMT_DSP     0x03
 131
 132 #define WM8580_AIF_LENGTH_MASK   0x0c
 133 #define WM8580_AIF_LENGTH_16     0x00
 134 #define WM8580_AIF_LENGTH_20     0x04
 135 #define WM8580_AIF_LENGTH_24     0x08
 136 #define WM8580_AIF_LENGTH_32     0x0c
 137
 138 #define WM8580_AIF_LRP         0x10
 139 #define WM8580_AIF_BCP         0x20
 140
 141 /* Powerdown Register 1 (register 32h) */
 142 #define WM8580_PWRDN1_PWDN     0x001
 143 #define WM8580_PWRDN1_ALLDACPD 0x040
 144
 145 /* Powerdown Register 2 (register 33h) */
 146 #define WM8580_PWRDN2_OSSCPD   0x001
 147 #define WM8580_PWRDN2_PLLAPD   0x002
 148 #define WM8580_PWRDN2_PLLBPD   0x004
 149 #define WM8580_PWRDN2_SPDIFPD  0x008
 150 #define WM8580_PWRDN2_SPDIFTXD 0x010
 151 #define WM8580_PWRDN2_SPDIFRXD 0x020
 152
 153 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 154
 155 /*
 156  * wm8580 register cache
 157  * We can't read the WM8580 register space when we
 158  * are using 2 wire for device control, so we cache them instead.
 159  */
 160 static const u16 wm8580_reg[] = {
 161         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 162         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 163         0x0010, 0x0002, 0x0002, 0x00c2, /*R11*/
 164         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 165         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 166         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 167         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 168         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 169         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 170         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 171         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 172         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 173         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 174         0x0000, 0x0000 /*R53*/
 175 };
 176
 177 struct pll_state {
 178         unsigned int in;
 179         unsigned int out;
 180 };
 181
 182 #define WM8580_NUM_SUPPLIES 3
 183 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 184         "AVDD",
 185         "DVDD",
 186         "PVDD",
 187 };
 188
 189 /* codec private data */
 190 struct wm8580_priv {
 191         enum snd_soc_control_type control_type;
 192         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 193         struct pll_state a;
 194         struct pll_state b;
 195         int sysclk[2];
 196 };
 197
 198 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 199
 200 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 201                          struct snd_ctl_elem_value *ucontrol)
 202 {
 203         struct soc_mixer_control *mc =
 204                 (struct soc_mixer_control *)kcontrol->private_value;
 205         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 206         u16 *reg_cache = codec->reg_cache;
 207         unsigned int reg = mc->reg;
 208         unsigned int reg2 = mc->rreg;
 209         int ret;
 210
 211         /* Clear the register cache so we write without VU set */
 212         reg_cache[reg] = 0;
 213         reg_cache[reg2] = 0;
 214
 215         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 216         if (ret < 0)
 217                 return ret;
 218
 219         /* Now write again with the volume update bit set */
 220         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 221         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 222
 223         return 0;
 224 }
 225
 226 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 227 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
 228                      WM8580_DIGITAL_ATTENUATION_DACL1,
 229                      WM8580_DIGITAL_ATTENUATION_DACR1,
 230                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 231 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
 232                      WM8580_DIGITAL_ATTENUATION_DACL2,
 233                      WM8580_DIGITAL_ATTENUATION_DACR2,
 234                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 235 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
 236                      WM8580_DIGITAL_ATTENUATION_DACL3,
 237                      WM8580_DIGITAL_ATTENUATION_DACR3,
 238                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 239
 240 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 241 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 242 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 243
 244 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 245 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 246 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 247
 248 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 249 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
 250 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
 251 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
 252
 253 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
 254 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 255 };
 256
 257 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 258 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 259 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 260 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 261
 262 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 263 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 264 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 265 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 266 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 267 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 268
 269 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 270
 271 SND_SOC_DAPM_INPUT("AINL"),
 272 SND_SOC_DAPM_INPUT("AINR"),
 273 };
 274
 275 static const struct snd_soc_dapm_route audio_map[] = {
 276         { "VOUT1L", NULL, "DAC1" },
 277         { "VOUT1R", NULL, "DAC1" },
 278
 279         { "VOUT2L", NULL, "DAC2" },
 280         { "VOUT2R", NULL, "DAC2" },
 281
 282         { "VOUT3L", NULL, "DAC3" },
 283         { "VOUT3R", NULL, "DAC3" },
 284
 285         { "ADC", NULL, "AINL" },
 286         { "ADC", NULL, "AINR" },
 287 };
 288
 289 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 290 {
 291         struct snd_soc_dapm_context *dapm = &codec->dapm;
 292
 293         snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets,
 294                                   ARRAY_SIZE(wm8580_dapm_widgets));
 295         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 296
 297         return 0;
 298 }
 299
 300 /* PLL divisors */
 301 struct _pll_div {
 302         u32 prescale:1;
 303         u32 postscale:1;
 304         u32 freqmode:2;
 305         u32 n:4;
 306         u32 k:24;
 307 };
 308
 309 /* The size in bits of the pll divide */
 310 #define FIXED_PLL_SIZE (1 << 22)
 311
 312 /* PLL rate to output rate divisions */
 313 static struct {
 314         unsigned int div;
 315         unsigned int freqmode;
 316         unsigned int postscale;
 317 } post_table[] = {
 318         {  2,  0, 0 },
 319         {  4,  0, 1 },
 320         {  4,  1, 0 },
 321         {  8,  1, 1 },
 322         {  8,  2, 0 },
 323         { 16,  2, 1 },
 324         { 12,  3, 0 },
 325         { 24,  3, 1 }
 326 };
 327
 328 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 329                        unsigned int source)
 330 {
 331         u64 Kpart;
 332         unsigned int K, Ndiv, Nmod;
 333         int i;
 334
 335         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 336
 337         /* Scale the output frequency up; the PLL should run in the
 338          * region of 90-100MHz.
 339          */
 340         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 341                 if (target * post_table[i].div >=  90000000 &&
 342                     target * post_table[i].div <= 100000000) {
 343                         pll_div->freqmode = post_table[i].freqmode;
 344                         pll_div->postscale = post_table[i].postscale;
 345                         target *= post_table[i].div;
 346                         break;
 347                 }
 348         }
 349
 350         if (i == ARRAY_SIZE(post_table)) {
 351                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 352                        "%u\n", target);
 353                 return -EINVAL;
 354         }
 355
 356         Ndiv = target / source;
 357
 358         if (Ndiv < 5) {
 359                 source /= 2;
 360                 pll_div->prescale = 1;
 361                 Ndiv = target / source;
 362         } else
 363                 pll_div->prescale = 0;
 364
 365         if ((Ndiv < 5) || (Ndiv > 13)) {
 366                 printk(KERN_ERR
 367                         "WM8580 N=%u outside supported range\n", Ndiv);
 368                 return -EINVAL;
 369         }
 370
 371         pll_div->n = Ndiv;
 372         Nmod = target % source;
 373         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 374
 375         do_div(Kpart, source);
 376
 377         K = Kpart & 0xFFFFFFFF;
 378
 379         pll_div->k = K;
 380
 381         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 382                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 383                  pll_div->postscale);
 384
 385         return 0;
 386 }
 387
 388 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 389                 int source, unsigned int freq_in, unsigned int freq_out)
 390 {
 391         int offset;
 392         struct snd_soc_codec *codec = codec_dai->codec;
 393         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 394         struct pll_state *state;
 395         struct _pll_div pll_div;
 396         unsigned int reg;
 397         unsigned int pwr_mask;
 398         int ret;
 399
 400         /* GCC isn't able to work out the ifs below for initialising/using
 401          * pll_div so suppress warnings.
 402          */
 403         memset(&pll_div, 0, sizeof(pll_div));
 404
 405         switch (pll_id) {
 406         case WM8580_PLLA:
 407                 state = &wm8580->a;
 408                 offset = 0;
 409                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 410                 break;
 411         case WM8580_PLLB:
 412                 state = &wm8580->b;
 413                 offset = 4;
 414                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 415                 break;
 416         default:
 417                 return -ENODEV;
 418         }
 419
 420         if (freq_in && freq_out) {
 421                 ret = pll_factors(&pll_div, freq_out, freq_in);
 422                 if (ret != 0)
 423                         return ret;
 424         }
 425
 426         state->in = freq_in;
 427         state->out = freq_out;
 428
 429         /* Always disable the PLL - it is not safe to leave it running
 430          * while reprogramming it.
 431          */
 432         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
 433
 434         if (!freq_in || !freq_out)
 435                 return 0;
 436
 437         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 438         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 439         snd_soc_write(codec, WM8580_PLLA3 + offset,
 440                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 441
 442         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 443         reg &= ~0x1b;
 444         reg |= pll_div.prescale | pll_div.postscale << 1 |
 445                 pll_div.freqmode << 3;
 446
 447         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 448
 449         /* All done, turn it on */
 450         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
 451
 452         return 0;
 453 }
 454
 455 static const int wm8580_sysclk_ratios[] = {
 456         128, 192, 256, 384, 512, 768, 1152,
 457 };
 458
 459 /*
 460  * Set PCM DAI bit size and sample rate.
 461  */
 462 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 463                                  struct snd_pcm_hw_params *params,
 464                                  struct snd_soc_dai *dai)
 465 {
 466         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 467         struct snd_soc_codec *codec = rtd->codec;
 468         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 469         u16 paifa = 0;
 470         u16 paifb = 0;
 471         int i, ratio, osr;
 472
 473         /* bit size */
 474         switch (params_format(params)) {
 475         case SNDRV_PCM_FORMAT_S16_LE:
 476                 paifa |= 0x8;
 477                 break;
 478         case SNDRV_PCM_FORMAT_S20_3LE:
 479                 paifa |= 0x0;
 480                 paifb |= WM8580_AIF_LENGTH_20;
 481                 break;
 482         case SNDRV_PCM_FORMAT_S24_LE:
 483                 paifa |= 0x0;
 484                 paifb |= WM8580_AIF_LENGTH_24;
 485                 break;
 486         case SNDRV_PCM_FORMAT_S32_LE:
 487                 paifa |= 0x0;
 488                 paifb |= WM8580_AIF_LENGTH_32;
 489                 break;
 490         default:
 491                 return -EINVAL;
 492         }
 493
 494         /* Look up the SYSCLK ratio; accept only exact matches */
 495         ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
 496         for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
 497                 if (ratio == wm8580_sysclk_ratios[i])
 498                         break;
 499         if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
 500                 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
 501                         wm8580->sysclk[dai->driver->id], params_rate(params));
 502                 return -EINVAL;
 503         }
 504         paifa |= i;
 505         dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
 506                 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
 507
 508         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 509                 switch (ratio) {
 510                 case 128:
 511                 case 192:
 512                         osr = WM8580_DACOSR;
 513                         dev_dbg(codec->dev, "Selecting 64x OSR\n");
 514                         break;
 515                 default:
 516                         osr = 0;
 517                         dev_dbg(codec->dev, "Selecting 128x OSR\n");
 518                         break;
 519                 }
 520
 521                 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
 522         }
 523
 524         snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
 525                             WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
 526                             paifa);
 527         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 528                             WM8580_AIF_LENGTH_MASK, paifb);
 529         return 0;
 530 }
 531
 532 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 533                                       unsigned int fmt)
 534 {
 535         struct snd_soc_codec *codec = codec_dai->codec;
 536         unsigned int aifa;
 537         unsigned int aifb;
 538         int can_invert_lrclk;
 539
 540         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 541         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 542
 543         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 544
 545         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 546         case SND_SOC_DAIFMT_CBS_CFS:
 547                 aifa &= ~WM8580_AIF_MS;
 548                 break;
 549         case SND_SOC_DAIFMT_CBM_CFM:
 550                 aifa |= WM8580_AIF_MS;
 551                 break;
 552         default:
 553                 return -EINVAL;
 554         }
 555
 556         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 557         case SND_SOC_DAIFMT_I2S:
 558                 can_invert_lrclk = 1;
 559                 aifb |= WM8580_AIF_FMT_I2S;
 560                 break;
 561         case SND_SOC_DAIFMT_RIGHT_J:
 562                 can_invert_lrclk = 1;
 563                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 564                 break;
 565         case SND_SOC_DAIFMT_LEFT_J:
 566                 can_invert_lrclk = 1;
 567                 aifb |= WM8580_AIF_FMT_LEFTJ;
 568                 break;
 569         case SND_SOC_DAIFMT_DSP_A:
 570                 can_invert_lrclk = 0;
 571                 aifb |= WM8580_AIF_FMT_DSP;
 572                 break;
 573         case SND_SOC_DAIFMT_DSP_B:
 574                 can_invert_lrclk = 0;
 575                 aifb |= WM8580_AIF_FMT_DSP;
 576                 aifb |= WM8580_AIF_LRP;
 577                 break;
 578         default:
 579                 return -EINVAL;
 580         }
 581
 582         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 583         case SND_SOC_DAIFMT_NB_NF:
 584                 break;
 585
 586         case SND_SOC_DAIFMT_IB_IF:
 587                 if (!can_invert_lrclk)
 588                         return -EINVAL;
 589                 aifb |= WM8580_AIF_BCP;
 590                 aifb |= WM8580_AIF_LRP;
 591                 break;
 592
 593         case SND_SOC_DAIFMT_IB_NF:
 594                 aifb |= WM8580_AIF_BCP;
 595                 break;
 596
 597         case SND_SOC_DAIFMT_NB_IF:
 598                 if (!can_invert_lrclk)
 599                         return -EINVAL;
 600                 aifb |= WM8580_AIF_LRP;
 601                 break;
 602
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 608         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 609
 610         return 0;
 611 }
 612
 613 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 614                                  int div_id, int div)
 615 {
 616         struct snd_soc_codec *codec = codec_dai->codec;
 617         unsigned int reg;
 618
 619         switch (div_id) {
 620         case WM8580_MCLK:
 621                 reg = snd_soc_read(codec, WM8580_PLLB4);
 622                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 623
 624                 switch (div) {
 625                 case WM8580_CLKSRC_MCLK:
 626                         /* Input */
 627                         break;
 628
 629                 case WM8580_CLKSRC_PLLA:
 630                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 631                         break;
 632                 case WM8580_CLKSRC_PLLB:
 633                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 634                         break;
 635
 636                 case WM8580_CLKSRC_OSC:
 637                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 638                         break;
 639
 640                 default:
 641                         return -EINVAL;
 642                 }
 643                 snd_soc_write(codec, WM8580_PLLB4, reg);
 644                 break;
 645
 646         case WM8580_CLKOUTSRC:
 647                 reg = snd_soc_read(codec, WM8580_PLLB4);
 648                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 649
 650                 switch (div) {
 651                 case WM8580_CLKSRC_NONE:
 652                         break;
 653
 654                 case WM8580_CLKSRC_PLLA:
 655                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 656                         break;
 657
 658                 case WM8580_CLKSRC_PLLB:
 659                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 660                         break;
 661
 662                 case WM8580_CLKSRC_OSC:
 663                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 664                         break;
 665
 666                 default:
 667                         return -EINVAL;
 668                 }
 669                 snd_soc_write(codec, WM8580_PLLB4, reg);
 670                 break;
 671
 672         default:
 673                 return -EINVAL;
 674         }
 675
 676         return 0;
 677 }
 678
 679 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 680                              unsigned int freq, int dir)
 681 {
 682         struct snd_soc_codec *codec = dai->codec;
 683         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 684         int sel, sel_mask, sel_shift;
 685
 686         switch (dai->driver->id) {
 687         case WM8580_DAI_PAIFRX:
 688                 sel_mask = 0x3;
 689                 sel_shift = 0;
 690                 break;
 691
 692         case WM8580_DAI_PAIFTX:
 693                 sel_mask = 0xc;
 694                 sel_shift = 2;
 695                 break;
 696
 697         default:
 698                 BUG_ON("Unknown DAI driver ID\n");
 699                 return -EINVAL;
 700         }
 701
 702         switch (clk_id) {
 703         case WM8580_CLKSRC_ADCMCLK:
 704                 if (dai->driver->id != WM8580_DAI_PAIFTX)
 705                         return -EINVAL;
 706                 sel = 0 << sel_shift;
 707                 break;
 708         case WM8580_CLKSRC_PLLA:
 709                 sel = 1 << sel_shift;
 710                 break;
 711         case WM8580_CLKSRC_PLLB:
 712                 sel = 2 << sel_shift;
 713                 break;
 714         case WM8580_CLKSRC_MCLK:
 715                 sel = 3 << sel_shift;
 716                 break;
 717         default:
 718                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
 719                 return -EINVAL;
 720         }
 721
 722         /* We really should validate PLL settings but not yet */
 723         wm8580->sysclk[dai->driver->id] = freq;
 724
 725         return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
 726 }
 727
 728 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 729 {
 730         struct snd_soc_codec *codec = codec_dai->codec;
 731         unsigned int reg;
 732
 733         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 734
 735         if (mute)
 736                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 737         else
 738                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 739
 740         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 741
 742         return 0;
 743 }
 744
 745 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 746         enum snd_soc_bias_level level)
 747 {
 748         switch (level) {
 749         case SND_SOC_BIAS_ON:
 750         case SND_SOC_BIAS_PREPARE:
 751                 break;
 752
 753         case SND_SOC_BIAS_STANDBY:
 754                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 755                         /* Power up and get individual control of the DACs */
 756                         snd_soc_update_bits(codec, WM8580_PWRDN1,
 757                                             WM8580_PWRDN1_PWDN |
 758                                             WM8580_PWRDN1_ALLDACPD, 0);
 759
 760                         /* Make VMID high impedance */
 761                         snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
 762                                             0x100, 0);
 763                 }
 764                 break;
 765
 766         case SND_SOC_BIAS_OFF:
 767                 snd_soc_update_bits(codec, WM8580_PWRDN1,
 768                                     WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
 769                 break;
 770         }
 771         codec->dapm.bias_level = level;
 772         return 0;
 773 }
 774
 775 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 776                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 777
 778 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 779         .set_sysclk     = wm8580_set_sysclk,
 780         .hw_params      = wm8580_paif_hw_params,
 781         .set_fmt        = wm8580_set_paif_dai_fmt,
 782         .set_clkdiv     = wm8580_set_dai_clkdiv,
 783         .set_pll        = wm8580_set_dai_pll,
 784         .digital_mute   = wm8580_digital_mute,
 785 };
 786
 787 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 788         .set_sysclk     = wm8580_set_sysclk,
 789         .hw_params      = wm8580_paif_hw_params,
 790         .set_fmt        = wm8580_set_paif_dai_fmt,
 791         .set_clkdiv     = wm8580_set_dai_clkdiv,
 792         .set_pll        = wm8580_set_dai_pll,
 793 };
 794
 795 static struct snd_soc_dai_driver wm8580_dai[] = {
 796         {
 797                 .name = "wm8580-hifi-playback",
 798                 .id     = WM8580_DAI_PAIFRX,
 799                 .playback = {
 800                         .stream_name = "Playback",
 801                         .channels_min = 1,
 802                         .channels_max = 6,
 803                         .rates = SNDRV_PCM_RATE_8000_192000,
 804                         .formats = WM8580_FORMATS,
 805                 },
 806                 .ops = &wm8580_dai_ops_playback,
 807         },
 808         {
 809                 .name = "wm8580-hifi-capture",
 810                 .id     =       WM8580_DAI_PAIFTX,
 811                 .capture = {
 812                         .stream_name = "Capture",
 813                         .channels_min = 2,
 814                         .channels_max = 2,
 815                         .rates = SNDRV_PCM_RATE_8000_192000,
 816                         .formats = WM8580_FORMATS,
 817                 },
 818                 .ops = &wm8580_dai_ops_capture,
 819         },
 820 };
 821
 822 static int wm8580_probe(struct snd_soc_codec *codec)
 823 {
 824         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 825         int ret = 0,i;
 826
 827         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
 828         if (ret < 0) {
 829                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 830                 return ret;
 831         }
 832
 833         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 834                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 835
 836         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 837                                  wm8580->supplies);
 838         if (ret != 0) {
 839                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 840                 return ret;
 841         }
 842
 843         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 844                                     wm8580->supplies);
 845         if (ret != 0) {
 846                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 847                 goto err_regulator_get;
 848         }
 849
 850         /* Get the codec into a known state */
 851         ret = snd_soc_write(codec, WM8580_RESET, 0);
 852         if (ret != 0) {
 853                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 854                 goto err_regulator_enable;
 855         }
 856
 857         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 858
 859         snd_soc_add_controls(codec, wm8580_snd_controls,
 860                              ARRAY_SIZE(wm8580_snd_controls));
 861         wm8580_add_widgets(codec);
 862
 863         return 0;
 864
 865 err_regulator_enable:
 866         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 867 err_regulator_get:
 868         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 869         return ret;
 870 }
 871
 872 /* power down chip */
 873 static int wm8580_remove(struct snd_soc_codec *codec)
 874 {
 875         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 876
 877         wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
 878
 879         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 880         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 881
 882         return 0;
 883 }
 884
 885 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 886         .probe =        wm8580_probe,
 887         .remove =       wm8580_remove,
 888         .set_bias_level = wm8580_set_bias_level,
 889         .reg_cache_size = ARRAY_SIZE(wm8580_reg),
 890         .reg_word_size = sizeof(u16),
 891         .reg_cache_default = wm8580_reg,
 892 };
 893
 894 static const struct of_device_id wm8580_of_match[] = {
 895         { .compatible = "wlf,wm8580" },
 896         { },
 897 };
 898
 899 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 900 static int wm8580_i2c_probe(struct i2c_client *i2c,
 901                             const struct i2c_device_id *id)
 902 {
 903         struct wm8580_priv *wm8580;
 904         int ret;
 905
 906         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 907         if (wm8580 == NULL)
 908                 return -ENOMEM;
 909
 910         i2c_set_clientdata(i2c, wm8580);
 911         wm8580->control_type = SND_SOC_I2C;
 912
 913         ret =  snd_soc_register_codec(&i2c->dev,
 914                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 915         if (ret < 0)
 916                 kfree(wm8580);
 917         return ret;
 918 }
 919
 920 static int wm8580_i2c_remove(struct i2c_client *client)
 921 {
 922         snd_soc_unregister_codec(&client->dev);
 923         kfree(i2c_get_clientdata(client));
 924         return 0;
 925 }
 926
 927 static const struct i2c_device_id wm8580_i2c_id[] = {
 928         { "wm8580", 0 },
 929         { }
 930 };
 931 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 932
 933 static struct i2c_driver wm8580_i2c_driver = {
 934         .driver = {
 935                 .name = "wm8580",
 936                 .owner = THIS_MODULE,
 937                 .of_match_table = wm8580_of_match,
 938         },
 939         .probe =    wm8580_i2c_probe,
 940         .remove =   wm8580_i2c_remove,
 941         .id_table = wm8580_i2c_id,
 942 };
 943 #endif
 944
 945 static int __init wm8580_modinit(void)
 946 {
 947         int ret = 0;
 948
 949 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 950         ret = i2c_add_driver(&wm8580_i2c_driver);
 951         if (ret != 0) {
 952                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 953         }
 954 #endif
 955
 956         return ret;
 957 }
 958 module_init(wm8580_modinit);
 959
 960 static void __exit wm8580_exit(void)
 961 {
 962 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 963         i2c_del_driver(&wm8580_i2c_driver);
 964 #endif
 965 }
 966 module_exit(wm8580_exit);
 967
 968 MODULE_DESCRIPTION("ASoC WM8580 driver");
 969 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 970 MODULE_LICENSE("GPL");