2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
37 /* WM8900 register space */
38 #define WM8900_REG_RESET 0x0
39 #define WM8900_REG_ID 0x0
40 #define WM8900_REG_POWER1 0x1
41 #define WM8900_REG_POWER2 0x2
42 #define WM8900_REG_POWER3 0x3
43 #define WM8900_REG_AUDIO1 0x4
44 #define WM8900_REG_AUDIO2 0x5
45 #define WM8900_REG_CLOCKING1 0x6
46 #define WM8900_REG_CLOCKING2 0x7
47 #define WM8900_REG_AUDIO3 0x8
48 #define WM8900_REG_AUDIO4 0x9
49 #define WM8900_REG_DACCTRL 0xa
50 #define WM8900_REG_LDAC_DV 0xb
51 #define WM8900_REG_RDAC_DV 0xc
52 #define WM8900_REG_SIDETONE 0xd
53 #define WM8900_REG_ADCCTRL 0xe
54 #define WM8900_REG_LADC_DV 0xf
55 #define WM8900_REG_RADC_DV 0x10
56 #define WM8900_REG_GPIO 0x12
57 #define WM8900_REG_INCTL 0x15
58 #define WM8900_REG_LINVOL 0x16
59 #define WM8900_REG_RINVOL 0x17
60 #define WM8900_REG_INBOOSTMIX1 0x18
61 #define WM8900_REG_INBOOSTMIX2 0x19
62 #define WM8900_REG_ADCPATH 0x1a
63 #define WM8900_REG_AUXBOOST 0x1b
64 #define WM8900_REG_ADDCTL 0x1e
65 #define WM8900_REG_FLLCTL1 0x24
66 #define WM8900_REG_FLLCTL2 0x25
67 #define WM8900_REG_FLLCTL3 0x26
68 #define WM8900_REG_FLLCTL4 0x27
69 #define WM8900_REG_FLLCTL5 0x28
70 #define WM8900_REG_FLLCTL6 0x29
71 #define WM8900_REG_LOUTMIXCTL1 0x2c
72 #define WM8900_REG_ROUTMIXCTL1 0x2d
73 #define WM8900_REG_BYPASS1 0x2e
74 #define WM8900_REG_BYPASS2 0x2f
75 #define WM8900_REG_AUXOUT_CTL 0x30
76 #define WM8900_REG_LOUT1CTL 0x33
77 #define WM8900_REG_ROUT1CTL 0x34
78 #define WM8900_REG_LOUT2CTL 0x35
79 #define WM8900_REG_ROUT2CTL 0x36
80 #define WM8900_REG_HPCTL1 0x3a
81 #define WM8900_REG_OUTBIASCTL 0x73
83 #define WM8900_MAXREG 0x80
85 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
88 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
92 #define WM8900_REG_GPIO_TEMP_ENA 0x2
94 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
96 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97 #define WM8900_REG_POWER1_FLL_ENA 0x0040
99 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
101 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
103 #define WM8900_REG_POWER3_DACL_ENA 0x0002
104 #define WM8900_REG_POWER3_DACR_ENA 0x0001
106 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
112 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
113 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
115 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118 #define WM8900_REG_DACCTRL_MUTE 0x004
119 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
130 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
131 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
132 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
133 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
134 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136 #define WM8900_LRC_MASK 0xfc00
138 struct snd_soc_codec_device soc_codec_dev_wm8900
;
141 u32 fll_in
; /* FLL input frequency */
142 u32 fll_out
; /* FLL output frequency */
146 * wm8900 register cache. We can't read the entire register space and we
147 * have slow control buses so we cache the registers.
149 static const u16 wm8900_reg_defaults
[WM8900_MAXREG
] = {
178 /* Remaining registers all zero */
182 * read wm8900 register cache
184 static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec
*codec
,
187 u16
*cache
= codec
->reg_cache
;
189 BUG_ON(reg
>= WM8900_MAXREG
);
191 if (reg
== WM8900_REG_ID
)
198 * write wm8900 register cache
200 static inline void wm8900_write_reg_cache(struct snd_soc_codec
*codec
,
201 u16 reg
, unsigned int value
)
203 u16
*cache
= codec
->reg_cache
;
205 BUG_ON(reg
>= WM8900_MAXREG
);
211 * write to the WM8900 register space
213 static int wm8900_write(struct snd_soc_codec
*codec
, unsigned int reg
,
218 if (value
== wm8900_read_reg_cache(codec
, reg
))
222 * D15..D9 WM8900 register offset
223 * D8...D0 register data
226 data
[1] = value
>> 8;
227 data
[2] = value
& 0x00ff;
229 wm8900_write_reg_cache(codec
, reg
, value
);
230 if (codec
->hw_write(codec
->control_data
, data
, 3) == 3)
237 * Read from the wm8900.
239 static unsigned int wm8900_chip_read(struct snd_soc_codec
*codec
, u8 reg
)
241 struct i2c_msg xfer
[2];
244 struct i2c_client
*client
= codec
->control_data
;
246 BUG_ON(reg
!= WM8900_REG_ID
&& reg
!= WM8900_REG_POWER1
);
249 xfer
[0].addr
= client
->addr
;
255 xfer
[1].addr
= client
->addr
;
256 xfer
[1].flags
= I2C_M_RD
;
258 xfer
[1].buf
= (u8
*)&data
;
260 ret
= i2c_transfer(client
->adapter
, xfer
, 2);
262 printk(KERN_CRIT
"i2c_transfer returned %d\n", ret
);
266 return (data
>> 8) | ((data
& 0xff) << 8);
270 * Read from the WM8900 register space. Most registers can't be read
271 * and are therefore supplied from cache.
273 static unsigned int wm8900_read(struct snd_soc_codec
*codec
, unsigned int reg
)
277 return wm8900_chip_read(codec
, reg
);
279 return wm8900_read_reg_cache(codec
, reg
);
283 static void wm8900_reset(struct snd_soc_codec
*codec
)
285 wm8900_write(codec
, WM8900_REG_RESET
, 0);
287 memcpy(codec
->reg_cache
, wm8900_reg_defaults
,
288 sizeof(codec
->reg_cache
));
291 static int wm8900_hp_event(struct snd_soc_dapm_widget
*w
,
292 struct snd_kcontrol
*kcontrol
, int event
)
294 struct snd_soc_codec
*codec
= w
->codec
;
295 u16 hpctl1
= wm8900_read(codec
, WM8900_REG_HPCTL1
);
298 case SND_SOC_DAPM_PRE_PMU
:
299 /* Clamp headphone outputs */
300 hpctl1
= WM8900_REG_HPCTL1_HP_CLAMP_IP
|
301 WM8900_REG_HPCTL1_HP_CLAMP_OP
;
302 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
305 case SND_SOC_DAPM_POST_PMU
:
306 /* Enable the input stage */
307 hpctl1
&= ~WM8900_REG_HPCTL1_HP_CLAMP_IP
;
308 hpctl1
|= WM8900_REG_HPCTL1_HP_SHORT
|
309 WM8900_REG_HPCTL1_HP_SHORT2
|
310 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA
;
311 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
315 /* Enable the output stage */
316 hpctl1
&= ~WM8900_REG_HPCTL1_HP_CLAMP_OP
;
317 hpctl1
|= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA
;
318 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
320 /* Remove the shorts */
321 hpctl1
&= ~WM8900_REG_HPCTL1_HP_SHORT2
;
322 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
323 hpctl1
&= ~WM8900_REG_HPCTL1_HP_SHORT
;
324 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
327 case SND_SOC_DAPM_PRE_PMD
:
328 /* Short the output */
329 hpctl1
|= WM8900_REG_HPCTL1_HP_SHORT
;
330 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
332 /* Disable the output stage */
333 hpctl1
&= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA
;
334 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
336 /* Clamp the outputs and power down input */
337 hpctl1
|= WM8900_REG_HPCTL1_HP_CLAMP_IP
|
338 WM8900_REG_HPCTL1_HP_CLAMP_OP
;
339 hpctl1
&= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA
;
340 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
343 case SND_SOC_DAPM_POST_PMD
:
344 /* Disable everything */
345 wm8900_write(codec
, WM8900_REG_HPCTL1
, 0);
355 static const DECLARE_TLV_DB_SCALE(out_pga_tlv
, -5700, 100, 0);
357 static const DECLARE_TLV_DB_SCALE(out_mix_tlv
, -1500, 300, 0);
359 static const DECLARE_TLV_DB_SCALE(in_boost_tlv
, -1200, 600, 0);
361 static const DECLARE_TLV_DB_SCALE(in_pga_tlv
, -1200, 100, 0);
363 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
365 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -7200, 75, 1);
367 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv
, -3600, 300, 0);
369 static const DECLARE_TLV_DB_SCALE(adc_tlv
, -7200, 75, 1);
371 static const char *mic_bias_level_txt
[] = { "0.9*AVDD", "0.65*AVDD" };
373 static const struct soc_enum mic_bias_level
=
374 SOC_ENUM_SINGLE(WM8900_REG_INCTL
, 8, 2, mic_bias_level_txt
);
376 static const char *dac_mute_rate_txt
[] = { "Fast", "Slow" };
378 static const struct soc_enum dac_mute_rate
=
379 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL
, 7, 2, dac_mute_rate_txt
);
381 static const char *dac_deemphasis_txt
[] = {
382 "Disabled", "32kHz", "44.1kHz", "48kHz"
385 static const struct soc_enum dac_deemphasis
=
386 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL
, 4, 4, dac_deemphasis_txt
);
388 static const char *adc_hpf_cut_txt
[] = {
389 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
392 static const struct soc_enum adc_hpf_cut
=
393 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL
, 5, 4, adc_hpf_cut_txt
);
395 static const char *lr_txt
[] = {
399 static const struct soc_enum aifl_src
=
400 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1
, 15, 2, lr_txt
);
402 static const struct soc_enum aifr_src
=
403 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1
, 14, 2, lr_txt
);
405 static const struct soc_enum dacl_src
=
406 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2
, 15, 2, lr_txt
);
408 static const struct soc_enum dacr_src
=
409 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2
, 14, 2, lr_txt
);
411 static const char *sidetone_txt
[] = {
412 "Disabled", "Left ADC", "Right ADC"
415 static const struct soc_enum dacl_sidetone
=
416 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE
, 2, 3, sidetone_txt
);
418 static const struct soc_enum dacr_sidetone
=
419 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE
, 0, 3, sidetone_txt
);
421 static const struct snd_kcontrol_new wm8900_snd_controls
[] = {
422 SOC_ENUM("Mic Bias Level", mic_bias_level
),
424 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL
, 0, 31, 0,
426 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL
, 6, 1, 1),
427 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL
, 7, 1, 0),
429 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL
, 0, 31, 0,
431 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL
, 6, 1, 1),
432 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL
, 7, 1, 0),
434 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL
, 6, 1, 1),
435 SOC_ENUM("DAC Mute Rate", dac_mute_rate
),
436 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL
, 9, 1, 0),
437 SOC_ENUM("DAC Deemphasis", dac_deemphasis
),
438 SOC_SINGLE("DAC Sloping Stopband Filter Switch", WM8900_REG_DACCTRL
, 8, 1, 0),
439 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL
,
442 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL
, 8, 1, 0),
443 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut
),
444 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL
, 1, 0, 1, 0),
445 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE
, 9, 12, 0,
447 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE
, 5, 12, 0,
449 SOC_ENUM("Left Digital Audio Source", aifl_src
),
450 SOC_ENUM("Right Digital Audio Source", aifr_src
),
452 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2
, 10, 4, 0,
454 SOC_ENUM("Left DAC Source", dacl_src
),
455 SOC_ENUM("Right DAC Source", dacr_src
),
456 SOC_ENUM("Left DAC Sidetone", dacl_sidetone
),
457 SOC_ENUM("Right DAC Sidetone", dacr_sidetone
),
458 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL
, 1, 0, 1, 0),
460 SOC_DOUBLE_R_TLV("Digital Playback Volume",
461 WM8900_REG_LDAC_DV
, WM8900_REG_RDAC_DV
,
463 SOC_DOUBLE_R_TLV("Digital Capture Volume",
464 WM8900_REG_LADC_DV
, WM8900_REG_RADC_DV
, 1, 119, 0, adc_tlv
),
466 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1
, 4, 7, 0,
468 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1
, 4, 7, 0,
470 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL
, 4, 7, 0,
472 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL
, 0, 7, 0,
475 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1
, 0, 7, 0,
477 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1
, 4, 7, 0,
479 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2
, 0, 7, 0,
481 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2
, 4, 7, 0,
484 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1
, 0, 3, 0,
486 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1
, 4, 3, 0,
488 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2
, 0, 3, 0,
490 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2
, 4, 3, 0,
492 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST
, 4, 3, 0,
494 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST
, 0, 3, 0,
497 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
498 0, 63, 0, out_pga_tlv
),
499 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
501 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
504 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
505 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
,
506 0, 63, 0, out_pga_tlv
),
507 SOC_DOUBLE_R("LINEOUT2 Switch",
508 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
, 6, 1, 1),
509 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
510 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
, 7, 1, 0),
511 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1
,
516 /* add non dapm controls */
517 static int wm8900_add_controls(struct snd_soc_codec
*codec
)
521 for (i
= 0; i
< ARRAY_SIZE(wm8900_snd_controls
); i
++) {
522 err
= snd_ctl_add(codec
->card
,
523 snd_soc_cnew(&wm8900_snd_controls
[i
],
532 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control
=
533 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3
, 6, 1, 0);
535 static const struct snd_kcontrol_new wm8900_dapm_routput2_control
=
536 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3
, 5, 1, 0);
538 static const struct snd_kcontrol_new wm8900_loutmix_controls
[] = {
539 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1
, 7, 1, 0),
540 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL
, 7, 1, 0),
541 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1
, 7, 1, 0),
542 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2
, 3, 1, 0),
543 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1
, 8, 1, 0),
546 static const struct snd_kcontrol_new wm8900_routmix_controls
[] = {
547 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1
, 7, 1, 0),
548 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL
, 3, 1, 0),
549 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1
, 3, 1, 0),
550 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2
, 7, 1, 0),
551 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1
, 8, 1, 0),
554 static const struct snd_kcontrol_new wm8900_linmix_controls
[] = {
555 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1
, 2, 1, 1),
556 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1
, 6, 1, 1),
557 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST
, 6, 1, 1),
558 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH
, 6, 1, 0),
561 static const struct snd_kcontrol_new wm8900_rinmix_controls
[] = {
562 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2
, 2, 1, 1),
563 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2
, 6, 1, 1),
564 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST
, 2, 1, 1),
565 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH
, 2, 1, 0),
568 static const struct snd_kcontrol_new wm8900_linpga_controls
[] = {
569 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL
, 6, 1, 0),
570 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL
, 5, 1, 0),
571 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL
, 4, 1, 0),
574 static const struct snd_kcontrol_new wm8900_rinpga_controls
[] = {
575 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL
, 2, 1, 0),
576 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL
, 1, 1, 0),
577 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL
, 0, 1, 0),
580 static const char *wm9700_lp_mux
[] = { "Disabled", "Enabled" };
582 static const struct soc_enum wm8900_lineout2_lp_mux
=
583 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1
, 1, 2, wm9700_lp_mux
);
585 static const struct snd_kcontrol_new wm8900_lineout2_lp
=
586 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux
);
588 static const struct snd_soc_dapm_widget wm8900_dapm_widgets
[] = {
590 /* Externally visible pins */
591 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
592 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
593 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
594 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
595 SND_SOC_DAPM_OUTPUT("HP_L"),
596 SND_SOC_DAPM_OUTPUT("HP_R"),
598 SND_SOC_DAPM_INPUT("RINPUT1"),
599 SND_SOC_DAPM_INPUT("LINPUT1"),
600 SND_SOC_DAPM_INPUT("RINPUT2"),
601 SND_SOC_DAPM_INPUT("LINPUT2"),
602 SND_SOC_DAPM_INPUT("RINPUT3"),
603 SND_SOC_DAPM_INPUT("LINPUT3"),
604 SND_SOC_DAPM_INPUT("AUX"),
606 SND_SOC_DAPM_VMID("VMID"),
609 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2
, 3, 0,
610 wm8900_linpga_controls
,
611 ARRAY_SIZE(wm8900_linpga_controls
)),
612 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2
, 2, 0,
613 wm8900_rinpga_controls
,
614 ARRAY_SIZE(wm8900_rinpga_controls
)),
616 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2
, 5, 0,
617 wm8900_linmix_controls
,
618 ARRAY_SIZE(wm8900_linmix_controls
)),
619 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2
, 4, 0,
620 wm8900_rinmix_controls
,
621 ARRAY_SIZE(wm8900_rinmix_controls
)),
623 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1
, 4, 0),
625 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2
, 1, 0),
626 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2
, 0, 0),
629 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3
, 1, 0),
630 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3
, 0, 0),
632 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3
, 7, 0, NULL
, 0,
634 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
635 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
637 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2
, 8, 0, NULL
, 0),
638 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2
, 7, 0, NULL
, 0),
640 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM
, 0, 0, &wm8900_lineout2_lp
),
641 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3
, 6, 0, NULL
, 0),
642 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3
, 5, 0, NULL
, 0),
644 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3
, 3, 0,
645 wm8900_loutmix_controls
,
646 ARRAY_SIZE(wm8900_loutmix_controls
)),
647 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3
, 2, 0,
648 wm8900_routmix_controls
,
649 ARRAY_SIZE(wm8900_routmix_controls
)),
652 /* Target, Path, Source */
653 static const struct snd_soc_dapm_route audio_map
[] = {
655 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
656 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
657 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
659 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
660 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
661 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
663 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
664 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
665 {"Left Input Mixer", "AUX Switch", "AUX"},
666 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
668 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
669 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
670 {"Right Input Mixer", "AUX Switch", "AUX"},
671 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
673 {"ADCL", NULL
, "Left Input Mixer"},
674 {"ADCR", NULL
, "Right Input Mixer"},
677 {"LINEOUT1L", NULL
, "LINEOUT1L PGA"},
678 {"LINEOUT1L PGA", NULL
, "Left Output Mixer"},
679 {"LINEOUT1R", NULL
, "LINEOUT1R PGA"},
680 {"LINEOUT1R PGA", NULL
, "Right Output Mixer"},
682 {"LINEOUT2L PGA", NULL
, "Left Output Mixer"},
683 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
684 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
685 {"LINEOUT2L", NULL
, "LINEOUT2 LP"},
687 {"LINEOUT2R PGA", NULL
, "Right Output Mixer"},
688 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
689 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
690 {"LINEOUT2R", NULL
, "LINEOUT2 LP"},
692 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
693 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
694 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
695 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
696 {"Left Output Mixer", "DACL Switch", "DACL"},
698 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
699 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
700 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
701 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
702 {"Right Output Mixer", "DACR Switch", "DACR"},
704 /* Note that the headphone output stage needs to be connected
705 * externally to LINEOUT2 via DC blocking capacitors. Other
706 * configurations are not supported.
708 * Note also that left and right headphone paths are treated as a
711 {"Headphone Amplifier", NULL
, "LINEOUT2 LP"},
712 {"Headphone Amplifier", NULL
, "LINEOUT2 LP"},
713 {"HP_L", NULL
, "Headphone Amplifier"},
714 {"HP_R", NULL
, "Headphone Amplifier"},
717 static int wm8900_add_widgets(struct snd_soc_codec
*codec
)
719 snd_soc_dapm_new_controls(codec
, wm8900_dapm_widgets
,
720 ARRAY_SIZE(wm8900_dapm_widgets
));
722 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
724 snd_soc_dapm_new_widgets(codec
);
729 static int wm8900_hw_params(struct snd_pcm_substream
*substream
,
730 struct snd_pcm_hw_params
*params
,
731 struct snd_soc_dai
*dai
)
733 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
734 struct snd_soc_device
*socdev
= rtd
->socdev
;
735 struct snd_soc_codec
*codec
= socdev
->codec
;
738 reg
= wm8900_read(codec
, WM8900_REG_AUDIO1
) & ~0x60;
740 switch (params_format(params
)) {
741 case SNDRV_PCM_FORMAT_S16_LE
:
743 case SNDRV_PCM_FORMAT_S20_3LE
:
746 case SNDRV_PCM_FORMAT_S24_LE
:
749 case SNDRV_PCM_FORMAT_S32_LE
:
756 wm8900_write(codec
, WM8900_REG_AUDIO1
, reg
);
765 u16 fll_slow_lock_ref
;
770 /* The size in bits of the FLL divide multiplied by 10
771 * to allow rounding later */
772 #define FIXED_FLL_SIZE ((1 << 16) * 10)
774 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
778 unsigned int K
, Ndiv
, Nmod
, target
;
783 /* The FLL must run at 90-100MHz which is then scaled down to
784 * the output value by FLLCLK_DIV. */
787 while (target
< 90000000) {
792 if (target
> 100000000)
793 printk(KERN_WARNING
"wm8900: FLL rate %d out of range, Fref=%d"
794 " Fout=%d\n", target
, Fref
, Fout
);
796 printk(KERN_ERR
"wm8900: Invalid FLL division rate %u, "
797 "Fref=%d, Fout=%d, target=%d\n",
798 div
, Fref
, Fout
, target
);
802 fll_div
->fllclk_div
= div
>> 2;
805 fll_div
->fll_slow_lock_ref
= 1;
807 fll_div
->fll_slow_lock_ref
= 0;
809 Ndiv
= target
/ Fref
;
812 fll_div
->fll_ratio
= 8;
814 fll_div
->fll_ratio
= 1;
816 fll_div
->n
= Ndiv
/ fll_div
->fll_ratio
;
817 Nmod
= (target
/ fll_div
->fll_ratio
) % Fref
;
819 /* Calculate fractional part - scale up so we can round. */
820 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
824 K
= Kpart
& 0xFFFFFFFF;
829 /* Move down to proper range now rounding is done */
832 BUG_ON(target
!= Fout
* (fll_div
->fllclk_div
<< 2));
833 BUG_ON(!K
&& target
!= Fref
* fll_div
->fll_ratio
* fll_div
->n
);
838 static int wm8900_set_fll(struct snd_soc_codec
*codec
,
839 int fll_id
, unsigned int freq_in
, unsigned int freq_out
)
841 struct wm8900_priv
*wm8900
= codec
->private_data
;
842 struct _fll_div fll_div
;
845 if (wm8900
->fll_in
== freq_in
&& wm8900
->fll_out
== freq_out
)
848 /* The digital side should be disabled during any change. */
849 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
850 wm8900_write(codec
, WM8900_REG_POWER1
,
851 reg
& (~WM8900_REG_POWER1_FLL_ENA
));
853 /* Disable the FLL? */
854 if (!freq_in
|| !freq_out
) {
855 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
856 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
857 reg
& (~WM8900_REG_CLOCKING1_MCLK_SRC
));
859 reg
= wm8900_read(codec
, WM8900_REG_FLLCTL1
);
860 wm8900_write(codec
, WM8900_REG_FLLCTL1
,
861 reg
& (~WM8900_REG_FLLCTL1_OSC_ENA
));
863 wm8900
->fll_in
= freq_in
;
864 wm8900
->fll_out
= freq_out
;
869 if (fll_factors(&fll_div
, freq_in
, freq_out
) != 0)
872 wm8900
->fll_in
= freq_in
;
873 wm8900
->fll_out
= freq_out
;
875 /* The osclilator *MUST* be enabled before we enable the
876 * digital circuit. */
877 wm8900_write(codec
, WM8900_REG_FLLCTL1
,
878 fll_div
.fll_ratio
| WM8900_REG_FLLCTL1_OSC_ENA
);
880 wm8900_write(codec
, WM8900_REG_FLLCTL4
, fll_div
.n
>> 5);
881 wm8900_write(codec
, WM8900_REG_FLLCTL5
,
882 (fll_div
.fllclk_div
<< 6) | (fll_div
.n
& 0x1f));
885 wm8900_write(codec
, WM8900_REG_FLLCTL2
,
886 (fll_div
.k
>> 8) | 0x100);
887 wm8900_write(codec
, WM8900_REG_FLLCTL3
, fll_div
.k
& 0xff);
889 wm8900_write(codec
, WM8900_REG_FLLCTL2
, 0);
891 if (fll_div
.fll_slow_lock_ref
)
892 wm8900_write(codec
, WM8900_REG_FLLCTL6
,
893 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF
);
895 wm8900_write(codec
, WM8900_REG_FLLCTL6
, 0);
897 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
898 wm8900_write(codec
, WM8900_REG_POWER1
,
899 reg
| WM8900_REG_POWER1_FLL_ENA
);
902 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
903 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
904 reg
| WM8900_REG_CLOCKING1_MCLK_SRC
);
909 static int wm8900_set_dai_pll(struct snd_soc_dai
*codec_dai
,
910 int pll_id
, unsigned int freq_in
, unsigned int freq_out
)
912 return wm8900_set_fll(codec_dai
->codec
, pll_id
, freq_in
, freq_out
);
915 static int wm8900_set_dai_clkdiv(struct snd_soc_dai
*codec_dai
,
918 struct snd_soc_codec
*codec
= codec_dai
->codec
;
922 case WM8900_BCLK_DIV
:
923 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
924 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
925 div
| (reg
& WM8900_REG_CLOCKING1_BCLK_MASK
));
927 case WM8900_OPCLK_DIV
:
928 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
929 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
930 div
| (reg
& WM8900_REG_CLOCKING1_OPCLK_MASK
));
932 case WM8900_DAC_LRCLK
:
933 reg
= wm8900_read(codec
, WM8900_REG_AUDIO4
);
934 wm8900_write(codec
, WM8900_REG_AUDIO4
,
935 div
| (reg
& WM8900_LRC_MASK
));
937 case WM8900_ADC_LRCLK
:
938 reg
= wm8900_read(codec
, WM8900_REG_AUDIO3
);
939 wm8900_write(codec
, WM8900_REG_AUDIO3
,
940 div
| (reg
& WM8900_LRC_MASK
));
942 case WM8900_DAC_CLKDIV
:
943 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING2
);
944 wm8900_write(codec
, WM8900_REG_CLOCKING2
,
945 div
| (reg
& WM8900_REG_CLOCKING2_DAC_CLKDIV
));
947 case WM8900_ADC_CLKDIV
:
948 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING2
);
949 wm8900_write(codec
, WM8900_REG_CLOCKING2
,
950 div
| (reg
& WM8900_REG_CLOCKING2_ADC_CLKDIV
));
952 case WM8900_LRCLK_MODE
:
953 reg
= wm8900_read(codec
, WM8900_REG_DACCTRL
);
954 wm8900_write(codec
, WM8900_REG_DACCTRL
,
955 div
| (reg
& WM8900_REG_DACCTRL_AIF_LRCLKRATE
));
965 static int wm8900_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
968 struct snd_soc_codec
*codec
= codec_dai
->codec
;
969 unsigned int clocking1
, aif1
, aif3
, aif4
;
971 clocking1
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
972 aif1
= wm8900_read(codec
, WM8900_REG_AUDIO1
);
973 aif3
= wm8900_read(codec
, WM8900_REG_AUDIO3
);
974 aif4
= wm8900_read(codec
, WM8900_REG_AUDIO4
);
976 /* set master/slave audio interface */
977 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
978 case SND_SOC_DAIFMT_CBS_CFS
:
979 clocking1
&= ~WM8900_REG_CLOCKING1_BCLK_DIR
;
980 aif3
&= ~WM8900_REG_AUDIO3_ADCLRC_DIR
;
981 aif4
&= ~WM8900_REG_AUDIO4_DACLRC_DIR
;
983 case SND_SOC_DAIFMT_CBS_CFM
:
984 clocking1
&= ~WM8900_REG_CLOCKING1_BCLK_DIR
;
985 aif3
|= WM8900_REG_AUDIO3_ADCLRC_DIR
;
986 aif4
|= WM8900_REG_AUDIO4_DACLRC_DIR
;
988 case SND_SOC_DAIFMT_CBM_CFM
:
989 clocking1
|= WM8900_REG_CLOCKING1_BCLK_DIR
;
990 aif3
|= WM8900_REG_AUDIO3_ADCLRC_DIR
;
991 aif4
|= WM8900_REG_AUDIO4_DACLRC_DIR
;
993 case SND_SOC_DAIFMT_CBM_CFS
:
994 clocking1
|= WM8900_REG_CLOCKING1_BCLK_DIR
;
995 aif3
&= ~WM8900_REG_AUDIO3_ADCLRC_DIR
;
996 aif4
&= ~WM8900_REG_AUDIO4_DACLRC_DIR
;
1002 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1003 case SND_SOC_DAIFMT_DSP_A
:
1004 aif1
|= WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1005 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1007 case SND_SOC_DAIFMT_DSP_B
:
1008 aif1
|= WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1009 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1011 case SND_SOC_DAIFMT_I2S
:
1012 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1015 case SND_SOC_DAIFMT_RIGHT_J
:
1016 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1018 case SND_SOC_DAIFMT_LEFT_J
:
1019 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1026 /* Clock inversion */
1027 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1028 case SND_SOC_DAIFMT_DSP_A
:
1029 case SND_SOC_DAIFMT_DSP_B
:
1030 /* frame inversion not valid for DSP modes */
1031 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1032 case SND_SOC_DAIFMT_NB_NF
:
1033 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1035 case SND_SOC_DAIFMT_IB_NF
:
1036 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1042 case SND_SOC_DAIFMT_I2S
:
1043 case SND_SOC_DAIFMT_RIGHT_J
:
1044 case SND_SOC_DAIFMT_LEFT_J
:
1045 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1046 case SND_SOC_DAIFMT_NB_NF
:
1047 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1048 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1050 case SND_SOC_DAIFMT_IB_IF
:
1051 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1052 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1054 case SND_SOC_DAIFMT_IB_NF
:
1055 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1056 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1058 case SND_SOC_DAIFMT_NB_IF
:
1059 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1060 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1070 wm8900_write(codec
, WM8900_REG_CLOCKING1
, clocking1
);
1071 wm8900_write(codec
, WM8900_REG_AUDIO1
, aif1
);
1072 wm8900_write(codec
, WM8900_REG_AUDIO3
, aif3
);
1073 wm8900_write(codec
, WM8900_REG_AUDIO4
, aif4
);
1078 static int wm8900_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1080 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1083 reg
= wm8900_read(codec
, WM8900_REG_DACCTRL
);
1086 reg
|= WM8900_REG_DACCTRL_MUTE
;
1088 reg
&= ~WM8900_REG_DACCTRL_MUTE
;
1090 wm8900_write(codec
, WM8900_REG_DACCTRL
, reg
);
1095 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1096 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1097 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1099 #define WM8900_PCM_FORMATS \
1100 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1101 SNDRV_PCM_FORMAT_S24_LE)
1103 struct snd_soc_dai wm8900_dai
= {
1104 .name
= "WM8900 HiFi",
1106 .stream_name
= "HiFi Playback",
1109 .rates
= WM8900_RATES
,
1110 .formats
= WM8900_PCM_FORMATS
,
1113 .stream_name
= "HiFi Capture",
1116 .rates
= WM8900_RATES
,
1117 .formats
= WM8900_PCM_FORMATS
,
1120 .hw_params
= wm8900_hw_params
,
1121 .set_clkdiv
= wm8900_set_dai_clkdiv
,
1122 .set_pll
= wm8900_set_dai_pll
,
1123 .set_fmt
= wm8900_set_dai_fmt
,
1124 .digital_mute
= wm8900_digital_mute
,
1127 EXPORT_SYMBOL_GPL(wm8900_dai
);
1129 static int wm8900_set_bias_level(struct snd_soc_codec
*codec
,
1130 enum snd_soc_bias_level level
)
1135 case SND_SOC_BIAS_ON
:
1136 /* Enable thermal shutdown */
1137 reg
= wm8900_read(codec
, WM8900_REG_GPIO
);
1138 wm8900_write(codec
, WM8900_REG_GPIO
,
1139 reg
| WM8900_REG_GPIO_TEMP_ENA
);
1140 reg
= wm8900_read(codec
, WM8900_REG_ADDCTL
);
1141 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1142 reg
| WM8900_REG_ADDCTL_TEMP_SD
);
1145 case SND_SOC_BIAS_PREPARE
:
1148 case SND_SOC_BIAS_STANDBY
:
1149 /* Charge capacitors if initial power up */
1150 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
1151 /* STARTUP_BIAS_ENA on */
1152 wm8900_write(codec
, WM8900_REG_POWER1
,
1153 WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1155 /* Startup bias mode */
1156 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1157 WM8900_REG_ADDCTL_BIAS_SRC
|
1158 WM8900_REG_ADDCTL_VMID_SOFTST
);
1161 wm8900_write(codec
, WM8900_REG_POWER1
,
1162 WM8900_REG_POWER1_STARTUP_BIAS_ENA
| 0x1);
1164 /* Allow capacitors to charge */
1165 schedule_timeout_interruptible(msecs_to_jiffies(400));
1168 wm8900_write(codec
, WM8900_REG_POWER1
,
1169 WM8900_REG_POWER1_STARTUP_BIAS_ENA
|
1170 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1172 wm8900_write(codec
, WM8900_REG_ADDCTL
, 0);
1174 wm8900_write(codec
, WM8900_REG_POWER1
,
1175 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1178 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
1179 wm8900_write(codec
, WM8900_REG_POWER1
,
1180 (reg
& WM8900_REG_POWER1_FLL_ENA
) |
1181 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1182 wm8900_write(codec
, WM8900_REG_POWER2
,
1183 WM8900_REG_POWER2_SYSCLK_ENA
);
1184 wm8900_write(codec
, WM8900_REG_POWER3
, 0);
1187 case SND_SOC_BIAS_OFF
:
1188 /* Startup bias enable */
1189 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
1190 wm8900_write(codec
, WM8900_REG_POWER1
,
1191 reg
& WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1192 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1193 WM8900_REG_ADDCTL_BIAS_SRC
|
1194 WM8900_REG_ADDCTL_VMID_SOFTST
);
1196 /* Discharge caps */
1197 wm8900_write(codec
, WM8900_REG_POWER1
,
1198 WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1199 schedule_timeout_interruptible(msecs_to_jiffies(500));
1202 wm8900_write(codec
, WM8900_REG_HPCTL1
, 0);
1205 wm8900_write(codec
, WM8900_REG_ADDCTL
, 0);
1206 wm8900_write(codec
, WM8900_REG_POWER1
, 0);
1207 wm8900_write(codec
, WM8900_REG_POWER2
, 0);
1208 wm8900_write(codec
, WM8900_REG_POWER3
, 0);
1210 /* Need to let things settle before stopping the clock
1211 * to ensure that restart works, see "Stopping the
1212 * master clock" in the datasheet. */
1213 schedule_timeout_interruptible(msecs_to_jiffies(1));
1214 wm8900_write(codec
, WM8900_REG_POWER2
,
1215 WM8900_REG_POWER2_SYSCLK_ENA
);
1218 codec
->bias_level
= level
;
1222 static int wm8900_suspend(struct platform_device
*pdev
, pm_message_t state
)
1224 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1225 struct snd_soc_codec
*codec
= socdev
->codec
;
1226 struct wm8900_priv
*wm8900
= codec
->private_data
;
1227 int fll_out
= wm8900
->fll_out
;
1228 int fll_in
= wm8900
->fll_in
;
1231 /* Stop the FLL in an orderly fashion */
1232 ret
= wm8900_set_fll(codec
, 0, 0, 0);
1234 dev_err(&pdev
->dev
, "Failed to stop FLL\n");
1238 wm8900
->fll_out
= fll_out
;
1239 wm8900
->fll_in
= fll_in
;
1241 wm8900_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1246 static int wm8900_resume(struct platform_device
*pdev
)
1248 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1249 struct snd_soc_codec
*codec
= socdev
->codec
;
1250 struct wm8900_priv
*wm8900
= codec
->private_data
;
1254 cache
= kmemdup(codec
->reg_cache
, sizeof(wm8900_reg_defaults
),
1257 wm8900_reset(codec
);
1258 wm8900_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1260 /* Restart the FLL? */
1261 if (wm8900
->fll_out
) {
1262 int fll_out
= wm8900
->fll_out
;
1263 int fll_in
= wm8900
->fll_in
;
1266 wm8900
->fll_out
= 0;
1268 ret
= wm8900_set_fll(codec
, 0, fll_in
, fll_out
);
1270 dev_err(&pdev
->dev
, "Failed to restart FLL\n");
1276 for (i
= 0; i
< WM8900_MAXREG
; i
++)
1277 wm8900_write(codec
, i
, cache
[i
]);
1280 dev_err(&pdev
->dev
, "Unable to allocate register cache\n");
1286 * initialise the WM8900 driver
1287 * register the mixer and dsp interfaces with the kernel
1289 static int wm8900_init(struct snd_soc_device
*socdev
)
1291 struct snd_soc_codec
*codec
= socdev
->codec
;
1294 struct i2c_client
*i2c_client
= socdev
->codec
->control_data
;
1296 codec
->name
= "WM8900";
1297 codec
->owner
= THIS_MODULE
;
1298 codec
->read
= wm8900_read
;
1299 codec
->write
= wm8900_write
;
1300 codec
->dai
= &wm8900_dai
;
1302 codec
->reg_cache_size
= WM8900_MAXREG
;
1303 codec
->reg_cache
= kmemdup(wm8900_reg_defaults
,
1304 sizeof(wm8900_reg_defaults
), GFP_KERNEL
);
1306 if (codec
->reg_cache
== NULL
)
1309 reg
= wm8900_read(codec
, WM8900_REG_ID
);
1310 if (reg
!= 0x8900) {
1311 dev_err(&i2c_client
->dev
, "Device is not a WM8900 - ID %x\n",
1316 codec
->private_data
= kzalloc(sizeof(struct wm8900_priv
), GFP_KERNEL
);
1317 if (codec
->private_data
== NULL
) {
1322 /* Read back from the chip */
1323 reg
= wm8900_chip_read(codec
, WM8900_REG_POWER1
);
1324 reg
= (reg
>> 12) & 0xf;
1325 dev_info(&i2c_client
->dev
, "WM8900 revision %d\n", reg
);
1327 wm8900_reset(codec
);
1329 /* Latch the volume update bits */
1330 wm8900_write(codec
, WM8900_REG_LINVOL
,
1331 wm8900_read(codec
, WM8900_REG_LINVOL
) | 0x100);
1332 wm8900_write(codec
, WM8900_REG_RINVOL
,
1333 wm8900_read(codec
, WM8900_REG_RINVOL
) | 0x100);
1334 wm8900_write(codec
, WM8900_REG_LOUT1CTL
,
1335 wm8900_read(codec
, WM8900_REG_LOUT1CTL
) | 0x100);
1336 wm8900_write(codec
, WM8900_REG_ROUT1CTL
,
1337 wm8900_read(codec
, WM8900_REG_ROUT1CTL
) | 0x100);
1338 wm8900_write(codec
, WM8900_REG_LOUT2CTL
,
1339 wm8900_read(codec
, WM8900_REG_LOUT2CTL
) | 0x100);
1340 wm8900_write(codec
, WM8900_REG_ROUT2CTL
,
1341 wm8900_read(codec
, WM8900_REG_ROUT2CTL
) | 0x100);
1342 wm8900_write(codec
, WM8900_REG_LDAC_DV
,
1343 wm8900_read(codec
, WM8900_REG_LDAC_DV
) | 0x100);
1344 wm8900_write(codec
, WM8900_REG_RDAC_DV
,
1345 wm8900_read(codec
, WM8900_REG_RDAC_DV
) | 0x100);
1346 wm8900_write(codec
, WM8900_REG_LADC_DV
,
1347 wm8900_read(codec
, WM8900_REG_LADC_DV
) | 0x100);
1348 wm8900_write(codec
, WM8900_REG_RADC_DV
,
1349 wm8900_read(codec
, WM8900_REG_RADC_DV
) | 0x100);
1351 /* Set the DAC and mixer output bias */
1352 wm8900_write(codec
, WM8900_REG_OUTBIASCTL
, 0x81);
1355 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1357 dev_err(&i2c_client
->dev
, "Failed to register new PCMs\n");
1361 /* Turn the chip on */
1362 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1363 wm8900_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1365 wm8900_add_controls(codec
);
1366 wm8900_add_widgets(codec
);
1368 ret
= snd_soc_init_card(socdev
);
1370 dev_err(&i2c_client
->dev
, "Failed to register card\n");
1376 snd_soc_free_pcms(socdev
);
1377 snd_soc_dapm_free(socdev
);
1379 kfree(codec
->reg_cache
);
1381 kfree(codec
->private_data
);
1385 static struct i2c_client
*wm8900_client
;
1387 static int wm8900_i2c_probe(struct i2c_client
*i2c
,
1388 const struct i2c_device_id
*id
)
1390 wm8900_client
= i2c
;
1391 wm8900_dai
.dev
= &i2c
->dev
;
1392 return snd_soc_register_dai(&wm8900_dai
);
1395 static int wm8900_i2c_remove(struct i2c_client
*client
)
1397 snd_soc_unregister_dai(&wm8900_dai
);
1398 wm8900_dai
.dev
= NULL
;
1399 wm8900_client
= NULL
;
1403 static const struct i2c_device_id wm8900_i2c_id
[] = {
1407 MODULE_DEVICE_TABLE(i2c
, wm8900_i2c_id
);
1409 static struct i2c_driver wm8900_i2c_driver
= {
1411 .name
= "WM8900 I2C codec",
1412 .owner
= THIS_MODULE
,
1414 .probe
= wm8900_i2c_probe
,
1415 .remove
= wm8900_i2c_remove
,
1416 .id_table
= wm8900_i2c_id
,
1419 static int wm8900_probe(struct platform_device
*pdev
)
1421 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1422 struct snd_soc_codec
*codec
;
1425 if (!wm8900_client
) {
1426 dev_err(&pdev
->dev
, "I2C client not yet instantiated\n");
1430 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1434 mutex_init(&codec
->mutex
);
1435 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1436 INIT_LIST_HEAD(&codec
->dapm_paths
);
1438 socdev
->codec
= codec
;
1440 codec
->set_bias_level
= wm8900_set_bias_level
;
1442 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
1443 codec
->control_data
= wm8900_client
;
1445 ret
= wm8900_init(socdev
);
1452 /* power down chip */
1453 static int wm8900_remove(struct platform_device
*pdev
)
1455 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1456 struct snd_soc_codec
*codec
= socdev
->codec
;
1458 if (codec
->control_data
)
1459 wm8900_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1461 snd_soc_free_pcms(socdev
);
1462 snd_soc_dapm_free(socdev
);
1468 struct snd_soc_codec_device soc_codec_dev_wm8900
= {
1469 .probe
= wm8900_probe
,
1470 .remove
= wm8900_remove
,
1471 .suspend
= wm8900_suspend
,
1472 .resume
= wm8900_resume
,
1474 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900
);
1476 static int __devinit
wm8900_modinit(void)
1478 return i2c_add_driver(&wm8900_i2c_driver
);
1480 module_init(wm8900_modinit
);
1482 static void __exit
wm8900_exit(void)
1484 i2c_del_driver(&wm8900_i2c_driver
);
1486 module_exit(wm8900_exit
);
1488 MODULE_DESCRIPTION("ASoC WM8900 driver");
1489 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1490 MODULE_LICENSE("GPL");