2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
37 /* WM8900 register space */
38 #define WM8900_REG_RESET 0x0
39 #define WM8900_REG_ID 0x0
40 #define WM8900_REG_POWER1 0x1
41 #define WM8900_REG_POWER2 0x2
42 #define WM8900_REG_POWER3 0x3
43 #define WM8900_REG_AUDIO1 0x4
44 #define WM8900_REG_AUDIO2 0x5
45 #define WM8900_REG_CLOCKING1 0x6
46 #define WM8900_REG_CLOCKING2 0x7
47 #define WM8900_REG_AUDIO3 0x8
48 #define WM8900_REG_AUDIO4 0x9
49 #define WM8900_REG_DACCTRL 0xa
50 #define WM8900_REG_LDAC_DV 0xb
51 #define WM8900_REG_RDAC_DV 0xc
52 #define WM8900_REG_SIDETONE 0xd
53 #define WM8900_REG_ADCCTRL 0xe
54 #define WM8900_REG_LADC_DV 0xf
55 #define WM8900_REG_RADC_DV 0x10
56 #define WM8900_REG_GPIO 0x12
57 #define WM8900_REG_INCTL 0x15
58 #define WM8900_REG_LINVOL 0x16
59 #define WM8900_REG_RINVOL 0x17
60 #define WM8900_REG_INBOOSTMIX1 0x18
61 #define WM8900_REG_INBOOSTMIX2 0x19
62 #define WM8900_REG_ADCPATH 0x1a
63 #define WM8900_REG_AUXBOOST 0x1b
64 #define WM8900_REG_ADDCTL 0x1e
65 #define WM8900_REG_FLLCTL1 0x24
66 #define WM8900_REG_FLLCTL2 0x25
67 #define WM8900_REG_FLLCTL3 0x26
68 #define WM8900_REG_FLLCTL4 0x27
69 #define WM8900_REG_FLLCTL5 0x28
70 #define WM8900_REG_FLLCTL6 0x29
71 #define WM8900_REG_LOUTMIXCTL1 0x2c
72 #define WM8900_REG_ROUTMIXCTL1 0x2d
73 #define WM8900_REG_BYPASS1 0x2e
74 #define WM8900_REG_BYPASS2 0x2f
75 #define WM8900_REG_AUXOUT_CTL 0x30
76 #define WM8900_REG_LOUT1CTL 0x33
77 #define WM8900_REG_ROUT1CTL 0x34
78 #define WM8900_REG_LOUT2CTL 0x35
79 #define WM8900_REG_ROUT2CTL 0x36
80 #define WM8900_REG_HPCTL1 0x3a
81 #define WM8900_REG_OUTBIASCTL 0x73
83 #define WM8900_MAXREG 0x80
85 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
88 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
92 #define WM8900_REG_GPIO_TEMP_ENA 0x2
94 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
96 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97 #define WM8900_REG_POWER1_FLL_ENA 0x0040
99 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
101 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
103 #define WM8900_REG_POWER3_DACL_ENA 0x0002
104 #define WM8900_REG_POWER3_DACR_ENA 0x0001
106 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
112 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
113 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
115 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118 #define WM8900_REG_DACCTRL_MUTE 0x004
119 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
130 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
131 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
132 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
133 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
134 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136 #define WM8900_LRC_MASK 0xfc00
138 struct snd_soc_codec_device soc_codec_dev_wm8900
;
141 struct snd_soc_codec codec
;
143 u16 reg_cache
[WM8900_MAXREG
];
145 u32 fll_in
; /* FLL input frequency */
146 u32 fll_out
; /* FLL output frequency */
150 * wm8900 register cache. We can't read the entire register space and we
151 * have slow control buses so we cache the registers.
153 static const u16 wm8900_reg_defaults
[WM8900_MAXREG
] = {
182 /* Remaining registers all zero */
186 * read wm8900 register cache
188 static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec
*codec
,
191 u16
*cache
= codec
->reg_cache
;
193 BUG_ON(reg
>= WM8900_MAXREG
);
195 if (reg
== WM8900_REG_ID
)
202 * write wm8900 register cache
204 static inline void wm8900_write_reg_cache(struct snd_soc_codec
*codec
,
205 u16 reg
, unsigned int value
)
207 u16
*cache
= codec
->reg_cache
;
209 BUG_ON(reg
>= WM8900_MAXREG
);
215 * write to the WM8900 register space
217 static int wm8900_write(struct snd_soc_codec
*codec
, unsigned int reg
,
222 if (value
== wm8900_read_reg_cache(codec
, reg
))
226 * D15..D9 WM8900 register offset
227 * D8...D0 register data
230 data
[1] = value
>> 8;
231 data
[2] = value
& 0x00ff;
233 wm8900_write_reg_cache(codec
, reg
, value
);
234 if (codec
->hw_write(codec
->control_data
, data
, 3) == 3)
241 * Read from the wm8900.
243 static unsigned int wm8900_chip_read(struct snd_soc_codec
*codec
, u8 reg
)
245 struct i2c_msg xfer
[2];
248 struct i2c_client
*client
= codec
->control_data
;
250 BUG_ON(reg
!= WM8900_REG_ID
&& reg
!= WM8900_REG_POWER1
);
253 xfer
[0].addr
= client
->addr
;
259 xfer
[1].addr
= client
->addr
;
260 xfer
[1].flags
= I2C_M_RD
;
262 xfer
[1].buf
= (u8
*)&data
;
264 ret
= i2c_transfer(client
->adapter
, xfer
, 2);
266 printk(KERN_CRIT
"i2c_transfer returned %d\n", ret
);
270 return (data
>> 8) | ((data
& 0xff) << 8);
274 * Read from the WM8900 register space. Most registers can't be read
275 * and are therefore supplied from cache.
277 static unsigned int wm8900_read(struct snd_soc_codec
*codec
, unsigned int reg
)
281 return wm8900_chip_read(codec
, reg
);
283 return wm8900_read_reg_cache(codec
, reg
);
287 static void wm8900_reset(struct snd_soc_codec
*codec
)
289 wm8900_write(codec
, WM8900_REG_RESET
, 0);
291 memcpy(codec
->reg_cache
, wm8900_reg_defaults
,
292 sizeof(codec
->reg_cache
));
295 static int wm8900_hp_event(struct snd_soc_dapm_widget
*w
,
296 struct snd_kcontrol
*kcontrol
, int event
)
298 struct snd_soc_codec
*codec
= w
->codec
;
299 u16 hpctl1
= wm8900_read(codec
, WM8900_REG_HPCTL1
);
302 case SND_SOC_DAPM_PRE_PMU
:
303 /* Clamp headphone outputs */
304 hpctl1
= WM8900_REG_HPCTL1_HP_CLAMP_IP
|
305 WM8900_REG_HPCTL1_HP_CLAMP_OP
;
306 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
309 case SND_SOC_DAPM_POST_PMU
:
310 /* Enable the input stage */
311 hpctl1
&= ~WM8900_REG_HPCTL1_HP_CLAMP_IP
;
312 hpctl1
|= WM8900_REG_HPCTL1_HP_SHORT
|
313 WM8900_REG_HPCTL1_HP_SHORT2
|
314 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA
;
315 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
319 /* Enable the output stage */
320 hpctl1
&= ~WM8900_REG_HPCTL1_HP_CLAMP_OP
;
321 hpctl1
|= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA
;
322 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
324 /* Remove the shorts */
325 hpctl1
&= ~WM8900_REG_HPCTL1_HP_SHORT2
;
326 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
327 hpctl1
&= ~WM8900_REG_HPCTL1_HP_SHORT
;
328 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
331 case SND_SOC_DAPM_PRE_PMD
:
332 /* Short the output */
333 hpctl1
|= WM8900_REG_HPCTL1_HP_SHORT
;
334 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
336 /* Disable the output stage */
337 hpctl1
&= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA
;
338 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
340 /* Clamp the outputs and power down input */
341 hpctl1
|= WM8900_REG_HPCTL1_HP_CLAMP_IP
|
342 WM8900_REG_HPCTL1_HP_CLAMP_OP
;
343 hpctl1
&= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA
;
344 wm8900_write(codec
, WM8900_REG_HPCTL1
, hpctl1
);
347 case SND_SOC_DAPM_POST_PMD
:
348 /* Disable everything */
349 wm8900_write(codec
, WM8900_REG_HPCTL1
, 0);
359 static const DECLARE_TLV_DB_SCALE(out_pga_tlv
, -5700, 100, 0);
361 static const DECLARE_TLV_DB_SCALE(out_mix_tlv
, -1500, 300, 0);
363 static const DECLARE_TLV_DB_SCALE(in_boost_tlv
, -1200, 600, 0);
365 static const DECLARE_TLV_DB_SCALE(in_pga_tlv
, -1200, 100, 0);
367 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
369 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -7200, 75, 1);
371 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv
, -3600, 300, 0);
373 static const DECLARE_TLV_DB_SCALE(adc_tlv
, -7200, 75, 1);
375 static const char *mic_bias_level_txt
[] = { "0.9*AVDD", "0.65*AVDD" };
377 static const struct soc_enum mic_bias_level
=
378 SOC_ENUM_SINGLE(WM8900_REG_INCTL
, 8, 2, mic_bias_level_txt
);
380 static const char *dac_mute_rate_txt
[] = { "Fast", "Slow" };
382 static const struct soc_enum dac_mute_rate
=
383 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL
, 7, 2, dac_mute_rate_txt
);
385 static const char *dac_deemphasis_txt
[] = {
386 "Disabled", "32kHz", "44.1kHz", "48kHz"
389 static const struct soc_enum dac_deemphasis
=
390 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL
, 4, 4, dac_deemphasis_txt
);
392 static const char *adc_hpf_cut_txt
[] = {
393 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
396 static const struct soc_enum adc_hpf_cut
=
397 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL
, 5, 4, adc_hpf_cut_txt
);
399 static const char *lr_txt
[] = {
403 static const struct soc_enum aifl_src
=
404 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1
, 15, 2, lr_txt
);
406 static const struct soc_enum aifr_src
=
407 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1
, 14, 2, lr_txt
);
409 static const struct soc_enum dacl_src
=
410 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2
, 15, 2, lr_txt
);
412 static const struct soc_enum dacr_src
=
413 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2
, 14, 2, lr_txt
);
415 static const char *sidetone_txt
[] = {
416 "Disabled", "Left ADC", "Right ADC"
419 static const struct soc_enum dacl_sidetone
=
420 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE
, 2, 3, sidetone_txt
);
422 static const struct soc_enum dacr_sidetone
=
423 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE
, 0, 3, sidetone_txt
);
425 static const struct snd_kcontrol_new wm8900_snd_controls
[] = {
426 SOC_ENUM("Mic Bias Level", mic_bias_level
),
428 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL
, 0, 31, 0,
430 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL
, 6, 1, 1),
431 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL
, 7, 1, 0),
433 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL
, 0, 31, 0,
435 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL
, 6, 1, 1),
436 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL
, 7, 1, 0),
438 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL
, 6, 1, 1),
439 SOC_ENUM("DAC Mute Rate", dac_mute_rate
),
440 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL
, 9, 1, 0),
441 SOC_ENUM("DAC Deemphasis", dac_deemphasis
),
442 SOC_SINGLE("DAC Sloping Stopband Filter Switch", WM8900_REG_DACCTRL
, 8, 1, 0),
443 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL
,
446 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL
, 8, 1, 0),
447 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut
),
448 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL
, 1, 0, 1, 0),
449 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE
, 9, 12, 0,
451 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE
, 5, 12, 0,
453 SOC_ENUM("Left Digital Audio Source", aifl_src
),
454 SOC_ENUM("Right Digital Audio Source", aifr_src
),
456 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2
, 10, 4, 0,
458 SOC_ENUM("Left DAC Source", dacl_src
),
459 SOC_ENUM("Right DAC Source", dacr_src
),
460 SOC_ENUM("Left DAC Sidetone", dacl_sidetone
),
461 SOC_ENUM("Right DAC Sidetone", dacr_sidetone
),
462 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL
, 1, 0, 1, 0),
464 SOC_DOUBLE_R_TLV("Digital Playback Volume",
465 WM8900_REG_LDAC_DV
, WM8900_REG_RDAC_DV
,
467 SOC_DOUBLE_R_TLV("Digital Capture Volume",
468 WM8900_REG_LADC_DV
, WM8900_REG_RADC_DV
, 1, 119, 0, adc_tlv
),
470 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1
, 4, 7, 0,
472 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1
, 4, 7, 0,
474 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL
, 4, 7, 0,
476 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL
, 0, 7, 0,
479 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1
, 0, 7, 0,
481 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1
, 4, 7, 0,
483 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2
, 0, 7, 0,
485 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2
, 4, 7, 0,
488 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1
, 0, 3, 0,
490 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1
, 4, 3, 0,
492 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2
, 0, 3, 0,
494 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2
, 4, 3, 0,
496 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST
, 4, 3, 0,
498 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST
, 0, 3, 0,
501 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
502 0, 63, 0, out_pga_tlv
),
503 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
505 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL
, WM8900_REG_ROUT1CTL
,
508 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
509 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
,
510 0, 63, 0, out_pga_tlv
),
511 SOC_DOUBLE_R("LINEOUT2 Switch",
512 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
, 6, 1, 1),
513 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
514 WM8900_REG_LOUT2CTL
, WM8900_REG_ROUT2CTL
, 7, 1, 0),
515 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1
,
520 /* add non dapm controls */
521 static int wm8900_add_controls(struct snd_soc_codec
*codec
)
525 for (i
= 0; i
< ARRAY_SIZE(wm8900_snd_controls
); i
++) {
526 err
= snd_ctl_add(codec
->card
,
527 snd_soc_cnew(&wm8900_snd_controls
[i
],
536 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control
=
537 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3
, 6, 1, 0);
539 static const struct snd_kcontrol_new wm8900_dapm_routput2_control
=
540 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3
, 5, 1, 0);
542 static const struct snd_kcontrol_new wm8900_loutmix_controls
[] = {
543 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1
, 7, 1, 0),
544 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL
, 7, 1, 0),
545 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1
, 7, 1, 0),
546 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2
, 3, 1, 0),
547 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1
, 8, 1, 0),
550 static const struct snd_kcontrol_new wm8900_routmix_controls
[] = {
551 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1
, 7, 1, 0),
552 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL
, 3, 1, 0),
553 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1
, 3, 1, 0),
554 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2
, 7, 1, 0),
555 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1
, 8, 1, 0),
558 static const struct snd_kcontrol_new wm8900_linmix_controls
[] = {
559 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1
, 2, 1, 1),
560 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1
, 6, 1, 1),
561 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST
, 6, 1, 1),
562 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH
, 6, 1, 0),
565 static const struct snd_kcontrol_new wm8900_rinmix_controls
[] = {
566 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2
, 2, 1, 1),
567 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2
, 6, 1, 1),
568 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST
, 2, 1, 1),
569 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH
, 2, 1, 0),
572 static const struct snd_kcontrol_new wm8900_linpga_controls
[] = {
573 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL
, 6, 1, 0),
574 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL
, 5, 1, 0),
575 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL
, 4, 1, 0),
578 static const struct snd_kcontrol_new wm8900_rinpga_controls
[] = {
579 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL
, 2, 1, 0),
580 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL
, 1, 1, 0),
581 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL
, 0, 1, 0),
584 static const char *wm9700_lp_mux
[] = { "Disabled", "Enabled" };
586 static const struct soc_enum wm8900_lineout2_lp_mux
=
587 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1
, 1, 2, wm9700_lp_mux
);
589 static const struct snd_kcontrol_new wm8900_lineout2_lp
=
590 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux
);
592 static const struct snd_soc_dapm_widget wm8900_dapm_widgets
[] = {
594 /* Externally visible pins */
595 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
596 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
597 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
598 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
599 SND_SOC_DAPM_OUTPUT("HP_L"),
600 SND_SOC_DAPM_OUTPUT("HP_R"),
602 SND_SOC_DAPM_INPUT("RINPUT1"),
603 SND_SOC_DAPM_INPUT("LINPUT1"),
604 SND_SOC_DAPM_INPUT("RINPUT2"),
605 SND_SOC_DAPM_INPUT("LINPUT2"),
606 SND_SOC_DAPM_INPUT("RINPUT3"),
607 SND_SOC_DAPM_INPUT("LINPUT3"),
608 SND_SOC_DAPM_INPUT("AUX"),
610 SND_SOC_DAPM_VMID("VMID"),
613 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2
, 3, 0,
614 wm8900_linpga_controls
,
615 ARRAY_SIZE(wm8900_linpga_controls
)),
616 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2
, 2, 0,
617 wm8900_rinpga_controls
,
618 ARRAY_SIZE(wm8900_rinpga_controls
)),
620 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2
, 5, 0,
621 wm8900_linmix_controls
,
622 ARRAY_SIZE(wm8900_linmix_controls
)),
623 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2
, 4, 0,
624 wm8900_rinmix_controls
,
625 ARRAY_SIZE(wm8900_rinmix_controls
)),
627 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1
, 4, 0),
629 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2
, 1, 0),
630 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2
, 0, 0),
633 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3
, 1, 0),
634 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3
, 0, 0),
636 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3
, 7, 0, NULL
, 0,
638 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
639 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
641 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2
, 8, 0, NULL
, 0),
642 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2
, 7, 0, NULL
, 0),
644 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM
, 0, 0, &wm8900_lineout2_lp
),
645 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3
, 6, 0, NULL
, 0),
646 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3
, 5, 0, NULL
, 0),
648 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3
, 3, 0,
649 wm8900_loutmix_controls
,
650 ARRAY_SIZE(wm8900_loutmix_controls
)),
651 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3
, 2, 0,
652 wm8900_routmix_controls
,
653 ARRAY_SIZE(wm8900_routmix_controls
)),
656 /* Target, Path, Source */
657 static const struct snd_soc_dapm_route audio_map
[] = {
659 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
660 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
661 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
663 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
664 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
665 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
667 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
668 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
669 {"Left Input Mixer", "AUX Switch", "AUX"},
670 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
672 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
673 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
674 {"Right Input Mixer", "AUX Switch", "AUX"},
675 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
677 {"ADCL", NULL
, "Left Input Mixer"},
678 {"ADCR", NULL
, "Right Input Mixer"},
681 {"LINEOUT1L", NULL
, "LINEOUT1L PGA"},
682 {"LINEOUT1L PGA", NULL
, "Left Output Mixer"},
683 {"LINEOUT1R", NULL
, "LINEOUT1R PGA"},
684 {"LINEOUT1R PGA", NULL
, "Right Output Mixer"},
686 {"LINEOUT2L PGA", NULL
, "Left Output Mixer"},
687 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
688 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
689 {"LINEOUT2L", NULL
, "LINEOUT2 LP"},
691 {"LINEOUT2R PGA", NULL
, "Right Output Mixer"},
692 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
693 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
694 {"LINEOUT2R", NULL
, "LINEOUT2 LP"},
696 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
697 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
698 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
699 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
700 {"Left Output Mixer", "DACL Switch", "DACL"},
702 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
703 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
704 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
705 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
706 {"Right Output Mixer", "DACR Switch", "DACR"},
708 /* Note that the headphone output stage needs to be connected
709 * externally to LINEOUT2 via DC blocking capacitors. Other
710 * configurations are not supported.
712 * Note also that left and right headphone paths are treated as a
715 {"Headphone Amplifier", NULL
, "LINEOUT2 LP"},
716 {"Headphone Amplifier", NULL
, "LINEOUT2 LP"},
717 {"HP_L", NULL
, "Headphone Amplifier"},
718 {"HP_R", NULL
, "Headphone Amplifier"},
721 static int wm8900_add_widgets(struct snd_soc_codec
*codec
)
723 snd_soc_dapm_new_controls(codec
, wm8900_dapm_widgets
,
724 ARRAY_SIZE(wm8900_dapm_widgets
));
726 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
728 snd_soc_dapm_new_widgets(codec
);
733 static int wm8900_hw_params(struct snd_pcm_substream
*substream
,
734 struct snd_pcm_hw_params
*params
,
735 struct snd_soc_dai
*dai
)
737 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
738 struct snd_soc_device
*socdev
= rtd
->socdev
;
739 struct snd_soc_codec
*codec
= socdev
->codec
;
742 reg
= wm8900_read(codec
, WM8900_REG_AUDIO1
) & ~0x60;
744 switch (params_format(params
)) {
745 case SNDRV_PCM_FORMAT_S16_LE
:
747 case SNDRV_PCM_FORMAT_S20_3LE
:
750 case SNDRV_PCM_FORMAT_S24_LE
:
753 case SNDRV_PCM_FORMAT_S32_LE
:
760 wm8900_write(codec
, WM8900_REG_AUDIO1
, reg
);
769 u16 fll_slow_lock_ref
;
774 /* The size in bits of the FLL divide multiplied by 10
775 * to allow rounding later */
776 #define FIXED_FLL_SIZE ((1 << 16) * 10)
778 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
782 unsigned int K
, Ndiv
, Nmod
, target
;
787 /* The FLL must run at 90-100MHz which is then scaled down to
788 * the output value by FLLCLK_DIV. */
791 while (target
< 90000000) {
796 if (target
> 100000000)
797 printk(KERN_WARNING
"wm8900: FLL rate %d out of range, Fref=%d"
798 " Fout=%d\n", target
, Fref
, Fout
);
800 printk(KERN_ERR
"wm8900: Invalid FLL division rate %u, "
801 "Fref=%d, Fout=%d, target=%d\n",
802 div
, Fref
, Fout
, target
);
806 fll_div
->fllclk_div
= div
>> 2;
809 fll_div
->fll_slow_lock_ref
= 1;
811 fll_div
->fll_slow_lock_ref
= 0;
813 Ndiv
= target
/ Fref
;
816 fll_div
->fll_ratio
= 8;
818 fll_div
->fll_ratio
= 1;
820 fll_div
->n
= Ndiv
/ fll_div
->fll_ratio
;
821 Nmod
= (target
/ fll_div
->fll_ratio
) % Fref
;
823 /* Calculate fractional part - scale up so we can round. */
824 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
828 K
= Kpart
& 0xFFFFFFFF;
833 /* Move down to proper range now rounding is done */
836 BUG_ON(target
!= Fout
* (fll_div
->fllclk_div
<< 2));
837 BUG_ON(!K
&& target
!= Fref
* fll_div
->fll_ratio
* fll_div
->n
);
842 static int wm8900_set_fll(struct snd_soc_codec
*codec
,
843 int fll_id
, unsigned int freq_in
, unsigned int freq_out
)
845 struct wm8900_priv
*wm8900
= codec
->private_data
;
846 struct _fll_div fll_div
;
849 if (wm8900
->fll_in
== freq_in
&& wm8900
->fll_out
== freq_out
)
852 /* The digital side should be disabled during any change. */
853 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
854 wm8900_write(codec
, WM8900_REG_POWER1
,
855 reg
& (~WM8900_REG_POWER1_FLL_ENA
));
857 /* Disable the FLL? */
858 if (!freq_in
|| !freq_out
) {
859 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
860 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
861 reg
& (~WM8900_REG_CLOCKING1_MCLK_SRC
));
863 reg
= wm8900_read(codec
, WM8900_REG_FLLCTL1
);
864 wm8900_write(codec
, WM8900_REG_FLLCTL1
,
865 reg
& (~WM8900_REG_FLLCTL1_OSC_ENA
));
867 wm8900
->fll_in
= freq_in
;
868 wm8900
->fll_out
= freq_out
;
873 if (fll_factors(&fll_div
, freq_in
, freq_out
) != 0)
876 wm8900
->fll_in
= freq_in
;
877 wm8900
->fll_out
= freq_out
;
879 /* The osclilator *MUST* be enabled before we enable the
880 * digital circuit. */
881 wm8900_write(codec
, WM8900_REG_FLLCTL1
,
882 fll_div
.fll_ratio
| WM8900_REG_FLLCTL1_OSC_ENA
);
884 wm8900_write(codec
, WM8900_REG_FLLCTL4
, fll_div
.n
>> 5);
885 wm8900_write(codec
, WM8900_REG_FLLCTL5
,
886 (fll_div
.fllclk_div
<< 6) | (fll_div
.n
& 0x1f));
889 wm8900_write(codec
, WM8900_REG_FLLCTL2
,
890 (fll_div
.k
>> 8) | 0x100);
891 wm8900_write(codec
, WM8900_REG_FLLCTL3
, fll_div
.k
& 0xff);
893 wm8900_write(codec
, WM8900_REG_FLLCTL2
, 0);
895 if (fll_div
.fll_slow_lock_ref
)
896 wm8900_write(codec
, WM8900_REG_FLLCTL6
,
897 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF
);
899 wm8900_write(codec
, WM8900_REG_FLLCTL6
, 0);
901 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
902 wm8900_write(codec
, WM8900_REG_POWER1
,
903 reg
| WM8900_REG_POWER1_FLL_ENA
);
906 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
907 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
908 reg
| WM8900_REG_CLOCKING1_MCLK_SRC
);
913 static int wm8900_set_dai_pll(struct snd_soc_dai
*codec_dai
,
914 int pll_id
, unsigned int freq_in
, unsigned int freq_out
)
916 return wm8900_set_fll(codec_dai
->codec
, pll_id
, freq_in
, freq_out
);
919 static int wm8900_set_dai_clkdiv(struct snd_soc_dai
*codec_dai
,
922 struct snd_soc_codec
*codec
= codec_dai
->codec
;
926 case WM8900_BCLK_DIV
:
927 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
928 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
929 div
| (reg
& WM8900_REG_CLOCKING1_BCLK_MASK
));
931 case WM8900_OPCLK_DIV
:
932 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
933 wm8900_write(codec
, WM8900_REG_CLOCKING1
,
934 div
| (reg
& WM8900_REG_CLOCKING1_OPCLK_MASK
));
936 case WM8900_DAC_LRCLK
:
937 reg
= wm8900_read(codec
, WM8900_REG_AUDIO4
);
938 wm8900_write(codec
, WM8900_REG_AUDIO4
,
939 div
| (reg
& WM8900_LRC_MASK
));
941 case WM8900_ADC_LRCLK
:
942 reg
= wm8900_read(codec
, WM8900_REG_AUDIO3
);
943 wm8900_write(codec
, WM8900_REG_AUDIO3
,
944 div
| (reg
& WM8900_LRC_MASK
));
946 case WM8900_DAC_CLKDIV
:
947 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING2
);
948 wm8900_write(codec
, WM8900_REG_CLOCKING2
,
949 div
| (reg
& WM8900_REG_CLOCKING2_DAC_CLKDIV
));
951 case WM8900_ADC_CLKDIV
:
952 reg
= wm8900_read(codec
, WM8900_REG_CLOCKING2
);
953 wm8900_write(codec
, WM8900_REG_CLOCKING2
,
954 div
| (reg
& WM8900_REG_CLOCKING2_ADC_CLKDIV
));
956 case WM8900_LRCLK_MODE
:
957 reg
= wm8900_read(codec
, WM8900_REG_DACCTRL
);
958 wm8900_write(codec
, WM8900_REG_DACCTRL
,
959 div
| (reg
& WM8900_REG_DACCTRL_AIF_LRCLKRATE
));
969 static int wm8900_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
972 struct snd_soc_codec
*codec
= codec_dai
->codec
;
973 unsigned int clocking1
, aif1
, aif3
, aif4
;
975 clocking1
= wm8900_read(codec
, WM8900_REG_CLOCKING1
);
976 aif1
= wm8900_read(codec
, WM8900_REG_AUDIO1
);
977 aif3
= wm8900_read(codec
, WM8900_REG_AUDIO3
);
978 aif4
= wm8900_read(codec
, WM8900_REG_AUDIO4
);
980 /* set master/slave audio interface */
981 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
982 case SND_SOC_DAIFMT_CBS_CFS
:
983 clocking1
&= ~WM8900_REG_CLOCKING1_BCLK_DIR
;
984 aif3
&= ~WM8900_REG_AUDIO3_ADCLRC_DIR
;
985 aif4
&= ~WM8900_REG_AUDIO4_DACLRC_DIR
;
987 case SND_SOC_DAIFMT_CBS_CFM
:
988 clocking1
&= ~WM8900_REG_CLOCKING1_BCLK_DIR
;
989 aif3
|= WM8900_REG_AUDIO3_ADCLRC_DIR
;
990 aif4
|= WM8900_REG_AUDIO4_DACLRC_DIR
;
992 case SND_SOC_DAIFMT_CBM_CFM
:
993 clocking1
|= WM8900_REG_CLOCKING1_BCLK_DIR
;
994 aif3
|= WM8900_REG_AUDIO3_ADCLRC_DIR
;
995 aif4
|= WM8900_REG_AUDIO4_DACLRC_DIR
;
997 case SND_SOC_DAIFMT_CBM_CFS
:
998 clocking1
|= WM8900_REG_CLOCKING1_BCLK_DIR
;
999 aif3
&= ~WM8900_REG_AUDIO3_ADCLRC_DIR
;
1000 aif4
&= ~WM8900_REG_AUDIO4_DACLRC_DIR
;
1006 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1007 case SND_SOC_DAIFMT_DSP_A
:
1008 aif1
|= WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1009 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1011 case SND_SOC_DAIFMT_DSP_B
:
1012 aif1
|= WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1013 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1015 case SND_SOC_DAIFMT_I2S
:
1016 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1019 case SND_SOC_DAIFMT_RIGHT_J
:
1020 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1022 case SND_SOC_DAIFMT_LEFT_J
:
1023 aif1
&= ~WM8900_REG_AUDIO1_AIF_FMT_MASK
;
1030 /* Clock inversion */
1031 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1032 case SND_SOC_DAIFMT_DSP_A
:
1033 case SND_SOC_DAIFMT_DSP_B
:
1034 /* frame inversion not valid for DSP modes */
1035 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1036 case SND_SOC_DAIFMT_NB_NF
:
1037 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1039 case SND_SOC_DAIFMT_IB_NF
:
1040 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1046 case SND_SOC_DAIFMT_I2S
:
1047 case SND_SOC_DAIFMT_RIGHT_J
:
1048 case SND_SOC_DAIFMT_LEFT_J
:
1049 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1050 case SND_SOC_DAIFMT_NB_NF
:
1051 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1052 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1054 case SND_SOC_DAIFMT_IB_IF
:
1055 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1056 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1058 case SND_SOC_DAIFMT_IB_NF
:
1059 aif1
|= WM8900_REG_AUDIO1_BCLK_INV
;
1060 aif1
&= ~WM8900_REG_AUDIO1_LRCLK_INV
;
1062 case SND_SOC_DAIFMT_NB_IF
:
1063 aif1
&= ~WM8900_REG_AUDIO1_BCLK_INV
;
1064 aif1
|= WM8900_REG_AUDIO1_LRCLK_INV
;
1074 wm8900_write(codec
, WM8900_REG_CLOCKING1
, clocking1
);
1075 wm8900_write(codec
, WM8900_REG_AUDIO1
, aif1
);
1076 wm8900_write(codec
, WM8900_REG_AUDIO3
, aif3
);
1077 wm8900_write(codec
, WM8900_REG_AUDIO4
, aif4
);
1082 static int wm8900_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1084 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1087 reg
= wm8900_read(codec
, WM8900_REG_DACCTRL
);
1090 reg
|= WM8900_REG_DACCTRL_MUTE
;
1092 reg
&= ~WM8900_REG_DACCTRL_MUTE
;
1094 wm8900_write(codec
, WM8900_REG_DACCTRL
, reg
);
1099 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1100 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1101 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1103 #define WM8900_PCM_FORMATS \
1104 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1105 SNDRV_PCM_FORMAT_S24_LE)
1107 struct snd_soc_dai wm8900_dai
= {
1108 .name
= "WM8900 HiFi",
1110 .stream_name
= "HiFi Playback",
1113 .rates
= WM8900_RATES
,
1114 .formats
= WM8900_PCM_FORMATS
,
1117 .stream_name
= "HiFi Capture",
1120 .rates
= WM8900_RATES
,
1121 .formats
= WM8900_PCM_FORMATS
,
1124 .hw_params
= wm8900_hw_params
,
1125 .set_clkdiv
= wm8900_set_dai_clkdiv
,
1126 .set_pll
= wm8900_set_dai_pll
,
1127 .set_fmt
= wm8900_set_dai_fmt
,
1128 .digital_mute
= wm8900_digital_mute
,
1131 EXPORT_SYMBOL_GPL(wm8900_dai
);
1133 static int wm8900_set_bias_level(struct snd_soc_codec
*codec
,
1134 enum snd_soc_bias_level level
)
1139 case SND_SOC_BIAS_ON
:
1140 /* Enable thermal shutdown */
1141 reg
= wm8900_read(codec
, WM8900_REG_GPIO
);
1142 wm8900_write(codec
, WM8900_REG_GPIO
,
1143 reg
| WM8900_REG_GPIO_TEMP_ENA
);
1144 reg
= wm8900_read(codec
, WM8900_REG_ADDCTL
);
1145 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1146 reg
| WM8900_REG_ADDCTL_TEMP_SD
);
1149 case SND_SOC_BIAS_PREPARE
:
1152 case SND_SOC_BIAS_STANDBY
:
1153 /* Charge capacitors if initial power up */
1154 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
1155 /* STARTUP_BIAS_ENA on */
1156 wm8900_write(codec
, WM8900_REG_POWER1
,
1157 WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1159 /* Startup bias mode */
1160 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1161 WM8900_REG_ADDCTL_BIAS_SRC
|
1162 WM8900_REG_ADDCTL_VMID_SOFTST
);
1165 wm8900_write(codec
, WM8900_REG_POWER1
,
1166 WM8900_REG_POWER1_STARTUP_BIAS_ENA
| 0x1);
1168 /* Allow capacitors to charge */
1169 schedule_timeout_interruptible(msecs_to_jiffies(400));
1172 wm8900_write(codec
, WM8900_REG_POWER1
,
1173 WM8900_REG_POWER1_STARTUP_BIAS_ENA
|
1174 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1176 wm8900_write(codec
, WM8900_REG_ADDCTL
, 0);
1178 wm8900_write(codec
, WM8900_REG_POWER1
,
1179 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1182 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
1183 wm8900_write(codec
, WM8900_REG_POWER1
,
1184 (reg
& WM8900_REG_POWER1_FLL_ENA
) |
1185 WM8900_REG_POWER1_BIAS_ENA
| 0x1);
1186 wm8900_write(codec
, WM8900_REG_POWER2
,
1187 WM8900_REG_POWER2_SYSCLK_ENA
);
1188 wm8900_write(codec
, WM8900_REG_POWER3
, 0);
1191 case SND_SOC_BIAS_OFF
:
1192 /* Startup bias enable */
1193 reg
= wm8900_read(codec
, WM8900_REG_POWER1
);
1194 wm8900_write(codec
, WM8900_REG_POWER1
,
1195 reg
& WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1196 wm8900_write(codec
, WM8900_REG_ADDCTL
,
1197 WM8900_REG_ADDCTL_BIAS_SRC
|
1198 WM8900_REG_ADDCTL_VMID_SOFTST
);
1200 /* Discharge caps */
1201 wm8900_write(codec
, WM8900_REG_POWER1
,
1202 WM8900_REG_POWER1_STARTUP_BIAS_ENA
);
1203 schedule_timeout_interruptible(msecs_to_jiffies(500));
1206 wm8900_write(codec
, WM8900_REG_HPCTL1
, 0);
1209 wm8900_write(codec
, WM8900_REG_ADDCTL
, 0);
1210 wm8900_write(codec
, WM8900_REG_POWER1
, 0);
1211 wm8900_write(codec
, WM8900_REG_POWER2
, 0);
1212 wm8900_write(codec
, WM8900_REG_POWER3
, 0);
1214 /* Need to let things settle before stopping the clock
1215 * to ensure that restart works, see "Stopping the
1216 * master clock" in the datasheet. */
1217 schedule_timeout_interruptible(msecs_to_jiffies(1));
1218 wm8900_write(codec
, WM8900_REG_POWER2
,
1219 WM8900_REG_POWER2_SYSCLK_ENA
);
1222 codec
->bias_level
= level
;
1226 static int wm8900_suspend(struct platform_device
*pdev
, pm_message_t state
)
1228 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1229 struct snd_soc_codec
*codec
= socdev
->codec
;
1230 struct wm8900_priv
*wm8900
= codec
->private_data
;
1231 int fll_out
= wm8900
->fll_out
;
1232 int fll_in
= wm8900
->fll_in
;
1235 /* Stop the FLL in an orderly fashion */
1236 ret
= wm8900_set_fll(codec
, 0, 0, 0);
1238 dev_err(&pdev
->dev
, "Failed to stop FLL\n");
1242 wm8900
->fll_out
= fll_out
;
1243 wm8900
->fll_in
= fll_in
;
1245 wm8900_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1250 static int wm8900_resume(struct platform_device
*pdev
)
1252 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1253 struct snd_soc_codec
*codec
= socdev
->codec
;
1254 struct wm8900_priv
*wm8900
= codec
->private_data
;
1258 cache
= kmemdup(codec
->reg_cache
, sizeof(wm8900_reg_defaults
),
1261 wm8900_reset(codec
);
1262 wm8900_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1264 /* Restart the FLL? */
1265 if (wm8900
->fll_out
) {
1266 int fll_out
= wm8900
->fll_out
;
1267 int fll_in
= wm8900
->fll_in
;
1270 wm8900
->fll_out
= 0;
1272 ret
= wm8900_set_fll(codec
, 0, fll_in
, fll_out
);
1274 dev_err(&pdev
->dev
, "Failed to restart FLL\n");
1280 for (i
= 0; i
< WM8900_MAXREG
; i
++)
1281 wm8900_write(codec
, i
, cache
[i
]);
1284 dev_err(&pdev
->dev
, "Unable to allocate register cache\n");
1289 static struct snd_soc_codec
*wm8900_codec
;
1291 static int wm8900_i2c_probe(struct i2c_client
*i2c
,
1292 const struct i2c_device_id
*id
)
1294 struct wm8900_priv
*wm8900
;
1295 struct snd_soc_codec
*codec
;
1299 wm8900
= kzalloc(sizeof(struct wm8900_priv
), GFP_KERNEL
);
1303 codec
= &wm8900
->codec
;
1304 codec
->private_data
= wm8900
;
1305 codec
->reg_cache
= &wm8900
->reg_cache
[0];
1306 codec
->reg_cache_size
= WM8900_MAXREG
;
1308 mutex_init(&codec
->mutex
);
1309 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1310 INIT_LIST_HEAD(&codec
->dapm_paths
);
1312 codec
->name
= "WM8900";
1313 codec
->owner
= THIS_MODULE
;
1314 codec
->read
= wm8900_read
;
1315 codec
->write
= wm8900_write
;
1316 codec
->dai
= &wm8900_dai
;
1318 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
1319 codec
->control_data
= i2c
;
1320 codec
->set_bias_level
= wm8900_set_bias_level
;
1321 codec
->dev
= &i2c
->dev
;
1323 reg
= wm8900_read(codec
, WM8900_REG_ID
);
1324 if (reg
!= 0x8900) {
1325 dev_err(&i2c
->dev
, "Device is not a WM8900 - ID %x\n", reg
);
1330 /* Read back from the chip */
1331 reg
= wm8900_chip_read(codec
, WM8900_REG_POWER1
);
1332 reg
= (reg
>> 12) & 0xf;
1333 dev_info(&i2c
->dev
, "WM8900 revision %d\n", reg
);
1335 wm8900_reset(codec
);
1337 /* Turn the chip on */
1338 wm8900_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1340 /* Latch the volume update bits */
1341 wm8900_write(codec
, WM8900_REG_LINVOL
,
1342 wm8900_read(codec
, WM8900_REG_LINVOL
) | 0x100);
1343 wm8900_write(codec
, WM8900_REG_RINVOL
,
1344 wm8900_read(codec
, WM8900_REG_RINVOL
) | 0x100);
1345 wm8900_write(codec
, WM8900_REG_LOUT1CTL
,
1346 wm8900_read(codec
, WM8900_REG_LOUT1CTL
) | 0x100);
1347 wm8900_write(codec
, WM8900_REG_ROUT1CTL
,
1348 wm8900_read(codec
, WM8900_REG_ROUT1CTL
) | 0x100);
1349 wm8900_write(codec
, WM8900_REG_LOUT2CTL
,
1350 wm8900_read(codec
, WM8900_REG_LOUT2CTL
) | 0x100);
1351 wm8900_write(codec
, WM8900_REG_ROUT2CTL
,
1352 wm8900_read(codec
, WM8900_REG_ROUT2CTL
) | 0x100);
1353 wm8900_write(codec
, WM8900_REG_LDAC_DV
,
1354 wm8900_read(codec
, WM8900_REG_LDAC_DV
) | 0x100);
1355 wm8900_write(codec
, WM8900_REG_RDAC_DV
,
1356 wm8900_read(codec
, WM8900_REG_RDAC_DV
) | 0x100);
1357 wm8900_write(codec
, WM8900_REG_LADC_DV
,
1358 wm8900_read(codec
, WM8900_REG_LADC_DV
) | 0x100);
1359 wm8900_write(codec
, WM8900_REG_RADC_DV
,
1360 wm8900_read(codec
, WM8900_REG_RADC_DV
) | 0x100);
1362 /* Set the DAC and mixer output bias */
1363 wm8900_write(codec
, WM8900_REG_OUTBIASCTL
, 0x81);
1365 wm8900_dai
.dev
= &i2c
->dev
;
1367 wm8900_codec
= codec
;
1369 ret
= snd_soc_register_codec(codec
);
1371 dev_err(&i2c
->dev
, "Failed to register codec: %d\n", ret
);
1375 ret
= snd_soc_register_dai(&wm8900_dai
);
1377 dev_err(&i2c
->dev
, "Failed to register DAI: %d\n", ret
);
1384 snd_soc_unregister_codec(codec
);
1387 wm8900_codec
= NULL
;
1391 static int wm8900_i2c_remove(struct i2c_client
*client
)
1393 snd_soc_unregister_dai(&wm8900_dai
);
1394 snd_soc_unregister_codec(wm8900_codec
);
1396 wm8900_set_bias_level(wm8900_codec
, SND_SOC_BIAS_OFF
);
1398 wm8900_dai
.dev
= NULL
;
1399 kfree(wm8900_codec
->private_data
);
1400 wm8900_codec
= NULL
;
1405 static const struct i2c_device_id wm8900_i2c_id
[] = {
1409 MODULE_DEVICE_TABLE(i2c
, wm8900_i2c_id
);
1411 static struct i2c_driver wm8900_i2c_driver
= {
1414 .owner
= THIS_MODULE
,
1416 .probe
= wm8900_i2c_probe
,
1417 .remove
= wm8900_i2c_remove
,
1418 .id_table
= wm8900_i2c_id
,
1421 static int wm8900_probe(struct platform_device
*pdev
)
1423 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1424 struct snd_soc_codec
*codec
;
1427 if (!wm8900_codec
) {
1428 dev_err(&pdev
->dev
, "I2C client not yet instantiated\n");
1432 codec
= wm8900_codec
;
1433 socdev
->codec
= codec
;
1436 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1438 dev_err(&pdev
->dev
, "Failed to register new PCMs\n");
1442 wm8900_add_controls(codec
);
1443 wm8900_add_widgets(codec
);
1445 ret
= snd_soc_init_card(socdev
);
1447 dev_err(&pdev
->dev
, "Failed to register card\n");
1454 snd_soc_free_pcms(socdev
);
1455 snd_soc_dapm_free(socdev
);
1460 /* power down chip */
1461 static int wm8900_remove(struct platform_device
*pdev
)
1463 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1465 snd_soc_free_pcms(socdev
);
1466 snd_soc_dapm_free(socdev
);
1471 struct snd_soc_codec_device soc_codec_dev_wm8900
= {
1472 .probe
= wm8900_probe
,
1473 .remove
= wm8900_remove
,
1474 .suspend
= wm8900_suspend
,
1475 .resume
= wm8900_resume
,
1477 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900
);
1479 static int __init
wm8900_modinit(void)
1481 return i2c_add_driver(&wm8900_i2c_driver
);
1483 module_init(wm8900_modinit
);
1485 static void __exit
wm8900_exit(void)
1487 i2c_del_driver(&wm8900_i2c_driver
);
1489 module_exit(wm8900_exit
);
1491 MODULE_DESCRIPTION("ASoC WM8900 driver");
1492 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1493 MODULE_LICENSE("GPL");