2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults
[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
50 0x0001, /* R8 - Analogue DAC 0 */
52 0x0001, /* R10 - Analogue ADC 0 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
109 0x0010, /* R67 - DC Servo 0 */
111 0x00A4, /* R69 - DC Servo 2 */
132 0x0000, /* R90 - Analogue HP 0 */
136 0x0000, /* R94 - Analogue Lineout 0 */
140 0x0000, /* R98 - Charge Pump 0 */
146 0x0000, /* R104 - Class W 0 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
156 0x0000, /* R114 - Control Interface */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
168 0x0000, /* R126 - Interrupt Control */
171 0x0000, /* R129 - Control Interface Test 1 */
191 0x6810, /* R149 - Charge Pump Test 1 */
206 0x0028, /* R164 - Clock Rate Test 4 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
218 struct snd_soc_codec
*codec
;
226 /* Reference count */
229 struct completion wseq
;
231 struct snd_soc_jack
*mic_jack
;
237 #ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip
;
242 static int wm8903_volatile_register(struct snd_soc_codec
*codec
, unsigned int reg
)
245 case WM8903_SW_RESET_AND_ID
:
246 case WM8903_REVISION_NUMBER
:
247 case WM8903_INTERRUPT_STATUS_1
:
248 case WM8903_WRITE_SEQUENCER_4
:
256 static int wm8903_run_sequence(struct snd_soc_codec
*codec
, unsigned int start
)
259 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
263 /* Enable the sequencer if it's not already on */
264 reg
[0] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_0
);
265 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
,
266 reg
[0] | WM8903_WSEQ_ENA
);
268 dev_dbg(codec
->dev
, "Starting sequence at %d\n", start
);
270 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_3
,
271 start
| WM8903_WSEQ_START
);
273 /* Wait for it to complete. If we have the interrupt wired up then
274 * that will break us out of the poll early.
277 wait_for_completion_timeout(&wm8903
->wseq
,
278 msecs_to_jiffies(10));
280 reg
[4] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_4
);
281 } while (reg
[4] & WM8903_WSEQ_BUSY
);
283 dev_dbg(codec
->dev
, "Sequence complete\n");
285 /* Disable the sequencer again if we enabled it */
286 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, reg
[0]);
291 static void wm8903_sync_reg_cache(struct snd_soc_codec
*codec
, u16
*cache
)
295 /* There really ought to be something better we can do here :/ */
296 for (i
= 0; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
297 cache
[i
] = codec
->hw_read(codec
, i
);
300 static void wm8903_reset(struct snd_soc_codec
*codec
)
302 snd_soc_write(codec
, WM8903_SW_RESET_AND_ID
, 0);
303 memcpy(codec
->reg_cache
, wm8903_reg_defaults
,
304 sizeof(wm8903_reg_defaults
));
307 #define WM8903_OUTPUT_SHORT 0x8
308 #define WM8903_OUTPUT_OUT 0x4
309 #define WM8903_OUTPUT_INT 0x2
310 #define WM8903_OUTPUT_IN 0x1
312 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
313 struct snd_kcontrol
*kcontrol
, int event
)
315 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
322 * Event for headphone and line out amplifier power changes. Special
323 * power up/down sequences are required in order to maximise pop/click
326 static int wm8903_output_event(struct snd_soc_dapm_widget
*w
,
327 struct snd_kcontrol
*kcontrol
, int event
)
329 struct snd_soc_codec
*codec
= w
->codec
;
337 case WM8903_POWER_MANAGEMENT_2
:
338 reg
= WM8903_ANALOGUE_HP_0
;
339 dcs_bit
= 0 + w
->shift
;
341 case WM8903_POWER_MANAGEMENT_3
:
342 reg
= WM8903_ANALOGUE_LINEOUT_0
;
343 dcs_bit
= 2 + w
->shift
;
347 return -EINVAL
; /* Spurious warning from some compilers */
359 return -EINVAL
; /* Spurious warning from some compilers */
362 if (event
& SND_SOC_DAPM_PRE_PMU
) {
363 val
= snd_soc_read(codec
, reg
);
365 /* Short the output */
366 val
&= ~(WM8903_OUTPUT_SHORT
<< shift
);
367 snd_soc_write(codec
, reg
, val
);
370 if (event
& SND_SOC_DAPM_POST_PMU
) {
371 val
= snd_soc_read(codec
, reg
);
373 val
|= (WM8903_OUTPUT_IN
<< shift
);
374 snd_soc_write(codec
, reg
, val
);
376 val
|= (WM8903_OUTPUT_INT
<< shift
);
377 snd_soc_write(codec
, reg
, val
);
379 /* Turn on the output ENA_OUTP */
380 val
|= (WM8903_OUTPUT_OUT
<< shift
);
381 snd_soc_write(codec
, reg
, val
);
383 /* Enable the DC servo */
384 dcs_reg
= snd_soc_read(codec
, WM8903_DC_SERVO_0
);
386 snd_soc_write(codec
, WM8903_DC_SERVO_0
, dcs_reg
);
388 /* Remove the short */
389 val
|= (WM8903_OUTPUT_SHORT
<< shift
);
390 snd_soc_write(codec
, reg
, val
);
393 if (event
& SND_SOC_DAPM_PRE_PMD
) {
394 val
= snd_soc_read(codec
, reg
);
396 /* Short the output */
397 val
&= ~(WM8903_OUTPUT_SHORT
<< shift
);
398 snd_soc_write(codec
, reg
, val
);
400 /* Disable the DC servo */
401 dcs_reg
= snd_soc_read(codec
, WM8903_DC_SERVO_0
);
403 snd_soc_write(codec
, WM8903_DC_SERVO_0
, dcs_reg
);
405 /* Then disable the intermediate and output stages */
406 val
&= ~((WM8903_OUTPUT_OUT
| WM8903_OUTPUT_INT
|
407 WM8903_OUTPUT_IN
) << shift
);
408 snd_soc_write(codec
, reg
, val
);
415 * When used with DAC outputs only the WM8903 charge pump supports
416 * operation in class W mode, providing very low power consumption
417 * when used with digital sources. Enable and disable this mode
418 * automatically depending on the mixer configuration.
420 * All the relevant controls are simple switches.
422 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
423 struct snd_ctl_elem_value
*ucontrol
)
425 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
426 struct snd_soc_codec
*codec
= widget
->codec
;
427 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
431 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
433 /* Turn it off if we're about to enable bypass */
434 if (ucontrol
->value
.integer
.value
[0]) {
435 if (wm8903
->class_w_users
== 0) {
436 dev_dbg(codec
->dev
, "Disabling Class W\n");
437 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
438 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
440 wm8903
->class_w_users
++;
443 /* Implement the change */
444 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
446 /* If we've just disabled the last bypass path turn Class W on */
447 if (!ucontrol
->value
.integer
.value
[0]) {
448 if (wm8903
->class_w_users
== 1) {
449 dev_dbg(codec
->dev
, "Enabling Class W\n");
450 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
451 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
453 wm8903
->class_w_users
--;
456 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
457 wm8903
->class_w_users
);
462 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
463 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
464 .info = snd_soc_info_volsw, \
465 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
466 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
469 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
471 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
473 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
476 /* If we're using deemphasis select the nearest available sample
479 if (wm8903
->deemph
) {
481 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
482 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
483 abs(wm8903_deemph
[best
] - wm8903
->fs
))
487 val
= best
<< WM8903_DEEMPH_SHIFT
;
493 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
494 best
, wm8903_deemph
[best
]);
496 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
497 WM8903_DEEMPH_MASK
, val
);
500 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
501 struct snd_ctl_elem_value
*ucontrol
)
503 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
504 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
506 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
511 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
512 struct snd_ctl_elem_value
*ucontrol
)
514 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
515 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
516 int deemph
= ucontrol
->value
.enumerated
.item
[0];
522 mutex_lock(&codec
->mutex
);
523 if (wm8903
->deemph
!= deemph
) {
524 wm8903
->deemph
= deemph
;
526 wm8903_set_deemph(codec
);
530 mutex_unlock(&codec
->mutex
);
535 /* ALSA can only do steps of .01dB */
536 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
538 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
539 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
541 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
542 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
543 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
544 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
545 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
547 static const char *hpf_mode_text
[] = {
548 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
551 static const struct soc_enum hpf_mode
=
552 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
554 static const char *osr_text
[] = {
555 "Low power", "High performance"
558 static const struct soc_enum adc_osr
=
559 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
561 static const struct soc_enum dac_osr
=
562 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
564 static const char *drc_slope_text
[] = {
565 "1", "1/2", "1/4", "1/8", "1/16", "0"
568 static const struct soc_enum drc_slope_r0
=
569 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
571 static const struct soc_enum drc_slope_r1
=
572 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
574 static const char *drc_attack_text
[] = {
576 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
577 "46.4ms", "92.8ms", "185.6ms"
580 static const struct soc_enum drc_attack
=
581 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
583 static const char *drc_decay_text
[] = {
584 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
588 static const struct soc_enum drc_decay
=
589 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
591 static const char *drc_ff_delay_text
[] = {
592 "5 samples", "9 samples"
595 static const struct soc_enum drc_ff_delay
=
596 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
598 static const char *drc_qr_decay_text
[] = {
599 "0.725ms", "1.45ms", "5.8ms"
602 static const struct soc_enum drc_qr_decay
=
603 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
605 static const char *drc_smoothing_text
[] = {
606 "Low", "Medium", "High"
609 static const struct soc_enum drc_smoothing
=
610 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
612 static const char *soft_mute_text
[] = {
613 "Fast (fs/2)", "Slow (fs/32)"
616 static const struct soc_enum soft_mute
=
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
619 static const char *mute_mode_text
[] = {
623 static const struct soc_enum mute_mode
=
624 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
626 static const char *companding_text
[] = {
630 static const struct soc_enum dac_companding
=
631 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
633 static const struct soc_enum adc_companding
=
634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
636 static const char *input_mode_text
[] = {
637 "Single-Ended", "Differential Line", "Differential Mic"
640 static const struct soc_enum linput_mode_enum
=
641 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
643 static const struct soc_enum rinput_mode_enum
=
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
646 static const char *linput_mux_text
[] = {
647 "IN1L", "IN2L", "IN3L"
650 static const struct soc_enum linput_enum
=
651 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
653 static const struct soc_enum linput_inv_enum
=
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
656 static const char *rinput_mux_text
[] = {
657 "IN1R", "IN2R", "IN3R"
660 static const struct soc_enum rinput_enum
=
661 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
663 static const struct soc_enum rinput_inv_enum
=
664 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
667 static const char *sidetone_text
[] = {
668 "None", "Left", "Right"
671 static const struct soc_enum lsidetone_enum
=
672 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
674 static const struct soc_enum rsidetone_enum
=
675 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
677 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
679 /* Input PGAs - No TLV since the scale depends on PGA mode */
680 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
682 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
684 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
687 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
689 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
691 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
695 SOC_ENUM("ADC OSR", adc_osr
),
696 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
697 SOC_ENUM("HPF Mode", hpf_mode
),
698 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
699 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
700 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
701 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
703 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
704 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
705 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
706 SOC_ENUM("DRC Attack Rate", drc_attack
),
707 SOC_ENUM("DRC Decay Rate", drc_decay
),
708 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
709 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
710 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
711 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
712 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
713 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
714 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
715 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
716 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
718 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
719 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
720 SOC_ENUM("ADC Companding Mode", adc_companding
),
721 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
723 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
724 12, 0, digital_sidetone_tlv
),
727 SOC_ENUM("DAC OSR", dac_osr
),
728 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
729 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
730 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
731 SOC_ENUM("DAC Mute Mode", mute_mode
),
732 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
733 SOC_ENUM("DAC Companding Mode", dac_companding
),
734 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
735 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
736 wm8903_get_deemph
, wm8903_put_deemph
),
739 SOC_DOUBLE_R("Headphone Switch",
740 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
742 SOC_DOUBLE_R("Headphone ZC Switch",
743 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
745 SOC_DOUBLE_R_TLV("Headphone Volume",
746 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
750 SOC_DOUBLE_R("Line Out Switch",
751 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
753 SOC_DOUBLE_R("Line Out ZC Switch",
754 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
756 SOC_DOUBLE_R_TLV("Line Out Volume",
757 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
761 SOC_DOUBLE_R("Speaker Switch",
762 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
763 SOC_DOUBLE_R("Speaker ZC Switch",
764 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
765 SOC_DOUBLE_R_TLV("Speaker Volume",
766 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
770 static const struct snd_kcontrol_new linput_mode_mux
=
771 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
773 static const struct snd_kcontrol_new rinput_mode_mux
=
774 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
776 static const struct snd_kcontrol_new linput_mux
=
777 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
779 static const struct snd_kcontrol_new linput_inv_mux
=
780 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
782 static const struct snd_kcontrol_new rinput_mux
=
783 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
785 static const struct snd_kcontrol_new rinput_inv_mux
=
786 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
788 static const struct snd_kcontrol_new lsidetone_mux
=
789 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
791 static const struct snd_kcontrol_new rsidetone_mux
=
792 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
794 static const struct snd_kcontrol_new left_output_mixer
[] = {
795 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
796 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
797 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
798 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
801 static const struct snd_kcontrol_new right_output_mixer
[] = {
802 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
803 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
804 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
805 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
808 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
809 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
810 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
811 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
812 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
816 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
817 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
818 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
819 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
821 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
825 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
826 SND_SOC_DAPM_INPUT("IN1L"),
827 SND_SOC_DAPM_INPUT("IN1R"),
828 SND_SOC_DAPM_INPUT("IN2L"),
829 SND_SOC_DAPM_INPUT("IN2R"),
830 SND_SOC_DAPM_INPUT("IN3L"),
831 SND_SOC_DAPM_INPUT("IN3R"),
833 SND_SOC_DAPM_OUTPUT("HPOUTL"),
834 SND_SOC_DAPM_OUTPUT("HPOUTR"),
835 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
836 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
837 SND_SOC_DAPM_OUTPUT("LOP"),
838 SND_SOC_DAPM_OUTPUT("LON"),
839 SND_SOC_DAPM_OUTPUT("ROP"),
840 SND_SOC_DAPM_OUTPUT("RON"),
842 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0
, 0, 0),
844 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
845 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
847 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
849 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
850 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
852 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
854 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
855 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
857 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6
, 1, 0),
858 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6
, 0, 0),
860 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
861 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
863 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6
, 3, 0),
864 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6
, 2, 0),
866 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
867 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
868 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
869 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
871 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
872 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
873 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
874 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
876 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2
,
877 1, 0, NULL
, 0, wm8903_output_event
,
878 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
879 SND_SOC_DAPM_PRE_PMD
),
880 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2
,
881 0, 0, NULL
, 0, wm8903_output_event
,
882 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
883 SND_SOC_DAPM_PRE_PMD
),
885 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3
, 1, 0,
886 NULL
, 0, wm8903_output_event
,
887 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
888 SND_SOC_DAPM_PRE_PMD
),
889 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3
, 0, 0,
890 NULL
, 0, wm8903_output_event
,
891 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
892 SND_SOC_DAPM_PRE_PMD
),
894 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
896 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
899 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
900 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
901 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
904 static const struct snd_soc_dapm_route intercon
[] = {
906 { "Left Input Mux", "IN1L", "IN1L" },
907 { "Left Input Mux", "IN2L", "IN2L" },
908 { "Left Input Mux", "IN3L", "IN3L" },
910 { "Left Input Inverting Mux", "IN1L", "IN1L" },
911 { "Left Input Inverting Mux", "IN2L", "IN2L" },
912 { "Left Input Inverting Mux", "IN3L", "IN3L" },
914 { "Right Input Mux", "IN1R", "IN1R" },
915 { "Right Input Mux", "IN2R", "IN2R" },
916 { "Right Input Mux", "IN3R", "IN3R" },
918 { "Right Input Inverting Mux", "IN1R", "IN1R" },
919 { "Right Input Inverting Mux", "IN2R", "IN2R" },
920 { "Right Input Inverting Mux", "IN3R", "IN3R" },
922 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
923 { "Left Input Mode Mux", "Differential Line",
925 { "Left Input Mode Mux", "Differential Line",
926 "Left Input Inverting Mux" },
927 { "Left Input Mode Mux", "Differential Mic",
929 { "Left Input Mode Mux", "Differential Mic",
930 "Left Input Inverting Mux" },
932 { "Right Input Mode Mux", "Single-Ended",
933 "Right Input Inverting Mux" },
934 { "Right Input Mode Mux", "Differential Line",
936 { "Right Input Mode Mux", "Differential Line",
937 "Right Input Inverting Mux" },
938 { "Right Input Mode Mux", "Differential Mic",
940 { "Right Input Mode Mux", "Differential Mic",
941 "Right Input Inverting Mux" },
943 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
944 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
946 { "ADCL", NULL
, "Left Input PGA" },
947 { "ADCL", NULL
, "CLK_DSP" },
948 { "ADCR", NULL
, "Right Input PGA" },
949 { "ADCR", NULL
, "CLK_DSP" },
951 { "DACL Sidetone", "Left", "ADCL" },
952 { "DACL Sidetone", "Right", "ADCR" },
953 { "DACR Sidetone", "Left", "ADCL" },
954 { "DACR Sidetone", "Right", "ADCR" },
956 { "DACL", NULL
, "DACL Sidetone" },
957 { "DACL", NULL
, "CLK_DSP" },
958 { "DACR", NULL
, "DACR Sidetone" },
959 { "DACR", NULL
, "CLK_DSP" },
961 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
962 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
963 { "Left Output Mixer", "DACL Switch", "DACL" },
964 { "Left Output Mixer", "DACR Switch", "DACR" },
966 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
967 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
968 { "Right Output Mixer", "DACL Switch", "DACL" },
969 { "Right Output Mixer", "DACR Switch", "DACR" },
971 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
972 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
973 { "Left Speaker Mixer", "DACL Switch", "DACL" },
974 { "Left Speaker Mixer", "DACR Switch", "DACR" },
976 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
977 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
978 { "Right Speaker Mixer", "DACL Switch", "DACL" },
979 { "Right Speaker Mixer", "DACR Switch", "DACR" },
981 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
982 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
984 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
985 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
987 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
988 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
990 { "HPOUTL", NULL
, "Left Headphone Output PGA" },
991 { "HPOUTR", NULL
, "Right Headphone Output PGA" },
993 { "LINEOUTL", NULL
, "Left Line Output PGA" },
994 { "LINEOUTR", NULL
, "Right Line Output PGA" },
996 { "LOP", NULL
, "Left Speaker PGA" },
997 { "LON", NULL
, "Left Speaker PGA" },
999 { "ROP", NULL
, "Right Speaker PGA" },
1000 { "RON", NULL
, "Right Speaker PGA" },
1002 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1003 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1004 { "Left Line Output PGA", NULL
, "Charge Pump" },
1005 { "Right Line Output PGA", NULL
, "Charge Pump" },
1008 static int wm8903_add_widgets(struct snd_soc_codec
*codec
)
1010 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1012 snd_soc_dapm_new_controls(dapm
, wm8903_dapm_widgets
,
1013 ARRAY_SIZE(wm8903_dapm_widgets
));
1014 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
1019 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1020 enum snd_soc_bias_level level
)
1025 case SND_SOC_BIAS_ON
:
1026 case SND_SOC_BIAS_PREPARE
:
1027 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1028 reg
&= ~(WM8903_VMID_RES_MASK
);
1029 reg
|= WM8903_VMID_RES_50K
;
1030 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1033 case SND_SOC_BIAS_STANDBY
:
1034 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1035 snd_soc_write(codec
, WM8903_CLOCK_RATES_2
,
1036 WM8903_CLK_SYS_ENA
);
1038 /* Change DC servo dither level in startup sequence */
1039 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, 0x11);
1040 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_1
, 0x1257);
1041 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_2
, 0x2);
1043 wm8903_run_sequence(codec
, 0);
1044 wm8903_sync_reg_cache(codec
, codec
->reg_cache
);
1046 /* By default no bypass paths are enabled so
1047 * enable Class W support.
1049 dev_dbg(codec
->dev
, "Enabling Class W\n");
1050 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1051 WM8903_CP_DYN_FREQ
|
1053 WM8903_CP_DYN_FREQ
|
1057 reg
= snd_soc_read(codec
, WM8903_VMID_CONTROL_0
);
1058 reg
&= ~(WM8903_VMID_RES_MASK
);
1059 reg
|= WM8903_VMID_RES_250K
;
1060 snd_soc_write(codec
, WM8903_VMID_CONTROL_0
, reg
);
1063 case SND_SOC_BIAS_OFF
:
1064 wm8903_run_sequence(codec
, 32);
1065 reg
= snd_soc_read(codec
, WM8903_CLOCK_RATES_2
);
1066 reg
&= ~WM8903_CLK_SYS_ENA
;
1067 snd_soc_write(codec
, WM8903_CLOCK_RATES_2
, reg
);
1071 codec
->dapm
.bias_level
= level
;
1076 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1077 int clk_id
, unsigned int freq
, int dir
)
1079 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1080 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1082 wm8903
->sysclk
= freq
;
1087 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1090 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1091 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1093 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1094 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1096 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1097 case SND_SOC_DAIFMT_CBS_CFS
:
1099 case SND_SOC_DAIFMT_CBS_CFM
:
1100 aif1
|= WM8903_LRCLK_DIR
;
1102 case SND_SOC_DAIFMT_CBM_CFM
:
1103 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1105 case SND_SOC_DAIFMT_CBM_CFS
:
1106 aif1
|= WM8903_BCLK_DIR
;
1112 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1113 case SND_SOC_DAIFMT_DSP_A
:
1116 case SND_SOC_DAIFMT_DSP_B
:
1117 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1119 case SND_SOC_DAIFMT_I2S
:
1122 case SND_SOC_DAIFMT_RIGHT_J
:
1125 case SND_SOC_DAIFMT_LEFT_J
:
1131 /* Clock inversion */
1132 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1133 case SND_SOC_DAIFMT_DSP_A
:
1134 case SND_SOC_DAIFMT_DSP_B
:
1135 /* frame inversion not valid for DSP modes */
1136 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1137 case SND_SOC_DAIFMT_NB_NF
:
1139 case SND_SOC_DAIFMT_IB_NF
:
1140 aif1
|= WM8903_AIF_BCLK_INV
;
1146 case SND_SOC_DAIFMT_I2S
:
1147 case SND_SOC_DAIFMT_RIGHT_J
:
1148 case SND_SOC_DAIFMT_LEFT_J
:
1149 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1150 case SND_SOC_DAIFMT_NB_NF
:
1152 case SND_SOC_DAIFMT_IB_IF
:
1153 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1155 case SND_SOC_DAIFMT_IB_NF
:
1156 aif1
|= WM8903_AIF_BCLK_INV
;
1158 case SND_SOC_DAIFMT_NB_IF
:
1159 aif1
|= WM8903_AIF_LRCLK_INV
;
1169 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1174 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1176 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1179 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1182 reg
|= WM8903_DAC_MUTE
;
1184 reg
&= ~WM8903_DAC_MUTE
;
1186 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1191 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1192 * for optimal performance so we list the lower rates first and match
1193 * on the last match we find. */
1199 } clk_sys_ratios
[] = {
1200 { 64, 0x0, 0x0, 1 },
1201 { 68, 0x0, 0x1, 1 },
1202 { 125, 0x0, 0x2, 1 },
1203 { 128, 0x1, 0x0, 1 },
1204 { 136, 0x1, 0x1, 1 },
1205 { 192, 0x2, 0x0, 1 },
1206 { 204, 0x2, 0x1, 1 },
1208 { 64, 0x0, 0x0, 2 },
1209 { 68, 0x0, 0x1, 2 },
1210 { 125, 0x0, 0x2, 2 },
1211 { 128, 0x1, 0x0, 2 },
1212 { 136, 0x1, 0x1, 2 },
1213 { 192, 0x2, 0x0, 2 },
1214 { 204, 0x2, 0x1, 2 },
1216 { 250, 0x2, 0x2, 1 },
1217 { 256, 0x3, 0x0, 1 },
1218 { 272, 0x3, 0x1, 1 },
1219 { 384, 0x4, 0x0, 1 },
1220 { 408, 0x4, 0x1, 1 },
1221 { 375, 0x4, 0x2, 1 },
1222 { 512, 0x5, 0x0, 1 },
1223 { 544, 0x5, 0x1, 1 },
1224 { 500, 0x5, 0x2, 1 },
1225 { 768, 0x6, 0x0, 1 },
1226 { 816, 0x6, 0x1, 1 },
1227 { 750, 0x6, 0x2, 1 },
1228 { 1024, 0x7, 0x0, 1 },
1229 { 1088, 0x7, 0x1, 1 },
1230 { 1000, 0x7, 0x2, 1 },
1231 { 1408, 0x8, 0x0, 1 },
1232 { 1496, 0x8, 0x1, 1 },
1233 { 1536, 0x9, 0x0, 1 },
1234 { 1632, 0x9, 0x1, 1 },
1235 { 1500, 0x9, 0x2, 1 },
1237 { 250, 0x2, 0x2, 2 },
1238 { 256, 0x3, 0x0, 2 },
1239 { 272, 0x3, 0x1, 2 },
1240 { 384, 0x4, 0x0, 2 },
1241 { 408, 0x4, 0x1, 2 },
1242 { 375, 0x4, 0x2, 2 },
1243 { 512, 0x5, 0x0, 2 },
1244 { 544, 0x5, 0x1, 2 },
1245 { 500, 0x5, 0x2, 2 },
1246 { 768, 0x6, 0x0, 2 },
1247 { 816, 0x6, 0x1, 2 },
1248 { 750, 0x6, 0x2, 2 },
1249 { 1024, 0x7, 0x0, 2 },
1250 { 1088, 0x7, 0x1, 2 },
1251 { 1000, 0x7, 0x2, 2 },
1252 { 1408, 0x8, 0x0, 2 },
1253 { 1496, 0x8, 0x1, 2 },
1254 { 1536, 0x9, 0x0, 2 },
1255 { 1632, 0x9, 0x1, 2 },
1256 { 1500, 0x9, 0x2, 2 },
1259 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1283 /* Sample rates for DSP */
1287 } sample_rates
[] = {
1302 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1303 struct snd_pcm_hw_params
*params
,
1304 struct snd_soc_dai
*dai
)
1306 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1307 struct snd_soc_codec
*codec
=rtd
->codec
;
1308 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1309 int fs
= params_rate(params
);
1319 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1320 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1321 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1322 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1323 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1324 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1326 /* Enable sloping stopband filter for low sample rates */
1328 dac_digital1
|= WM8903_DAC_SB_FILT
;
1330 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1332 /* Configure sample rate logic for DSP - choose nearest rate */
1334 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1335 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1336 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1337 if (cur_val
<= best_val
) {
1343 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1344 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1345 clock1
|= sample_rates
[dsp_config
].value
;
1347 aif1
&= ~WM8903_AIF_WL_MASK
;
1349 switch (params_format(params
)) {
1350 case SNDRV_PCM_FORMAT_S16_LE
:
1353 case SNDRV_PCM_FORMAT_S20_3LE
:
1357 case SNDRV_PCM_FORMAT_S24_LE
:
1361 case SNDRV_PCM_FORMAT_S32_LE
:
1369 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1370 wm8903
->sysclk
, fs
);
1372 /* We may not have an MCLK which allows us to generate exactly
1373 * the clock we want, particularly with USB derived inputs, so
1377 best_val
= abs((wm8903
->sysclk
/
1378 (clk_sys_ratios
[0].mclk_div
*
1379 clk_sys_ratios
[0].div
)) - fs
);
1380 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1381 cur_val
= abs((wm8903
->sysclk
/
1382 (clk_sys_ratios
[i
].mclk_div
*
1383 clk_sys_ratios
[i
].div
)) - fs
);
1385 if (cur_val
<= best_val
) {
1391 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1392 clock0
|= WM8903_MCLKDIV2
;
1393 clk_sys
= wm8903
->sysclk
/ 2;
1395 clock0
&= ~WM8903_MCLKDIV2
;
1396 clk_sys
= wm8903
->sysclk
;
1399 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1400 WM8903_CLK_SYS_MODE_MASK
);
1401 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1402 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1404 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1405 clk_sys_ratios
[clk_config
].rate
,
1406 clk_sys_ratios
[clk_config
].mode
,
1407 clk_sys_ratios
[clk_config
].div
);
1409 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1411 /* We may not get quite the right frequency if using
1412 * approximate clocks so look for the closest match that is
1413 * higher than the target (we need to ensure that there enough
1414 * BCLKs to clock out the samples).
1417 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1419 while (i
< ARRAY_SIZE(bclk_divs
)) {
1420 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1421 if (cur_val
< 0) /* BCLK table is sorted */
1428 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1429 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1431 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1432 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1433 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1435 aif2
|= bclk_divs
[bclk_div
].div
;
1438 wm8903
->fs
= params_rate(params
);
1439 wm8903_set_deemph(codec
);
1441 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1442 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1443 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1444 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1445 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1446 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1452 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1454 * @codec: WM8903 codec
1455 * @jack: jack to report detection events on
1456 * @det: value to report for presence detection
1457 * @shrt: value to report for short detection
1459 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1460 * being used to bring out signals to the processor then only platform
1461 * data configuration is needed for WM8903 and processor GPIOs should
1462 * be configured using snd_soc_jack_add_gpios() instead.
1464 * The current threasholds for detection should be configured using
1465 * micdet_cfg in the platform data. Using this function will force on
1466 * the microphone bias for the device.
1468 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1471 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1472 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1474 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1477 /* Store the configuration */
1478 wm8903
->mic_jack
= jack
;
1479 wm8903
->mic_det
= det
;
1480 wm8903
->mic_short
= shrt
;
1482 /* Enable interrupts we've got a report configured for */
1484 irq_mask
&= ~WM8903_MICDET_EINT
;
1486 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1488 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1489 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1493 /* Enable mic detection, this may not have been set through
1494 * platform data (eg, if the defaults are OK). */
1495 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1496 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1497 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1498 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1500 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1501 WM8903_MICDET_ENA
, 0);
1506 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1508 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1510 struct snd_soc_codec
*codec
= data
;
1511 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1515 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1517 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1519 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1520 dev_dbg(codec
->dev
, "Write sequencer done\n");
1521 complete(&wm8903
->wseq
);
1525 * The rest is microphone jack detection. We need to manually
1526 * invert the polarity of the interrupt after each event - to
1527 * simplify the code keep track of the last state we reported
1528 * and just invert the relevant bits in both the report and
1529 * the polarity register.
1531 mic_report
= wm8903
->mic_last_report
;
1532 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1534 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1535 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1536 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1539 if (int_val
& WM8903_MICSHRT_EINT
) {
1540 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1542 mic_report
^= wm8903
->mic_short
;
1543 int_pol
^= WM8903_MICSHRT_INV
;
1546 if (int_val
& WM8903_MICDET_EINT
) {
1547 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1549 mic_report
^= wm8903
->mic_det
;
1550 int_pol
^= WM8903_MICDET_INV
;
1552 msleep(wm8903
->mic_delay
);
1555 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1556 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1558 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1559 wm8903
->mic_short
| wm8903
->mic_det
);
1561 wm8903
->mic_last_report
= mic_report
;
1566 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1567 SNDRV_PCM_RATE_11025 | \
1568 SNDRV_PCM_RATE_16000 | \
1569 SNDRV_PCM_RATE_22050 | \
1570 SNDRV_PCM_RATE_32000 | \
1571 SNDRV_PCM_RATE_44100 | \
1572 SNDRV_PCM_RATE_48000 | \
1573 SNDRV_PCM_RATE_88200 | \
1574 SNDRV_PCM_RATE_96000)
1576 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1577 SNDRV_PCM_RATE_11025 | \
1578 SNDRV_PCM_RATE_16000 | \
1579 SNDRV_PCM_RATE_22050 | \
1580 SNDRV_PCM_RATE_32000 | \
1581 SNDRV_PCM_RATE_44100 | \
1582 SNDRV_PCM_RATE_48000)
1584 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1585 SNDRV_PCM_FMTBIT_S20_3LE |\
1586 SNDRV_PCM_FMTBIT_S24_LE)
1588 static struct snd_soc_dai_ops wm8903_dai_ops
= {
1589 .hw_params
= wm8903_hw_params
,
1590 .digital_mute
= wm8903_digital_mute
,
1591 .set_fmt
= wm8903_set_dai_fmt
,
1592 .set_sysclk
= wm8903_set_dai_sysclk
,
1595 static struct snd_soc_dai_driver wm8903_dai
= {
1596 .name
= "wm8903-hifi",
1598 .stream_name
= "Playback",
1601 .rates
= WM8903_PLAYBACK_RATES
,
1602 .formats
= WM8903_FORMATS
,
1605 .stream_name
= "Capture",
1608 .rates
= WM8903_CAPTURE_RATES
,
1609 .formats
= WM8903_FORMATS
,
1611 .ops
= &wm8903_dai_ops
,
1612 .symmetric_rates
= 1,
1615 static int wm8903_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1617 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1622 static int wm8903_resume(struct snd_soc_codec
*codec
)
1625 u16
*reg_cache
= codec
->reg_cache
;
1626 u16
*tmp_cache
= kmemdup(reg_cache
, sizeof(wm8903_reg_defaults
),
1629 /* Bring the codec back up to standby first to minimise pop/clicks */
1630 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1632 /* Sync back everything else */
1634 for (i
= 2; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
1635 if (tmp_cache
[i
] != reg_cache
[i
])
1636 snd_soc_write(codec
, i
, tmp_cache
[i
]);
1639 dev_err(codec
->dev
, "Failed to allocate temporary cache\n");
1645 #ifdef CONFIG_GPIOLIB
1646 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1648 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1651 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1653 if (offset
>= WM8903_NUM_GPIO
)
1659 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1661 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1662 struct snd_soc_codec
*codec
= wm8903
->codec
;
1663 unsigned int mask
, val
;
1665 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1666 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1669 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1673 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1675 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1676 struct snd_soc_codec
*codec
= wm8903
->codec
;
1679 reg
= snd_soc_read(codec
, WM8903_GPIO_CONTROL_1
+ offset
);
1681 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1684 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1685 unsigned offset
, int value
)
1687 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1688 struct snd_soc_codec
*codec
= wm8903
->codec
;
1689 unsigned int mask
, val
;
1691 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1692 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1693 (value
<< WM8903_GP2_LVL_SHIFT
);
1695 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1699 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1701 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1702 struct snd_soc_codec
*codec
= wm8903
->codec
;
1704 snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1705 WM8903_GP1_LVL_MASK
,
1706 !!value
<< WM8903_GP1_LVL_SHIFT
);
1709 static struct gpio_chip wm8903_template_chip
= {
1711 .owner
= THIS_MODULE
,
1712 .request
= wm8903_gpio_request
,
1713 .direction_input
= wm8903_gpio_direction_in
,
1714 .get
= wm8903_gpio_get
,
1715 .direction_output
= wm8903_gpio_direction_out
,
1716 .set
= wm8903_gpio_set
,
1720 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1722 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1723 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1726 wm8903
->gpio_chip
= wm8903_template_chip
;
1727 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1728 wm8903
->gpio_chip
.dev
= codec
->dev
;
1730 if (pdata
&& pdata
->gpio_base
)
1731 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1733 wm8903
->gpio_chip
.base
= -1;
1735 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1737 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
1740 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1742 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1745 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1747 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1750 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1754 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1759 static int wm8903_probe(struct snd_soc_codec
*codec
)
1761 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1762 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1764 int trigger
, irq_pol
;
1767 wm8903
->codec
= codec
;
1768 init_completion(&wm8903
->wseq
);
1770 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1772 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1776 val
= snd_soc_read(codec
, WM8903_SW_RESET_AND_ID
);
1777 if (val
!= wm8903_reg_defaults
[WM8903_SW_RESET_AND_ID
]) {
1779 "Device with ID register %x is not a WM8903\n", val
);
1783 val
= snd_soc_read(codec
, WM8903_REVISION_NUMBER
);
1784 dev_info(codec
->dev
, "WM8903 revision %d\n",
1785 val
& WM8903_CHIP_REV_MASK
);
1787 wm8903_reset(codec
);
1789 /* Set up GPIOs and microphone detection */
1791 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1792 if (pdata
->gpio_cfg
[i
] == WM8903_GPIO_NO_CONFIG
)
1795 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1796 pdata
->gpio_cfg
[i
] & 0xffff);
1799 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1802 /* Microphone detection needs the WSEQ clock */
1803 if (pdata
->micdet_cfg
)
1804 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1805 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1807 wm8903
->mic_delay
= pdata
->micdet_delay
;
1811 if (pdata
&& pdata
->irq_active_low
) {
1812 trigger
= IRQF_TRIGGER_LOW
;
1813 irq_pol
= WM8903_IRQ_POL
;
1815 trigger
= IRQF_TRIGGER_HIGH
;
1819 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1820 WM8903_IRQ_POL
, irq_pol
);
1822 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1823 trigger
| IRQF_ONESHOT
,
1826 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1831 /* Enable write sequencer interrupts */
1832 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1833 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1836 /* power on device */
1837 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1839 /* Latch volume update bits */
1840 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
1841 val
|= WM8903_ADCVU
;
1842 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
1843 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
1845 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
1846 val
|= WM8903_DACVU
;
1847 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
1848 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
1850 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
1851 val
|= WM8903_HPOUTVU
;
1852 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
1853 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
1855 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
1856 val
|= WM8903_LINEOUTVU
;
1857 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
1858 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
1860 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
1861 val
|= WM8903_SPKVU
;
1862 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
1863 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
1865 /* Enable DAC soft mute by default */
1866 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1867 val
|= WM8903_DAC_MUTEMODE
;
1868 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, val
);
1870 snd_soc_add_controls(codec
, wm8903_snd_controls
,
1871 ARRAY_SIZE(wm8903_snd_controls
));
1872 wm8903_add_widgets(codec
);
1874 wm8903_init_gpio(codec
);
1879 /* power down chip */
1880 static int wm8903_remove(struct snd_soc_codec
*codec
)
1882 wm8903_free_gpio(codec
);
1883 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1887 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
1888 .probe
= wm8903_probe
,
1889 .remove
= wm8903_remove
,
1890 .suspend
= wm8903_suspend
,
1891 .resume
= wm8903_resume
,
1892 .set_bias_level
= wm8903_set_bias_level
,
1893 .reg_cache_size
= ARRAY_SIZE(wm8903_reg_defaults
),
1894 .reg_word_size
= sizeof(u16
),
1895 .reg_cache_default
= wm8903_reg_defaults
,
1896 .volatile_register
= wm8903_volatile_register
,
1899 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1900 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
1901 const struct i2c_device_id
*id
)
1903 struct wm8903_priv
*wm8903
;
1906 wm8903
= kzalloc(sizeof(struct wm8903_priv
), GFP_KERNEL
);
1910 i2c_set_clientdata(i2c
, wm8903
);
1911 wm8903
->irq
= i2c
->irq
;
1913 ret
= snd_soc_register_codec(&i2c
->dev
,
1914 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
1920 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
1922 snd_soc_unregister_codec(&client
->dev
);
1923 kfree(i2c_get_clientdata(client
));
1927 static const struct i2c_device_id wm8903_i2c_id
[] = {
1931 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
1933 static struct i2c_driver wm8903_i2c_driver
= {
1935 .name
= "wm8903-codec",
1936 .owner
= THIS_MODULE
,
1938 .probe
= wm8903_i2c_probe
,
1939 .remove
= __devexit_p(wm8903_i2c_remove
),
1940 .id_table
= wm8903_i2c_id
,
1944 static int __init
wm8903_modinit(void)
1947 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1948 ret
= i2c_add_driver(&wm8903_i2c_driver
);
1950 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
1956 module_init(wm8903_modinit
);
1958 static void __exit
wm8903_exit(void)
1960 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1961 i2c_del_driver(&wm8903_i2c_driver
);
1964 module_exit(wm8903_exit
);
1966 MODULE_DESCRIPTION("ASoC WM8903 driver");
1967 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1968 MODULE_LICENSE("GPL");