projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: Convert WM8903 bias management to use snd_soc_update_bits()
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
1 /*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
15 * - Digital microphone support.
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
37
38 #include "wm8903.h"
39
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215 };
216
217 struct wm8903_priv {
218 struct snd_soc_codec *codec;
219
220 int sysclk;
221 int irq;
222
223 int fs;
224 int deemph;
225
226 int dcs_pending;
227 int dcs_cache[4];
228
229 /* Reference count */
230 int class_w_users;
231
232 struct completion wseq;
233
234 struct snd_soc_jack *mic_jack;
235 int mic_det;
236 int mic_short;
237 int mic_last_report;
238 int mic_delay;
239
240 #ifdef CONFIG_GPIOLIB
241 struct gpio_chip gpio_chip;
242 #endif
243 };
244
245 static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
246 {
247 switch (reg) {
248 case WM8903_SW_RESET_AND_ID:
249 case WM8903_REVISION_NUMBER:
250 case WM8903_INTERRUPT_STATUS_1:
251 case WM8903_WRITE_SEQUENCER_4:
252 case WM8903_POWER_MANAGEMENT_3:
253 case WM8903_POWER_MANAGEMENT_2:
254 case WM8903_DC_SERVO_READBACK_1:
255 case WM8903_DC_SERVO_READBACK_2:
256 case WM8903_DC_SERVO_READBACK_3:
257 case WM8903_DC_SERVO_READBACK_4:
258 return 1;
259
260 default:
261 return 0;
262 }
263 }
264
265 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
266 {
267 u16 reg[5];
268 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
269
270 BUG_ON(start > 48);
271
272 /* Enable the sequencer if it's not already on */
273 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
274 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
275 reg[0] | WM8903_WSEQ_ENA);
276
277 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
278
279 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
280 start | WM8903_WSEQ_START);
281
282 /* Wait for it to complete. If we have the interrupt wired up then
283 * that will break us out of the poll early.
284 */
285 do {
286 wait_for_completion_timeout(&wm8903->wseq,
287 msecs_to_jiffies(10));
288
289 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
290 } while (reg[4] & WM8903_WSEQ_BUSY);
291
292 dev_dbg(codec->dev, "Sequence complete\n");
293
294 /* Disable the sequencer again if we enabled it */
295 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
296
297 return 0;
298 }
299
300 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
301 {
302 int i;
303
304 /* There really ought to be something better we can do here :/ */
305 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
306 cache[i] = codec->hw_read(codec, i);
307 }
308
309 static void wm8903_reset(struct snd_soc_codec *codec)
310 {
311 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
312 memcpy(codec->reg_cache, wm8903_reg_defaults,
313 sizeof(wm8903_reg_defaults));
314 }
315
316 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
317 struct snd_kcontrol *kcontrol, int event)
318 {
319 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
320 mdelay(4);
321
322 return 0;
323 }
324
325 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
326 struct snd_kcontrol *kcontrol, int event)
327 {
328 struct snd_soc_codec *codec = w->codec;
329 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
330
331 switch (event) {
332 case SND_SOC_DAPM_POST_PMU:
333 wm8903->dcs_pending |= 1 << w->shift;
334 break;
335 case SND_SOC_DAPM_PRE_PMD:
336 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
337 1 << w->shift, 0);
338 break;
339 }
340
341 return 0;
342 }
343
344 #define WM8903_DCS_MODE_WRITE_STOP 0
345 #define WM8903_DCS_MODE_START_STOP 2
346
347 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
348 enum snd_soc_dapm_type event, int subseq)
349 {
350 struct snd_soc_codec *codec = container_of(dapm,
351 struct snd_soc_codec, dapm);
352 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
353 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
354 int i, val;
355
356 /* Complete any pending DC servo starts */
357 if (wm8903->dcs_pending) {
358 dev_dbg(codec->dev, "Starting DC servo for %x\n",
359 wm8903->dcs_pending);
360
361 /* If we've no cached values then we need to do startup */
362 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
363 if (!(wm8903->dcs_pending & (1 << i)))
364 continue;
365
366 if (wm8903->dcs_cache[i]) {
367 dev_dbg(codec->dev,
368 "Restore DC servo %d value %x\n",
369 3 - i, wm8903->dcs_cache[i]);
370
371 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
372 wm8903->dcs_cache[i] & 0xff);
373 } else {
374 dev_dbg(codec->dev,
375 "Calibrate DC servo %d\n", 3 - i);
376 dcs_mode = WM8903_DCS_MODE_START_STOP;
377 }
378 }
379
380 /* Don't trust the cache for analogue */
381 if (wm8903->class_w_users)
382 dcs_mode = WM8903_DCS_MODE_START_STOP;
383
384 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
385 WM8903_DCS_MODE_MASK, dcs_mode);
386
387 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
388 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
389
390 switch (dcs_mode) {
391 case WM8903_DCS_MODE_WRITE_STOP:
392 break;
393
394 case WM8903_DCS_MODE_START_STOP:
395 msleep(270);
396
397 /* Cache the measured offsets for digital */
398 if (wm8903->class_w_users)
399 break;
400
401 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
402 if (!(wm8903->dcs_pending & (1 << i)))
403 continue;
404
405 val = snd_soc_read(codec,
406 WM8903_DC_SERVO_READBACK_1 + i);
407 dev_dbg(codec->dev, "DC servo %d: %x\n",
408 3 - i, val);
409 wm8903->dcs_cache[i] = val;
410 }
411 break;
412
413 default:
414 pr_warn("DCS mode %d delay not set\n", dcs_mode);
415 break;
416 }
417
418 wm8903->dcs_pending = 0;
419 }
420 }
421
422 /*
423 * When used with DAC outputs only the WM8903 charge pump supports
424 * operation in class W mode, providing very low power consumption
425 * when used with digital sources. Enable and disable this mode
426 * automatically depending on the mixer configuration.
427 *
428 * All the relevant controls are simple switches.
429 */
430 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
431 struct snd_ctl_elem_value *ucontrol)
432 {
433 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
434 struct snd_soc_codec *codec = widget->codec;
435 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
436 u16 reg;
437 int ret;
438
439 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
440
441 /* Turn it off if we're about to enable bypass */
442 if (ucontrol->value.integer.value[0]) {
443 if (wm8903->class_w_users == 0) {
444 dev_dbg(codec->dev, "Disabling Class W\n");
445 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
446 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
447 }
448 wm8903->class_w_users++;
449 }
450
451 /* Implement the change */
452 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
453
454 /* If we've just disabled the last bypass path turn Class W on */
455 if (!ucontrol->value.integer.value[0]) {
456 if (wm8903->class_w_users == 1) {
457 dev_dbg(codec->dev, "Enabling Class W\n");
458 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
459 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
460 }
461 wm8903->class_w_users--;
462 }
463
464 dev_dbg(codec->dev, "Bypass use count now %d\n",
465 wm8903->class_w_users);
466
467 return ret;
468 }
469
470 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
471 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
472 .info = snd_soc_info_volsw, \
473 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
474 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
475
476
477 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
478
479 static int wm8903_set_deemph(struct snd_soc_codec *codec)
480 {
481 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
482 int val, i, best;
483
484 /* If we're using deemphasis select the nearest available sample
485 * rate.
486 */
487 if (wm8903->deemph) {
488 best = 1;
489 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
490 if (abs(wm8903_deemph[i] - wm8903->fs) <
491 abs(wm8903_deemph[best] - wm8903->fs))
492 best = i;
493 }
494
495 val = best << WM8903_DEEMPH_SHIFT;
496 } else {
497 best = 0;
498 val = 0;
499 }
500
501 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
502 best, wm8903_deemph[best]);
503
504 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
505 WM8903_DEEMPH_MASK, val);
506 }
507
508 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
509 struct snd_ctl_elem_value *ucontrol)
510 {
511 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
512 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
513
514 ucontrol->value.enumerated.item[0] = wm8903->deemph;
515
516 return 0;
517 }
518
519 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
520 struct snd_ctl_elem_value *ucontrol)
521 {
522 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
523 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
524 int deemph = ucontrol->value.enumerated.item[0];
525 int ret = 0;
526
527 if (deemph > 1)
528 return -EINVAL;
529
530 mutex_lock(&codec->mutex);
531 if (wm8903->deemph != deemph) {
532 wm8903->deemph = deemph;
533
534 wm8903_set_deemph(codec);
535
536 ret = 1;
537 }
538 mutex_unlock(&codec->mutex);
539
540 return ret;
541 }
542
543 /* ALSA can only do steps of .01dB */
544 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
545
546 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
547 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
548
549 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
550 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
551 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
552 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
553 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
554
555 static const char *hpf_mode_text[] = {
556 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
557 };
558
559 static const struct soc_enum hpf_mode =
560 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
561
562 static const char *osr_text[] = {
563 "Low power", "High performance"
564 };
565
566 static const struct soc_enum adc_osr =
567 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
568
569 static const struct soc_enum dac_osr =
570 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
571
572 static const char *drc_slope_text[] = {
573 "1", "1/2", "1/4", "1/8", "1/16", "0"
574 };
575
576 static const struct soc_enum drc_slope_r0 =
577 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
578
579 static const struct soc_enum drc_slope_r1 =
580 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
581
582 static const char *drc_attack_text[] = {
583 "instantaneous",
584 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
585 "46.4ms", "92.8ms", "185.6ms"
586 };
587
588 static const struct soc_enum drc_attack =
589 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
590
591 static const char *drc_decay_text[] = {
592 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
593 "23.87s", "47.56s"
594 };
595
596 static const struct soc_enum drc_decay =
597 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
598
599 static const char *drc_ff_delay_text[] = {
600 "5 samples", "9 samples"
601 };
602
603 static const struct soc_enum drc_ff_delay =
604 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
605
606 static const char *drc_qr_decay_text[] = {
607 "0.725ms", "1.45ms", "5.8ms"
608 };
609
610 static const struct soc_enum drc_qr_decay =
611 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
612
613 static const char *drc_smoothing_text[] = {
614 "Low", "Medium", "High"
615 };
616
617 static const struct soc_enum drc_smoothing =
618 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
619
620 static const char *soft_mute_text[] = {
621 "Fast (fs/2)", "Slow (fs/32)"
622 };
623
624 static const struct soc_enum soft_mute =
625 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
626
627 static const char *mute_mode_text[] = {
628 "Hard", "Soft"
629 };
630
631 static const struct soc_enum mute_mode =
632 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
633
634 static const char *companding_text[] = {
635 "ulaw", "alaw"
636 };
637
638 static const struct soc_enum dac_companding =
639 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
640
641 static const struct soc_enum adc_companding =
642 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
643
644 static const char *input_mode_text[] = {
645 "Single-Ended", "Differential Line", "Differential Mic"
646 };
647
648 static const struct soc_enum linput_mode_enum =
649 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
650
651 static const struct soc_enum rinput_mode_enum =
652 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
653
654 static const char *linput_mux_text[] = {
655 "IN1L", "IN2L", "IN3L"
656 };
657
658 static const struct soc_enum linput_enum =
659 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
660
661 static const struct soc_enum linput_inv_enum =
662 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
663
664 static const char *rinput_mux_text[] = {
665 "IN1R", "IN2R", "IN3R"
666 };
667
668 static const struct soc_enum rinput_enum =
669 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
670
671 static const struct soc_enum rinput_inv_enum =
672 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
673
674
675 static const char *sidetone_text[] = {
676 "None", "Left", "Right"
677 };
678
679 static const struct soc_enum lsidetone_enum =
680 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
681
682 static const struct soc_enum rsidetone_enum =
683 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
684
685 static const char *aif_text[] = {
686 "Left", "Right"
687 };
688
689 static const struct soc_enum lcapture_enum =
690 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
691
692 static const struct soc_enum rcapture_enum =
693 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
694
695 static const struct soc_enum lplay_enum =
696 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
697
698 static const struct soc_enum rplay_enum =
699 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
700
701 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
702
703 /* Input PGAs - No TLV since the scale depends on PGA mode */
704 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
705 7, 1, 1),
706 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
707 0, 31, 0),
708 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
709 6, 1, 0),
710
711 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
712 7, 1, 1),
713 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
714 0, 31, 0),
715 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
716 6, 1, 0),
717
718 /* ADCs */
719 SOC_ENUM("ADC OSR", adc_osr),
720 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
721 SOC_ENUM("HPF Mode", hpf_mode),
722 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
723 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
724 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
725 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
726 drc_tlv_thresh),
727 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
728 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
729 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
730 SOC_ENUM("DRC Attack Rate", drc_attack),
731 SOC_ENUM("DRC Decay Rate", drc_decay),
732 SOC_ENUM("DRC FF Delay", drc_ff_delay),
733 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
734 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
735 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
736 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
737 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
738 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
739 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
740 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
741
742 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
743 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
744 SOC_ENUM("ADC Companding Mode", adc_companding),
745 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
746
747 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
748 12, 0, digital_sidetone_tlv),
749
750 /* DAC */
751 SOC_ENUM("DAC OSR", dac_osr),
752 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
753 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
754 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
755 SOC_ENUM("DAC Mute Mode", mute_mode),
756 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
757 SOC_ENUM("DAC Companding Mode", dac_companding),
758 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
759 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
760 wm8903_get_deemph, wm8903_put_deemph),
761
762 /* Headphones */
763 SOC_DOUBLE_R("Headphone Switch",
764 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
765 8, 1, 1),
766 SOC_DOUBLE_R("Headphone ZC Switch",
767 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
768 6, 1, 0),
769 SOC_DOUBLE_R_TLV("Headphone Volume",
770 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
771 0, 63, 0, out_tlv),
772
773 /* Line out */
774 SOC_DOUBLE_R("Line Out Switch",
775 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
776 8, 1, 1),
777 SOC_DOUBLE_R("Line Out ZC Switch",
778 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
779 6, 1, 0),
780 SOC_DOUBLE_R_TLV("Line Out Volume",
781 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
782 0, 63, 0, out_tlv),
783
784 /* Speaker */
785 SOC_DOUBLE_R("Speaker Switch",
786 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
787 SOC_DOUBLE_R("Speaker ZC Switch",
788 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
789 SOC_DOUBLE_R_TLV("Speaker Volume",
790 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
791 0, 63, 0, out_tlv),
792 };
793
794 static const struct snd_kcontrol_new linput_mode_mux =
795 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
796
797 static const struct snd_kcontrol_new rinput_mode_mux =
798 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
799
800 static const struct snd_kcontrol_new linput_mux =
801 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
802
803 static const struct snd_kcontrol_new linput_inv_mux =
804 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
805
806 static const struct snd_kcontrol_new rinput_mux =
807 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
808
809 static const struct snd_kcontrol_new rinput_inv_mux =
810 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
811
812 static const struct snd_kcontrol_new lsidetone_mux =
813 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
814
815 static const struct snd_kcontrol_new rsidetone_mux =
816 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
817
818 static const struct snd_kcontrol_new lcapture_mux =
819 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
820
821 static const struct snd_kcontrol_new rcapture_mux =
822 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
823
824 static const struct snd_kcontrol_new lplay_mux =
825 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
826
827 static const struct snd_kcontrol_new rplay_mux =
828 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
829
830 static const struct snd_kcontrol_new left_output_mixer[] = {
831 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
832 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
833 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
834 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
835 };
836
837 static const struct snd_kcontrol_new right_output_mixer[] = {
838 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
839 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
840 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
841 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
842 };
843
844 static const struct snd_kcontrol_new left_speaker_mixer[] = {
845 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
846 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
847 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
848 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
849 0, 1, 0),
850 };
851
852 static const struct snd_kcontrol_new right_speaker_mixer[] = {
853 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
854 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
855 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
856 1, 1, 0),
857 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
858 0, 1, 0),
859 };
860
861 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
862 SND_SOC_DAPM_INPUT("IN1L"),
863 SND_SOC_DAPM_INPUT("IN1R"),
864 SND_SOC_DAPM_INPUT("IN2L"),
865 SND_SOC_DAPM_INPUT("IN2R"),
866 SND_SOC_DAPM_INPUT("IN3L"),
867 SND_SOC_DAPM_INPUT("IN3R"),
868
869 SND_SOC_DAPM_OUTPUT("HPOUTL"),
870 SND_SOC_DAPM_OUTPUT("HPOUTR"),
871 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
872 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
873 SND_SOC_DAPM_OUTPUT("LOP"),
874 SND_SOC_DAPM_OUTPUT("LON"),
875 SND_SOC_DAPM_OUTPUT("ROP"),
876 SND_SOC_DAPM_OUTPUT("RON"),
877
878 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
879
880 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
881 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
882 &linput_inv_mux),
883 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
884
885 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
886 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
887 &rinput_inv_mux),
888 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
889
890 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
891 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
892
893 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
894 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
895
896 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
897 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
898
899 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
900 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
901
902 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
903 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
904
905 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
906 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
907
908 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
909 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
910
911 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
912 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
913
914 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
915 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
916 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
917 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
918
919 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
920 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
921 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
922 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
923
924 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
925 4, 0, NULL, 0),
926 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
927 0, 0, NULL, 0),
928
929 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
930 NULL, 0),
931 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
932 NULL, 0),
933
934 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
935 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
936 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
937 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
938 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
939 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
940
941 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
942 NULL, 0),
943 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
944 NULL, 0),
945 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
946 NULL, 0),
947 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
948 NULL, 0),
949 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
950 NULL, 0),
951 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
952 NULL, 0),
953
954 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
955 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
956 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
957 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
958 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
959 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
960 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
961 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
962 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
963
964 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
965 NULL, 0),
966 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
967 NULL, 0),
968
969 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
970 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
971 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
972 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
973 };
974
975 static const struct snd_soc_dapm_route intercon[] = {
976
977 { "CLK_DSP", NULL, "CLK_SYS" },
978 { "Mic Bias", NULL, "CLK_SYS" },
979 { "HPL_DCS", NULL, "CLK_SYS" },
980 { "HPR_DCS", NULL, "CLK_SYS" },
981 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
982 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
983
984 { "Left Input Mux", "IN1L", "IN1L" },
985 { "Left Input Mux", "IN2L", "IN2L" },
986 { "Left Input Mux", "IN3L", "IN3L" },
987
988 { "Left Input Inverting Mux", "IN1L", "IN1L" },
989 { "Left Input Inverting Mux", "IN2L", "IN2L" },
990 { "Left Input Inverting Mux", "IN3L", "IN3L" },
991
992 { "Right Input Mux", "IN1R", "IN1R" },
993 { "Right Input Mux", "IN2R", "IN2R" },
994 { "Right Input Mux", "IN3R", "IN3R" },
995
996 { "Right Input Inverting Mux", "IN1R", "IN1R" },
997 { "Right Input Inverting Mux", "IN2R", "IN2R" },
998 { "Right Input Inverting Mux", "IN3R", "IN3R" },
999
1000 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
1001 { "Left Input Mode Mux", "Differential Line",
1002 "Left Input Mux" },
1003 { "Left Input Mode Mux", "Differential Line",
1004 "Left Input Inverting Mux" },
1005 { "Left Input Mode Mux", "Differential Mic",
1006 "Left Input Mux" },
1007 { "Left Input Mode Mux", "Differential Mic",
1008 "Left Input Inverting Mux" },
1009
1010 { "Right Input Mode Mux", "Single-Ended",
1011 "Right Input Inverting Mux" },
1012 { "Right Input Mode Mux", "Differential Line",
1013 "Right Input Mux" },
1014 { "Right Input Mode Mux", "Differential Line",
1015 "Right Input Inverting Mux" },
1016 { "Right Input Mode Mux", "Differential Mic",
1017 "Right Input Mux" },
1018 { "Right Input Mode Mux", "Differential Mic",
1019 "Right Input Inverting Mux" },
1020
1021 { "Left Input PGA", NULL, "Left Input Mode Mux" },
1022 { "Right Input PGA", NULL, "Right Input Mode Mux" },
1023
1024 { "Left Capture Mux", "Left", "ADCL" },
1025 { "Left Capture Mux", "Right", "ADCR" },
1026
1027 { "Right Capture Mux", "Left", "ADCL" },
1028 { "Right Capture Mux", "Right", "ADCR" },
1029
1030 { "AIFTXL", NULL, "Left Capture Mux" },
1031 { "AIFTXR", NULL, "Right Capture Mux" },
1032
1033 { "ADCL", NULL, "Left Input PGA" },
1034 { "ADCL", NULL, "CLK_DSP" },
1035 { "ADCR", NULL, "Right Input PGA" },
1036 { "ADCR", NULL, "CLK_DSP" },
1037
1038 { "Left Playback Mux", "Left", "AIFRXL" },
1039 { "Left Playback Mux", "Right", "AIFRXR" },
1040
1041 { "Right Playback Mux", "Left", "AIFRXL" },
1042 { "Right Playback Mux", "Right", "AIFRXR" },
1043
1044 { "DACL Sidetone", "Left", "ADCL" },
1045 { "DACL Sidetone", "Right", "ADCR" },
1046 { "DACR Sidetone", "Left", "ADCL" },
1047 { "DACR Sidetone", "Right", "ADCR" },
1048
1049 { "DACL", NULL, "Left Playback Mux" },
1050 { "DACL", NULL, "DACL Sidetone" },
1051 { "DACL", NULL, "CLK_DSP" },
1052
1053 { "DACR", NULL, "Right Playback Mux" },
1054 { "DACR", NULL, "DACR Sidetone" },
1055 { "DACR", NULL, "CLK_DSP" },
1056
1057 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1058 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1059 { "Left Output Mixer", "DACL Switch", "DACL" },
1060 { "Left Output Mixer", "DACR Switch", "DACR" },
1061
1062 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1063 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1064 { "Right Output Mixer", "DACL Switch", "DACL" },
1065 { "Right Output Mixer", "DACR Switch", "DACR" },
1066
1067 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1068 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1069 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1070 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1071
1072 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1073 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1074 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1075 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1076
1077 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1078 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1079
1080 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1081 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1082
1083 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1084 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1085
1086 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" },
1087 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" },
1088 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" },
1089 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" },
1090
1091 { "HPL_DCS", NULL, "DCS Master" },
1092 { "HPR_DCS", NULL, "DCS Master" },
1093 { "LINEOUTL_DCS", NULL, "DCS Master" },
1094 { "LINEOUTR_DCS", NULL, "DCS Master" },
1095
1096 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1097 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1098 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1099 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1100
1101 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1102 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1103 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1104 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1105
1106 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1107 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1108 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1109 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1110
1111 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1112 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1113 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1114 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
1115
1116 { "LOP", NULL, "Left Speaker PGA" },
1117 { "LON", NULL, "Left Speaker PGA" },
1118
1119 { "ROP", NULL, "Right Speaker PGA" },
1120 { "RON", NULL, "Right Speaker PGA" },
1121
1122 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1123 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1124 { "Left Line Output PGA", NULL, "Charge Pump" },
1125 { "Right Line Output PGA", NULL, "Charge Pump" },
1126 };
1127
1128 static int wm8903_add_widgets(struct snd_soc_codec *codec)
1129 {
1130 struct snd_soc_dapm_context *dapm = &codec->dapm;
1131
1132 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1133 ARRAY_SIZE(wm8903_dapm_widgets));
1134 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
1135
1136 return 0;
1137 }
1138
1139 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1140 enum snd_soc_bias_level level)
1141 {
1142 switch (level) {
1143 case SND_SOC_BIAS_ON:
1144 break;
1145 case SND_SOC_BIAS_PREPARE:
1146 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1147 WM8903_VMID_RES_MASK,
1148 WM8903_VMID_RES_50K);
1149 break;
1150
1151 case SND_SOC_BIAS_STANDBY:
1152 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1153 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
1154 WM8903_CLK_SYS_ENA);
1155
1156 /* Change DC servo dither level in startup sequence */
1157 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1158 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1159 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1160
1161 wm8903_run_sequence(codec, 0);
1162 wm8903_sync_reg_cache(codec, codec->reg_cache);
1163
1164 /* By default no bypass paths are enabled so
1165 * enable Class W support.
1166 */
1167 dev_dbg(codec->dev, "Enabling Class W\n");
1168 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1169 WM8903_CP_DYN_FREQ |
1170 WM8903_CP_DYN_V,
1171 WM8903_CP_DYN_FREQ |
1172 WM8903_CP_DYN_V);
1173 }
1174
1175 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1176 WM8903_VMID_RES_MASK,
1177 WM8903_VMID_RES_250K);
1178 break;
1179
1180 case SND_SOC_BIAS_OFF:
1181 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1182 WM8903_CLK_SYS_ENA, WM8903_CLK_SYS_ENA);
1183 wm8903_run_sequence(codec, 32);
1184 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1185 WM8903_CLK_SYS_ENA, 0);
1186 break;
1187 }
1188
1189 codec->dapm.bias_level = level;
1190
1191 return 0;
1192 }
1193
1194 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1195 int clk_id, unsigned int freq, int dir)
1196 {
1197 struct snd_soc_codec *codec = codec_dai->codec;
1198 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1199
1200 wm8903->sysclk = freq;
1201
1202 return 0;
1203 }
1204
1205 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1206 unsigned int fmt)
1207 {
1208 struct snd_soc_codec *codec = codec_dai->codec;
1209 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1210
1211 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1212 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1213
1214 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1215 case SND_SOC_DAIFMT_CBS_CFS:
1216 break;
1217 case SND_SOC_DAIFMT_CBS_CFM:
1218 aif1 |= WM8903_LRCLK_DIR;
1219 break;
1220 case SND_SOC_DAIFMT_CBM_CFM:
1221 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1222 break;
1223 case SND_SOC_DAIFMT_CBM_CFS:
1224 aif1 |= WM8903_BCLK_DIR;
1225 break;
1226 default:
1227 return -EINVAL;
1228 }
1229
1230 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1231 case SND_SOC_DAIFMT_DSP_A:
1232 aif1 |= 0x3;
1233 break;
1234 case SND_SOC_DAIFMT_DSP_B:
1235 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1236 break;
1237 case SND_SOC_DAIFMT_I2S:
1238 aif1 |= 0x2;
1239 break;
1240 case SND_SOC_DAIFMT_RIGHT_J:
1241 aif1 |= 0x1;
1242 break;
1243 case SND_SOC_DAIFMT_LEFT_J:
1244 break;
1245 default:
1246 return -EINVAL;
1247 }
1248
1249 /* Clock inversion */
1250 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1251 case SND_SOC_DAIFMT_DSP_A:
1252 case SND_SOC_DAIFMT_DSP_B:
1253 /* frame inversion not valid for DSP modes */
1254 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1255 case SND_SOC_DAIFMT_NB_NF:
1256 break;
1257 case SND_SOC_DAIFMT_IB_NF:
1258 aif1 |= WM8903_AIF_BCLK_INV;
1259 break;
1260 default:
1261 return -EINVAL;
1262 }
1263 break;
1264 case SND_SOC_DAIFMT_I2S:
1265 case SND_SOC_DAIFMT_RIGHT_J:
1266 case SND_SOC_DAIFMT_LEFT_J:
1267 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1268 case SND_SOC_DAIFMT_NB_NF:
1269 break;
1270 case SND_SOC_DAIFMT_IB_IF:
1271 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1272 break;
1273 case SND_SOC_DAIFMT_IB_NF:
1274 aif1 |= WM8903_AIF_BCLK_INV;
1275 break;
1276 case SND_SOC_DAIFMT_NB_IF:
1277 aif1 |= WM8903_AIF_LRCLK_INV;
1278 break;
1279 default:
1280 return -EINVAL;
1281 }
1282 break;
1283 default:
1284 return -EINVAL;
1285 }
1286
1287 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1288
1289 return 0;
1290 }
1291
1292 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1293 {
1294 struct snd_soc_codec *codec = codec_dai->codec;
1295 u16 reg;
1296
1297 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1298
1299 if (mute)
1300 reg |= WM8903_DAC_MUTE;
1301 else
1302 reg &= ~WM8903_DAC_MUTE;
1303
1304 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1305
1306 return 0;
1307 }
1308
1309 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1310 * for optimal performance so we list the lower rates first and match
1311 * on the last match we find. */
1312 static struct {
1313 int div;
1314 int rate;
1315 int mode;
1316 int mclk_div;
1317 } clk_sys_ratios[] = {
1318 { 64, 0x0, 0x0, 1 },
1319 { 68, 0x0, 0x1, 1 },
1320 { 125, 0x0, 0x2, 1 },
1321 { 128, 0x1, 0x0, 1 },
1322 { 136, 0x1, 0x1, 1 },
1323 { 192, 0x2, 0x0, 1 },
1324 { 204, 0x2, 0x1, 1 },
1325
1326 { 64, 0x0, 0x0, 2 },
1327 { 68, 0x0, 0x1, 2 },
1328 { 125, 0x0, 0x2, 2 },
1329 { 128, 0x1, 0x0, 2 },
1330 { 136, 0x1, 0x1, 2 },
1331 { 192, 0x2, 0x0, 2 },
1332 { 204, 0x2, 0x1, 2 },
1333
1334 { 250, 0x2, 0x2, 1 },
1335 { 256, 0x3, 0x0, 1 },
1336 { 272, 0x3, 0x1, 1 },
1337 { 384, 0x4, 0x0, 1 },
1338 { 408, 0x4, 0x1, 1 },
1339 { 375, 0x4, 0x2, 1 },
1340 { 512, 0x5, 0x0, 1 },
1341 { 544, 0x5, 0x1, 1 },
1342 { 500, 0x5, 0x2, 1 },
1343 { 768, 0x6, 0x0, 1 },
1344 { 816, 0x6, 0x1, 1 },
1345 { 750, 0x6, 0x2, 1 },
1346 { 1024, 0x7, 0x0, 1 },
1347 { 1088, 0x7, 0x1, 1 },
1348 { 1000, 0x7, 0x2, 1 },
1349 { 1408, 0x8, 0x0, 1 },
1350 { 1496, 0x8, 0x1, 1 },
1351 { 1536, 0x9, 0x0, 1 },
1352 { 1632, 0x9, 0x1, 1 },
1353 { 1500, 0x9, 0x2, 1 },
1354
1355 { 250, 0x2, 0x2, 2 },
1356 { 256, 0x3, 0x0, 2 },
1357 { 272, 0x3, 0x1, 2 },
1358 { 384, 0x4, 0x0, 2 },
1359 { 408, 0x4, 0x1, 2 },
1360 { 375, 0x4, 0x2, 2 },
1361 { 512, 0x5, 0x0, 2 },
1362 { 544, 0x5, 0x1, 2 },
1363 { 500, 0x5, 0x2, 2 },
1364 { 768, 0x6, 0x0, 2 },
1365 { 816, 0x6, 0x1, 2 },
1366 { 750, 0x6, 0x2, 2 },
1367 { 1024, 0x7, 0x0, 2 },
1368 { 1088, 0x7, 0x1, 2 },
1369 { 1000, 0x7, 0x2, 2 },
1370 { 1408, 0x8, 0x0, 2 },
1371 { 1496, 0x8, 0x1, 2 },
1372 { 1536, 0x9, 0x0, 2 },
1373 { 1632, 0x9, 0x1, 2 },
1374 { 1500, 0x9, 0x2, 2 },
1375 };
1376
1377 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1378 static struct {
1379 int ratio;
1380 int div;
1381 } bclk_divs[] = {
1382 { 10, 0 },
1383 { 20, 2 },
1384 { 30, 3 },
1385 { 40, 4 },
1386 { 50, 5 },
1387 { 60, 7 },
1388 { 80, 8 },
1389 { 100, 9 },
1390 { 120, 11 },
1391 { 160, 12 },
1392 { 200, 13 },
1393 { 220, 14 },
1394 { 240, 15 },
1395 { 300, 17 },
1396 { 320, 18 },
1397 { 440, 19 },
1398 { 480, 20 },
1399 };
1400
1401 /* Sample rates for DSP */
1402 static struct {
1403 int rate;
1404 int value;
1405 } sample_rates[] = {
1406 { 8000, 0 },
1407 { 11025, 1 },
1408 { 12000, 2 },
1409 { 16000, 3 },
1410 { 22050, 4 },
1411 { 24000, 5 },
1412 { 32000, 6 },
1413 { 44100, 7 },
1414 { 48000, 8 },
1415 { 88200, 9 },
1416 { 96000, 10 },
1417 { 0, 0 },
1418 };
1419
1420 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1421 struct snd_pcm_hw_params *params,
1422 struct snd_soc_dai *dai)
1423 {
1424 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1425 struct snd_soc_codec *codec =rtd->codec;
1426 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1427 int fs = params_rate(params);
1428 int bclk;
1429 int bclk_div;
1430 int i;
1431 int dsp_config;
1432 int clk_config;
1433 int best_val;
1434 int cur_val;
1435 int clk_sys;
1436
1437 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1438 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1439 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1440 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1441 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1442 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1443
1444 /* Enable sloping stopband filter for low sample rates */
1445 if (fs <= 24000)
1446 dac_digital1 |= WM8903_DAC_SB_FILT;
1447 else
1448 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1449
1450 /* Configure sample rate logic for DSP - choose nearest rate */
1451 dsp_config = 0;
1452 best_val = abs(sample_rates[dsp_config].rate - fs);
1453 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1454 cur_val = abs(sample_rates[i].rate - fs);
1455 if (cur_val <= best_val) {
1456 dsp_config = i;
1457 best_val = cur_val;
1458 }
1459 }
1460
1461 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1462 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1463 clock1 |= sample_rates[dsp_config].value;
1464
1465 aif1 &= ~WM8903_AIF_WL_MASK;
1466 bclk = 2 * fs;
1467 switch (params_format(params)) {
1468 case SNDRV_PCM_FORMAT_S16_LE:
1469 bclk *= 16;
1470 break;
1471 case SNDRV_PCM_FORMAT_S20_3LE:
1472 bclk *= 20;
1473 aif1 |= 0x4;
1474 break;
1475 case SNDRV_PCM_FORMAT_S24_LE:
1476 bclk *= 24;
1477 aif1 |= 0x8;
1478 break;
1479 case SNDRV_PCM_FORMAT_S32_LE:
1480 bclk *= 32;
1481 aif1 |= 0xc;
1482 break;
1483 default:
1484 return -EINVAL;
1485 }
1486
1487 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1488 wm8903->sysclk, fs);
1489
1490 /* We may not have an MCLK which allows us to generate exactly
1491 * the clock we want, particularly with USB derived inputs, so
1492 * approximate.
1493 */
1494 clk_config = 0;
1495 best_val = abs((wm8903->sysclk /
1496 (clk_sys_ratios[0].mclk_div *
1497 clk_sys_ratios[0].div)) - fs);
1498 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1499 cur_val = abs((wm8903->sysclk /
1500 (clk_sys_ratios[i].mclk_div *
1501 clk_sys_ratios[i].div)) - fs);
1502
1503 if (cur_val <= best_val) {
1504 clk_config = i;
1505 best_val = cur_val;
1506 }
1507 }
1508
1509 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1510 clock0 |= WM8903_MCLKDIV2;
1511 clk_sys = wm8903->sysclk / 2;
1512 } else {
1513 clock0 &= ~WM8903_MCLKDIV2;
1514 clk_sys = wm8903->sysclk;
1515 }
1516
1517 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1518 WM8903_CLK_SYS_MODE_MASK);
1519 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1520 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1521
1522 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1523 clk_sys_ratios[clk_config].rate,
1524 clk_sys_ratios[clk_config].mode,
1525 clk_sys_ratios[clk_config].div);
1526
1527 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1528
1529 /* We may not get quite the right frequency if using
1530 * approximate clocks so look for the closest match that is
1531 * higher than the target (we need to ensure that there enough
1532 * BCLKs to clock out the samples).
1533 */
1534 bclk_div = 0;
1535 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1536 i = 1;
1537 while (i < ARRAY_SIZE(bclk_divs)) {
1538 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1539 if (cur_val < 0) /* BCLK table is sorted */
1540 break;
1541 bclk_div = i;
1542 best_val = cur_val;
1543 i++;
1544 }
1545
1546 aif2 &= ~WM8903_BCLK_DIV_MASK;
1547 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1548
1549 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1550 bclk_divs[bclk_div].ratio / 10, bclk,
1551 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1552
1553 aif2 |= bclk_divs[bclk_div].div;
1554 aif3 |= bclk / fs;
1555
1556 wm8903->fs = params_rate(params);
1557 wm8903_set_deemph(codec);
1558
1559 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1560 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1561 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1562 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1563 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1564 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1565
1566 return 0;
1567 }
1568
1569 /**
1570 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1571 *
1572 * @codec: WM8903 codec
1573 * @jack: jack to report detection events on
1574 * @det: value to report for presence detection
1575 * @shrt: value to report for short detection
1576 *
1577 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1578 * being used to bring out signals to the processor then only platform
1579 * data configuration is needed for WM8903 and processor GPIOs should
1580 * be configured using snd_soc_jack_add_gpios() instead.
1581 *
1582 * The current threasholds for detection should be configured using
1583 * micdet_cfg in the platform data. Using this function will force on
1584 * the microphone bias for the device.
1585 */
1586 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1587 int det, int shrt)
1588 {
1589 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1590 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1591
1592 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1593 det, shrt);
1594
1595 /* Store the configuration */
1596 wm8903->mic_jack = jack;
1597 wm8903->mic_det = det;
1598 wm8903->mic_short = shrt;
1599
1600 /* Enable interrupts we've got a report configured for */
1601 if (det)
1602 irq_mask &= ~WM8903_MICDET_EINT;
1603 if (shrt)
1604 irq_mask &= ~WM8903_MICSHRT_EINT;
1605
1606 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1607 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1608 irq_mask);
1609
1610 if (det && shrt) {
1611 /* Enable mic detection, this may not have been set through
1612 * platform data (eg, if the defaults are OK). */
1613 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1614 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1615 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1616 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1617 } else {
1618 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1619 WM8903_MICDET_ENA, 0);
1620 }
1621
1622 return 0;
1623 }
1624 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1625
1626 static irqreturn_t wm8903_irq(int irq, void *data)
1627 {
1628 struct snd_soc_codec *codec = data;
1629 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1630 int mic_report;
1631 int int_pol;
1632 int int_val = 0;
1633 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
1634
1635 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
1636
1637 if (int_val & WM8903_WSEQ_BUSY_EINT) {
1638 dev_dbg(codec->dev, "Write sequencer done\n");
1639 complete(&wm8903->wseq);
1640 }
1641
1642 /*
1643 * The rest is microphone jack detection. We need to manually
1644 * invert the polarity of the interrupt after each event - to
1645 * simplify the code keep track of the last state we reported
1646 * and just invert the relevant bits in both the report and
1647 * the polarity register.
1648 */
1649 mic_report = wm8903->mic_last_report;
1650 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1651
1652 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1653 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1654 trace_snd_soc_jack_irq(dev_name(codec->dev));
1655 #endif
1656
1657 if (int_val & WM8903_MICSHRT_EINT) {
1658 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1659
1660 mic_report ^= wm8903->mic_short;
1661 int_pol ^= WM8903_MICSHRT_INV;
1662 }
1663
1664 if (int_val & WM8903_MICDET_EINT) {
1665 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1666
1667 mic_report ^= wm8903->mic_det;
1668 int_pol ^= WM8903_MICDET_INV;
1669
1670 msleep(wm8903->mic_delay);
1671 }
1672
1673 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1674 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1675
1676 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1677 wm8903->mic_short | wm8903->mic_det);
1678
1679 wm8903->mic_last_report = mic_report;
1680
1681 return IRQ_HANDLED;
1682 }
1683
1684 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1685 SNDRV_PCM_RATE_11025 | \
1686 SNDRV_PCM_RATE_16000 | \
1687 SNDRV_PCM_RATE_22050 | \
1688 SNDRV_PCM_RATE_32000 | \
1689 SNDRV_PCM_RATE_44100 | \
1690 SNDRV_PCM_RATE_48000 | \
1691 SNDRV_PCM_RATE_88200 | \
1692 SNDRV_PCM_RATE_96000)
1693
1694 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1695 SNDRV_PCM_RATE_11025 | \
1696 SNDRV_PCM_RATE_16000 | \
1697 SNDRV_PCM_RATE_22050 | \
1698 SNDRV_PCM_RATE_32000 | \
1699 SNDRV_PCM_RATE_44100 | \
1700 SNDRV_PCM_RATE_48000)
1701
1702 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1703 SNDRV_PCM_FMTBIT_S20_3LE |\
1704 SNDRV_PCM_FMTBIT_S24_LE)
1705
1706 static struct snd_soc_dai_ops wm8903_dai_ops = {
1707 .hw_params = wm8903_hw_params,
1708 .digital_mute = wm8903_digital_mute,
1709 .set_fmt = wm8903_set_dai_fmt,
1710 .set_sysclk = wm8903_set_dai_sysclk,
1711 };
1712
1713 static struct snd_soc_dai_driver wm8903_dai = {
1714 .name = "wm8903-hifi",
1715 .playback = {
1716 .stream_name = "Playback",
1717 .channels_min = 2,
1718 .channels_max = 2,
1719 .rates = WM8903_PLAYBACK_RATES,
1720 .formats = WM8903_FORMATS,
1721 },
1722 .capture = {
1723 .stream_name = "Capture",
1724 .channels_min = 2,
1725 .channels_max = 2,
1726 .rates = WM8903_CAPTURE_RATES,
1727 .formats = WM8903_FORMATS,
1728 },
1729 .ops = &wm8903_dai_ops,
1730 .symmetric_rates = 1,
1731 };
1732
1733 static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
1734 {
1735 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1736
1737 return 0;
1738 }
1739
1740 static int wm8903_resume(struct snd_soc_codec *codec)
1741 {
1742 int i;
1743 u16 *reg_cache = codec->reg_cache;
1744 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
1745 GFP_KERNEL);
1746
1747 /* Bring the codec back up to standby first to minimise pop/clicks */
1748 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1749
1750 /* Sync back everything else */
1751 if (tmp_cache) {
1752 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1753 if (tmp_cache[i] != reg_cache[i])
1754 snd_soc_write(codec, i, tmp_cache[i]);
1755 kfree(tmp_cache);
1756 } else {
1757 dev_err(codec->dev, "Failed to allocate temporary cache\n");
1758 }
1759
1760 return 0;
1761 }
1762
1763 #ifdef CONFIG_GPIOLIB
1764 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1765 {
1766 return container_of(chip, struct wm8903_priv, gpio_chip);
1767 }
1768
1769 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1770 {
1771 if (offset >= WM8903_NUM_GPIO)
1772 return -EINVAL;
1773
1774 return 0;
1775 }
1776
1777 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1778 {
1779 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1780 struct snd_soc_codec *codec = wm8903->codec;
1781 unsigned int mask, val;
1782
1783 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1784 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1785 WM8903_GP1_DIR;
1786
1787 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1788 mask, val);
1789 }
1790
1791 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1792 {
1793 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1794 struct snd_soc_codec *codec = wm8903->codec;
1795 int reg;
1796
1797 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1798
1799 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1800 }
1801
1802 static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1803 unsigned offset, int value)
1804 {
1805 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1806 struct snd_soc_codec *codec = wm8903->codec;
1807 unsigned int mask, val;
1808
1809 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1810 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1811 (value << WM8903_GP2_LVL_SHIFT);
1812
1813 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1814 mask, val);
1815 }
1816
1817 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1818 {
1819 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1820 struct snd_soc_codec *codec = wm8903->codec;
1821
1822 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1823 WM8903_GP1_LVL_MASK,
1824 !!value << WM8903_GP1_LVL_SHIFT);
1825 }
1826
1827 static struct gpio_chip wm8903_template_chip = {
1828 .label = "wm8903",
1829 .owner = THIS_MODULE,
1830 .request = wm8903_gpio_request,
1831 .direction_input = wm8903_gpio_direction_in,
1832 .get = wm8903_gpio_get,
1833 .direction_output = wm8903_gpio_direction_out,
1834 .set = wm8903_gpio_set,
1835 .can_sleep = 1,
1836 };
1837
1838 static void wm8903_init_gpio(struct snd_soc_codec *codec)
1839 {
1840 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1841 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1842 int ret;
1843
1844 wm8903->gpio_chip = wm8903_template_chip;
1845 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1846 wm8903->gpio_chip.dev = codec->dev;
1847
1848 if (pdata && pdata->gpio_base)
1849 wm8903->gpio_chip.base = pdata->gpio_base;
1850 else
1851 wm8903->gpio_chip.base = -1;
1852
1853 ret = gpiochip_add(&wm8903->gpio_chip);
1854 if (ret != 0)
1855 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1856 }
1857
1858 static void wm8903_free_gpio(struct snd_soc_codec *codec)
1859 {
1860 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1861 int ret;
1862
1863 ret = gpiochip_remove(&wm8903->gpio_chip);
1864 if (ret != 0)
1865 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1866 }
1867 #else
1868 static void wm8903_init_gpio(struct snd_soc_codec *codec)
1869 {
1870 }
1871
1872 static void wm8903_free_gpio(struct snd_soc_codec *codec)
1873 {
1874 }
1875 #endif
1876
1877 static int wm8903_probe(struct snd_soc_codec *codec)
1878 {
1879 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1880 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1881 int ret, i;
1882 int trigger, irq_pol;
1883 u16 val;
1884
1885 wm8903->codec = codec;
1886 init_completion(&wm8903->wseq);
1887
1888 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1889 if (ret != 0) {
1890 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1891 return ret;
1892 }
1893
1894 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1895 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1896 dev_err(codec->dev,
1897 "Device with ID register %x is not a WM8903\n", val);
1898 return -ENODEV;
1899 }
1900
1901 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1902 dev_info(codec->dev, "WM8903 revision %c\n",
1903 (val & WM8903_CHIP_REV_MASK) + 'A');
1904
1905 wm8903_reset(codec);
1906
1907 /* Set up GPIOs and microphone detection */
1908 if (pdata) {
1909 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1910 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
1911 continue;
1912
1913 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1914 pdata->gpio_cfg[i] & 0xffff);
1915 }
1916
1917 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1918 pdata->micdet_cfg);
1919
1920 /* Microphone detection needs the WSEQ clock */
1921 if (pdata->micdet_cfg)
1922 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1923 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1924
1925 wm8903->mic_delay = pdata->micdet_delay;
1926 }
1927
1928 if (wm8903->irq) {
1929 if (pdata && pdata->irq_active_low) {
1930 trigger = IRQF_TRIGGER_LOW;
1931 irq_pol = WM8903_IRQ_POL;
1932 } else {
1933 trigger = IRQF_TRIGGER_HIGH;
1934 irq_pol = 0;
1935 }
1936
1937 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1938 WM8903_IRQ_POL, irq_pol);
1939
1940 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
1941 trigger | IRQF_ONESHOT,
1942 "wm8903", codec);
1943 if (ret != 0) {
1944 dev_err(codec->dev, "Failed to request IRQ: %d\n",
1945 ret);
1946 return ret;
1947 }
1948
1949 /* Enable write sequencer interrupts */
1950 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1951 WM8903_IM_WSEQ_BUSY_EINT, 0);
1952 }
1953
1954 /* power on device */
1955 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1956
1957 /* Latch volume update bits */
1958 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1959 val |= WM8903_ADCVU;
1960 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1961 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1962
1963 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1964 val |= WM8903_DACVU;
1965 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1966 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1967
1968 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1969 val |= WM8903_HPOUTVU;
1970 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1971 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1972
1973 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1974 val |= WM8903_LINEOUTVU;
1975 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1976 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1977
1978 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1979 val |= WM8903_SPKVU;
1980 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1981 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1982
1983 /* Enable DAC soft mute by default */
1984 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1985 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1986 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
1987
1988 snd_soc_add_controls(codec, wm8903_snd_controls,
1989 ARRAY_SIZE(wm8903_snd_controls));
1990 wm8903_add_widgets(codec);
1991
1992 wm8903_init_gpio(codec);
1993
1994 return ret;
1995 }
1996
1997 /* power down chip */
1998 static int wm8903_remove(struct snd_soc_codec *codec)
1999 {
2000 wm8903_free_gpio(codec);
2001 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2002 return 0;
2003 }
2004
2005 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2006 .probe = wm8903_probe,
2007 .remove = wm8903_remove,
2008 .suspend = wm8903_suspend,
2009 .resume = wm8903_resume,
2010 .set_bias_level = wm8903_set_bias_level,
2011 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2012 .reg_word_size = sizeof(u16),
2013 .reg_cache_default = wm8903_reg_defaults,
2014 .volatile_register = wm8903_volatile_register,
2015 .seq_notifier = wm8903_seq_notifier,
2016 };
2017
2018 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2019 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2020 const struct i2c_device_id *id)
2021 {
2022 struct wm8903_priv *wm8903;
2023 int ret;
2024
2025 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2026 if (wm8903 == NULL)
2027 return -ENOMEM;
2028
2029 i2c_set_clientdata(i2c, wm8903);
2030 wm8903->irq = i2c->irq;
2031
2032 ret = snd_soc_register_codec(&i2c->dev,
2033 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2034 if (ret < 0)
2035 kfree(wm8903);
2036 return ret;
2037 }
2038
2039 static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2040 {
2041 snd_soc_unregister_codec(&client->dev);
2042 kfree(i2c_get_clientdata(client));
2043 return 0;
2044 }
2045
2046 static const struct i2c_device_id wm8903_i2c_id[] = {
2047 { "wm8903", 0 },
2048 { }
2049 };
2050 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2051
2052 static struct i2c_driver wm8903_i2c_driver = {
2053 .driver = {
2054 .name = "wm8903",
2055 .owner = THIS_MODULE,
2056 },
2057 .probe = wm8903_i2c_probe,
2058 .remove = __devexit_p(wm8903_i2c_remove),
2059 .id_table = wm8903_i2c_id,
2060 };
2061 #endif
2062
2063 static int __init wm8903_modinit(void)
2064 {
2065 int ret = 0;
2066 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2067 ret = i2c_add_driver(&wm8903_i2c_driver);
2068 if (ret != 0) {
2069 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2070 ret);
2071 }
2072 #endif
2073 return ret;
2074 }
2075 module_init(wm8903_modinit);
2076
2077 static void __exit wm8903_exit(void)
2078 {
2079 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2080 i2c_del_driver(&wm8903_i2c_driver);
2081 #endif
2082 }
2083 module_exit(wm8903_exit);
2084
2085 MODULE_DESCRIPTION("ASoC WM8903 driver");
2086 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2087 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.07343 seconds and 5 git commands to generate.