2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
5 * Copyright 2011 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/jack.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/tlv.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/wm8903.h>
36 #include <trace/events/asoc.h>
40 /* Register defaults at reset */
41 static u16 wm8903_reg_defaults
[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
50 0x0001, /* R8 - Analogue DAC 0 */
52 0x0001, /* R10 - Analogue ADC 0 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
109 0x0010, /* R67 - DC Servo 0 */
111 0x00A4, /* R69 - DC Servo 2 */
132 0x0000, /* R90 - Analogue HP 0 */
136 0x0000, /* R94 - Analogue Lineout 0 */
140 0x0000, /* R98 - Charge Pump 0 */
146 0x0000, /* R104 - Class W 0 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
156 0x0000, /* R114 - Control Interface */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
168 0x0000, /* R126 - Interrupt Control */
171 0x0000, /* R129 - Control Interface Test 1 */
191 0x6810, /* R149 - Charge Pump Test 1 */
206 0x0028, /* R164 - Clock Rate Test 4 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
218 struct snd_soc_codec
*codec
;
229 /* Reference count */
232 struct completion wseq
;
234 struct snd_soc_jack
*mic_jack
;
240 #ifdef CONFIG_GPIOLIB
241 struct gpio_chip gpio_chip
;
245 static int wm8903_volatile_register(struct snd_soc_codec
*codec
, unsigned int reg
)
248 case WM8903_SW_RESET_AND_ID
:
249 case WM8903_REVISION_NUMBER
:
250 case WM8903_INTERRUPT_STATUS_1
:
251 case WM8903_WRITE_SEQUENCER_4
:
252 case WM8903_POWER_MANAGEMENT_3
:
253 case WM8903_POWER_MANAGEMENT_2
:
254 case WM8903_DC_SERVO_READBACK_1
:
255 case WM8903_DC_SERVO_READBACK_2
:
256 case WM8903_DC_SERVO_READBACK_3
:
257 case WM8903_DC_SERVO_READBACK_4
:
265 static int wm8903_run_sequence(struct snd_soc_codec
*codec
, unsigned int start
)
268 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
272 /* Enable the sequencer if it's not already on */
273 reg
[0] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_0
);
274 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
,
275 reg
[0] | WM8903_WSEQ_ENA
);
277 dev_dbg(codec
->dev
, "Starting sequence at %d\n", start
);
279 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_3
,
280 start
| WM8903_WSEQ_START
);
282 /* Wait for it to complete. If we have the interrupt wired up then
283 * that will break us out of the poll early.
286 wait_for_completion_timeout(&wm8903
->wseq
,
287 msecs_to_jiffies(10));
289 reg
[4] = snd_soc_read(codec
, WM8903_WRITE_SEQUENCER_4
);
290 } while (reg
[4] & WM8903_WSEQ_BUSY
);
292 dev_dbg(codec
->dev
, "Sequence complete\n");
294 /* Disable the sequencer again if we enabled it */
295 snd_soc_write(codec
, WM8903_WRITE_SEQUENCER_0
, reg
[0]);
300 static void wm8903_reset(struct snd_soc_codec
*codec
)
302 snd_soc_write(codec
, WM8903_SW_RESET_AND_ID
, 0);
303 memcpy(codec
->reg_cache
, wm8903_reg_defaults
,
304 sizeof(wm8903_reg_defaults
));
307 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
308 struct snd_kcontrol
*kcontrol
, int event
)
310 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
316 static int wm8903_dcs_event(struct snd_soc_dapm_widget
*w
,
317 struct snd_kcontrol
*kcontrol
, int event
)
319 struct snd_soc_codec
*codec
= w
->codec
;
320 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
323 case SND_SOC_DAPM_POST_PMU
:
324 wm8903
->dcs_pending
|= 1 << w
->shift
;
326 case SND_SOC_DAPM_PRE_PMD
:
327 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
335 #define WM8903_DCS_MODE_WRITE_STOP 0
336 #define WM8903_DCS_MODE_START_STOP 2
338 static void wm8903_seq_notifier(struct snd_soc_dapm_context
*dapm
,
339 enum snd_soc_dapm_type event
, int subseq
)
341 struct snd_soc_codec
*codec
= container_of(dapm
,
342 struct snd_soc_codec
, dapm
);
343 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
344 int dcs_mode
= WM8903_DCS_MODE_WRITE_STOP
;
347 /* Complete any pending DC servo starts */
348 if (wm8903
->dcs_pending
) {
349 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
350 wm8903
->dcs_pending
);
352 /* If we've no cached values then we need to do startup */
353 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
354 if (!(wm8903
->dcs_pending
& (1 << i
)))
357 if (wm8903
->dcs_cache
[i
]) {
359 "Restore DC servo %d value %x\n",
360 3 - i
, wm8903
->dcs_cache
[i
]);
362 snd_soc_write(codec
, WM8903_DC_SERVO_4
+ i
,
363 wm8903
->dcs_cache
[i
] & 0xff);
366 "Calibrate DC servo %d\n", 3 - i
);
367 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
371 /* Don't trust the cache for analogue */
372 if (wm8903
->class_w_users
)
373 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
375 snd_soc_update_bits(codec
, WM8903_DC_SERVO_2
,
376 WM8903_DCS_MODE_MASK
, dcs_mode
);
378 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
379 WM8903_DCS_ENA_MASK
, wm8903
->dcs_pending
);
382 case WM8903_DCS_MODE_WRITE_STOP
:
385 case WM8903_DCS_MODE_START_STOP
:
388 /* Cache the measured offsets for digital */
389 if (wm8903
->class_w_users
)
392 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
393 if (!(wm8903
->dcs_pending
& (1 << i
)))
396 val
= snd_soc_read(codec
,
397 WM8903_DC_SERVO_READBACK_1
+ i
);
398 dev_dbg(codec
->dev
, "DC servo %d: %x\n",
400 wm8903
->dcs_cache
[i
] = val
;
405 pr_warn("DCS mode %d delay not set\n", dcs_mode
);
409 wm8903
->dcs_pending
= 0;
414 * When used with DAC outputs only the WM8903 charge pump supports
415 * operation in class W mode, providing very low power consumption
416 * when used with digital sources. Enable and disable this mode
417 * automatically depending on the mixer configuration.
419 * All the relevant controls are simple switches.
421 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
422 struct snd_ctl_elem_value
*ucontrol
)
424 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
425 struct snd_soc_codec
*codec
= widget
->codec
;
426 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
430 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
432 /* Turn it off if we're about to enable bypass */
433 if (ucontrol
->value
.integer
.value
[0]) {
434 if (wm8903
->class_w_users
== 0) {
435 dev_dbg(codec
->dev
, "Disabling Class W\n");
436 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
437 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
439 wm8903
->class_w_users
++;
442 /* Implement the change */
443 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
445 /* If we've just disabled the last bypass path turn Class W on */
446 if (!ucontrol
->value
.integer
.value
[0]) {
447 if (wm8903
->class_w_users
== 1) {
448 dev_dbg(codec
->dev
, "Enabling Class W\n");
449 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
450 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
452 wm8903
->class_w_users
--;
455 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
456 wm8903
->class_w_users
);
461 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
462 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
463 .info = snd_soc_info_volsw, \
464 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
465 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
468 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
470 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
472 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
475 /* If we're using deemphasis select the nearest available sample
478 if (wm8903
->deemph
) {
480 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
481 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
482 abs(wm8903_deemph
[best
] - wm8903
->fs
))
486 val
= best
<< WM8903_DEEMPH_SHIFT
;
492 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
493 best
, wm8903_deemph
[best
]);
495 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
496 WM8903_DEEMPH_MASK
, val
);
499 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
500 struct snd_ctl_elem_value
*ucontrol
)
502 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
503 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
505 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
510 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
511 struct snd_ctl_elem_value
*ucontrol
)
513 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
514 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
515 int deemph
= ucontrol
->value
.enumerated
.item
[0];
521 mutex_lock(&codec
->mutex
);
522 if (wm8903
->deemph
!= deemph
) {
523 wm8903
->deemph
= deemph
;
525 wm8903_set_deemph(codec
);
529 mutex_unlock(&codec
->mutex
);
534 /* ALSA can only do steps of .01dB */
535 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
537 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
538 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
540 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
541 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
542 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
543 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
544 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
546 static const char *hpf_mode_text
[] = {
547 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
550 static const struct soc_enum hpf_mode
=
551 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
553 static const char *osr_text
[] = {
554 "Low power", "High performance"
557 static const struct soc_enum adc_osr
=
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
560 static const struct soc_enum dac_osr
=
561 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
563 static const char *drc_slope_text
[] = {
564 "1", "1/2", "1/4", "1/8", "1/16", "0"
567 static const struct soc_enum drc_slope_r0
=
568 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
570 static const struct soc_enum drc_slope_r1
=
571 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
573 static const char *drc_attack_text
[] = {
575 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
576 "46.4ms", "92.8ms", "185.6ms"
579 static const struct soc_enum drc_attack
=
580 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
582 static const char *drc_decay_text
[] = {
583 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
587 static const struct soc_enum drc_decay
=
588 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
590 static const char *drc_ff_delay_text
[] = {
591 "5 samples", "9 samples"
594 static const struct soc_enum drc_ff_delay
=
595 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
597 static const char *drc_qr_decay_text
[] = {
598 "0.725ms", "1.45ms", "5.8ms"
601 static const struct soc_enum drc_qr_decay
=
602 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
604 static const char *drc_smoothing_text
[] = {
605 "Low", "Medium", "High"
608 static const struct soc_enum drc_smoothing
=
609 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
611 static const char *soft_mute_text
[] = {
612 "Fast (fs/2)", "Slow (fs/32)"
615 static const struct soc_enum soft_mute
=
616 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
618 static const char *mute_mode_text
[] = {
622 static const struct soc_enum mute_mode
=
623 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
625 static const char *companding_text
[] = {
629 static const struct soc_enum dac_companding
=
630 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
632 static const struct soc_enum adc_companding
=
633 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
635 static const char *input_mode_text
[] = {
636 "Single-Ended", "Differential Line", "Differential Mic"
639 static const struct soc_enum linput_mode_enum
=
640 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
642 static const struct soc_enum rinput_mode_enum
=
643 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
645 static const char *linput_mux_text
[] = {
646 "IN1L", "IN2L", "IN3L"
649 static const struct soc_enum linput_enum
=
650 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
652 static const struct soc_enum linput_inv_enum
=
653 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
655 static const char *rinput_mux_text
[] = {
656 "IN1R", "IN2R", "IN3R"
659 static const struct soc_enum rinput_enum
=
660 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
662 static const struct soc_enum rinput_inv_enum
=
663 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
666 static const char *sidetone_text
[] = {
667 "None", "Left", "Right"
670 static const struct soc_enum lsidetone_enum
=
671 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
673 static const struct soc_enum rsidetone_enum
=
674 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
676 static const char *aif_text
[] = {
680 static const struct soc_enum lcapture_enum
=
681 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
683 static const struct soc_enum rcapture_enum
=
684 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
686 static const struct soc_enum lplay_enum
=
687 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
689 static const struct soc_enum rplay_enum
=
690 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
692 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
694 /* Input PGAs - No TLV since the scale depends on PGA mode */
695 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
697 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
699 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
702 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
704 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
706 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
710 SOC_ENUM("ADC OSR", adc_osr
),
711 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
712 SOC_ENUM("HPF Mode", hpf_mode
),
713 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
714 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
715 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
716 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
718 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
719 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
720 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
721 SOC_ENUM("DRC Attack Rate", drc_attack
),
722 SOC_ENUM("DRC Decay Rate", drc_decay
),
723 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
724 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
725 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
726 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
727 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
728 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
729 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
730 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
731 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
733 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
734 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
735 SOC_ENUM("ADC Companding Mode", adc_companding
),
736 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
738 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
739 12, 0, digital_sidetone_tlv
),
742 SOC_ENUM("DAC OSR", dac_osr
),
743 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
744 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
745 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
746 SOC_ENUM("DAC Mute Mode", mute_mode
),
747 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
748 SOC_ENUM("DAC Companding Mode", dac_companding
),
749 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
750 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
751 wm8903_get_deemph
, wm8903_put_deemph
),
754 SOC_DOUBLE_R("Headphone Switch",
755 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
757 SOC_DOUBLE_R("Headphone ZC Switch",
758 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
760 SOC_DOUBLE_R_TLV("Headphone Volume",
761 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
765 SOC_DOUBLE_R("Line Out Switch",
766 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
768 SOC_DOUBLE_R("Line Out ZC Switch",
769 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
771 SOC_DOUBLE_R_TLV("Line Out Volume",
772 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
776 SOC_DOUBLE_R("Speaker Switch",
777 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
778 SOC_DOUBLE_R("Speaker ZC Switch",
779 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
780 SOC_DOUBLE_R_TLV("Speaker Volume",
781 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
785 static const struct snd_kcontrol_new linput_mode_mux
=
786 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
788 static const struct snd_kcontrol_new rinput_mode_mux
=
789 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
791 static const struct snd_kcontrol_new linput_mux
=
792 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
794 static const struct snd_kcontrol_new linput_inv_mux
=
795 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
797 static const struct snd_kcontrol_new rinput_mux
=
798 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
800 static const struct snd_kcontrol_new rinput_inv_mux
=
801 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
803 static const struct snd_kcontrol_new lsidetone_mux
=
804 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
806 static const struct snd_kcontrol_new rsidetone_mux
=
807 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
809 static const struct snd_kcontrol_new lcapture_mux
=
810 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
812 static const struct snd_kcontrol_new rcapture_mux
=
813 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
815 static const struct snd_kcontrol_new lplay_mux
=
816 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
818 static const struct snd_kcontrol_new rplay_mux
=
819 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
821 static const struct snd_kcontrol_new left_output_mixer
[] = {
822 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
823 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
824 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
825 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
828 static const struct snd_kcontrol_new right_output_mixer
[] = {
829 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
830 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
831 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
832 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
835 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
836 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
837 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
838 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
839 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
843 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
844 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
845 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
846 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
848 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
852 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
853 SND_SOC_DAPM_INPUT("IN1L"),
854 SND_SOC_DAPM_INPUT("IN1R"),
855 SND_SOC_DAPM_INPUT("IN2L"),
856 SND_SOC_DAPM_INPUT("IN2R"),
857 SND_SOC_DAPM_INPUT("IN3L"),
858 SND_SOC_DAPM_INPUT("IN3R"),
860 SND_SOC_DAPM_OUTPUT("HPOUTL"),
861 SND_SOC_DAPM_OUTPUT("HPOUTR"),
862 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
863 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
864 SND_SOC_DAPM_OUTPUT("LOP"),
865 SND_SOC_DAPM_OUTPUT("LON"),
866 SND_SOC_DAPM_OUTPUT("ROP"),
867 SND_SOC_DAPM_OUTPUT("RON"),
869 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0
, 0, 0),
871 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
872 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
874 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
876 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
877 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
879 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
881 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
882 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
884 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
885 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
887 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
888 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
890 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
891 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
893 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
894 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
896 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
897 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
899 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
900 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
902 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
903 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
905 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
906 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
907 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
908 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
910 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
911 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
912 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
913 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
915 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0
,
917 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0
,
920 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
922 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
925 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
926 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
927 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
928 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
929 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
930 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
932 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
934 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
936 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
938 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
940 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
942 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
945 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0
, 4, 0, NULL
, 0),
946 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM
, 3, 0, wm8903_dcs_event
,
947 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
948 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM
, 2, 0, wm8903_dcs_event
,
949 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
950 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM
, 1, 0, wm8903_dcs_event
,
951 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
952 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM
, 0, 0, wm8903_dcs_event
,
953 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
955 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
957 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
960 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
961 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
962 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
963 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
966 static const struct snd_soc_dapm_route intercon
[] = {
968 { "CLK_DSP", NULL
, "CLK_SYS" },
969 { "Mic Bias", NULL
, "CLK_SYS" },
970 { "HPL_DCS", NULL
, "CLK_SYS" },
971 { "HPR_DCS", NULL
, "CLK_SYS" },
972 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
973 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
975 { "Left Input Mux", "IN1L", "IN1L" },
976 { "Left Input Mux", "IN2L", "IN2L" },
977 { "Left Input Mux", "IN3L", "IN3L" },
979 { "Left Input Inverting Mux", "IN1L", "IN1L" },
980 { "Left Input Inverting Mux", "IN2L", "IN2L" },
981 { "Left Input Inverting Mux", "IN3L", "IN3L" },
983 { "Right Input Mux", "IN1R", "IN1R" },
984 { "Right Input Mux", "IN2R", "IN2R" },
985 { "Right Input Mux", "IN3R", "IN3R" },
987 { "Right Input Inverting Mux", "IN1R", "IN1R" },
988 { "Right Input Inverting Mux", "IN2R", "IN2R" },
989 { "Right Input Inverting Mux", "IN3R", "IN3R" },
991 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
992 { "Left Input Mode Mux", "Differential Line",
994 { "Left Input Mode Mux", "Differential Line",
995 "Left Input Inverting Mux" },
996 { "Left Input Mode Mux", "Differential Mic",
998 { "Left Input Mode Mux", "Differential Mic",
999 "Left Input Inverting Mux" },
1001 { "Right Input Mode Mux", "Single-Ended",
1002 "Right Input Inverting Mux" },
1003 { "Right Input Mode Mux", "Differential Line",
1004 "Right Input Mux" },
1005 { "Right Input Mode Mux", "Differential Line",
1006 "Right Input Inverting Mux" },
1007 { "Right Input Mode Mux", "Differential Mic",
1008 "Right Input Mux" },
1009 { "Right Input Mode Mux", "Differential Mic",
1010 "Right Input Inverting Mux" },
1012 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
1013 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
1015 { "Left Capture Mux", "Left", "ADCL" },
1016 { "Left Capture Mux", "Right", "ADCR" },
1018 { "Right Capture Mux", "Left", "ADCL" },
1019 { "Right Capture Mux", "Right", "ADCR" },
1021 { "AIFTXL", NULL
, "Left Capture Mux" },
1022 { "AIFTXR", NULL
, "Right Capture Mux" },
1024 { "ADCL", NULL
, "Left Input PGA" },
1025 { "ADCL", NULL
, "CLK_DSP" },
1026 { "ADCR", NULL
, "Right Input PGA" },
1027 { "ADCR", NULL
, "CLK_DSP" },
1029 { "Left Playback Mux", "Left", "AIFRXL" },
1030 { "Left Playback Mux", "Right", "AIFRXR" },
1032 { "Right Playback Mux", "Left", "AIFRXL" },
1033 { "Right Playback Mux", "Right", "AIFRXR" },
1035 { "DACL Sidetone", "Left", "ADCL" },
1036 { "DACL Sidetone", "Right", "ADCR" },
1037 { "DACR Sidetone", "Left", "ADCL" },
1038 { "DACR Sidetone", "Right", "ADCR" },
1040 { "DACL", NULL
, "Left Playback Mux" },
1041 { "DACL", NULL
, "DACL Sidetone" },
1042 { "DACL", NULL
, "CLK_DSP" },
1044 { "DACR", NULL
, "Right Playback Mux" },
1045 { "DACR", NULL
, "DACR Sidetone" },
1046 { "DACR", NULL
, "CLK_DSP" },
1048 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1049 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1050 { "Left Output Mixer", "DACL Switch", "DACL" },
1051 { "Left Output Mixer", "DACR Switch", "DACR" },
1053 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1054 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1055 { "Right Output Mixer", "DACL Switch", "DACL" },
1056 { "Right Output Mixer", "DACR Switch", "DACR" },
1058 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1059 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1060 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1061 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1063 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1064 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1065 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1066 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1068 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
1069 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
1071 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
1072 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
1074 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
1075 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
1077 { "HPL_ENA_DLY", NULL
, "Left Headphone Output PGA" },
1078 { "HPR_ENA_DLY", NULL
, "Right Headphone Output PGA" },
1079 { "LINEOUTL_ENA_DLY", NULL
, "Left Line Output PGA" },
1080 { "LINEOUTR_ENA_DLY", NULL
, "Right Line Output PGA" },
1082 { "HPL_DCS", NULL
, "DCS Master" },
1083 { "HPR_DCS", NULL
, "DCS Master" },
1084 { "LINEOUTL_DCS", NULL
, "DCS Master" },
1085 { "LINEOUTR_DCS", NULL
, "DCS Master" },
1087 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
1088 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
1089 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
1090 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
1092 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
1093 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
1094 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
1095 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
1097 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
1098 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
1099 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
1100 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
1102 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
1103 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
1104 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1105 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1107 { "LOP", NULL
, "Left Speaker PGA" },
1108 { "LON", NULL
, "Left Speaker PGA" },
1110 { "ROP", NULL
, "Right Speaker PGA" },
1111 { "RON", NULL
, "Right Speaker PGA" },
1113 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1114 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1115 { "Left Line Output PGA", NULL
, "Charge Pump" },
1116 { "Right Line Output PGA", NULL
, "Charge Pump" },
1119 static int wm8903_add_widgets(struct snd_soc_codec
*codec
)
1121 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1123 snd_soc_dapm_new_controls(dapm
, wm8903_dapm_widgets
,
1124 ARRAY_SIZE(wm8903_dapm_widgets
));
1125 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
1130 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1131 enum snd_soc_bias_level level
)
1134 case SND_SOC_BIAS_ON
:
1137 case SND_SOC_BIAS_PREPARE
:
1138 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1139 WM8903_VMID_RES_MASK
,
1140 WM8903_VMID_RES_50K
);
1143 case SND_SOC_BIAS_STANDBY
:
1144 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1145 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1146 WM8903_POBCTRL
| WM8903_ISEL_MASK
|
1147 WM8903_STARTUP_BIAS_ENA
|
1150 (2 << WM8903_ISEL_SHIFT
) |
1151 WM8903_STARTUP_BIAS_ENA
);
1153 snd_soc_update_bits(codec
,
1154 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1155 WM8903_SPK_DISCHARGE
,
1156 WM8903_SPK_DISCHARGE
);
1160 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1161 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1162 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
);
1164 snd_soc_update_bits(codec
,
1165 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1166 WM8903_SPK_DISCHARGE
, 0);
1168 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1169 WM8903_VMID_TIE_ENA
|
1171 WM8903_VMID_IO_ENA
|
1172 WM8903_VMID_SOFT_MASK
|
1173 WM8903_VMID_RES_MASK
|
1174 WM8903_VMID_BUF_ENA
,
1175 WM8903_VMID_TIE_ENA
|
1177 WM8903_VMID_IO_ENA
|
1178 (2 << WM8903_VMID_SOFT_SHIFT
) |
1179 WM8903_VMID_RES_250K
|
1180 WM8903_VMID_BUF_ENA
);
1184 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1185 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1188 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1189 WM8903_VMID_SOFT_MASK
, 0);
1191 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1192 WM8903_VMID_RES_MASK
,
1193 WM8903_VMID_RES_50K
);
1195 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1196 WM8903_BIAS_ENA
| WM8903_POBCTRL
,
1199 /* By default no bypass paths are enabled so
1200 * enable Class W support.
1202 dev_dbg(codec
->dev
, "Enabling Class W\n");
1203 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1204 WM8903_CP_DYN_FREQ
|
1206 WM8903_CP_DYN_FREQ
|
1210 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1211 WM8903_VMID_RES_MASK
,
1212 WM8903_VMID_RES_250K
);
1215 case SND_SOC_BIAS_OFF
:
1216 snd_soc_update_bits(codec
, WM8903_CLOCK_RATES_2
,
1217 WM8903_CLK_SYS_ENA
, WM8903_CLK_SYS_ENA
);
1218 wm8903_run_sequence(codec
, 32);
1219 snd_soc_update_bits(codec
, WM8903_CLOCK_RATES_2
,
1220 WM8903_CLK_SYS_ENA
, 0);
1224 codec
->dapm
.bias_level
= level
;
1229 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1230 int clk_id
, unsigned int freq
, int dir
)
1232 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1233 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1235 wm8903
->sysclk
= freq
;
1240 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1243 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1244 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1246 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1247 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1249 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1250 case SND_SOC_DAIFMT_CBS_CFS
:
1252 case SND_SOC_DAIFMT_CBS_CFM
:
1253 aif1
|= WM8903_LRCLK_DIR
;
1255 case SND_SOC_DAIFMT_CBM_CFM
:
1256 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1258 case SND_SOC_DAIFMT_CBM_CFS
:
1259 aif1
|= WM8903_BCLK_DIR
;
1265 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1266 case SND_SOC_DAIFMT_DSP_A
:
1269 case SND_SOC_DAIFMT_DSP_B
:
1270 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1272 case SND_SOC_DAIFMT_I2S
:
1275 case SND_SOC_DAIFMT_RIGHT_J
:
1278 case SND_SOC_DAIFMT_LEFT_J
:
1284 /* Clock inversion */
1285 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1286 case SND_SOC_DAIFMT_DSP_A
:
1287 case SND_SOC_DAIFMT_DSP_B
:
1288 /* frame inversion not valid for DSP modes */
1289 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1290 case SND_SOC_DAIFMT_NB_NF
:
1292 case SND_SOC_DAIFMT_IB_NF
:
1293 aif1
|= WM8903_AIF_BCLK_INV
;
1299 case SND_SOC_DAIFMT_I2S
:
1300 case SND_SOC_DAIFMT_RIGHT_J
:
1301 case SND_SOC_DAIFMT_LEFT_J
:
1302 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1303 case SND_SOC_DAIFMT_NB_NF
:
1305 case SND_SOC_DAIFMT_IB_IF
:
1306 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1308 case SND_SOC_DAIFMT_IB_NF
:
1309 aif1
|= WM8903_AIF_BCLK_INV
;
1311 case SND_SOC_DAIFMT_NB_IF
:
1312 aif1
|= WM8903_AIF_LRCLK_INV
;
1322 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1327 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1329 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1332 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1335 reg
|= WM8903_DAC_MUTE
;
1337 reg
&= ~WM8903_DAC_MUTE
;
1339 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1344 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1345 * for optimal performance so we list the lower rates first and match
1346 * on the last match we find. */
1352 } clk_sys_ratios
[] = {
1353 { 64, 0x0, 0x0, 1 },
1354 { 68, 0x0, 0x1, 1 },
1355 { 125, 0x0, 0x2, 1 },
1356 { 128, 0x1, 0x0, 1 },
1357 { 136, 0x1, 0x1, 1 },
1358 { 192, 0x2, 0x0, 1 },
1359 { 204, 0x2, 0x1, 1 },
1361 { 64, 0x0, 0x0, 2 },
1362 { 68, 0x0, 0x1, 2 },
1363 { 125, 0x0, 0x2, 2 },
1364 { 128, 0x1, 0x0, 2 },
1365 { 136, 0x1, 0x1, 2 },
1366 { 192, 0x2, 0x0, 2 },
1367 { 204, 0x2, 0x1, 2 },
1369 { 250, 0x2, 0x2, 1 },
1370 { 256, 0x3, 0x0, 1 },
1371 { 272, 0x3, 0x1, 1 },
1372 { 384, 0x4, 0x0, 1 },
1373 { 408, 0x4, 0x1, 1 },
1374 { 375, 0x4, 0x2, 1 },
1375 { 512, 0x5, 0x0, 1 },
1376 { 544, 0x5, 0x1, 1 },
1377 { 500, 0x5, 0x2, 1 },
1378 { 768, 0x6, 0x0, 1 },
1379 { 816, 0x6, 0x1, 1 },
1380 { 750, 0x6, 0x2, 1 },
1381 { 1024, 0x7, 0x0, 1 },
1382 { 1088, 0x7, 0x1, 1 },
1383 { 1000, 0x7, 0x2, 1 },
1384 { 1408, 0x8, 0x0, 1 },
1385 { 1496, 0x8, 0x1, 1 },
1386 { 1536, 0x9, 0x0, 1 },
1387 { 1632, 0x9, 0x1, 1 },
1388 { 1500, 0x9, 0x2, 1 },
1390 { 250, 0x2, 0x2, 2 },
1391 { 256, 0x3, 0x0, 2 },
1392 { 272, 0x3, 0x1, 2 },
1393 { 384, 0x4, 0x0, 2 },
1394 { 408, 0x4, 0x1, 2 },
1395 { 375, 0x4, 0x2, 2 },
1396 { 512, 0x5, 0x0, 2 },
1397 { 544, 0x5, 0x1, 2 },
1398 { 500, 0x5, 0x2, 2 },
1399 { 768, 0x6, 0x0, 2 },
1400 { 816, 0x6, 0x1, 2 },
1401 { 750, 0x6, 0x2, 2 },
1402 { 1024, 0x7, 0x0, 2 },
1403 { 1088, 0x7, 0x1, 2 },
1404 { 1000, 0x7, 0x2, 2 },
1405 { 1408, 0x8, 0x0, 2 },
1406 { 1496, 0x8, 0x1, 2 },
1407 { 1536, 0x9, 0x0, 2 },
1408 { 1632, 0x9, 0x1, 2 },
1409 { 1500, 0x9, 0x2, 2 },
1412 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1436 /* Sample rates for DSP */
1440 } sample_rates
[] = {
1455 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1456 struct snd_pcm_hw_params
*params
,
1457 struct snd_soc_dai
*dai
)
1459 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1460 struct snd_soc_codec
*codec
=rtd
->codec
;
1461 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1462 int fs
= params_rate(params
);
1472 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1473 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1474 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1475 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1476 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1477 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1479 /* Enable sloping stopband filter for low sample rates */
1481 dac_digital1
|= WM8903_DAC_SB_FILT
;
1483 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1485 /* Configure sample rate logic for DSP - choose nearest rate */
1487 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1488 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1489 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1490 if (cur_val
<= best_val
) {
1496 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1497 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1498 clock1
|= sample_rates
[dsp_config
].value
;
1500 aif1
&= ~WM8903_AIF_WL_MASK
;
1502 switch (params_format(params
)) {
1503 case SNDRV_PCM_FORMAT_S16_LE
:
1506 case SNDRV_PCM_FORMAT_S20_3LE
:
1510 case SNDRV_PCM_FORMAT_S24_LE
:
1514 case SNDRV_PCM_FORMAT_S32_LE
:
1522 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1523 wm8903
->sysclk
, fs
);
1525 /* We may not have an MCLK which allows us to generate exactly
1526 * the clock we want, particularly with USB derived inputs, so
1530 best_val
= abs((wm8903
->sysclk
/
1531 (clk_sys_ratios
[0].mclk_div
*
1532 clk_sys_ratios
[0].div
)) - fs
);
1533 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1534 cur_val
= abs((wm8903
->sysclk
/
1535 (clk_sys_ratios
[i
].mclk_div
*
1536 clk_sys_ratios
[i
].div
)) - fs
);
1538 if (cur_val
<= best_val
) {
1544 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1545 clock0
|= WM8903_MCLKDIV2
;
1546 clk_sys
= wm8903
->sysclk
/ 2;
1548 clock0
&= ~WM8903_MCLKDIV2
;
1549 clk_sys
= wm8903
->sysclk
;
1552 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1553 WM8903_CLK_SYS_MODE_MASK
);
1554 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1555 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1557 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1558 clk_sys_ratios
[clk_config
].rate
,
1559 clk_sys_ratios
[clk_config
].mode
,
1560 clk_sys_ratios
[clk_config
].div
);
1562 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1564 /* We may not get quite the right frequency if using
1565 * approximate clocks so look for the closest match that is
1566 * higher than the target (we need to ensure that there enough
1567 * BCLKs to clock out the samples).
1570 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1572 while (i
< ARRAY_SIZE(bclk_divs
)) {
1573 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1574 if (cur_val
< 0) /* BCLK table is sorted */
1581 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1582 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1584 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1585 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1586 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1588 aif2
|= bclk_divs
[bclk_div
].div
;
1591 wm8903
->fs
= params_rate(params
);
1592 wm8903_set_deemph(codec
);
1594 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1595 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1596 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1597 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1598 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1599 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1605 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1607 * @codec: WM8903 codec
1608 * @jack: jack to report detection events on
1609 * @det: value to report for presence detection
1610 * @shrt: value to report for short detection
1612 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1613 * being used to bring out signals to the processor then only platform
1614 * data configuration is needed for WM8903 and processor GPIOs should
1615 * be configured using snd_soc_jack_add_gpios() instead.
1617 * The current threasholds for detection should be configured using
1618 * micdet_cfg in the platform data. Using this function will force on
1619 * the microphone bias for the device.
1621 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1624 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1625 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1627 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1630 /* Store the configuration */
1631 wm8903
->mic_jack
= jack
;
1632 wm8903
->mic_det
= det
;
1633 wm8903
->mic_short
= shrt
;
1635 /* Enable interrupts we've got a report configured for */
1637 irq_mask
&= ~WM8903_MICDET_EINT
;
1639 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1641 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1642 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1646 /* Enable mic detection, this may not have been set through
1647 * platform data (eg, if the defaults are OK). */
1648 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1649 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1650 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1651 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1653 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1654 WM8903_MICDET_ENA
, 0);
1659 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1661 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1663 struct snd_soc_codec
*codec
= data
;
1664 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1668 int mask
= ~snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1_MASK
);
1670 int_val
= snd_soc_read(codec
, WM8903_INTERRUPT_STATUS_1
) & mask
;
1672 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1673 dev_dbg(codec
->dev
, "Write sequencer done\n");
1674 complete(&wm8903
->wseq
);
1678 * The rest is microphone jack detection. We need to manually
1679 * invert the polarity of the interrupt after each event - to
1680 * simplify the code keep track of the last state we reported
1681 * and just invert the relevant bits in both the report and
1682 * the polarity register.
1684 mic_report
= wm8903
->mic_last_report
;
1685 int_pol
= snd_soc_read(codec
, WM8903_INTERRUPT_POLARITY_1
);
1687 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1688 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1689 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
1692 if (int_val
& WM8903_MICSHRT_EINT
) {
1693 dev_dbg(codec
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1695 mic_report
^= wm8903
->mic_short
;
1696 int_pol
^= WM8903_MICSHRT_INV
;
1699 if (int_val
& WM8903_MICDET_EINT
) {
1700 dev_dbg(codec
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1702 mic_report
^= wm8903
->mic_det
;
1703 int_pol
^= WM8903_MICDET_INV
;
1705 msleep(wm8903
->mic_delay
);
1708 snd_soc_update_bits(codec
, WM8903_INTERRUPT_POLARITY_1
,
1709 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1711 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1712 wm8903
->mic_short
| wm8903
->mic_det
);
1714 wm8903
->mic_last_report
= mic_report
;
1719 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1720 SNDRV_PCM_RATE_11025 | \
1721 SNDRV_PCM_RATE_16000 | \
1722 SNDRV_PCM_RATE_22050 | \
1723 SNDRV_PCM_RATE_32000 | \
1724 SNDRV_PCM_RATE_44100 | \
1725 SNDRV_PCM_RATE_48000 | \
1726 SNDRV_PCM_RATE_88200 | \
1727 SNDRV_PCM_RATE_96000)
1729 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1730 SNDRV_PCM_RATE_11025 | \
1731 SNDRV_PCM_RATE_16000 | \
1732 SNDRV_PCM_RATE_22050 | \
1733 SNDRV_PCM_RATE_32000 | \
1734 SNDRV_PCM_RATE_44100 | \
1735 SNDRV_PCM_RATE_48000)
1737 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1738 SNDRV_PCM_FMTBIT_S20_3LE |\
1739 SNDRV_PCM_FMTBIT_S24_LE)
1741 static struct snd_soc_dai_ops wm8903_dai_ops
= {
1742 .hw_params
= wm8903_hw_params
,
1743 .digital_mute
= wm8903_digital_mute
,
1744 .set_fmt
= wm8903_set_dai_fmt
,
1745 .set_sysclk
= wm8903_set_dai_sysclk
,
1748 static struct snd_soc_dai_driver wm8903_dai
= {
1749 .name
= "wm8903-hifi",
1751 .stream_name
= "Playback",
1754 .rates
= WM8903_PLAYBACK_RATES
,
1755 .formats
= WM8903_FORMATS
,
1758 .stream_name
= "Capture",
1761 .rates
= WM8903_CAPTURE_RATES
,
1762 .formats
= WM8903_FORMATS
,
1764 .ops
= &wm8903_dai_ops
,
1765 .symmetric_rates
= 1,
1768 static int wm8903_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1770 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1775 static int wm8903_resume(struct snd_soc_codec
*codec
)
1778 u16
*reg_cache
= codec
->reg_cache
;
1779 u16
*tmp_cache
= kmemdup(reg_cache
, sizeof(wm8903_reg_defaults
),
1782 /* Bring the codec back up to standby first to minimise pop/clicks */
1783 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1785 /* Sync back everything else */
1787 for (i
= 2; i
< ARRAY_SIZE(wm8903_reg_defaults
); i
++)
1788 if (tmp_cache
[i
] != reg_cache
[i
])
1789 snd_soc_write(codec
, i
, tmp_cache
[i
]);
1792 dev_err(codec
->dev
, "Failed to allocate temporary cache\n");
1798 #ifdef CONFIG_GPIOLIB
1799 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1801 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1804 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1806 if (offset
>= WM8903_NUM_GPIO
)
1812 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1814 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1815 struct snd_soc_codec
*codec
= wm8903
->codec
;
1816 unsigned int mask
, val
;
1818 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1819 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1822 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1826 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1828 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1829 struct snd_soc_codec
*codec
= wm8903
->codec
;
1832 reg
= snd_soc_read(codec
, WM8903_GPIO_CONTROL_1
+ offset
);
1834 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1837 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1838 unsigned offset
, int value
)
1840 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1841 struct snd_soc_codec
*codec
= wm8903
->codec
;
1842 unsigned int mask
, val
;
1844 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1845 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1846 (value
<< WM8903_GP2_LVL_SHIFT
);
1848 return snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1852 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1854 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1855 struct snd_soc_codec
*codec
= wm8903
->codec
;
1857 snd_soc_update_bits(codec
, WM8903_GPIO_CONTROL_1
+ offset
,
1858 WM8903_GP1_LVL_MASK
,
1859 !!value
<< WM8903_GP1_LVL_SHIFT
);
1862 static struct gpio_chip wm8903_template_chip
= {
1864 .owner
= THIS_MODULE
,
1865 .request
= wm8903_gpio_request
,
1866 .direction_input
= wm8903_gpio_direction_in
,
1867 .get
= wm8903_gpio_get
,
1868 .direction_output
= wm8903_gpio_direction_out
,
1869 .set
= wm8903_gpio_set
,
1873 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1875 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1876 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1879 wm8903
->gpio_chip
= wm8903_template_chip
;
1880 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1881 wm8903
->gpio_chip
.dev
= codec
->dev
;
1883 if (pdata
&& pdata
->gpio_base
)
1884 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1886 wm8903
->gpio_chip
.base
= -1;
1888 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1890 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
1893 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1895 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1898 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1900 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1903 static void wm8903_init_gpio(struct snd_soc_codec
*codec
)
1907 static void wm8903_free_gpio(struct snd_soc_codec
*codec
)
1912 static int wm8903_probe(struct snd_soc_codec
*codec
)
1914 struct wm8903_platform_data
*pdata
= dev_get_platdata(codec
->dev
);
1915 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1917 int trigger
, irq_pol
;
1920 wm8903
->codec
= codec
;
1921 init_completion(&wm8903
->wseq
);
1923 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1925 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1929 val
= snd_soc_read(codec
, WM8903_SW_RESET_AND_ID
);
1930 if (val
!= wm8903_reg_defaults
[WM8903_SW_RESET_AND_ID
]) {
1932 "Device with ID register %x is not a WM8903\n", val
);
1936 val
= snd_soc_read(codec
, WM8903_REVISION_NUMBER
);
1937 dev_info(codec
->dev
, "WM8903 revision %c\n",
1938 (val
& WM8903_CHIP_REV_MASK
) + 'A');
1940 wm8903_reset(codec
);
1942 /* Set up GPIOs and microphone detection */
1944 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
1945 if (pdata
->gpio_cfg
[i
] == WM8903_GPIO_NO_CONFIG
)
1948 snd_soc_write(codec
, WM8903_GPIO_CONTROL_1
+ i
,
1949 pdata
->gpio_cfg
[i
] & 0xffff);
1952 snd_soc_write(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1955 /* Microphone detection needs the WSEQ clock */
1956 if (pdata
->micdet_cfg
)
1957 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1958 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1960 wm8903
->mic_delay
= pdata
->micdet_delay
;
1964 if (pdata
&& pdata
->irq_active_low
) {
1965 trigger
= IRQF_TRIGGER_LOW
;
1966 irq_pol
= WM8903_IRQ_POL
;
1968 trigger
= IRQF_TRIGGER_HIGH
;
1972 snd_soc_update_bits(codec
, WM8903_INTERRUPT_CONTROL
,
1973 WM8903_IRQ_POL
, irq_pol
);
1975 ret
= request_threaded_irq(wm8903
->irq
, NULL
, wm8903_irq
,
1976 trigger
| IRQF_ONESHOT
,
1979 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
1984 /* Enable write sequencer interrupts */
1985 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1986 WM8903_IM_WSEQ_BUSY_EINT
, 0);
1989 /* power on device */
1990 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1992 /* Latch volume update bits */
1993 val
= snd_soc_read(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
);
1994 val
|= WM8903_ADCVU
;
1995 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_LEFT
, val
);
1996 snd_soc_write(codec
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
, val
);
1998 val
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
);
1999 val
|= WM8903_DACVU
;
2000 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_LEFT
, val
);
2001 snd_soc_write(codec
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
, val
);
2003 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT1_LEFT
);
2004 val
|= WM8903_HPOUTVU
;
2005 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_LEFT
, val
);
2006 snd_soc_write(codec
, WM8903_ANALOGUE_OUT1_RIGHT
, val
);
2008 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT2_LEFT
);
2009 val
|= WM8903_LINEOUTVU
;
2010 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_LEFT
, val
);
2011 snd_soc_write(codec
, WM8903_ANALOGUE_OUT2_RIGHT
, val
);
2013 val
= snd_soc_read(codec
, WM8903_ANALOGUE_OUT3_LEFT
);
2014 val
|= WM8903_SPKVU
;
2015 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_LEFT
, val
);
2016 snd_soc_write(codec
, WM8903_ANALOGUE_OUT3_RIGHT
, val
);
2018 /* Enable DAC soft mute by default */
2019 snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
2020 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
2021 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
2023 snd_soc_add_controls(codec
, wm8903_snd_controls
,
2024 ARRAY_SIZE(wm8903_snd_controls
));
2025 wm8903_add_widgets(codec
);
2027 wm8903_init_gpio(codec
);
2032 /* power down chip */
2033 static int wm8903_remove(struct snd_soc_codec
*codec
)
2035 wm8903_free_gpio(codec
);
2036 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2040 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
2041 .probe
= wm8903_probe
,
2042 .remove
= wm8903_remove
,
2043 .suspend
= wm8903_suspend
,
2044 .resume
= wm8903_resume
,
2045 .set_bias_level
= wm8903_set_bias_level
,
2046 .reg_cache_size
= ARRAY_SIZE(wm8903_reg_defaults
),
2047 .reg_word_size
= sizeof(u16
),
2048 .reg_cache_default
= wm8903_reg_defaults
,
2049 .volatile_register
= wm8903_volatile_register
,
2050 .seq_notifier
= wm8903_seq_notifier
,
2053 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2054 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
2055 const struct i2c_device_id
*id
)
2057 struct wm8903_priv
*wm8903
;
2060 wm8903
= kzalloc(sizeof(struct wm8903_priv
), GFP_KERNEL
);
2064 i2c_set_clientdata(i2c
, wm8903
);
2065 wm8903
->irq
= i2c
->irq
;
2067 ret
= snd_soc_register_codec(&i2c
->dev
,
2068 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
2074 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
2076 snd_soc_unregister_codec(&client
->dev
);
2077 kfree(i2c_get_clientdata(client
));
2081 static const struct i2c_device_id wm8903_i2c_id
[] = {
2085 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
2087 static struct i2c_driver wm8903_i2c_driver
= {
2090 .owner
= THIS_MODULE
,
2092 .probe
= wm8903_i2c_probe
,
2093 .remove
= __devexit_p(wm8903_i2c_remove
),
2094 .id_table
= wm8903_i2c_id
,
2098 static int __init
wm8903_modinit(void)
2101 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2102 ret
= i2c_add_driver(&wm8903_i2c_driver
);
2104 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
2110 module_init(wm8903_modinit
);
2112 static void __exit
wm8903_exit(void)
2114 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2115 i2c_del_driver(&wm8903_i2c_driver
);
2118 module_exit(wm8903_exit
);
2120 MODULE_DESCRIPTION("ASoC WM8903 driver");
2121 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2122 MODULE_LICENSE("GPL");